diff --git a/.github/workflows/github-actions-lint-tcl.yml b/.github/workflows/github-actions-lint-tcl.yml
new file mode 100644
index 0000000000..5e52158e62
--- /dev/null
+++ b/.github/workflows/github-actions-lint-tcl.yml
@@ -0,0 +1,27 @@
+name: Lint Tcl code
+
+on:
+ push:
+ branches:
+ - master
+ pull_request:
+ branches:
+ - master
+
+jobs:
+ build:
+ runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
+ steps:
+ - name: Checkout repository
+ uses: actions/checkout@v4
+
+ - name: Install Dependencies
+ run: |
+ python3 -m pip install -U --user tclint==0.4.2
+
+ - name: Lint
+ run: |
+ tclfmt --version
+ tclfmt --in-place .
+ git diff --exit-code
+ tclint --no-check-style .
diff --git a/MODULE.bazel b/MODULE.bazel
index 86dc8624e4..574d678f5d 100644
--- a/MODULE.bazel
+++ b/MODULE.bazel
@@ -11,7 +11,7 @@ bazel_dep(name = "bazel-orfs")
# To bump version, run: bazelisk run @bazel-orfs//:bump
git_override(
module_name = "bazel-orfs",
- commit = "9a3778bdbe63106a894a03e865335a31ebc860d1",
+ commit = "f8a4b694b37c8f5322323eba9a9ae37f9541ee17",
remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
)
@@ -20,13 +20,13 @@ bazel_dep(name = "rules_python", version = "1.2.0")
python = use_extension("@rules_python//python/extensions:python.bzl", "python")
python.toolchain(
ignore_root_user_error = True,
- python_version = "3.12",
+ python_version = "3.13",
)
pip = use_extension("@rules_python//python/extensions:pip.bzl", "pip")
pip.parse(
hub_name = "orfs-pip",
- python_version = "3.12",
+ python_version = "3.13",
requirements_lock = "//flow:util/requirements_lock.txt",
)
use_repo(pip, "orfs-pip")
@@ -35,12 +35,12 @@ orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories")
# To bump version, run: bazelisk run @bazel-orfs//:bump
orfs.default(
- image = "docker.io/openroad/orfs:v3.0-3190-g5ac9869c",
+ image = "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf",
# Use local files instead of docker image
makefile = "//flow:makefile",
makefile_yosys = "//flow:makefile_yosys",
pdk = "//flow:asap7",
- sha256 = "2ca999699bc91144074b7f23f42da9330d7279437c386a1413fba4a6a7520916",
+ sha256 = "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e",
)
use_repo(orfs, "com_github_nixos_patchelf_download")
use_repo(orfs, "docker_orfs")
diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock
index 92f3178152..45ece7112e 100644
--- a/MODULE.bazel.lock
+++ b/MODULE.bazel.lock
@@ -638,7 +638,7 @@
"@@bazel-orfs~//:extension.bzl%orfs_repositories": {
"general": {
"bzlTransitiveDigest": "opZMguyG+UPmDQ6vhzXe/u0WnKyao2m9IAQt+JWkhcA=",
- "usagesDigest": "2NcMguz4FONad7PT2HxaMW3QgfrJL+IvDGhrVn5dQhU=",
+ "usagesDigest": "ZjAOFUXNXojx6a5mgorvg9pXsDXOsJv7KzaZaxOrWXU=",
"recordedFileInputs": {},
"recordedDirentsInputs": {},
"envVariables": {},
@@ -658,8 +658,8 @@
"bzlFile": "@@bazel-orfs~//:docker.bzl",
"ruleClassName": "docker_pkg",
"attributes": {
- "image": "docker.io/openroad/orfs:v3.0-3190-g5ac9869c",
- "sha256": "2ca999699bc91144074b7f23f42da9330d7279437c386a1413fba4a6a7520916",
+ "image": "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf",
+ "sha256": "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e",
"build_file": "@@bazel-orfs~//:docker.BUILD.bazel",
"timeout": 3600,
"patch_cmds": [
@@ -941,12 +941,12 @@
},
"@@rules_python~//python/extensions:pip.bzl%pip": {
"general": {
- "bzlTransitiveDigest": "UVXSWhRHdKjw09doJ4m4mjTHC+BIiApwOePiq04rmBA=",
- "usagesDigest": "pH3zwwfC5Cl9+K3uTBlFrrKV8Gno7nf5+n1aL4X3uGU=",
+ "bzlTransitiveDigest": "wDKx+PsqgAb8Kll8JbxI6+g8BUNJT48gxqvlHp+uPaM=",
+ "usagesDigest": "Pmo+R+aERo0wl9TIu+O0dXTNmE8JG2ElzftJqGKKsXk=",
"recordedFileInputs": {
"@@rules_python~//tools/publish/requirements_linux.txt": "d576e0d8542df61396a9b38deeaa183c24135ed5e8e73bb9622f298f2671811e",
- "@@bazel-orfs~//requirements_lock_3_13.txt": "fcabafb7192fe8f92d82e7ec8ddd8e3fd6787f8acea3ec694f105ed63821416a",
- "@@//flow/util/requirements_lock.txt": "016f788600d492820c9a6ff951c31a26735bcdb24a5a1bc83f68a726c6e4c884",
+ "@@bazel-orfs~//requirements_lock_3_13.txt": "6d409e2c9f81ceee67c23e6f26b6742b4ee6c32826c7d0591c5c57df72a6a16b",
+ "@@//flow/util/requirements_lock.txt": "21d4a2f4b126820247f3f9b3554210fc78861c0a367c2b52d87771900b40520c",
"@@rules_fuzzing~//fuzzing/requirements.txt": "ab04664be026b632a0d2a2446c4f65982b7654f5b6851d2f9d399a19b7242a5b",
"@@rules_python~//tools/publish/requirements_windows.txt": "d18538a3982beab378fd5687f4db33162ee1ece69801f9a451661b1b64286b76",
"@@protobuf~//python/requirements.txt": "983be60d3cec4b319dcab6d48aeb3f5b2f7c3350f26b3a9e97486c37967c73c5",
@@ -1028,6 +1028,16 @@
"requirement": "packaging==24.2 --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f"
}
},
+ "bazel-orfs-pip_313_pandas": {
+ "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
+ "ruleClassName": "whl_library",
+ "attributes": {
+ "dep_template": "@bazel-orfs-pip//{name}:{target}",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "bazel-orfs-pip_313",
+ "requirement": "pandas==2.3.0 --hash=sha256:034abd6f3db8b9880aaee98f4f5d4dbec7c4829938463ec046517220b2f8574e --hash=sha256:094e271a15b579650ebf4c5155c05dcd2a14fd4fdd72cf4854b2f7ad31ea30be --hash=sha256:14a0cc77b0f089d2d2ffe3007db58f170dae9b9f54e569b299db871a3ab5bf46 --hash=sha256:1a881bc1309f3fce34696d07b00f13335c41f5f5a8770a33b09ebe23261cfc67 --hash=sha256:1d2b33e68d0ce64e26a4acc2e72d747292084f4e8db4c847c6f5f6cbe56ed6d8 --hash=sha256:213cd63c43263dbb522c1f8a7c9d072e25900f6975596f883f4bebd77295d4f3 --hash=sha256:23c2b2dc5213810208ca0b80b8666670eb4660bbfd9d45f58592cc4ddcfd62e1 --hash=sha256:2c7e2fc25f89a49a11599ec1e76821322439d90820108309bf42130d2f36c983 --hash=sha256:2eb4728a18dcd2908c7fccf74a982e241b467d178724545a48d0caf534b38ebf --hash=sha256:34600ab34ebf1131a7613a260a61dbe8b62c188ec0ea4c296da7c9a06b004133 --hash=sha256:39ff73ec07be5e90330cc6ff5705c651ace83374189dcdcb46e6ff54b4a72cd6 --hash=sha256:404d681c698e3c8a40a61d0cd9412cc7364ab9a9cc6e144ae2992e11a2e77a20 --hash=sha256:40cecc4ea5abd2921682b57532baea5588cc5f80f0231c624056b146887274d2 --hash=sha256:430a63bae10b5086995db1b02694996336e5a8ac9a96b4200572b413dfdfccb9 --hash=sha256:4930255e28ff5545e2ca404637bcc56f031893142773b3468dc021c6c32a1390 --hash=sha256:6021910b086b3ca756755e86ddc64e0ddafd5e58e076c72cb1585162e5ad259b --hash=sha256:625466edd01d43b75b1883a64d859168e4556261a5035b32f9d743b67ef44634 --hash=sha256:75651c14fde635e680496148a8526b328e09fe0572d9ae9b638648c46a544ba3 --hash=sha256:84141f722d45d0c2a89544dd29d35b3abfc13d2250ed7e68394eda7564bd6324 --hash=sha256:8adff9f138fc614347ff33812046787f7d43b3cef7c0f0171b3340cae333f6ca --hash=sha256:951805d146922aed8357e4cc5671b8b0b9be1027f0619cea132a9f3f65f2f09c --hash=sha256:9efc0acbbffb5236fbdf0409c04edce96bec4bdaa649d49985427bd1ec73e085 --hash=sha256:9ff730713d4c4f2f1c860e36c005c7cefc1c7c80c21c0688fd605aa43c9fcf09 --hash=sha256:a6872d695c896f00df46b71648eea332279ef4077a409e2fe94220208b6bb675 --hash=sha256:b198687ca9c8529662213538a9bb1e60fa0bf0f6af89292eb68fea28743fcd5a --hash=sha256:b9d8c3187be7479ea5c3d30c32a5d73d62a621166675063b2edd21bc47614027 --hash=sha256:ba24af48643b12ffe49b27065d3babd52702d95ab70f50e1b34f71ca703e2c0d --hash=sha256:bb32dc743b52467d488e7a7c8039b821da2826a9ba4f85b89ea95274f863280f --hash=sha256:bb3be958022198531eb7ec2008cfc78c5b1eed51af8600c6c5d9160d89d8d249 --hash=sha256:bf5be867a0541a9fb47a4be0c5790a4bccd5b77b92f0a59eeec9375fafc2aa14 --hash=sha256:c06f6f144ad0a1bf84699aeea7eff6068ca5c63ceb404798198af7eb86082e33 --hash=sha256:c6da97aeb6a6d233fb6b17986234cc723b396b50a3c6804776351994f2a658fd --hash=sha256:e0f51973ba93a9f97185049326d75b942b9aeb472bec616a129806facb129ebb --hash=sha256:e1991bbb96f4050b09b5f811253c4f3cf05ee89a589379aa36cd623f21a31d6f --hash=sha256:e5f08eb9a445d07720776df6e641975665c9ea12c9d8a331e0f6890f2dcd76ef --hash=sha256:e78ad363ddb873a631e92a3c063ade1ecfb34cae71e9a2be6ad100f875ac1042 --hash=sha256:ed16339bc354a73e0a609df36d256672c7d296f3f767ac07257801aa064ff73c --hash=sha256:f4dd97c19bd06bc557ad787a15b6489d2614ddaab5d104a0310eb314c724b2d2 --hash=sha256:f925f1ef673b4bd0271b1809b72b3270384f2b7d9d14a189b12b7fc02574d575 --hash=sha256:f95a2aef32614ed86216d3c450ab12a4e82084e8102e355707a1d96e33d51c34 --hash=sha256:fa07e138b3f6c04addfeaf56cc7fdb96c3b68a3fe5e5401251f231fce40a0d7a --hash=sha256:fa35c266c8cd1a67d75971a1912b185b492d257092bdd2709bbdebe574ed228d"
+ }
+ },
"bazel-orfs-pip_313_pillow": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
@@ -1058,6 +1068,16 @@
"requirement": "python-dateutil==2.9.0.post0 --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427"
}
},
+ "bazel-orfs-pip_313_pytz": {
+ "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
+ "ruleClassName": "whl_library",
+ "attributes": {
+ "dep_template": "@bazel-orfs-pip//{name}:{target}",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "bazel-orfs-pip_313",
+ "requirement": "pytz==2025.2 --hash=sha256:360b9e3dbb49a209c21ad61809c7fb453643e048b38924c765813546746e81c3 --hash=sha256:5ddf76296dd8c44c26eb8f4b6f35488f3ccbf6fbbd7adee0b7262d43f0ec2f00"
+ }
+ },
"bazel-orfs-pip_313_pyyaml": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
@@ -1078,123 +1098,133 @@
"requirement": "six==1.17.0 --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81"
}
},
- "orfs-pip_312_contourpy": {
+ "bazel-orfs-pip_313_tzdata": {
+ "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
+ "ruleClassName": "whl_library",
+ "attributes": {
+ "dep_template": "@bazel-orfs-pip//{name}:{target}",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "bazel-orfs-pip_313",
+ "requirement": "tzdata==2025.2 --hash=sha256:1a403fada01ff9221ca8044d701868fa132215d84beb92242d9acd2147f667a8 --hash=sha256:b60a638fcc0daffadf82fe0f57e53d06bdec2f36c4df66280ae79bce6bd6f2b9"
+ }
+ },
+ "orfs-pip_313_contourpy": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "contourpy==1.3.1 --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 --hash=sha256:05e806338bfeaa006acbdeba0ad681a10be63b26e1b17317bfac3c5d98f36cda --hash=sha256:08d9d449a61cf53033612cb368f3a1b26cd7835d9b8cd326647efe43bca7568d --hash=sha256:0ffa84be8e0bd33410b17189f7164c3589c229ce5db85798076a3fa136d0e509 --hash=sha256:113231fe3825ebf6f15eaa8bc1f5b0ddc19d42b733345eae0934cb291beb88b6 --hash=sha256:14c102b0eab282427b662cb590f2e9340a9d91a1c297f48729431f2dcd16e14f --hash=sha256:174e758c66bbc1c8576992cec9599ce8b6672b741b5d336b5c74e35ac382b18e --hash=sha256:19c1555a6801c2f084c7ddc1c6e11f02eb6a6016ca1318dd5452ba3f613a1751 --hash=sha256:19d40d37c1c3a4961b4619dd9d77b12124a453cc3d02bb31a07d58ef684d3d86 --hash=sha256:1bf98051f1045b15c87868dbaea84f92408337d4f81d0e449ee41920ea121d3b --hash=sha256:20914c8c973f41456337652a6eeca26d2148aa96dd7ac323b74516988bea89fc --hash=sha256:287ccc248c9e0d0566934e7d606201abd74761b5703d804ff3df8935f523d546 --hash=sha256:2ba94a401342fc0f8b948e57d977557fbf4d515f03c67682dd5c6191cb2d16ec --hash=sha256:31c1b55c1f34f80557d3830d3dd93ba722ce7e33a0b472cba0ec3b6535684d8f --hash=sha256:36987a15e8ace5f58d4d5da9dca82d498c2bbb28dff6e5d04fbfcc35a9cb3a82 --hash=sha256:3a04ecd68acbd77fa2d39723ceca4c3197cb2969633836ced1bea14e219d077c --hash=sha256:3e8b974d8db2c5610fb4e76307e265de0edb655ae8169e8b21f41807ccbeec4b --hash=sha256:3ea9924d28fc5586bf0b42d15f590b10c224117e74409dd7a0be3b62b74a501c --hash=sha256:4318af1c925fb9a4fb190559ef3eec206845f63e80fb603d47f2d6d67683901c --hash=sha256:44a29502ca9c7b5ba389e620d44f2fbe792b1fb5734e8b931ad307071ec58c53 --hash=sha256:47734d7073fb4590b4a40122b35917cd77be5722d80683b249dac1de266aac80 --hash=sha256:4d76d5993a34ef3df5181ba3c92fabb93f1eaa5729504fb03423fcd9f3177242 --hash=sha256:4dbbc03a40f916a8420e420d63e96a1258d3d1b58cbdfd8d1f07b49fcbd38e85 --hash=sha256:500360b77259914f7805af7462e41f9cb7ca92ad38e9f94d6c8641b089338124 --hash=sha256:523a8ee12edfa36f6d2a49407f705a6ef4c5098de4f498619787e272de93f2d5 --hash=sha256:573abb30e0e05bf31ed067d2f82500ecfdaec15627a59d63ea2d95714790f5c2 --hash=sha256:5b75aa69cb4d6f137b36f7eb2ace9280cfb60c55dc5f61c731fdf6f037f958a3 --hash=sha256:61332c87493b00091423e747ea78200659dc09bdf7fd69edd5e98cef5d3e9a8d --hash=sha256:805617228ba7e2cbbfb6c503858e626ab528ac2a32a04a2fe88ffaf6b02c32bc --hash=sha256:841ad858cff65c2c04bf93875e384ccb82b654574a6d7f30453a04f04af71342 --hash=sha256:89785bb2a1980c1bd87f0cb1517a71cde374776a5f150936b82580ae6ead44a1 --hash=sha256:8eb96e79b9f3dcadbad2a3891672f81cdcab7f95b27f28f1c67d75f045b6b4f1 --hash=sha256:974d8145f8ca354498005b5b981165b74a195abfae9a8129df3e56771961d595 --hash=sha256:9ddeb796389dadcd884c7eb07bd14ef12408aaae358f0e2ae24114d797eede30 --hash=sha256:a045f341a77b77e1c5de31e74e966537bba9f3c4099b35bf4c2e3939dd54cdab --hash=sha256:a0cffcbede75c059f535725c1680dfb17b6ba8753f0c74b14e6a9c68c29d7ea3 --hash=sha256:a761d9ccfc5e2ecd1bf05534eda382aa14c3e4f9205ba5b1684ecfe400716ef2 --hash=sha256:a7895f46d47671fa7ceec40f31fae721da51ad34bdca0bee83e38870b1f47ffd --hash=sha256:a9fa36448e6a3a1a9a2ba23c02012c43ed88905ec80163f2ffe2421c7192a5d7 --hash=sha256:ab29962927945d89d9b293eabd0d59aea28d887d4f3be6c22deaefbb938a7277 --hash=sha256:abbb49fb7dac584e5abc6636b7b2a7227111c4f771005853e7d25176daaf8453 --hash=sha256:ac4578ac281983f63b400f7fe6c101bedc10651650eef012be1ccffcbacf3697 --hash=sha256:adce39d67c0edf383647a3a007de0a45fd1b08dedaa5318404f1a73059c2512b --hash=sha256:ade08d343436a94e633db932e7e8407fe7de8083967962b46bdfc1b0ced39454 --hash=sha256:b2bdca22a27e35f16794cf585832e542123296b4687f9fd96822db6bae17bfc9 --hash=sha256:b2f926efda994cdf3c8d3fdb40b9962f86edbc4457e739277b961eced3d0b4c1 --hash=sha256:b457d6430833cee8e4b8e9b6f07aa1c161e5e0d52e118dc102c8f9bd7dd060d6 --hash=sha256:c414fc1ed8ee1dbd5da626cf3710c6013d3d27456651d156711fa24f24bd1291 --hash=sha256:cb76c1a154b83991a3cbbf0dfeb26ec2833ad56f95540b442c73950af2013750 --hash=sha256:dfd97abd83335045a913e3bcc4a09c0ceadbe66580cf573fe961f4a825efa699 --hash=sha256:e914a8cb05ce5c809dd0fe350cfbb4e881bde5e2a38dc04e3afe1b3e58bd158e --hash=sha256:ece6df05e2c41bd46776fbc712e0996f7c94e0d0543af1656956d150c4ca7c81 --hash=sha256:efa874e87e4a647fd2e4f514d5e91c7d493697127beb95e77d2f7561f6905bd9 --hash=sha256:f611e628ef06670df83fce17805c344710ca5cde01edfdc72751311da8585375"
}
},
- "orfs-pip_312_cycler": {
+ "orfs-pip_313_cycler": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "cycler==0.12.1 --hash=sha256:85cef7cff222d8644161529808465972e51340599459b8ac3ccbac5a854e0d30 --hash=sha256:88bb128f02ba341da8ef447245a9e138fae777f6a23943da4540077d3601eb1c"
}
},
- "orfs-pip_312_fonttools": {
+ "orfs-pip_313_fonttools": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "fonttools==4.55.7 --hash=sha256:05568a66b090ed9d79aefdce2ceb180bb64fc856961deaedc29f5ad51355ce2c --hash=sha256:087ace2d06894ccdb03e6975d05da6bb9cec0c689b2a9983c059880e33a1464a --hash=sha256:09740feed51f9ed816aebf5d82071b7fecf693ac3a7e0fc8ea433f5dc3bd92f5 --hash=sha256:0ed25d7b5fa4ae6a805c2a9cc0e5307d45cbb3b8e155584fe932d0f3b6a997bf --hash=sha256:1101976c703ff4008a928fc3fef42caf06d035bfc4614230d7e797cbe356feb0 --hash=sha256:12e81d44f762156d28b5c93a6b65d98ed73678be45b22546de8ed29736c3cb96 --hash=sha256:1d4be8354c245c00aecfc90f5d3da8606226f0ac22e1cb0837b39139e4c2df85 --hash=sha256:23df0f1003abaf8a435543f59583fc247e7ae1b047ee2263510e0654a5f207e0 --hash=sha256:2dbc08e227fbeb716776905a7bd3c4fc62c8e37c8ef7d481acd10cb5fde12222 --hash=sha256:2e6dffe9cbcd163ef617fab1f81682e4d1629b7a5b9c5e598274dc2d03e88bcd --hash=sha256:3098355e7a7b5ac48d5dc29684a65271187b865b85675033958b57c40364ee34 --hash=sha256:30c3501328363b73a90acc8a722dd199c993f2c4369ea16886128d94e91897ec --hash=sha256:3304dfcf9ca204dd0ef691a287bd851ddd8e8250108658c0677c3fdfec853a20 --hash=sha256:371197de1283cc99f5f10eb91496520eb0e2d079312d014fd6cef9e802174c6a --hash=sha256:3976db357484bf4cb533dfd0d1a444b38ad06062458715ebf21e38c71aff325d --hash=sha256:418ece624fbc04e199f58398ffef3eaad645baba65434871b09eb7350a3a346b --hash=sha256:5ff0daf8b2e0612e5761fed2e4a2f54eff9d9ec0aeb4091c9f3666f9a118325e --hash=sha256:6899e3d97225a8218f525e9754da0376e1c62953a0d57a76c5abaada51e0d140 --hash=sha256:69ed0660750993150f7c4d966c0c1ffaa0385f23ccef85c2ff108062d80dd7ea --hash=sha256:6eb93cbba484a463b5ee83f7dd3211905f27a3871d20d90fb72de84c6c5056e3 --hash=sha256:775ed0700ee6f781436641f18a0c61b1846a8c1aecae6da6b395c4417e2cb567 --hash=sha256:77e5115a425d53be6e31cd0fe9210f62a488bccf81eb113ab5dd7f4fa88e4d81 --hash=sha256:7858dc6823296a053d85b831fa8428781c6c6f06fca44582bf7b6b2ff32a9089 --hash=sha256:7ff8e606f905048dc91a55a06d994b68065bf35752ae199df54a9bf30013dcaa --hash=sha256:82163d58b43eff6e2025a25c32905fdb9042a163cc1ff82dab393e7ffc77a7d5 --hash=sha256:833927d089e6585019f2c85e3f8f7d87733e3fe81cd704ebaca7afa27e2e7113 --hash=sha256:8ef5ee98fc320c158e4e459a5ee40d1ac3728d4ce11c3c8dfd854aa0aa5c042f --hash=sha256:9074a2848ea5b607377e16998dfcf90cf5eb614d0c388541b9782d5cc038e149 --hash=sha256:916e1d926823b4b3b3815c59fc79f4ed670696fdd5fd9a5e690a0503eef38f79 --hash=sha256:9ec71d0cc0242899f87e4c230ed0b22c7b8681f288fb80e3d81c2c54c5bd2c79 --hash=sha256:a3d19ea483b3cd8833e9e2ee8115f3d2044d55d3743d84f9c23b48b52d7516d8 --hash=sha256:a7831d16c95b60866772a15fdcc03772625c4bb6d858e0ad8ef3d6e48709b2ef --hash=sha256:b89da448e0073408d7b2c44935f9fdae4fdc93644899f99f6102ef883ecf083c --hash=sha256:bee4920ebeb540849bc3555d871e2a8487e39ce8263c281f74d5b6d44d2bf1df --hash=sha256:c135c91d47351b84893fb6fcbb8f178eba14f7cb195850264c0675c85e4238b6 --hash=sha256:c26445a7be689f8b70df7d5d2e2c85ec4407bdb769902a23dd45ac44f767575d --hash=sha256:c2680a3e6e2e2d104a7ea81fb89323e1a9122c23b03d6569d0768887d0d76e69 --hash=sha256:c665df9c9d99937a5bf807bace1c0c95bd13f55de8c82aaf9856b868dcbfe5d9 --hash=sha256:d4b1c5939c0521525f45522823508e6fad21175bca978583688ea3b3736e6625 --hash=sha256:d4bd27f0fa5120aaa39f76de5768959bc97300e0f59a3160d466b51436a38aea --hash=sha256:e10c7fb80cdfdc32244514cbea0906e9f53e3cc80d64d3389da09502fd999b55 --hash=sha256:e2cbafedb9462be7cf68c66b6ca1d8309842fe36b729f1b1969595f5d660e5c2 --hash=sha256:e4bde87985012adbd7559bc363d802fb335e92a07ff86a76cf02bebb0b8566d1 --hash=sha256:e696d6e2baf4cc57ded34bb87e5d3a9e4da9732f3d9e8e2c6db0746e57a6dc0b --hash=sha256:ee7aa8bb716318e3d835ef473978e22b7a39c0f1b3b08cc0b0ee1bba6f73bc1e --hash=sha256:f0899cd23967950e7b902ea75af06cfe5f59ac71eb38e98a774c9e596790e6aa --hash=sha256:f0c45eae32d090763820756b18322a70571dada3f1cbe003debc37a9c35bc260 --hash=sha256:f3b63648600dd0081bdd6856a86d014a7f1d2d11c3c974542f866478d832e103 --hash=sha256:f669910b64d27750398f6c56c651367d4954b05c86ff067af1c9949e109cf1e2 --hash=sha256:fd4ebc475d43f3de2b26e0cf551eff92c24e22d1aee03dc1b33adb52fc2e6cb2"
}
},
- "orfs-pip_312_kiwisolver": {
+ "orfs-pip_313_kiwisolver": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "kiwisolver==1.4.8 --hash=sha256:01c3d31902c7db5fb6182832713d3b4122ad9317c2c5877d0539227d96bb2e50 --hash=sha256:034d2c891f76bd3edbdb3ea11140d8510dca675443da7304205a2eaa45d8334c --hash=sha256:085940635c62697391baafaaeabdf3dd7a6c3643577dde337f4d66eba021b2b8 --hash=sha256:08e77738ed7538f036cd1170cbed942ef749137b1311fa2bbe2a7fda2f6bf3cc --hash=sha256:111793b232842991be367ed828076b03d96202c19221b5ebab421ce8bcad016f --hash=sha256:11e1022b524bd48ae56c9b4f9296bce77e15a2e42a502cceba602f804b32bb79 --hash=sha256:151dffc4865e5fe6dafce5480fab84f950d14566c480c08a53c663a0020504b6 --hash=sha256:16523b40aab60426ffdebe33ac374457cf62863e330a90a0383639ce14bf44b2 --hash=sha256:1732e065704b47c9afca7ffa272f845300a4eb959276bf6970dc07265e73b605 --hash=sha256:1c8ceb754339793c24aee1c9fb2485b5b1f5bb1c2c214ff13368431e51fc9a09 --hash=sha256:23454ff084b07ac54ca8be535f4174170c1094a4cff78fbae4f73a4bcc0d4dab --hash=sha256:23d5f023bdc8c7e54eb65f03ca5d5bb25b601eac4d7f1a042888a1f45237987e --hash=sha256:257af1622860e51b1a9d0ce387bf5c2c4f36a90594cb9514f55b074bcc787cfc --hash=sha256:286b18e86682fd2217a48fc6be6b0f20c1d0ed10958d8dc53453ad58d7be0bf8 --hash=sha256:291331973c64bb9cce50bbe871fb2e675c4331dab4f31abe89f175ad7679a4d7 --hash=sha256:2f0121b07b356a22fb0414cec4666bbe36fd6d0d759db3d37228f496ed67c880 --hash=sha256:3452046c37c7692bd52b0e752b87954ef86ee2224e624ef7ce6cb21e8c41cc1b --hash=sha256:34d142fba9c464bc3bbfeff15c96eab0e7310343d6aefb62a79d51421fcc5f1b --hash=sha256:369b75d40abedc1da2c1f4de13f3482cb99e3237b38726710f4a793432b1c5ff --hash=sha256:36dbbfd34838500a31f52c9786990d00150860e46cd5041386f217101350f0d3 --hash=sha256:370fd2df41660ed4e26b8c9d6bbcad668fbe2560462cba151a721d49e5b6628c --hash=sha256:3a96c0e790ee875d65e340ab383700e2b4891677b7fcd30a699146f9384a2bb0 --hash=sha256:3b9b4d2892fefc886f30301cdd80debd8bb01ecdf165a449eb6e78f79f0fabd6 --hash=sha256:3cd3bc628b25f74aedc6d374d5babf0166a92ff1317f46267f12d2ed54bc1d30 --hash=sha256:3ddc373e0eef45b59197de815b1b28ef89ae3955e7722cc9710fb91cd77b7f47 --hash=sha256:4191ee8dfd0be1c3666ccbac178c5a05d5f8d689bbe3fc92f3c4abec817f8fe0 --hash=sha256:54a62808ac74b5e55a04a408cda6156f986cefbcf0ada13572696b507cc92fa1 --hash=sha256:577facaa411c10421314598b50413aa1ebcf5126f704f1e5d72d7e4e9f020d90 --hash=sha256:641f2ddf9358c80faa22e22eb4c9f54bd3f0e442e038728f500e3b978d00aa7d --hash=sha256:65ea09a5a3faadd59c2ce96dc7bf0f364986a315949dc6374f04396b0d60e09b --hash=sha256:68269e60ee4929893aad82666821aaacbd455284124817af45c11e50a4b42e3c --hash=sha256:69b5637c3f316cab1ec1c9a12b8c5f4750a4c4b71af9157645bf32830e39c03a --hash=sha256:7506488470f41169b86d8c9aeff587293f530a23a23a49d6bc64dab66bedc71e --hash=sha256:768cade2c2df13db52475bd28d3a3fac8c9eff04b0e9e2fda0f3760f20b3f7fc --hash=sha256:77e6f57a20b9bd4e1e2cedda4d0b986ebd0216236f0106e55c28aea3d3d69b16 --hash=sha256:782bb86f245ec18009890e7cb8d13a5ef54dcf2ebe18ed65f795e635a96a1c6a --hash=sha256:7a3ad337add5148cf51ce0b55642dc551c0b9d6248458a757f98796ca7348712 --hash=sha256:7cd2785b9391f2873ad46088ed7599a6a71e762e1ea33e87514b1a441ed1da1c --hash=sha256:7e9a60b50fe8b2ec6f448fe8d81b07e40141bfced7f896309df271a0b92f80f3 --hash=sha256:84a2f830d42707de1d191b9490ac186bf7997a9495d4e9072210a1296345f7dc --hash=sha256:856b269c4d28a5c0d5e6c1955ec36ebfd1651ac00e1ce0afa3e28da95293b561 --hash=sha256:858416b7fb777a53f0c59ca08190ce24e9abbd3cffa18886a5781b8e3e26f65d --hash=sha256:87b287251ad6488e95b4f0b4a79a6d04d3ea35fde6340eb38fbd1ca9cd35bbbc --hash=sha256:88c6f252f6816a73b1f8c904f7bbe02fd67c09a69f7cb8a0eecdbf5ce78e63db --hash=sha256:893f5525bb92d3d735878ec00f781b2de998333659507d29ea4466208df37bed --hash=sha256:89c107041f7b27844179ea9c85d6da275aa55ecf28413e87624d033cf1f6b751 --hash=sha256:918139571133f366e8362fa4a297aeba86c7816b7ecf0bc79168080e2bd79957 --hash=sha256:99cea8b9dd34ff80c521aef46a1dddb0dcc0283cf18bde6d756f1e6f31772165 --hash=sha256:a17b7c4f5b2c51bb68ed379defd608a03954a1845dfed7cc0117f1cc8a9b7fd2 --hash=sha256:a3c44cb68861de93f0c4a8175fbaa691f0aa22550c331fefef02b618a9dcb476 --hash=sha256:a4d3601908c560bdf880f07d94f31d734afd1bb71e96585cace0e38ef44c6d84 --hash=sha256:a5ce1e481a74b44dd5e92ff03ea0cb371ae7a0268318e202be06c8f04f4f1246 --hash=sha256:a66f60f8d0c87ab7f59b6fb80e642ebb29fec354a4dfad687ca4092ae69d04f4 --hash=sha256:b21dbe165081142b1232a240fc6383fd32cdd877ca6cc89eab93e5f5883e1c25 --hash=sha256:b47a465040146981dc9db8647981b8cb96366fbc8d452b031e4f8fdffec3f26d --hash=sha256:b5773efa2be9eb9fcf5415ea3ab70fc785d598729fd6057bea38d539ead28271 --hash=sha256:b83dc6769ddbc57613280118fb4ce3cd08899cc3369f7d0e0fab518a7cf37fdb --hash=sha256:bade438f86e21d91e0cf5dd7c0ed00cda0f77c8c1616bd83f9fc157fa6760d31 --hash=sha256:bcb1ebc3547619c3b58a39e2448af089ea2ef44b37988caf432447374941574e --hash=sha256:be4816dc51c8a471749d664161b434912eee82f2ea66bd7628bd14583a833e85 --hash=sha256:c07b29089b7ba090b6f1a669f1411f27221c3662b3a1b7010e67b59bb5a6f10b --hash=sha256:c2b9a96e0f326205af81a15718a9073328df1173a2619a68553decb7097fd5d7 --hash=sha256:c5020c83e8553f770cb3b5fc13faac40f17e0b205bd237aebd21d53d733adb03 --hash=sha256:c72941acb7b67138f35b879bbe85be0f6c6a70cab78fe3ef6db9c024d9223e5b --hash=sha256:c8bf637892dc6e6aad2bc6d4d69d08764166e5e3f69d469e55427b6ac001b19d --hash=sha256:cc978a80a0db3a66d25767b03688f1147a69e6237175c0f4ffffaaedf744055a --hash=sha256:ce2cf1e5688edcb727fdf7cd1bbd0b6416758996826a8be1d958f91880d0809d --hash=sha256:d47b28d1dfe0793d5e96bce90835e17edf9a499b53969b03c6c47ea5985844c3 --hash=sha256:d47cfb2650f0e103d4bf68b0b5804c68da97272c84bb12850d877a95c056bd67 --hash=sha256:d5536185fce131780ebd809f8e623bf4030ce1b161353166c49a3c74c287897f --hash=sha256:d561d2d8883e0819445cfe58d7ddd673e4015c3c57261d7bdcd3710d0d14005c --hash=sha256:d6af5e8815fd02997cb6ad9bbed0ee1e60014438ee1a5c2444c96f87b8843502 --hash=sha256:d6d6bd87df62c27d4185de7c511c6248040afae67028a8a22012b010bc7ad062 --hash=sha256:dace81d28c787956bfbfbbfd72fdcef014f37d9b48830829e488fdb32b49d954 --hash=sha256:e063ef9f89885a1d68dd8b2e18f5ead48653176d10a0e324e3b0030e3a69adeb --hash=sha256:e7a019419b7b510f0f7c9dceff8c5eae2392037eae483a7f9162625233802b0a --hash=sha256:eaa973f1e05131de5ff3569bbba7f5fd07ea0595d3870ed4a526d486fe57fa1b --hash=sha256:eb158fe28ca0c29f2260cca8c43005329ad58452c36f0edf298204de32a9a3ed --hash=sha256:ed33ca2002a779a2e20eeb06aea7721b6e47f2d4b8a8ece979d8ba9e2a167e34 --hash=sha256:fc2ace710ba7c1dfd1a3b42530b62b9ceed115f19a1656adefce7b1782a37794"
}
},
- "orfs-pip_312_matplotlib": {
+ "orfs-pip_313_matplotlib": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "matplotlib==3.10.0 --hash=sha256:01d2b19f13aeec2e759414d3bfe19ddfb16b13a1250add08d46d5ff6f9be83c6 --hash=sha256:12eaf48463b472c3c0f8dbacdbf906e573013df81a0ab82f0616ea4b11281908 --hash=sha256:2c5829a5a1dd5a71f0e31e6e8bb449bc0ee9dbfb05ad28fc0c6b55101b3a4be6 --hash=sha256:2fbbabc82fde51391c4da5006f965e36d86d95f6ee83fb594b279564a4c5d0d2 --hash=sha256:3547d153d70233a8496859097ef0312212e2689cdf8d7ed764441c77604095ae --hash=sha256:359f87baedb1f836ce307f0e850d12bb5f1936f70d035561f90d41d305fdacea --hash=sha256:3b427392354d10975c1d0f4ee18aa5844640b512d5311ef32efd4dd7db106ede --hash=sha256:4659665bc7c9b58f8c00317c3c2a299f7f258eeae5a5d56b4c64226fca2f7c59 --hash=sha256:4673ff67a36152c48ddeaf1135e74ce0d4bce1bbf836ae40ed39c29edf7e2765 --hash=sha256:503feb23bd8c8acc75541548a1d709c059b7184cde26314896e10a9f14df5f12 --hash=sha256:5439f4c5a3e2e8eab18e2f8c3ef929772fd5641876db71f08127eed95ab64683 --hash=sha256:5cdbaf909887373c3e094b0318d7ff230b2ad9dcb64da7ade654182872ab2593 --hash=sha256:5e6c6461e1fc63df30bf6f80f0b93f5b6784299f721bc28530477acd51bfc3d1 --hash=sha256:5fd41b0ec7ee45cd960a8e71aea7c946a28a0b8a4dcee47d2856b2af051f334c --hash=sha256:607b16c8a73943df110f99ee2e940b8a1cbf9714b65307c040d422558397dac5 --hash=sha256:7e8632baebb058555ac0cde75db885c61f1212e47723d63921879806b40bec6a --hash=sha256:81713dd0d103b379de4516b861d964b1d789a144103277769238c732229d7f03 --hash=sha256:845d96568ec873be63f25fa80e9e7fae4be854a66a7e2f0c8ccc99e94a8bd4ef --hash=sha256:95b710fea129c76d30be72c3b38f330269363fbc6e570a5dd43580487380b5ff --hash=sha256:96f2886f5c1e466f21cc41b70c5a0cd47bfa0015eb2d5793c88ebce658600e25 --hash=sha256:994c07b9d9fe8d25951e3202a68c17900679274dadfc1248738dcfa1bd40d7f3 --hash=sha256:9ade1003376731a971e398cc4ef38bb83ee8caf0aee46ac6daa4b0506db1fd06 --hash=sha256:9b0558bae37f154fffda54d779a592bc97ca8b4701f1c710055b609a3bac44c8 --hash=sha256:a2a43cbefe22d653ab34bb55d42384ed30f611bcbdea1f8d7f431011a2e1c62e --hash=sha256:a994f29e968ca002b50982b27168addfd65f0105610b6be7fa515ca4b5307c95 --hash=sha256:ad2e15300530c1a94c63cfa546e3b7864bd18ea2901317bae8bbf06a5ade6dcf --hash=sha256:ae80dc3a4add4665cf2faa90138384a7ffe2a4e37c58d83e115b54287c4f06ef --hash=sha256:b886d02a581b96704c9d1ffe55709e49b4d2d52709ccebc4be42db856e511278 --hash=sha256:c40ba2eb08b3f5de88152c2333c58cee7edcead0a2a0d60fcafa116b17117adc --hash=sha256:c55b20591ced744aa04e8c3e4b7543ea4d650b6c3c4b208c08a05b4010e8b442 --hash=sha256:c58a9622d5dbeb668f407f35f4e6bfac34bb9ecdcc81680c04d0258169747997 --hash=sha256:d44cb942af1693cced2604c33a9abcef6205601c445f6d0dc531d813af8a2f5a --hash=sha256:d907fddb39f923d011875452ff1eca29a9e7f21722b873e90db32e5d8ddff12e --hash=sha256:fd44fc75522f58612ec4a33958a7e5552562b7705b42ef1b4f8c0818e304a363"
}
},
- "orfs-pip_312_numpy": {
+ "orfs-pip_313_numpy": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "numpy==2.2.2 --hash=sha256:02935e2c3c0c6cbe9c7955a8efa8908dd4221d7755644c59d1bba28b94fd334f --hash=sha256:0349b025e15ea9d05c3d63f9657707a4e1d471128a3b1d876c095f328f8ff7f0 --hash=sha256:09d6a2032faf25e8d0cadde7fd6145118ac55d2740132c1d845f98721b5ebcfd --hash=sha256:0bc61b307655d1a7f9f4b043628b9f2b721e80839914ede634e3d485913e1fb2 --hash=sha256:0eec19f8af947a61e968d5429f0bd92fec46d92b0008d0a6685b40d6adf8a4f4 --hash=sha256:106397dbbb1896f99e044efc90360d098b3335060375c26aa89c0d8a97c5f648 --hash=sha256:128c41c085cab8a85dc29e66ed88c05613dccf6bc28b3866cd16050a2f5448be --hash=sha256:149d1113ac15005652e8d0d3f6fd599360e1a708a4f98e43c9c77834a28238cb --hash=sha256:159ff6ee4c4a36a23fe01b7c3d07bd8c14cc433d9720f977fcd52c13c0098160 --hash=sha256:22ea3bb552ade325530e72a0c557cdf2dea8914d3a5e1fecf58fa5dbcc6f43cd --hash=sha256:23ae9f0c2d889b7b2d88a3791f6c09e2ef827c2446f1c4a3e3e76328ee4afd9a --hash=sha256:250c16b277e3b809ac20d1f590716597481061b514223c7badb7a0f9993c7f84 --hash=sha256:2ec6c689c61df613b783aeb21f945c4cbe6c51c28cb70aae8430577ab39f163e --hash=sha256:2ffbb1acd69fdf8e89dd60ef6182ca90a743620957afb7066385a7bbe88dc748 --hash=sha256:3074634ea4d6df66be04f6728ee1d173cfded75d002c75fac79503a880bf3825 --hash=sha256:356ca982c188acbfa6af0d694284d8cf20e95b1c3d0aefa8929376fea9146f60 --hash=sha256:3fbe72d347fbc59f94124125e73fc4976a06927ebc503ec5afbfb35f193cd957 --hash=sha256:40c7ff5da22cd391944a28c6a9c638a5eef77fcf71d6e3a79e1d9d9e82752715 --hash=sha256:41184c416143defa34cc8eb9d070b0a5ba4f13a0fa96a709e20584638254b317 --hash=sha256:451e854cfae0febe723077bd0cf0a4302a5d84ff25f0bfece8f29206c7bed02e --hash=sha256:4525b88c11906d5ab1b0ec1f290996c0020dd318af8b49acaa46f198b1ffc283 --hash=sha256:463247edcee4a5537841d5350bc87fe8e92d7dd0e8c71c995d2c6eecb8208278 --hash=sha256:4dbd80e453bd34bd003b16bd802fac70ad76bd463f81f0c518d1245b1c55e3d9 --hash=sha256:57b4012e04cc12b78590a334907e01b3a85efb2107df2b8733ff1ed05fce71de --hash=sha256:5a8c863ceacae696aff37d1fd636121f1a512117652e5dfb86031c8d84836369 --hash=sha256:5acea83b801e98541619af398cc0109ff48016955cc0818f478ee9ef1c5c3dcb --hash=sha256:642199e98af1bd2b6aeb8ecf726972d238c9877b0f6e8221ee5ab945ec8a2189 --hash=sha256:64bd6e1762cd7f0986a740fee4dff927b9ec2c5e4d9a28d056eb17d332158014 --hash=sha256:6d9fc9d812c81e6168b6d405bf00b8d6739a7f72ef22a9214c4241e0dc70b323 --hash=sha256:7079129b64cb78bdc8d611d1fd7e8002c0a2565da6a47c4df8062349fee90e3e --hash=sha256:7dca87ca328f5ea7dafc907c5ec100d187911f94825f8700caac0b3f4c384b49 --hash=sha256:860fd59990c37c3ef913c3ae390b3929d005243acca1a86facb0773e2d8d9e50 --hash=sha256:8e6da5cffbbe571f93588f562ed130ea63ee206d12851b60819512dd3e1ba50d --hash=sha256:8ec0636d3f7d68520afc6ac2dc4b8341ddb725039de042faf0e311599f54eb37 --hash=sha256:9491100aba630910489c1d0158034e1c9a6546f0b1340f716d522dc103788e39 --hash=sha256:97b974d3ba0fb4612b77ed35d7627490e8e3dff56ab41454d9e8b23448940576 --hash=sha256:995f9e8181723852ca458e22de5d9b7d3ba4da3f11cc1cb113f093b271d7965a --hash=sha256:9dd47ff0cb2a656ad69c38da850df3454da88ee9a6fde0ba79acceee0e79daba --hash=sha256:9fad446ad0bc886855ddf5909cbf8cb5d0faa637aaa6277fb4b19ade134ab3c7 --hash=sha256:a972cec723e0563aa0823ee2ab1df0cb196ed0778f173b381c871a03719d4826 --hash=sha256:ac9bea18d6d58a995fac1b2cb4488e17eceeac413af014b1dd26170b766d8467 --hash=sha256:b0531f0b0e07643eb089df4c509d30d72c9ef40defa53e41363eca8a8cc61495 --hash=sha256:b208cfd4f5fe34e1535c08983a1a6803fdbc7a1e86cf13dd0c61de0b51a0aadc --hash=sha256:b3482cb7b3325faa5f6bc179649406058253d91ceda359c104dac0ad320e1391 --hash=sha256:b6fb9c32a91ec32a689ec6410def76443e3c750e7cfc3fb2206b985ffb2b85f0 --hash=sha256:b78ea78450fd96a498f50ee096f69c75379af5138f7881a51355ab0e11286c97 --hash=sha256:bd249bc894af67cbd8bad2c22e7cbcd46cf87ddfca1f1289d1e7e54868cc785c --hash=sha256:c7d1fd447e33ee20c1f33f2c8e6634211124a9aabde3c617687d8b739aa69eac --hash=sha256:d0bbe7dd86dca64854f4b6ce2ea5c60b51e36dfd597300057cf473d3615f2369 --hash=sha256:d6d6a0910c3b4368d89dde073e630882cdb266755565155bc33520283b2d9df8 --hash=sha256:da1eeb460ecce8d5b8608826595c777728cdf28ce7b5a5a8c8ac8d949beadcf2 --hash=sha256:e0c8854b09bc4de7b041148d8550d3bd712b5c21ff6a8ed308085f190235d7ff --hash=sha256:e0d4142eb40ca6f94539e4db929410f2a46052a0fe7a2c1c59f6179c39938d2a --hash=sha256:e9e82dcb3f2ebbc8cb5ce1102d5f1c5ed236bf8a11730fb45ba82e2841ec21df --hash=sha256:ed6906f61834d687738d25988ae117683705636936cc605be0bb208b23df4d8f"
}
},
- "orfs-pip_312_packaging": {
+ "orfs-pip_313_packaging": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "packaging==24.2 --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f"
}
},
- "orfs-pip_312_pillow": {
+ "orfs-pip_313_pillow": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "pillow==11.1.0 --hash=sha256:015c6e863faa4779251436db398ae75051469f7c903b043a48f078e437656f83 --hash=sha256:0a2f91f8a8b367e7a57c6e91cd25af510168091fb89ec5146003e424e1558a96 --hash=sha256:11633d58b6ee5733bde153a8dafd25e505ea3d32e261accd388827ee987baf65 --hash=sha256:2062ffb1d36544d42fcaa277b069c88b01bb7298f4efa06731a7fd6cc290b81a --hash=sha256:31eba6bbdd27dde97b0174ddf0297d7a9c3a507a8a1480e1e60ef914fe23d352 --hash=sha256:3362c6ca227e65c54bf71a5f88b3d4565ff1bcbc63ae72c34b07bbb1cc59a43f --hash=sha256:368da70808b36d73b4b390a8ffac11069f8a5c85f29eff1f1b01bcf3ef5b2a20 --hash=sha256:36ba10b9cb413e7c7dfa3e189aba252deee0602c86c309799da5a74009ac7a1c --hash=sha256:3764d53e09cdedd91bee65c2527815d315c6b90d7b8b79759cc48d7bf5d4f114 --hash=sha256:3a5fe20a7b66e8135d7fd617b13272626a28278d0e578c98720d9ba4b2439d49 --hash=sha256:3cdcdb0b896e981678eee140d882b70092dac83ac1cdf6b3a60e2216a73f2b91 --hash=sha256:4637b88343166249fe8aa94e7c4a62a180c4b3898283bb5d3d2fd5fe10d8e4e0 --hash=sha256:4db853948ce4e718f2fc775b75c37ba2efb6aaea41a1a5fc57f0af59eee774b2 --hash=sha256:4dd43a78897793f60766563969442020e90eb7847463eca901e41ba186a7d4a5 --hash=sha256:54251ef02a2309b5eec99d151ebf5c9904b77976c8abdcbce7891ed22df53884 --hash=sha256:54ce1c9a16a9561b6d6d8cb30089ab1e5eb66918cb47d457bd996ef34182922e --hash=sha256:593c5fd6be85da83656b93ffcccc2312d2d149d251e98588b14fbc288fd8909c --hash=sha256:5bb94705aea800051a743aa4874bb1397d4695fb0583ba5e425ee0328757f196 --hash=sha256:67cd427c68926108778a9005f2a04adbd5e67c442ed21d95389fe1d595458756 --hash=sha256:70ca5ef3b3b1c4a0812b5c63c57c23b63e53bc38e758b37a951e5bc466449861 --hash=sha256:73ddde795ee9b06257dac5ad42fcb07f3b9b813f8c1f7f870f402f4dc54b5269 --hash=sha256:758e9d4ef15d3560214cddbc97b8ef3ef86ce04d62ddac17ad39ba87e89bd3b1 --hash=sha256:7d33d2fae0e8b170b6a6c57400e077412240f6f5bb2a342cf1ee512a787942bb --hash=sha256:7fdadc077553621911f27ce206ffcbec7d3f8d7b50e0da39f10997e8e2bb7f6a --hash=sha256:8000376f139d4d38d6851eb149b321a52bb8893a88dae8ee7d95840431977081 --hash=sha256:837060a8599b8f5d402e97197d4924f05a2e0d68756998345c829c33186217b1 --hash=sha256:89dbdb3e6e9594d512780a5a1c42801879628b38e3efc7038094430844e271d8 --hash=sha256:8c730dc3a83e5ac137fbc92dfcfe1511ce3b2b5d7578315b63dbbb76f7f51d90 --hash=sha256:8e275ee4cb11c262bd108ab2081f750db2a1c0b8c12c1897f27b160c8bd57bbc --hash=sha256:9044b5e4f7083f209c4e35aa5dd54b1dd5b112b108648f5c902ad586d4f945c5 --hash=sha256:93a18841d09bcdd774dcdc308e4537e1f867b3dec059c131fde0327899734aa1 --hash=sha256:9409c080586d1f683df3f184f20e36fb647f2e0bc3988094d4fd8c9f4eb1b3b3 --hash=sha256:96f82000e12f23e4f29346e42702b6ed9a2f2fea34a740dd5ffffcc8c539eb35 --hash=sha256:9aa9aeddeed452b2f616ff5507459e7bab436916ccb10961c4a382cd3e03f47f --hash=sha256:9ee85f0696a17dd28fbcfceb59f9510aa71934b483d1f5601d1030c3c8304f3c --hash=sha256:a07dba04c5e22824816b2615ad7a7484432d7f540e6fa86af60d2de57b0fcee2 --hash=sha256:a3cd561ded2cf2bbae44d4605837221b987c216cff94f49dfeed63488bb228d2 --hash=sha256:a697cd8ba0383bba3d2d3ada02b34ed268cb548b369943cd349007730c92bddf --hash=sha256:a76da0a31da6fcae4210aa94fd779c65c75786bc9af06289cd1c184451ef7a65 --hash=sha256:a85b653980faad27e88b141348707ceeef8a1186f75ecc600c395dcac19f385b --hash=sha256:a8d65b38173085f24bc07f8b6c505cbb7418009fa1a1fcb111b1f4961814a442 --hash=sha256:aa8dd43daa836b9a8128dbe7d923423e5ad86f50a7a14dc688194b7be5c0dea2 --hash=sha256:ab8a209b8485d3db694fa97a896d96dd6533d63c22829043fd9de627060beade --hash=sha256:abc56501c3fd148d60659aae0af6ddc149660469082859fa7b066a298bde9482 --hash=sha256:ad5db5781c774ab9a9b2c4302bbf0c1014960a0a7be63278d13ae6fdf88126fe --hash=sha256:ae98e14432d458fc3de11a77ccb3ae65ddce70f730e7c76140653048c71bfcbc --hash=sha256:b20be51b37a75cc54c2c55def3fa2c65bb94ba859dde241cd0a4fd302de5ae0a --hash=sha256:b523466b1a31d0dcef7c5be1f20b942919b62fd6e9a9be199d035509cbefc0ec --hash=sha256:b5d658fbd9f0d6eea113aea286b21d3cd4d3fd978157cbf2447a6035916506d3 --hash=sha256:b6123aa4a59d75f06e9dd3dac5bf8bc9aa383121bb3dd9a7a612e05eabc9961a --hash=sha256:bd165131fd51697e22421d0e467997ad31621b74bfc0b75956608cb2906dda07 --hash=sha256:bf902d7413c82a1bfa08b06a070876132a5ae6b2388e2712aab3a7cbc02205c6 --hash=sha256:c12fc111ef090845de2bb15009372175d76ac99969bdf31e2ce9b42e4b8cd88f --hash=sha256:c1eec9d950b6fe688edee07138993e54ee4ae634c51443cfb7c1e7613322718e --hash=sha256:c640e5a06869c75994624551f45e5506e4256562ead981cce820d5ab39ae2192 --hash=sha256:cc1331b6d5a6e144aeb5e626f4375f5b7ae9934ba620c0ac6b3e43d5e683a0f0 --hash=sha256:cfd5cd998c2e36a862d0e27b2df63237e67273f2fc78f47445b14e73a810e7e6 --hash=sha256:d3d8da4a631471dfaf94c10c85f5277b1f8e42ac42bade1ac67da4b4a7359b73 --hash=sha256:d44ff19eea13ae4acdaaab0179fa68c0c6f2f45d66a4d8ec1eda7d6cecbcc15f --hash=sha256:dd0052e9db3474df30433f83a71b9b23bd9e4ef1de13d92df21a52c0303b8ab6 --hash=sha256:dd0e081319328928531df7a0e63621caf67652c8464303fd102141b785ef9547 --hash=sha256:dda60aa465b861324e65a78c9f5cf0f4bc713e4309f83bc387be158b077963d9 --hash=sha256:e06695e0326d05b06833b40b7ef477e475d0b1ba3a6d27da1bb48c23209bf457 --hash=sha256:e1abe69aca89514737465752b4bcaf8016de61b3be1397a8fc260ba33321b3a8 --hash=sha256:e267b0ed063341f3e60acd25c05200df4193e15a4a5807075cd71225a2386e26 --hash=sha256:e5449ca63da169a2e6068dd0e2fcc8d91f9558aba89ff6d02121ca8ab11e79e5 --hash=sha256:e63e4e5081de46517099dc30abe418122f54531a6ae2ebc8680bcd7096860eab --hash=sha256:f189805c8be5ca5add39e6f899e6ce2ed824e65fb45f3c28cb2841911da19070 --hash=sha256:f7955ecf5609dee9442cbface754f2c6e541d9e6eda87fad7f7a989b0bdb9d71 --hash=sha256:f86d3a7a9af5d826744fabf4afd15b9dfef44fe69a98541f666f66fbb8d3fef9 --hash=sha256:fbd43429d0d7ed6533b25fc993861b8fd512c42d04514a0dd6337fb3ccf22761"
}
},
- "orfs-pip_312_pyparsing": {
+ "orfs-pip_313_pyparsing": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "pyparsing==3.2.1 --hash=sha256:506ff4f4386c4cec0590ec19e6302d3aedb992fdc02c761e90416f158dacf8e1 --hash=sha256:61980854fd66de3a90028d679a954d5f2623e83144b5afe5ee86f43d762e5f0a"
}
},
- "orfs-pip_312_python_dateutil": {
+ "orfs-pip_313_python_dateutil": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "python-dateutil==2.9.0.post0 --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427"
}
},
- "orfs-pip_312_pyyaml": {
+ "orfs-pip_313_pyyaml": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "pyyaml==6.0.2 --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a --hash=sha256:29717114e51c84ddfba879543fb232a6ed60086602313ca38cce623c1d62cfbf --hash=sha256:2e99c6826ffa974fe6e27cdb5ed0021786b03fc98e5ee3c5bfe1fd5015f42b99 --hash=sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8 --hash=sha256:3ad2a3decf9aaba3d29c8f537ac4b243e36bef957511b4766cb0057d32b0be85 --hash=sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19 --hash=sha256:41e4e3953a79407c794916fa277a82531dd93aad34e29c2a514c2c0c5fe971cc --hash=sha256:43fa96a3ca0d6b1812e01ced1044a003533c47f6ee8aca31724f78e93ccc089a --hash=sha256:50187695423ffe49e2deacb8cd10510bc361faac997de9efef88badc3bb9e2d1 --hash=sha256:5ac9328ec4831237bec75defaf839f7d4564be1e6b25ac710bd1a96321cc8317 --hash=sha256:5d225db5a45f21e78dd9358e58a98702a0302f2659a3c6cd320564b75b86f47c --hash=sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631 --hash=sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d --hash=sha256:68ccc6023a3400877818152ad9a1033e3db8625d899c72eacb5a668902e4d652 --hash=sha256:70b189594dbe54f75ab3a1acec5f1e3faa7e8cf2f1e08d9b561cb41b845f69d5 --hash=sha256:797b4f722ffa07cc8d62053e4cff1486fa6dc094105d13fea7b1de7d8bf71c9e --hash=sha256:7c36280e6fb8385e520936c3cb3b8042851904eba0e58d277dca80a5cfed590b --hash=sha256:7e7401d0de89a9a855c839bc697c079a4af81cf878373abd7dc625847d25cbd8 --hash=sha256:80bab7bfc629882493af4aa31a4cfa43a4c57c83813253626916b8c7ada83476 --hash=sha256:82d09873e40955485746739bcb8b4586983670466c23382c19cffecbf1fd8706 --hash=sha256:8388ee1976c416731879ac16da0aff3f63b286ffdd57cdeb95f3f2e085687563 --hash=sha256:8824b5a04a04a047e72eea5cec3bc266db09e35de6bdfe34c9436ac5ee27d237 --hash=sha256:8b9c7197f7cb2738065c481a0461e50ad02f18c78cd75775628afb4d7137fb3b --hash=sha256:9056c1ecd25795207ad294bcf39f2db3d845767be0ea6e6a34d856f006006083 --hash=sha256:936d68689298c36b53b29f23c6dbb74de12b4ac12ca6cfe0e047bedceea56180 --hash=sha256:9b22676e8097e9e22e36d6b7bda33190d0d400f345f23d4065d48f4ca7ae0425 --hash=sha256:a4d3091415f010369ae4ed1fc6b79def9416358877534caf6a0fdd2146c87a3e --hash=sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f --hash=sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725 --hash=sha256:bc2fa7c6b47d6bc618dd7fb02ef6fdedb1090ec036abab80d4681424b84c1183 --hash=sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab --hash=sha256:cc1c1159b3d456576af7a3e4d1ba7e6924cb39de8f67111c735f6fc832082774 --hash=sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725 --hash=sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e --hash=sha256:d7fded462629cfa4b685c5416b949ebad6cec74af5e2d42905d41e257e0869f5 --hash=sha256:d84a1718ee396f54f3a086ea0a66d8e552b2ab2017ef8b420e92edbc841c352d --hash=sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290 --hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4"
}
},
- "orfs-pip_312_six": {
+ "orfs-pip_313_six": {
"bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl",
"ruleClassName": "whl_library",
"attributes": {
"dep_template": "@orfs-pip//{name}:{target}",
- "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python",
- "repo": "orfs-pip_312",
+ "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python",
+ "repo": "orfs-pip_313",
"requirement": "six==1.17.0 --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81"
}
},
@@ -3813,11 +3843,14 @@
"matplotlib": "{\"bazel-orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}",
"numpy": "{\"bazel-orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}",
"packaging": "{\"bazel-orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}",
+ "pandas": "{\"bazel-orfs-pip_313_pandas\":[{\"version\":\"3.13\"}]}",
"pillow": "{\"bazel-orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}",
"pyparsing": "{\"bazel-orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}",
"python_dateutil": "{\"bazel-orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}",
+ "pytz": "{\"bazel-orfs-pip_313_pytz\":[{\"version\":\"3.13\"}]}",
"pyyaml": "{\"bazel-orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}",
- "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}"
+ "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}",
+ "tzdata": "{\"bazel-orfs-pip_313_tzdata\":[{\"version\":\"3.13\"}]}"
},
"packages": [
"contourpy",
@@ -3827,11 +3860,14 @@
"matplotlib",
"numpy",
"packaging",
+ "pandas",
"pillow",
"pyparsing",
"python_dateutil",
+ "pytz",
"pyyaml",
- "six"
+ "six",
+ "tzdata"
],
"groups": {}
}
@@ -3843,18 +3879,18 @@
"repo_name": "orfs-pip",
"extra_hub_aliases": {},
"whl_map": {
- "contourpy": "{\"orfs-pip_312_contourpy\":[{\"version\":\"3.12\"}]}",
- "cycler": "{\"orfs-pip_312_cycler\":[{\"version\":\"3.12\"}]}",
- "fonttools": "{\"orfs-pip_312_fonttools\":[{\"version\":\"3.12\"}]}",
- "kiwisolver": "{\"orfs-pip_312_kiwisolver\":[{\"version\":\"3.12\"}]}",
- "matplotlib": "{\"orfs-pip_312_matplotlib\":[{\"version\":\"3.12\"}]}",
- "numpy": "{\"orfs-pip_312_numpy\":[{\"version\":\"3.12\"}]}",
- "packaging": "{\"orfs-pip_312_packaging\":[{\"version\":\"3.12\"}]}",
- "pillow": "{\"orfs-pip_312_pillow\":[{\"version\":\"3.12\"}]}",
- "pyparsing": "{\"orfs-pip_312_pyparsing\":[{\"version\":\"3.12\"}]}",
- "python_dateutil": "{\"orfs-pip_312_python_dateutil\":[{\"version\":\"3.12\"}]}",
- "pyyaml": "{\"orfs-pip_312_pyyaml\":[{\"version\":\"3.12\"}]}",
- "six": "{\"orfs-pip_312_six\":[{\"version\":\"3.12\"}]}"
+ "contourpy": "{\"orfs-pip_313_contourpy\":[{\"version\":\"3.13\"}]}",
+ "cycler": "{\"orfs-pip_313_cycler\":[{\"version\":\"3.13\"}]}",
+ "fonttools": "{\"orfs-pip_313_fonttools\":[{\"version\":\"3.13\"}]}",
+ "kiwisolver": "{\"orfs-pip_313_kiwisolver\":[{\"version\":\"3.13\"}]}",
+ "matplotlib": "{\"orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}",
+ "numpy": "{\"orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}",
+ "packaging": "{\"orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}",
+ "pillow": "{\"orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}",
+ "pyparsing": "{\"orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}",
+ "python_dateutil": "{\"orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}",
+ "pyyaml": "{\"orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}",
+ "six": "{\"orfs-pip_313_six\":[{\"version\":\"3.13\"}]}"
},
"packages": [
"contourpy",
diff --git a/README.md b/README.md
index 56d3a2a1f7..515be0b597 100644
--- a/README.md
+++ b/README.md
@@ -46,6 +46,14 @@ timeline
## Tool Installation
+There are different ways to install and develop OpenROAD and ORFS, which is the best fit depends use-case, experience and personal taste.
+
+### Use Bazel, avoid installing anything at all and adapt the flow to your needs in your own repository
+
+[bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) provides a seamless, reproducible way to manage dependencies and adapt the flow without requiring manual installations(no Docker images, sudo bash scripts, etc.)
+
+By leveraging [Bazel](https://bazel.build/)'s robust build system, all dependencies are automatically resolved, versioned, and built in a consistent environment. This eliminates setup complexity, ensures fast incremental builds, and allows for easy customization of the flow, making it an efficient choice for both [beginners](https://github.com/Pinata-Consulting/RegFileStudy) and [advanced](https://github.com/The-OpenROAD-Project/megaboom) users.
+
### Docker Based Installation
To ease dependency installation issues, ORFS uses docker images.
diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
index aae3928c65..0478d053c3 100644
--- a/docs/user/FlowVariables.md
+++ b/docs/user/FlowVariables.md
@@ -1,10 +1,48 @@
-# Environment Variables for the OpenROAD Flow Scripts
+# Variables for the OpenROAD Flow Scripts
-
-Environment variables are used in the OpenROAD flow to define various
+Variables are used in the OpenROAD flow to define various
platform, design and tool specific variables to allow finer control and
-user overrides at various flow stages. These are defined in the
-`config.mk` file located in the platform and design specific directories.
+user overrides at various flow stages.
+
+These are normally defined in the `config.mk` file located in the platform and design-specific directories, but can also be defined on the command line or via environment variables. For example:
+
+- Command line: `make PLACE_DENSITY=0.5`
+- Environment variable: `export PLACE_DENSITY=0.5`
+
+This works provided that `config.mk` has defined it as a default value using the `export PLACE_DENSITY?=0.4` syntax.
+
+The actual value used is determined by the priority rules set by `make`:
+
+1. **Makefile Definitions**: Variables defined in the `Makefile` or included files are used when they are defined using the no-override `=` operator, `export PLACE_DENSITY=0.4` syntax. The priority within the included files is the `DESIGN_CONFIG` file, then `Makefile` definitions and finally platform(PDK) defined variables.
+2. **Command Line**: Variables defined on the command line take the highest priority in overriding defaults.
+3. **Environment Variables**: Variables exported in the shell environment are used if not overridden by the command line.
+4. **Default Values**: Variables defined with the `?=` operator in the `Makefile` are used only if the variable is not already defined elsewhere.
+
+## Effects of variables
+
+The variables for ORFS are not fully independent and can interact in complex ways. Small changes to a combination of variables can have large consequences, such as on macro placement, which can lead to vastly different quality of results.
+
+Due to the large number of variables, some of which are continuous and require long runtimes, other discrete, it is not feasible to perform an exhaustive end-to-end search for the best combination of variables.
+
+Instead, the following approaches are used to determine reasonable values, up to a point of diminishing returns:
+
+- **Experience**: Leveraging domain expertise to set initial values.
+- **AI**: Using machine learning techniques to explore variable combinations.
+- **Parameter Sweeps**: Testing a smaller subset of variables to identify optimal ranges.
+
+These values are then set in configuration files and kept under source control alongside the RTL input.
+
+## Types of variables
+
+Variables values are set in ORFS scripts or `config.mk` files and are kept in source control together with configuration files and RTL.
+
+It is an ongoing effort to move variables upwards in the categories below.
+
+| Category | Definition | User Involvement | Examples | Automation Potential | Notes |
+|--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------|
+| **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. |
+| **Easy** | Requires input, but easy to tune using reports or visuals. | Moderate – copy/edit from reports | `PLACE_DENSITY` | **Medium–High** | Smooth response curves, intuitive tuning. |
+| **Complex** | Small changes in values may result in large effects. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier "good values". | **Low–Medium** | Needs scripted sweeps and statistical evaluation. |
## Platform
@@ -20,7 +58,7 @@ variable. For OpenROAD Flow Scripts we have the following public platforms:
- `nangate45`
- `asap7`
-## Platform Specific Environment Variables
+## Platform Specific Variables
The table below lists the complete set of variables used in each of the
@@ -50,160 +88,161 @@ configuration file.
## Variables in alphabetic order
-| Variable | Description | Default | Deprecated |
-| --- | --- | --- | --- |
-| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| |
-| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | |
-| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | |
-| ABC_LOAD_IN_FF| During synthesis set_load value used.| | |
-| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | |
-| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | |
-| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | |
-| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | |
-| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | |
-| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | |
-| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | |
-| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | |
-| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | |
-| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| |
-| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| |
-| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | |
-| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | |
-| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | |
-| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | |
-| CORE_UTILIZATION| The core utilization percentage (0-100).| | |
-| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | |
-| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | |
-| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | |
-| CTS_BUF_LIST| List of cells used to construct the clock tree. Overrides buffer inference.| | |
-| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| |
-| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| |
-| CTS_LIB_NAME| Name of the Liberty library to use in selecting the clock buffers.| | |
-| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | |
-| DESIGN_NAME| The name of the top-level module of the design.| | |
-| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | |
-| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| |
-| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | |
-| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| |
-| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | |
-| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | |
-| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | |
-| DONT_USE_LIBS| Set liberty files as `dont_use`.| | |
-| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| |
-| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| |
-| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| |
-| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | |
-| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | |
-| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | |
-| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | |
-| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| |
-| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | |
-| GDS_FILES| Path to platform GDS files.| | |
-| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| |
-| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | |
-| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| |
-| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | |
-| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| |
-| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| |
-| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| |
-| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| |
-| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | |
-| IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | |
-| IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | |
-| IR_DROP_LAYER| Default metal layer to report IR drop.| | |
-| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | |
-| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | |
-| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | |
-| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | |
-| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | |
-| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | |
-| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | |
-| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | |
-| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | |
-| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | |
-| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | |
-| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | |
-| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| |
-| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | |
-| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | |
-| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | |
-| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | |
-| PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | |
-| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | |
-| PLACE_PINS_ARGS| Arguments to place_pins| | |
-| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | |
-| PLATFORM| Specifies process design kit or technology node to be used.| | |
-| PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | |
-| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | |
-| PROCESS| Technology node or process in use.| | |
-| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | |
-| RCX_RULES| RC Extraction rules file path.| | |
-| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| |
-| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | yes|
-| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | |
-| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | |
-| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| |
-| RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| 0| |
-| RESYNTH_TIMING_RECOVER| Enable re-synthesis for timing optimization.| 0| |
-| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| |
-| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| |
-| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | |
-| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| |
-| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| |
-| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| |
-| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| |
-| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| |
-| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| |
-| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | |
-| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| |
-| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | |
-| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| |
-| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | |
-| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | |
-| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| |
-| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| |
-| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | |
-| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| |
-| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| |
-| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| | |
-| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run| |
-| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | |
-| SC_LEF| Path to technology standard cell LEF file.| | |
-| SDC_FILE| The path to design constraint (SDC) file.| | |
-| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
-| SEAL_GDS| Seal macro to place around the design.| | |
-| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| | |
-| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| |
-| SET_RC_TCL| Metal & Via RC definition file path.| | |
-| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | |
-| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | |
-| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| |
-| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | |
-| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | |
-| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | |
-| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | |
-| SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| |
-| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | |
-| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
-| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | |
-| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
-| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | |
-| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
-| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| |
-| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
-| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | |
-| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
-| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | |
-| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | |
-| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | |
-| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | |
-| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| |
-| USE_FILL| Whether to perform metal density filling.| 0| |
-| VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | |
-| VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | |
-| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | |
-| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | |
-| YOSYS_FLAGS| Flags to pass to yosys.| -v 3| |
+| Variable | Description | Default |
+| --- | --- | --- |
+| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0|
+| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| |
+| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| |
+| ABC_LOAD_IN_FF| During synthesis set_load value used.| |
+| ABSTRACT_SOURCE| Which .odb file to use to create abstract| |
+| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| |
+| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| |
+| ADDITIONAL_GDS| Hardened macro GDS files listed here.| |
+| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| |
+| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| |
+| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| |
+| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| |
+| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| |
+| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0|
+| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0|
+| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| |
+| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
+| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| 1.0|
+| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| 1.0|
+| CORE_UTILIZATION| The core utilization percentage (0-100).| |
+| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| |
+| CTS_ARGS| Override `clock_tree_synthesis` arguments.| |
+| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| |
+| CTS_BUF_LIST| List of cells used to construct the clock tree. Overrides buffer inference.| |
+| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20|
+| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50|
+| CTS_LIB_NAME| Name of the Liberty library to use in selecting the clock buffers.| |
+| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| |
+| DESIGN_NAME| The name of the top-level module of the design.| |
+| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| |
+| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0|
+| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| |
+| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64|
+| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| |
+| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
+| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
+| DONT_USE_LIBS| Set liberty files as `dont_use`.| |
+| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1|
+| EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| |
+| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1|
+| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0|
+| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| |
+| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| |
+| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| |
+| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| |
+| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base|
+| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| |
+| GDS_FILES| Path to platform GDS files.| |
+| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0|
+| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| |
+| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose|
+| GND_NETS_VOLTAGES| Used for IR Drop calculation.| |
+| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1|
+| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1|
+| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1|
+| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0|
+| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| |
+| IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| |
+| IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| |
+| IR_DROP_LAYER| Default metal layer to report IR drop.| |
+| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| |
+| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| |
+| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| |
+| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| |
+| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| |
+| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| |
+| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| |
+| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| |
+| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| |
+| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| |
+| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| |
+| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| |
+| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0|
+| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| |
+| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| |
+| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| |
+| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| |
+| PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| |
+| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| |
+| PLACE_PINS_ARGS| Arguments to place_pins| |
+| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| |
+| PLATFORM| Specifies process design kit or technology node to be used.| |
+| PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| |
+| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| |
+| PROCESS| Technology node or process in use.| |
+| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| |
+| RCX_RULES| RC Extraction rules file path.| |
+| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0|
+| REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| |
+| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| |
+| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| |
+| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1|
+| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5|
+| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1|
+| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| |
+| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0|
+| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05|
+| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0|
+| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0|
+| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0|
+| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0|
+| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| |
+| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2|
+| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| |
+| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33|
+| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| |
+| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| |
+| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0|
+| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0|
+| RTLMP_RPT_DIR| Path to the directory where reports are saved.| |
+| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50|
+| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0|
+| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| |
+| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run|
+| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| |
+| SC_LEF| Path to technology standard cell LEF file.| |
+| SDC_FILE| The path to design constraint (SDC) file.| |
+| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| |
+| SEAL_GDS| Seal macro to place around the design.| |
+| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| |
+| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0|
+| SET_RC_TCL| Metal & Via RC definition file path.| |
+| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| |
+| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| |
+| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0|
+| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| |
+| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| |
+| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| |
+| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
+| SYNTH_ARGS| Optional synthesis variables for yosys.| |
+| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| |
+| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| |
+| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| |
+| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0|
+| SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .|
+| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| |
+| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096|
+| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0|
+| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
+| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
+| TAPCELL_TCL| Path to Endcap and Welltie cells file.| |
+| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| |
+| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| |
+| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| |
+| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| |
+| TIE_SEPARATION| Distance separating tie high/low instances from the load.| |
+| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
+| USE_FILL| Whether to perform metal density filling.| 0|
+| VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
+| VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| |
+| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| |
+| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| |
+| YOSYS_FLAGS| Flags to pass to yosys.| -v 3|
## synth variables
- [ABC_AREA](#ABC_AREA)
@@ -258,8 +297,6 @@ configuration file.
- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
- [PLACE_SITE](#PLACE_SITE)
- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
-- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER)
-- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
- [RTLMP_AREA_WT](#RTLMP_AREA_WT)
- [RTLMP_ARGS](#RTLMP_ARGS)
- [RTLMP_BOUNDARY_WT](#RTLMP_BOUNDARY_WT)
@@ -292,6 +329,7 @@ configuration file.
- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
- [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)
+- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO)
- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
- [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN)
- [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN)
@@ -308,6 +346,7 @@ configuration file.
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
+- [TIE_SEPARATION](#TIE_SEPARATION)
## cts variables
@@ -430,6 +469,7 @@ configuration file.
- [SET_RC_TCL](#SET_RC_TCL)
- [SLEW_MARGIN](#SLEW_MARGIN)
- [SYNTH_ARGS](#SYNTH_ARGS)
+- [SYNTH_HIER_SEPARATOR](#SYNTH_HIER_SEPARATOR)
- [TAP_CELL_NAME](#TAP_CELL_NAME)
- [TECH_LEF](#TECH_LEF)
- [USE_FILL](#USE_FILL)
diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh
index 769758230b..abd9993c8b 100755
--- a/etc/DependencyInstaller.sh
+++ b/etc/DependencyInstaller.sh
@@ -170,7 +170,7 @@ _installUbuntuPackages() {
fi
else
if [[ $1 == 20.04 ]]; then
- klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135
+ klayoutChecksum=f78d41edf5bcfa5f1990bde1a9307e9e
else
klayoutChecksum=54748a49e1ab53e14cf5bf95feb2f25a
fi
diff --git a/flow/Makefile b/flow/Makefile
index ff50e84654..c96bf8f3c6 100644
--- a/flow/Makefile
+++ b/flow/Makefile
@@ -146,7 +146,7 @@ SHELL := /usr/bin/env bash
# location
# - default is current install / clone directory
ifeq ($(origin FLOW_HOME), undefined)
-FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
+ FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
endif
export FLOW_HOME
@@ -184,17 +184,9 @@ $(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKN
.PHONY: versions.txt
versions.txt:
mkdir -p $(OBJECTS_DIR)
- @if [ -z "$(YOSYS_EXE)" ]; then \
- echo >> $(OBJECTS_DIR)/$@ "yosys not installed"; \
- else \
- $(YOSYS_EXE) -V > $(OBJECTS_DIR)/$@; \
- fi
- @echo openroad `$(OPENROAD_EXE) -version` >> $(OBJECTS_DIR)/$@
- @if [ -z "$(KLAYOUT_CMD)" ]; then \
- echo >> $(OBJECTS_DIR)/$@ "klayout not installed"; \
- else \
- $(KLAYOUT_CMD) -zz -v >> $(OBJECTS_DIR)/$@; \
- fi
+ @echo "yosys $(if $(YOSYS_EXE),$(shell $(YOSYS_EXE) -V 2>&1),not available)" > $(OBJECTS_DIR)/$@
+ @echo "openroad $(if $(OPENROAD_EXE),$(shell $(OPENROAD_EXE) -version 2>&1),not available)" >> $(OBJECTS_DIR)/$@
+ @echo "klayout $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -zz -v 2>&1),not available)" >> $(OBJECTS_DIR)/$@
# Pre-process libraries
# ==============================================================================
@@ -204,10 +196,10 @@ versions.txt:
.SECONDEXPANSION:
$(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
@mkdir -p $(OBJECTS_DIR)/lib
- $(UTILS_DIR)/preprocessLib.py -i $^ -o $@
+ $(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@
$(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS)
- $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
+ $(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
# Pre-process KLayout tech
# ==============================================================================
@@ -271,9 +263,9 @@ do-synth-report:
.PHONY: memory
memory:
if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \
- python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \
+ $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \
fi
- python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json
+ $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json
# ==============================================================================
@@ -549,7 +541,8 @@ clean_cts:
route: $(RESULTS_DIR)/5_route.odb \
$(RESULTS_DIR)/5_route.sdc
-.PHONY: grt
+.PHONY: grt globalroute
+globalroute: grt
grt: $(RESULTS_DIR)/5_1_grt.odb
# ==============================================================================
@@ -619,12 +612,12 @@ finish: $(LOG_DIR)/6_report.log \
.PHONY: elapsed
elapsed:
- -@$(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR)
+ -@$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR)
# Useful when working with macros, see elapsed time for all macros in platform
.PHONY: elapsed-all
elapsed-all:
- @$(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d)
+ @$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d)
$(eval $(call do-step,6_1_fill,$(RESULTS_DIR)/5_route.odb $(RESULTS_DIR)/5_route.sdc $(FILL_CONFIG),density_fill))
diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc
index 15c31e02f8..8256fd752b 100644
--- a/flow/designs/asap7/aes-block/constraint.sdc
+++ b/flow/designs/asap7/aes-block/constraint.sdc
@@ -1,4 +1,4 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 475
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json
index 817f066d5b..69341b0032 100644
--- a/flow/designs/asap7/aes-block/rules-base.json
+++ b/flow/designs/asap7/aes-block/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 2293.17,
+ "value": 2131.37,
"compare": "<="
},
"constraints__clocks__count": {
@@ -24,7 +24,7 @@
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1244,
+ "value": 1078,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 77091,
+ "value": 75984,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -68.19,
+ "value": -152.45,
"compare": ">="
},
"finish__design__instance__area": {
diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc
index e45d9100bd..f5bce962e5 100644
--- a/flow/designs/asap7/aes-mbff/constraint.sdc
+++ b/flow/designs/asap7/aes-mbff/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 400
+set clk_period 400
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json
index a55c9a0b72..5b87e6a78e 100644
--- a/flow/designs/asap7/aes-mbff/rules-base.json
+++ b/flow/designs/asap7/aes-mbff/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 1972.31,
+ "value": 1928.39,
"compare": "<="
},
"constraints__clocks__count": {
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 2273,
+ "value": 2214,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 19686,
+ "value": 19594,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 1712,
+ "value": 1704,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1712,
+ "value": 1704,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 89339,
+ "value": 76679,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -68.71,
+ "value": -42.46,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 2359,
+ "value": 2272,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 856,
+ "value": 852,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -21.4,
+ "value": -15.57,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc
index e45d9100bd..f5bce962e5 100644
--- a/flow/designs/asap7/aes/constraint.sdc
+++ b/flow/designs/asap7/aes/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 400
+set clk_period 400
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes/rules-base.json b/flow/designs/asap7/aes/rules-base.json
index 47f49f188b..6038bda668 100644
--- a/flow/designs/asap7/aes/rules-base.json
+++ b/flow/designs/asap7/aes/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 1972.31,
+ "value": 1928.39,
"compare": "<="
},
"constraints__clocks__count": {
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 2273,
+ "value": 2214,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 19686,
+ "value": 19594,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 1712,
+ "value": 1704,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1712,
+ "value": 1704,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 86627,
+ "value": 74787,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -70.11,
+ "value": -34.79,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 2350,
+ "value": 2278,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 856,
+ "value": 852,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -19.6,
+ "value": -13.72,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc
index e45d9100bd..f5bce962e5 100644
--- a/flow/designs/asap7/aes_lvt/constraint.sdc
+++ b/flow/designs/asap7/aes_lvt/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 400
+set clk_period 400
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json
index 051ab64450..2b534e1efd 100644
--- a/flow/designs/asap7/aes_lvt/rules-base.json
+++ b/flow/designs/asap7/aes_lvt/rules-base.json
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 77902,
+ "value": 72549,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -29.62,
+ "value": -16.32,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 2142,
+ "value": 2103,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -12.43,
+ "value": -10.0,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/cva6/autotuner.json b/flow/designs/asap7/cva6/autotuner.json
new file mode 100644
index 0000000000..a7315e9578
--- /dev/null
+++ b/flow/designs/asap7/cva6/autotuner.json
@@ -0,0 +1,43 @@
+{
+ "_SDC_FILE_PATH": "constraint.sdc",
+ "_SDC_CLK_PERIOD": {
+ "type": "float",
+ "minmax": [
+ 1000,
+ 1300
+ ],
+ "step": 0
+ },
+ "CORE_UTILIZATION": {
+ "type": "int",
+ "minmax": [
+ 65,
+ 75
+ ],
+ "step": 1
+ },
+ "CORE_MARGIN": {
+ "type": "float",
+ "minmax": [
+ 1.5,
+ 2
+ ],
+ "step": 1
+ },
+ "CTS_CLUSTER_SIZE": {
+ "type": "int",
+ "minmax": [
+ 40,
+ 60
+ ],
+ "step": 1
+ },
+ "CTS_CLUSTER_DIAMETER": {
+ "type": "int",
+ "minmax": [
+ 15,
+ 25
+ ],
+ "step": 1
+ }
+}
diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk
index 255fb80ebf..45b0278e17 100644
--- a/flow/designs/asap7/cva6/config.mk
+++ b/flow/designs/asap7/cva6/config.mk
@@ -65,7 +65,10 @@ export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/
$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
- $(PLATFORM_DIR)/verilog/fakeram7_256x256.sv
+ $(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \
+ $(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \
+ $(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \
+ $(PLATFORM_DIR)/verilog/fakeram7_64x25.sv
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
@@ -73,16 +76,22 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include
export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
-export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x256.lef
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \
+ $(PLATFORM_DIR)/lef/fakeram7_128x64.lef \
+ $(PLATFORM_DIR)/lef/fakeram7_64x28.lef \
+ $(PLATFORM_DIR)/lef/fakeram7_64x25.lef
-export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib
+export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \
+ $(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \
+ $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \
+ $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
-export CORE_UTILIZATION = 40
+export CORE_UTILIZATION = 70
export CORE_MARGIN = 2
-export MACRO_HALO = 5
-export PLACE_DENSITY = 0.50
+export MACRO_PLACE_HALO = 3 3
+export PLACE_DENSITY = 0.73
# a smoketest for this option, there are a
# few last gasp iterations
@@ -92,3 +101,7 @@ export SKIP_LAST_GASP ?= 1
export SYNTH_MINIMUM_KEEP_SIZE ?= 40000
export SYNTH_HDL_FRONTEND = slang
+
+export ASAP7_USE_VT = RVT LVT SLVT
+
+export CTS_LIB_NAME = asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120
diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc
index 3c9064541c..d0f4fbb0d9 100644
--- a/flow/designs/asap7/cva6/constraint.sdc
+++ b/flow/designs/asap7/cva6/constraint.sdc
@@ -3,7 +3,7 @@
set clk_name main_clk
set clk_port clk_i
set clk_ports_list [list $clk_port]
-set clk_period 1300
+set clk_period 1200
set input_delay 0.46
set output_delay 0.11
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
diff --git a/flow/designs/asap7/cva6/rules-base.json b/flow/designs/asap7/cva6/rules-base.json
index 7096cba6f1..203bb993c4 100644
--- a/flow/designs/asap7/cva6/rules-base.json
+++ b/flow/designs/asap7/cva6/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 40631.65,
+ "value": 19725.15,
"compare": "<="
},
"constraints__clocks__count": {
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 45043,
+ "value": 20690,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 163049,
+ "value": 136421,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 14178,
+ "value": 11863,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 14178,
+ "value": 11863,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1884562,
+ "value": 1074578,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -216.36,
+ "value": -139.89,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 45315,
+ "value": 20850,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 7089,
+ "value": 5931,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 101,
+ "value": 100,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -20.3,
+ "value": -10.0,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc
index 71e846bd4a..43759e0718 100644
--- a/flow/designs/asap7/ethmac/constraint.sdc
+++ b/flow/designs/asap7/ethmac/constraint.sdc
@@ -4,7 +4,7 @@ set clk_io_pct 0.2
set clk_port [get_ports $top_clk_name]
create_clock -name $top_clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
set tx_clk_name mtx_clk_pad_i
@@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name]
set tx_clk_period 300
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
-set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
+set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
set rx_clk_name mrx_clk_pad_i
@@ -20,12 +20,12 @@ set rx_clk_port [get_ports $rx_clk_name]
set rx_clk_period 300
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
-set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
+set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
set_clock_groups -name core_clock -logically_exclusive \
- -group [get_clocks $top_clk_name] \
- -group [get_clocks $tx_clk_name] \
- -group [get_clocks $rx_clk_name]
+ -group [get_clocks $top_clk_name] \
+ -group [get_clocks $tx_clk_name] \
+ -group [get_clocks $rx_clk_name]
set_max_fanout 10 [current_design]
diff --git a/flow/designs/asap7/ethmac/rules-base.json b/flow/designs/asap7/ethmac/rules-base.json
index ad4a2c2eca..c6e93e2063 100644
--- a/flow/designs/asap7/ethmac/rules-base.json
+++ b/flow/designs/asap7/ethmac/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 9662,
+ "value": 9343,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 71326,
+ "value": 71068,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 6202,
+ "value": 6180,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 6202,
+ "value": 6180,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 559393,
+ "value": 232938,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -187.76,
+ "value": -144.87,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 10048,
+ "value": 9507,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 3101,
+ "value": 3090,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -44.05,
+ "value": -42.0,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc
index c9a876f18f..6d59823cb6 100644
--- a/flow/designs/asap7/ethmac_lvt/constraint.sdc
+++ b/flow/designs/asap7/ethmac_lvt/constraint.sdc
@@ -4,7 +4,7 @@ set clk_io_pct 0.2
set clk_port [get_ports $top_clk_name]
create_clock -name $top_clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
set tx_clk_name mtx_clk_pad_i
@@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name]
set tx_clk_period 300
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
-set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
+set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
set rx_clk_name mrx_clk_pad_i
@@ -20,10 +20,10 @@ set rx_clk_port [get_ports $rx_clk_name]
set rx_clk_period 300
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
-set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
+set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
set_clock_groups -name core_clock -logically_exclusive \
- -group [get_clocks $top_clk_name] \
- -group [get_clocks $tx_clk_name] \
- -group [get_clocks $rx_clk_name]
+ -group [get_clocks $top_clk_name] \
+ -group [get_clocks $tx_clk_name] \
+ -group [get_clocks $rx_clk_name]
diff --git a/flow/designs/asap7/ethmac_lvt/rules-base.json b/flow/designs/asap7/ethmac_lvt/rules-base.json
index e6752b88b5..36f0d0a851 100644
--- a/flow/designs/asap7/ethmac_lvt/rules-base.json
+++ b/flow/designs/asap7/ethmac_lvt/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 9583,
+ "value": 8660,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 69566,
+ "value": 66074,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 6049,
+ "value": 5746,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 6049,
+ "value": 5746,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 653875,
+ "value": 250591,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -225.06,
+ "value": -55.18,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 9943,
+ "value": 8806,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 3025,
+ "value": 2873,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -22.89,
+ "value": -22.5,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json
index 8b4b672953..3b2e302854 100644
--- a/flow/designs/asap7/gcd-ccs/rules-base.json
+++ b/flow/designs/asap7/gcd-ccs/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 543,
+ "value": 540,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1357,
+ "value": 1224,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -96.02,
+ "value": -94.0,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 57,
+ "value": 56,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 43,
+ "value": 24,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc
index b4a21ce6a4..dc5d070adf 100644
--- a/flow/designs/asap7/gcd/constraint.sdc
+++ b/flow/designs/asap7/gcd/constraint.sdc
@@ -1,15 +1,15 @@
current_design gcd
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
-set clk_period 310
+set clk_period 310
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json
index b335dc0836..186b37c73d 100644
--- a/flow/designs/asap7/gcd/rules-base.json
+++ b/flow/designs/asap7/gcd/rules-base.json
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1410,
+ "value": 1286,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -74.47,
+ "value": -73.56,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 60,
+ "value": 59,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -33.05,
+ "value": -32.76,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc
index a58c555b69..956a60e40e 100644
--- a/flow/designs/asap7/ibex/constraint.sdc
+++ b/flow/designs/asap7/ibex/constraint.sdc
@@ -1,4 +1,4 @@
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 1260
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc
index 7d9d39b7c1..0627af5b19 100644
--- a/flow/designs/asap7/ibex/constraint_pos_slack.sdc
+++ b/flow/designs/asap7/ibex/constraint_pos_slack.sdc
@@ -1,4 +1,4 @@
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 1468
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/ibex/rules-base.json b/flow/designs/asap7/ibex/rules-base.json
index 7e13390189..ab9f3184ac 100644
--- a/flow/designs/asap7/ibex/rules-base.json
+++ b/flow/designs/asap7/ibex/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 2616.39,
+ "value": 2612.72,
"compare": "<="
},
"constraints__clocks__count": {
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 2950,
+ "value": 2805,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 24427,
+ "value": 22941,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 2124,
+ "value": 1995,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 2124,
+ "value": 1995,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 132532,
+ "value": 106483,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -108.44,
+ "value": -75.22,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 3035,
+ "value": 2867,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 1062,
+ "value": 997,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -15.17,
+ "value": -11.43,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
index 7f2469a084..3800daaf8b 100644
--- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
+++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
@@ -1,6 +1,6 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 900
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc
index d37e20a0ee..46a528441e 100644
--- a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc
+++ b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc
@@ -7,7 +7,7 @@ set_units -time 1.0ps
current_design jpeg_encoder
create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk]
-set_propagated_clock [ all_clocks ]
+set_propagated_clock [all_clocks]
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}]
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}]
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[3]}]
@@ -36,113 +36,113 @@ set_load -pin_load -max 3.0 [get_ports {amp[1]}]
set_load -pin_load -max 3.0 [get_ports {amp[0]}]
set_load -pin_load -max 3.0 [get_ports douten]
set_max_delay 500 -from [list \
- [get_clocks tclk] ] -to [list \
- [get_ports douten] \
- [get_ports {amp[0]}] \
- [get_ports {amp[1]}] \
- [get_ports {amp[2]}] \
- [get_ports {amp[3]}] \
- [get_ports {amp[4]}] \
- [get_ports {amp[5]}] \
- [get_ports {amp[6]}] \
- [get_ports {amp[7]}] \
- [get_ports {amp[8]}] \
- [get_ports {amp[9]}] \
- [get_ports {amp[10]}] \
- [get_ports {amp[11]}] \
- [get_ports {rlen[0]}] \
- [get_ports {rlen[1]}] \
- [get_ports {rlen[2]}] \
- [get_ports {rlen[3]}] \
- [get_ports {size[0]}] \
- [get_ports {size[1]}] \
- [get_ports {size[2]}] \
- [get_ports {size[3]}] \
- [get_ports {qnt_cnt[0]}] \
- [get_ports {qnt_cnt[1]}] \
- [get_ports {qnt_cnt[2]}] \
- [get_ports {qnt_cnt[3]}] \
- [get_ports {qnt_cnt[4]}] \
- [get_ports {qnt_cnt[5]}] ]
+ [get_clocks tclk]] -to [list \
+ [get_ports douten] \
+ [get_ports {amp[0]}] \
+ [get_ports {amp[1]}] \
+ [get_ports {amp[2]}] \
+ [get_ports {amp[3]}] \
+ [get_ports {amp[4]}] \
+ [get_ports {amp[5]}] \
+ [get_ports {amp[6]}] \
+ [get_ports {amp[7]}] \
+ [get_ports {amp[8]}] \
+ [get_ports {amp[9]}] \
+ [get_ports {amp[10]}] \
+ [get_ports {amp[11]}] \
+ [get_ports {rlen[0]}] \
+ [get_ports {rlen[1]}] \
+ [get_ports {rlen[2]}] \
+ [get_ports {rlen[3]}] \
+ [get_ports {size[0]}] \
+ [get_ports {size[1]}] \
+ [get_ports {size[2]}] \
+ [get_ports {size[3]}] \
+ [get_ports {qnt_cnt[0]}] \
+ [get_ports {qnt_cnt[1]}] \
+ [get_ports {qnt_cnt[2]}] \
+ [get_ports {qnt_cnt[3]}] \
+ [get_ports {qnt_cnt[4]}] \
+ [get_ports {qnt_cnt[5]}]]
set_min_delay 500 \
- -from [list \
- [get_ports ena] \
- [get_ports rst] ] \
- -to [list \
- [get_clocks tclk] ]
+ -from [list \
+ [get_ports ena] \
+ [get_ports rst]] \
+ -to [list \
+ [get_clocks tclk]]
group_path -weight 1.000000 -name cg_enable_group_tclk -through [list \
- [get_pins qnr_RC_CG_HIER_INST3/enable] \
- [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
- [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
- [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
- [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
- [get_pins qnr_RC_CG_HIER_INST3/enable] \
- [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
- [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
- [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
- [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
- [get_pins qnr_RC_CG_HIER_INST3/enable] \
- [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
- [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
- [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
- [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
- [get_pins RC_CG_DECLONE_HIER_INST/enable] \
- [get_pins qnr_RC_CG_HIER_INST3/enable] \
- [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
- [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
- [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
- [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
- [get_pins RC_CG_DECLONE_HIER_INST/enable] ]
+ [get_pins qnr_RC_CG_HIER_INST3/enable] \
+ [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
+ [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
+ [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
+ [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
+ [get_pins qnr_RC_CG_HIER_INST3/enable] \
+ [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
+ [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
+ [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
+ [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
+ [get_pins qnr_RC_CG_HIER_INST3/enable] \
+ [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
+ [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
+ [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
+ [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
+ [get_pins RC_CG_DECLONE_HIER_INST/enable] \
+ [get_pins qnr_RC_CG_HIER_INST3/enable] \
+ [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
+ [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
+ [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
+ [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
+ [get_pins RC_CG_DECLONE_HIER_INST/enable]]
set_clock_gating_check -setup 0.0
-set_input_delay 100 -clock tclk [get_ports ena]
-set_input_delay 100 -clock tclk [get_ports rst]
+set_input_delay 100 -clock tclk [get_ports ena]
+set_input_delay 100 -clock tclk [get_ports rst]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}]
-set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}]
-set_input_delay 100 -clock tclk [get_ports {din[0]}]
-set_input_delay 100 -clock tclk [get_ports {din[1]}]
-set_input_delay 100 -clock tclk [get_ports {din[2]}]
-set_input_delay 100 -clock tclk [get_ports {din[3]}]
-set_input_delay 100 -clock tclk [get_ports {din[4]}]
-set_input_delay 100 -clock tclk [get_ports {din[5]}]
-set_input_delay 100 -clock tclk [get_ports {din[6]}]
-set_input_delay 100 -clock tclk [get_ports {din[7]}]
-set_input_delay 100 -clock tclk [get_ports dstrb]
-set_output_delay 100 -clock tclk [get_ports douten]
-set_output_delay 100 -clock tclk [get_ports {amp[0]}]
-set_output_delay 100 -clock tclk [get_ports {amp[1]}]
-set_output_delay 100 -clock tclk [get_ports {amp[2]}]
-set_output_delay 100 -clock tclk [get_ports {amp[3]}]
-set_output_delay 100 -clock tclk [get_ports {amp[4]}]
-set_output_delay 100 -clock tclk [get_ports {amp[5]}]
-set_output_delay 100 -clock tclk [get_ports {amp[6]}]
-set_output_delay 100 -clock tclk [get_ports {amp[7]}]
-set_output_delay 100 -clock tclk [get_ports {amp[8]}]
-set_output_delay 100 -clock tclk [get_ports {amp[9]}]
-set_output_delay 100 -clock tclk [get_ports {amp[10]}]
-set_output_delay 100 -clock tclk [get_ports {amp[11]}]
-set_output_delay 100 -clock tclk [get_ports {rlen[0]}]
-set_output_delay 100 -clock tclk [get_ports {rlen[1]}]
-set_output_delay 100 -clock tclk [get_ports {rlen[2]}]
-set_output_delay 100 -clock tclk [get_ports {rlen[3]}]
-set_output_delay 100 -clock tclk [get_ports {size[0]}]
-set_output_delay 100 -clock tclk [get_ports {size[1]}]
-set_output_delay 100 -clock tclk [get_ports {size[2]}]
-set_output_delay 100 -clock tclk [get_ports {size[3]}]
-set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}]
-set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}]
-set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}]
-set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}]
-set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}]
-set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}]
+set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}]
+set_input_delay 100 -clock tclk [get_ports {din[0]}]
+set_input_delay 100 -clock tclk [get_ports {din[1]}]
+set_input_delay 100 -clock tclk [get_ports {din[2]}]
+set_input_delay 100 -clock tclk [get_ports {din[3]}]
+set_input_delay 100 -clock tclk [get_ports {din[4]}]
+set_input_delay 100 -clock tclk [get_ports {din[5]}]
+set_input_delay 100 -clock tclk [get_ports {din[6]}]
+set_input_delay 100 -clock tclk [get_ports {din[7]}]
+set_input_delay 100 -clock tclk [get_ports dstrb]
+set_output_delay 100 -clock tclk [get_ports douten]
+set_output_delay 100 -clock tclk [get_ports {amp[0]}]
+set_output_delay 100 -clock tclk [get_ports {amp[1]}]
+set_output_delay 100 -clock tclk [get_ports {amp[2]}]
+set_output_delay 100 -clock tclk [get_ports {amp[3]}]
+set_output_delay 100 -clock tclk [get_ports {amp[4]}]
+set_output_delay 100 -clock tclk [get_ports {amp[5]}]
+set_output_delay 100 -clock tclk [get_ports {amp[6]}]
+set_output_delay 100 -clock tclk [get_ports {amp[7]}]
+set_output_delay 100 -clock tclk [get_ports {amp[8]}]
+set_output_delay 100 -clock tclk [get_ports {amp[9]}]
+set_output_delay 100 -clock tclk [get_ports {amp[10]}]
+set_output_delay 100 -clock tclk [get_ports {amp[11]}]
+set_output_delay 100 -clock tclk [get_ports {rlen[0]}]
+set_output_delay 100 -clock tclk [get_ports {rlen[1]}]
+set_output_delay 100 -clock tclk [get_ports {rlen[2]}]
+set_output_delay 100 -clock tclk [get_ports {rlen[3]}]
+set_output_delay 100 -clock tclk [get_ports {size[0]}]
+set_output_delay 100 -clock tclk [get_ports {size[1]}]
+set_output_delay 100 -clock tclk [get_ports {size[2]}]
+set_output_delay 100 -clock tclk [get_ports {size[3]}]
+set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}]
+set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}]
+set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}]
+set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}]
+set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}]
+set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}]
set_max_fanout 40.000 [current_design]
set_max_transition 80.0 [current_design]
set_clock_uncertainty -setup 20.0 [get_clocks tclk]
diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json
index aa8d38a509..37cf7724de 100644
--- a/flow/designs/asap7/jpeg/rules-base.json
+++ b/flow/designs/asap7/jpeg/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 7648,
+ "value": 7287,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 65384,
+ "value": 63593,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 5686,
+ "value": 5530,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 5686,
+ "value": 5530,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 317533,
+ "value": 181528,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -54.68,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 7738,
+ "value": 7375,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 2843,
+ "value": 2765,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk
index 975596c3a4..4b77c09e67 100644
--- a/flow/designs/asap7/jpeg_lvt/config.mk
+++ b/flow/designs/asap7/jpeg_lvt/config.mk
@@ -8,15 +8,6 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export ABC_AREA = 1
-export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
-
-export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds
-export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef
-
export CORE_UTILIZATION = 30
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 2
@@ -25,3 +16,6 @@ export PLACE_DENSITY = 0.60
export TNS_END_PERCENT = 100
export RECOVER_POWER = 100
+export ASAP7_USE_VT = LVT
+
+
diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
index a1f1601f12..2e77403245 100644
--- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
+++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
@@ -1,6 +1,6 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 1100
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json
index 37a1f60261..8f6bc56ba2 100644
--- a/flow/designs/asap7/jpeg_lvt/rules-base.json
+++ b/flow/designs/asap7/jpeg_lvt/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 7707,
+ "value": 7477,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 67276,
+ "value": 66675,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 5850,
+ "value": 5798,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 5850,
+ "value": 5798,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 315524,
+ "value": 187616,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -67.87,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 7778,
+ "value": 7543,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 2925,
+ "value": 2899,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc
index 2a2d4d2f56..66d1e5725e 100644
--- a/flow/designs/asap7/mock-alu/constraints.sdc
+++ b/flow/designs/asap7/mock-alu/constraints.sdc
@@ -5,15 +5,15 @@ set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set output_regs [get_cells *io_out_REG*]
-if {[llength $output_regs] == 0} {
- puts "Error: Could not find *io_out_REG*"
- exit 1
+if { [llength $output_regs] == 0 } {
+ puts "Error: Could not find *io_out_REG*"
+ exit 1
}
diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json
index 350a675995..bbec5f551f 100644
--- a/flow/designs/asap7/mock-alu/rules-base.json
+++ b/flow/designs/asap7/mock-alu/rules-base.json
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 61395,
+ "value": 59049,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -521.3,
+ "value": -506.14,
"compare": ">="
},
"finish__design__instance__area": {
@@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 116,
+ "value": 100,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
diff --git a/flow/designs/asap7/mock-array/Element/io.tcl b/flow/designs/asap7/mock-array/Element/io.tcl
index 07e4edceb6..e0e50243c7 100644
--- a/flow/designs/asap7/mock-array/Element/io.tcl
+++ b/flow/designs/asap7/mock-array/Element/io.tcl
@@ -1,58 +1,51 @@
# bazel has root of OpenROAD-flow-scripts as working directory
foreach prefix {"" flow/} {
set f ${prefix}designs/src/mock-array/util.tcl
- if {[file exists $f]} {
+ if { [file exists $f] } {
source $f
}
}
set assignments [list \
- top bottom \
- [list [ concat \
- {*}[match_pins io_ins_down.*] \
- {*}[match_pins io_outs_up.*] \
- ] \
- [ concat \
- {*}[match_pins io_outs_down.*] \
- {*}[match_pins io_ins_up.*] \
- ]] \
- left right \
- [list [ concat \
- {*}[match_pins io_ins_right.*] \
- {*}[match_pins io_outs_left.*] \
- ] \
- [ concat \
- {*}[match_pins io_outs_right.*] \
- {*}[match_pins io_ins_left.*] \
- ]] \
- left right \
- [list [ concat \
- {*}[match_pins io_lsbIns_.*] \
- ] \
- [ concat \
- {*}[match_pins io_lsbOuts_.*] \
- ]]
-]
+ top bottom \
+ [list [concat \
+ {*}[match_pins io_ins_down.*] \
+ {*}[match_pins io_outs_up.*]] \
+ [concat \
+ {*}[match_pins io_outs_down.*] \
+ {*}[match_pins io_ins_up.*]]] \
+ left right \
+ [list [concat \
+ {*}[match_pins io_ins_right.*] \
+ {*}[match_pins io_outs_left.*]] \
+ [concat \
+ {*}[match_pins io_outs_right.*] \
+ {*}[match_pins io_ins_left.*]]] \
+ left right \
+ [list [concat \
+ {*}[match_pins io_lsbIns_.*]] \
+ [concat \
+ {*}[match_pins io_lsbOuts_.*]]]]
-proc zip {list1 list2} {
- set result {}
- set length [llength $list1]
- set skip [expr [llength $list2] - [llength $list1]]
- for {set i 0} {$i < $length} {incr i} {
- lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i]
- }
- return $result
+proc zip { list1 list2 } {
+ set result {}
+ set length [llength $list1]
+ set skip [expr [llength $list2] - [llength $list1]]
+ for { set i 0 } { $i < $length } { incr i } {
+ lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i]
+ }
+ return $result
}
foreach {direction direction2 names} $assignments {
- set mirrored [zip {*}$names]
- set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1]
- # Test pins across multiple metal layers; so don't group
- # pins as a group of pins must be on a single metal layer.
- #
- # set_io_pin_constraint -group -order -pin_names [lindex $names 1]
- set_io_pin_constraint -mirrored_pins $mirrored
+ set mirrored [zip {*}$names]
+ set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1]
+ # Test pins across multiple metal layers; so don't group
+ # pins as a group of pins must be on a single metal layer.
+ #
+ # set_io_pin_constraint -group -order -pin_names [lindex $names 1]
+ set_io_pin_constraint -mirrored_pins $mirrored
}
set_io_pin_constraint -region top:* -pin_names clock
diff --git a/flow/designs/asap7/mock-array/io.tcl b/flow/designs/asap7/mock-array/io.tcl
index 9f1cdde4a5..1bf0ee962b 100644
--- a/flow/designs/asap7/mock-array/io.tcl
+++ b/flow/designs/asap7/mock-array/io.tcl
@@ -1,35 +1,30 @@
# bazel has root of OpenROAD-flow-scripts as working directory
foreach prefix {"" flow/} {
set f ${prefix}designs/src/mock-array/util.tcl
- if {[file exists $f]} {
+ if { [file exists $f] } {
source $f
}
}
set assignments [list \
- top \
- [ concat \
- {*}[match_pins io_ins_down_.*] \
- {*}[match_pins io_outs_up_.*] \
- ] \
- bottom \
- [ concat \
- {*}[match_pins io_ins_up_.*] \
- {*}[match_pins io_outs_down_.*] \
- ] \
- left \
- [ concat \
- {*}[match_pins io_ins_right_.*] \
- {*}[match_pins io_outs_left_.*] \
- ] \
- right \
- [ concat \
- {*}[match_pins io_ins_left_.*] \
- {*}[match_pins io_outs_right_.*] \
- {*}[match_pins io_lsbs_.*] \
- ] \
-]
+ top \
+ [concat \
+ {*}[match_pins io_ins_down_.*] \
+ {*}[match_pins io_outs_up_.*]] \
+ bottom \
+ [concat \
+ {*}[match_pins io_ins_up_.*] \
+ {*}[match_pins io_outs_down_.*]] \
+ left \
+ [concat \
+ {*}[match_pins io_ins_right_.*] \
+ {*}[match_pins io_outs_left_.*]] \
+ right \
+ [concat \
+ {*}[match_pins io_ins_left_.*] \
+ {*}[match_pins io_outs_right_.*] \
+ {*}[match_pins io_lsbs_.*]]]
foreach {direction names} $assignments {
- set_io_pin_constraint -region $direction:* -pin_names $names
+ set_io_pin_constraint -region $direction:* -pin_names $names
}
diff --git a/flow/designs/asap7/mock-array/macro-placement.tcl b/flow/designs/asap7/mock-array/macro-placement.tcl
index 18bd768798..9b1bc3fb70 100644
--- a/flow/designs/asap7/mock-array/macro-placement.tcl
+++ b/flow/designs/asap7/mock-array/macro-placement.tcl
@@ -15,11 +15,11 @@ set x_offset [expr [$core xMin] + ([$core dx] - (7 * $x_pitch) - [$bbox getDX])/
set y_offset [expr [$core yMin] + ([$core dy] - (7 * $y_pitch) - [$bbox getDY])/2]
# Loop through the 8x8 array, add the offset, and invoke place_macro
-for {set i 0} {$i < 8} {incr i} {
- for {set j 0} {$j < 8} {incr j} {
- set macro_name [format "ces_%d_%d" $i $j]
- set x_location [expr {$j * $x_pitch + $x_offset}]
- set y_location [expr {$i * $y_pitch + $y_offset}]
- place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0
- }
+for { set i 0 } { $i < 8 } { incr i } {
+ for { set j 0 } { $j < 8 } { incr j } {
+ set macro_name [format "ces_%d_%d" $i $j]
+ set x_location [expr { $j * $x_pitch + $x_offset }]
+ set y_location [expr { $i * $y_pitch + $y_offset }]
+ place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0
+ }
}
diff --git a/flow/designs/asap7/mock-array/power.tcl b/flow/designs/asap7/mock-array/power.tcl
index c53beade09..5f7f136cf9 100644
--- a/flow/designs/asap7/mock-array/power.tcl
+++ b/flow/designs/asap7/mock-array/power.tcl
@@ -1,7 +1,7 @@
source $::env(SCRIPTS_DIR)/util.tcl
foreach libFile $::env(LIB_FILES) {
- if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} {
+ if { [lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1 } {
read_liberty $libFile
}
}
@@ -14,8 +14,8 @@ log_cmd link_design MockArray
log_cmd read_sdc $::env(RESULTS_DIR)/6_final.sdc
log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef
puts "read_spef for ces_*_* macros"
-for {set x 0} {$x < 8} {incr x} {
- for {set y 0} {$y < 8} {incr y} {
+for { set x 0 } { $x < 8 } { incr x } {
+ for { set y 0 } { $y < 8 } { incr y } {
read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef
}
}
@@ -36,7 +36,7 @@ set clock_period [expr [get_property [get_clocks] period] * 1e-12]
foreach pin $pins {
set activity [get_property $pin activity]
set activity_origin [lindex $activity 2]
- if {$activity_origin != "vcd"} {
+ if { $activity_origin != "vcd" } {
continue
}
puts $fp "set_power_activity \
@@ -51,32 +51,32 @@ set no_vcd_activity {}
foreach pin $pins {
set activity [get_property $pin activity]
set activity_origin [lindex $activity 2]
- if {$activity_origin == "vcd"} {
+ if { $activity_origin == "vcd" } {
continue
}
- if {$activity_origin == "constant"} {
+ if { $activity_origin == "constant" } {
continue
}
- if {$activity_origin == "unknown"} {
+ if { $activity_origin == "unknown" } {
continue
}
- if {[get_property $pin is_hierarchical]} {
+ if { [get_property $pin is_hierarchical] } {
continue
}
- if {$activity_origin == "clock"} {
+ if { $activity_origin == "clock" } {
continue
}
set direction [get_property $pin direction]
- if {$direction == "internal"} {
+ if { $direction == "internal" } {
continue
}
lappend no_vcd_activity "[get_full_name $pin] $activity $direction"
- if {[llength $no_vcd_activity] >= 10} {
+ if { [llength $no_vcd_activity] >= 10 } {
break
}
}
-if {[llength $no_vcd_activity] > 0} {
+if { [llength $no_vcd_activity] > 0 } {
puts "Error: Listing [llength $no_vcd_activity] pins without activity from $vcd_file:"
foreach pin $no_vcd_activity {
puts $pin
@@ -85,8 +85,8 @@ if {[llength $no_vcd_activity] > 0} {
}
set ces {}
-for {set x 0} {$x < 8} {incr x} {
- for {set y 0} {$y < 8} {incr y} {
+for { set x 0 } { $x < 8 } { incr x } {
+ for { set y 0 } { $y < 8 } { incr y } {
lappend ces ces_${x}_${y}
}
}
@@ -94,7 +94,7 @@ for {set x 0} {$x < 8} {incr x} {
puts {report_power -instances [get_cells $ces]}
report_power -instances [get_cells $ces]
-proc total_power {} {
+proc total_power { } {
return [lindex [sta::design_power [sta::corners]] 3]
}
@@ -108,12 +108,12 @@ set total_power_user_activity [total_power]
puts "Total power from VCD: $total_power_vcd"
puts "Total power from user activity: $total_power_user_activity"
-if {$total_power_vcd == $total_power_user_activity} {
+if { $total_power_vcd == $total_power_user_activity } {
puts "Error: settting user power activity had no effect, expected some loss in accuracy"
exit 1
}
-if {abs($total_power_vcd - $total_power_user_activity) > 1e-3} {
+if { abs($total_power_vcd - $total_power_user_activity) > 1e-3 } {
puts "Error: Total power mismatch between VCD and user activity: $total_power_vcd vs $total_power_user_activity"
exit 1
}
diff --git a/flow/designs/asap7/mock-array/rules-base.json b/flow/designs/asap7/mock-array/rules-base.json
index e9501321df..f11664d7bf 100644
--- a/flow/designs/asap7/mock-array/rules-base.json
+++ b/flow/designs/asap7/mock-array/rules-base.json
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -92.28,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -25.4,
+ "value": -10.0,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/mock-cpu/constraint.sdc b/flow/designs/asap7/mock-cpu/constraint.sdc
index 15002f21dd..8f5b42e89f 100644
--- a/flow/designs/asap7/mock-cpu/constraint.sdc
+++ b/flow/designs/asap7/mock-cpu/constraint.sdc
@@ -31,7 +31,7 @@ set_false_path -to [get_ports *rst_n]
set non_clk_inputs {}
set clock_ports [list [get_ports $clk1_name] [get_ports $clk2_name]]
foreach input [all_inputs] {
- if {[lsearch -exact $clock_ports $input] == -1} {
+ if { [lsearch -exact $clock_ports $input] == -1 } {
lappend non_clk_inputs $input
}
}
diff --git a/flow/designs/asap7/mock-cpu/io.tcl b/flow/designs/asap7/mock-cpu/io.tcl
index 01693e7da3..322f85c1f4 100644
--- a/flow/designs/asap7/mock-cpu/io.tcl
+++ b/flow/designs/asap7/mock-cpu/io.tcl
@@ -1,7 +1,7 @@
# bazel has root of OpenROAD-flow-scripts as working directory
foreach prefix {"" flow/} {
set f ${prefix}designs/src/mock-array/util.tcl
- if {[file exists $f]} {
+ if { [file exists $f] } {
source $f
}
}
diff --git a/flow/designs/asap7/mock-cpu/rules-base.json b/flow/designs/asap7/mock-cpu/rules-base.json
index d299f58c15..4cd178023b 100644
--- a/flow/designs/asap7/mock-cpu/rules-base.json
+++ b/flow/designs/asap7/mock-cpu/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 7398,
+ "value": 7389,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 53867,
+ "value": 52446,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -52,7 +52,7 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 7961,
+ "value": 7638,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 101,
+ "value": 100,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
diff --git a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json
index 0c8bd5dfeb..e38e846845 100644
--- a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json
+++ b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 2616,
+ "value": 2395,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 148204,
+ "value": 95161,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -187.67,
+ "value": -79.2,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 2667,
+ "value": 2464,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -22.19,
+ "value": -11.73,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc
index 74dca22a8f..3cea613851 100644
--- a/flow/designs/asap7/riscv32i/constraint.sdc
+++ b/flow/designs/asap7/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
current_design riscv_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 1260
set clk_io_pct 0.125
@@ -10,5 +10,5 @@ set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/riscv32i/rules-base.json b/flow/designs/asap7/riscv32i/rules-base.json
index abf9096660..ce0d33577c 100644
--- a/flow/designs/asap7/riscv32i/rules-base.json
+++ b/flow/designs/asap7/riscv32i/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 3191,
+ "value": 3109,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 12507,
+ "value": 11777,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 1088,
+ "value": 1024,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1088,
+ "value": 1024,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 137800,
+ "value": 83651,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -113.89,
+ "value": -44.21,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 3234,
+ "value": 3180,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 827,
+ "value": 512,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -14.39,
+ "value": -10.0,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc
index f679177441..955b0805d5 100644
--- a/flow/designs/asap7/swerv_wrapper/constraint.sdc
+++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc
@@ -1,8 +1,8 @@
current_design swerv_wrapper
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
-set clk_period 2500
+set clk_period 2500
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json
index 6f5045049c..e1ce5d7c25 100644
--- a/flow/designs/asap7/swerv_wrapper/rules-base.json
+++ b/flow/designs/asap7/swerv_wrapper/rules-base.json
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1919981,
+ "value": 1867701,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 950,
+ "value": 286,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc
index cc49402954..0d7aa226f0 100644
--- a/flow/designs/asap7/uart/constraint.sdc
+++ b/flow/designs/asap7/uart/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 300
+set clk_period 300
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/uart/rules-base.json b/flow/designs/asap7/uart/rules-base.json
index 220aa64156..80006ed54c 100644
--- a/flow/designs/asap7/uart/rules-base.json
+++ b/flow/designs/asap7/uart/rules-base.json
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -24.54,
+ "value": -20.24,
"compare": ">="
},
"finish__design__instance__area": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -13.14,
+ "value": -11.75,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc
index a930ae4ba7..ae1bc48d58 100644
--- a/flow/designs/gf12/aes/constraint.sdc
+++ b/flow/designs/gf12/aes/constraint.sdc
@@ -1,17 +1,17 @@
current_design aes_cipher_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 420
+set clk_period 420
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set_timing_derate -early 0.9500
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
index cfb21ab138..28194633ef 100644
--- a/flow/designs/gf12/ariane/config.mk
+++ b/flow/designs/gf12/ariane/config.mk
@@ -24,9 +24,6 @@ export PLACE_DENSITY ?= 0.50
export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl
-# to be removed once gpl is fixed for "corner buffers" issue
-export GPL_KEEP_OVERFLOW = 0
-
export MACRO_PLACE_HALO = 7 7
export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
diff --git a/flow/designs/gf12/ariane/constraint.sdc b/flow/designs/gf12/ariane/constraint.sdc
index 2430c4b71e..d5971e4984 100644
--- a/flow/designs/gf12/ariane/constraint.sdc
+++ b/flow/designs/gf12/ariane/constraint.sdc
@@ -1,495 +1,495 @@
-create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850}
-set_input_delay -clock core_clock 1000 [get_ports rst_ni]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}]
-set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}]
-set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}]
-set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}]
-set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}]
-set_input_delay -clock core_clock 1000 [get_ports ipi_i]
-set_input_delay -clock core_clock 1000 [get_ports time_irq_i]
-set_input_delay -clock core_clock 1000 [get_ports debug_req_i]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}]
-set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}]
-set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}]
+create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850}
+set_input_delay -clock core_clock 1000 [get_ports rst_ni]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}]
+set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}]
+set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}]
+set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}]
+set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}]
+set_input_delay -clock core_clock 1000 [get_ports ipi_i]
+set_input_delay -clock core_clock 1000 [get_ports time_irq_i]
+set_input_delay -clock core_clock 1000 [get_ports debug_req_i]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}]
+set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}]
+set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}]
diff --git a/flow/designs/gf12/ariane/constraint_hier.sdc b/flow/designs/gf12/ariane/constraint_hier.sdc
index 89c4ae0115..1a22a7607f 100644
--- a/flow/designs/gf12/ariane/constraint_hier.sdc
+++ b/flow/designs/gf12/ariane/constraint_hier.sdc
@@ -1,495 +1,495 @@
-create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500}
-set_input_delay -clock core_clock 1500 [get_ports rst_ni]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}]
-set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}]
-set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}]
-set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}]
-set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}]
-set_input_delay -clock core_clock 1500 [get_ports ipi_i]
-set_input_delay -clock core_clock 1500 [get_ports time_irq_i]
-set_input_delay -clock core_clock 1500 [get_ports debug_req_i]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}]
-set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}]
-set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}]
+create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500}
+set_input_delay -clock core_clock 1500 [get_ports rst_ni]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}]
+set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}]
+set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}]
+set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}]
+set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}]
+set_input_delay -clock core_clock 1500 [get_ports ipi_i]
+set_input_delay -clock core_clock 1500 [get_ports time_irq_i]
+set_input_delay -clock core_clock 1500 [get_ports debug_req_i]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}]
+set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}]
+set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}]
diff --git a/flow/designs/gf12/ariane133/ariane.sdc b/flow/designs/gf12/ariane133/ariane.sdc
index c756ae05a3..4ddcb37965 100644
--- a/flow/designs/gf12/ariane133/ariane.sdc
+++ b/flow/designs/gf12/ariane133/ariane.sdc
@@ -7,5 +7,5 @@ set_units -time 1ps
current_design ariane
create_clock -name "core_clock" -period 1300.0 -waveform {0.0 900.0} [get_ports clk_i]
-set_clock_gating_check -setup 0.0
+set_clock_gating_check -setup 0.0
set_wire_load_mode "top"
diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk
index 53f9f1d165..83e6a775b3 100644
--- a/flow/designs/gf12/bp_single/config.mk
+++ b/flow/designs/gf12/bp_single/config.mk
@@ -66,5 +66,8 @@ else
export DESIGN_TYPE = CHIP_NODEN
endif
+# Override cts arguments to set `-no_insertion_delay`
+export CTS_ARGS = -no_insertion_delay -sink_clustering_enable -balance_levels -repair_clock_nets
+
# enable slack margin for setup and hold fix after CTS
export SETUP_SLACK_MARGIN ?= 100
diff --git a/flow/designs/gf12/bp_single/fastroute.tcl b/flow/designs/gf12/bp_single/fastroute.tcl
index 24379738d7..e05f213a65 100644
--- a/flow/designs/gf12/bp_single/fastroute.tcl
+++ b/flow/designs/gf12/bp_single/fastroute.tcl
@@ -3,5 +3,4 @@ set_global_routing_layer_adjustment M3 0.6
set_global_routing_layer_adjustment C4-C5 0.5
set_global_routing_layer_adjustment K1-K4 0.45
-set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER)
-
+set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER)
diff --git a/flow/designs/gf12/bp_single/rules-base.json b/flow/designs/gf12/bp_single/rules-base.json
index 9f270fcfe6..be33224b80 100644
--- a/flow/designs/gf12/bp_single/rules-base.json
+++ b/flow/designs/gf12/bp_single/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 509289,
+ "value": 491681,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 546190,
+ "value": 535708,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 47495,
+ "value": 46583,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 47495,
+ "value": 46583,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,11 +32,11 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 7863419,
+ "value": 6200511,
"compare": "<="
},
"detailedroute__route__drc_errors": {
- "value": 1,
+ "value": 0,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
@@ -48,19 +48,19 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -183.6,
+ "value": -144.83,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 519153,
+ "value": 500408,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 23747,
+ "value": 23292,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 230,
+ "value": 479,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
diff --git a/flow/designs/gf12/ca53/fastroute.tcl b/flow/designs/gf12/ca53/fastroute.tcl
index 177a36a3e5..7b9941dfdb 100644
--- a/flow/designs/gf12/ca53/fastroute.tcl
+++ b/flow/designs/gf12/ca53/fastroute.tcl
@@ -3,5 +3,4 @@ set_global_routing_layer_adjustment M3 0.5
set_global_routing_layer_adjustment C4-K4 0.5
#set_global_routing_layer_adjustment H1-H2 0.5
-set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER)
-
+set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER)
diff --git a/flow/designs/gf12/coyote/constraint.sdc b/flow/designs/gf12/coyote/constraint.sdc
index a27541fdcd..d80a6cd806 100644
--- a/flow/designs/gf12/coyote/constraint.sdc
+++ b/flow/designs/gf12/coyote/constraint.sdc
@@ -814,10 +814,10 @@ set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dca
set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}]
set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}]
set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}]
-set_false_path\
- -to [list [get_ports {rocc_ctrl_o_exception_}]\
- [get_ports {rocc_ctrl_o_host_id_}]\
- [get_ports {rocc_ctrl_o_s_}]]
+set_false_path \
+ -to [list [get_ports {rocc_ctrl_o_exception_}] \
+ [get_ports {rocc_ctrl_o_host_id_}] \
+ [get_ports {rocc_ctrl_o_s_}]]
###############################################################################
# Environment
###############################################################################
diff --git a/flow/designs/gf12/coyote/constraint_hier.sdc b/flow/designs/gf12/coyote/constraint_hier.sdc
index 19f548615f..d8a085a067 100644
--- a/flow/designs/gf12/coyote/constraint_hier.sdc
+++ b/flow/designs/gf12/coyote/constraint_hier.sdc
@@ -814,10 +814,10 @@ set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dca
set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}]
set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}]
set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}]
-set_false_path\
- -to [list [get_ports {rocc_ctrl_o_exception_}]\
- [get_ports {rocc_ctrl_o_host_id_}]\
- [get_ports {rocc_ctrl_o_s_}]]
+set_false_path \
+ -to [list [get_ports {rocc_ctrl_o_exception_}] \
+ [get_ports {rocc_ctrl_o_host_id_}] \
+ [get_ports {rocc_ctrl_o_s_}]]
###############################################################################
# Environment
###############################################################################
diff --git a/flow/designs/gf12/coyote/io.tcl b/flow/designs/gf12/coyote/io.tcl
index 39d22dc7cf..eddd0b8d59 100644
--- a/flow/designs/gf12/coyote/io.tcl
+++ b/flow/designs/gf12/coyote/io.tcl
@@ -1 +1 @@
-exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-20 -region bottom:450-750
\ No newline at end of file
+exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-20 -region bottom:450-750
diff --git a/flow/designs/gf12/coyote/rules-base.json b/flow/designs/gf12/coyote/rules-base.json
index 6c4fc6394a..8359e8a556 100644
--- a/flow/designs/gf12/coyote/rules-base.json
+++ b/flow/designs/gf12/coyote/rules-base.json
@@ -32,11 +32,11 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 5770855,
+ "value": 5678019,
"compare": "<="
},
"detailedroute__route__drc_errors": {
- "value": 0,
+ "value": 1,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
@@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 100,
+ "value": 266,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc
index e1df1eb91a..18fe09d581 100644
--- a/flow/designs/gf12/gcd/constraint.sdc
+++ b/flow/designs/gf12/gcd/constraint.sdc
@@ -1,17 +1,17 @@
current_design gcd
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
-set clk_period 280
+set clk_period 280
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
#
set_timing_derate -early 0.9500
diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc
index 1684b897b5..3d19120721 100644
--- a/flow/designs/gf12/ibex/constraint.sdc
+++ b/flow/designs/gf12/ibex/constraint.sdc
@@ -1,17 +1,17 @@
current_design ibex_core
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
-set clk_period 1020
+set clk_period 1020
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set_timing_derate -early 0.9500
diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc
index 86761946c6..d196f8f423 100644
--- a/flow/designs/gf12/jpeg/constraint.sdc
+++ b/flow/designs/gf12/jpeg/constraint.sdc
@@ -1,17 +1,17 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 770
+set clk_period 770
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set_timing_derate -early 0.9500
diff --git a/flow/designs/gf12/swerv_wrapper/constraint.sdc b/flow/designs/gf12/swerv_wrapper/constraint.sdc
index a7296dd71c..186b5121f8 100644
--- a/flow/designs/gf12/swerv_wrapper/constraint.sdc
+++ b/flow/designs/gf12/swerv_wrapper/constraint.sdc
@@ -8,11 +8,11 @@ current_design swerv_wrapper
###############################################################################
create_clock -name core_clock -period 1500.0 -waveform {0.0000 750.0} [get_ports {clk}]
set_clock_uncertainty -setup 70.0000 core_clock
-set_clock_uncertainty -hold 70.0000 core_clock
+set_clock_uncertainty -hold 70.0000 core_clock
#set_propagated_clock [get_clocks {core_clock}]
create_clock -name jtag_clock -period 1500 -waveform {0.0000 750.0} [get_ports {jtag_tck}]
set_clock_uncertainty -setup 70.0000 jtag_clock
-set_clock_uncertainty -hold 70.0000 jtag_clock
+set_clock_uncertainty -hold 70.0000 jtag_clock
#set_propagated_clock [get_clocks {jtag_clock}]
# There is sync logic between jtag and core_clock
@@ -25,7 +25,7 @@ set_clock_uncertainty -hold 70.0000 jtag_clock
# Design Rules
###############################################################################
set clock_ports "jtag_tck clk"
-set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n"
+set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n"
#set input_not_jtag_ports [remove_from_collection [all_inputs] "$jtag_ports $clock_ports"]
set input_not_jtag_ports [list]
foreach input [all_inputs] {
@@ -40,9 +40,9 @@ foreach input [all_inputs] {
lappend input_not_jtag_ports $input
}
}
-set_input_delay 375 -clock jtag_clock $jtag_ports
+set_input_delay 375 -clock jtag_clock $jtag_ports
set_output_delay 375 -clock jtag_clock [get_ports "jtag_tdo"]
-set_input_delay 750 -clock core_clock $input_not_jtag_ports
+set_input_delay 750 -clock core_clock $input_not_jtag_ports
set ports_list [list]
foreach output [all_outputs] {
set addFlag 1
@@ -63,5 +63,3 @@ set_driving_cell -lib_cell BUFH_X2N_A9PP84TR_C14 [all_inputs]
foreach input [all_inputs] {
set_load 0 $input
}
-
-
diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc
index e5604adf91..02e8f6f066 100644
--- a/flow/designs/gf12/tinyRocket/constraint.sdc
+++ b/flow/designs/gf12/tinyRocket/constraint.sdc
@@ -1,13 +1,13 @@
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clock
-set clk_period 800
+set clk_period 800
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json
index 171d847296..1478ea051c 100644
--- a/flow/designs/gf180/aes-hybrid/rules-base.json
+++ b/flow/designs/gf180/aes-hybrid/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 21061,
+ "value": 26088,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 2,
+ "value": 84,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1815251,
+ "value": 1799784,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -1.2,
+ "value": -1.43,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 685668,
+ "value": 803898,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc
index 2e7189ca5f..da8e0a8244 100644
--- a/flow/designs/gf180/aes/constraint.sdc
+++ b/flow/designs/gf180/aes/constraint.sdc
@@ -1,19 +1,18 @@
current_design aes_cipher_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 3
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
-create_clock -name $clk_name -period $clk_period $clk_port
+create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
-
diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json
index 7b11b18d98..9de3ce5b90 100644
--- a/flow/designs/gf180/aes/rules-base.json
+++ b/flow/designs/gf180/aes/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 21792,
+ "value": 25876,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 0,
+ "value": 72,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1512295,
+ "value": 1477421,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -1.28,
+ "value": -1.25,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 762481,
+ "value": 905336,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc
index e6e7f6257a..d91411c4dc 100644
--- a/flow/designs/gf180/ibex/constraint.sdc
+++ b/flow/designs/gf180/ibex/constraint.sdc
@@ -1,6 +1,6 @@
current_design ibex_core
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 10.0
set clk_io_pct 0.2
@@ -11,6 +11,6 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set_false_path -from [get_ports {rst_ni}]
diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json
index aaaa3c0bf8..9f50f9890d 100644
--- a/flow/designs/gf180/ibex/rules-base.json
+++ b/flow/designs/gf180/ibex/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 738423.39,
+ "value": 731295.7,
"compare": "<="
},
"constraints__clocks__count": {
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 845748,
+ "value": 813057,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 17828,
+ "value": 17103,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 1550,
+ "value": 1487,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1550,
+ "value": 1487,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,11 +32,11 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1753283,
+ "value": 1544585,
"compare": "<="
},
"detailedroute__route__drc_errors": {
- "value": 1,
+ "value": 0,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 1067423,
+ "value": 985974,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 785,
+ "value": 744,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc
index d123c56533..5862d8ce02 100644
--- a/flow/designs/gf180/jpeg/constraint.sdc
+++ b/flow/designs/gf180/jpeg/constraint.sdc
@@ -1,6 +1,6 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 7.5
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/jpeg/io.tcl b/flow/designs/gf180/jpeg/io.tcl
index e023ab42b4..0c81b1f9fa 100644
--- a/flow/designs/gf180/jpeg/io.tcl
+++ b/flow/designs/gf180/jpeg/io.tcl
@@ -1 +1 @@
-exclude_io_pin_region -region top:* -region bottom:*
\ No newline at end of file
+exclude_io_pin_region -region top:* -region bottom:*
diff --git a/flow/designs/gf180/jpeg/rules-base.json b/flow/designs/gf180/jpeg/rules-base.json
index 7e687cf3b3..87365b1740 100644
--- a/flow/designs/gf180/jpeg/rules-base.json
+++ b/flow/designs/gf180/jpeg/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 2383064,
+ "value": 2366631,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 54888,
+ "value": 53829,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,19 +20,19 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 4773,
+ "value": 4681,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 4773,
+ "value": 4681,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 4,
+ "value": 0,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 4344677,
+ "value": 2985307,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,19 +44,19 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 16,
+ "value": 6,
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.47,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 2842064,
+ "value": 2695462,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 2386,
+ "value": 2340,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc
index 26f4484628..e38107b41f 100644
--- a/flow/designs/gf180/riscv32i/constraint.sdc
+++ b/flow/designs/gf180/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 10.0
+set clk_period 10.0
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -8,5 +8,5 @@ set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json
index 0f614f7f60..50900a70fd 100644
--- a/flow/designs/gf180/riscv32i/rules-base.json
+++ b/flow/designs/gf180/riscv32i/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 414808,
+ "value": 383765,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 8511,
+ "value": 8224,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 740,
+ "value": 715,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 740,
+ "value": 715,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 891236,
+ "value": 754102,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 521614,
+ "value": 475666,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 370,
+ "value": 358,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl
index c89b0808dd..15070643eb 100644
--- a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl
+++ b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl
@@ -18,7 +18,7 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
####################################
# standard cell grid
####################################
-define_pdn_grid -name {block} -voltage_domains {CORE}
+define_pdn_grid -name {block} -voltage_domains {CORE}
add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4}
add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8}
diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc
index e921f859f9..5c231242df 100644
--- a/flow/designs/gf180/uart-blocks/constraint.sdc
+++ b/flow/designs/gf180/uart-blocks/constraint.sdc
@@ -1,4 +1,4 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 6
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json
index eaea660e58..e54080e043 100644
--- a/flow/designs/gf180/uart-blocks/rules-base.json
+++ b/flow/designs/gf180/uart-blocks/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 731,
+ "value": 726,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 64,
+ "value": 63,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 64,
+ "value": 63,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
diff --git a/flow/designs/gf180/uart-blocks/tapcell.tcl b/flow/designs/gf180/uart-blocks/tapcell.tcl
index b3d1bf1303..aa4a9daa9d 100644
--- a/flow/designs/gf180/uart-blocks/tapcell.tcl
+++ b/flow/designs/gf180/uart-blocks/tapcell.tcl
@@ -1,8 +1,7 @@
- tapcell \
- -endcap_cpp "12" \
- -distance 100 \
- -tapcell_master $::env(TIE_CELL) \
- -endcap_master $::env(ENDCAP_CELL) \
- -halo_width_x $::env(MACRO_ROWS_HALO_X) \
- -halo_width_y $::env(MACRO_ROWS_HALO_Y)
-
+tapcell \
+ -endcap_cpp "12" \
+ -distance 100 \
+ -tapcell_master $::env(TIE_CELL) \
+ -endcap_master $::env(ENDCAP_CELL) \
+ -halo_width_x $::env(MACRO_ROWS_HALO_X) \
+ -halo_width_y $::env(MACRO_ROWS_HALO_Y)
diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc
index ffe2329cf5..5c231242df 100644
--- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc
+++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 6
+set clk_period 6
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl
index f5185790be..fce426a382 100644
--- a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl
+++ b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl
@@ -18,7 +18,7 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
####################################
# standard cell grid
####################################
-define_pdn_grid -name {block} -voltage_domains {CORE}
+define_pdn_grid -name {block} -voltage_domains {CORE}
add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4}
add_pdn_connect -grid {block} -layers {Metal1 Metal4}
diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc
index ec67329fda..f32c9be836 100644
--- a/flow/designs/ihp-sg13g2/aes/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/aes/constraint.sdc
@@ -1,8 +1,8 @@
current_design aes_cipher_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 4.5
+set clk_period 4.5
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,6 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
-
diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json
index ce2965075c..c0dbd17b30 100644
--- a/flow/designs/ihp-sg13g2/aes/rules-base.json
+++ b/flow/designs/ihp-sg13g2/aes/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 253595,
+ "value": 229478,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 19280,
+ "value": 18996,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -28,7 +28,7 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 3,
+ "value": 166,
"compare": "<="
},
"detailedroute__route__wirelength": {
@@ -44,11 +44,11 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 24,
+ "value": 5,
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.13,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 841,
+ "value": 826,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc
index 0e975c114d..20c0c7a73e 100644
--- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc
@@ -1,6 +1,6 @@
current_design gcd
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
set clk_period 2.6
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/gcd/rules-base.json b/flow/designs/ihp-sg13g2/gcd/rules-base.json
index bc7b71a86d..e8f4653148 100644
--- a/flow/designs/ihp-sg13g2/gcd/rules-base.json
+++ b/flow/designs/ihp-sg13g2/gcd/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 505,
+ "value": 494,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.16,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk
new file mode 100644
index 0000000000..68feb648f2
--- /dev/null
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk
@@ -0,0 +1,20 @@
+export DESIGN_NAME = I2cDeviceCtrl
+export TOP_DESIGN_NICKNAME = i2c-gpio-expander
+export DESIGN_NICKNAME = ${TOP_DESIGN_NICKNAME}_${DESIGN_NAME}
+export PLATFORM = ihp-sg13g2
+
+export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/${TOP_DESIGN_NICKNAME}/I2cGpioExpander.v \
+
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/constraint.sdc
+
+export DIE_AREA = 0.0 0.0 147.84 147.42
+export CORE_AREA = 18.72 18.9 128.64 128.52
+
+export MAX_ROUTING_LAYER = TopMetal2
+
+export TNS_END_PERCENT = 100
+export PLACE_DENSITY = 0.75
+
+export CORNERS = slow typ fast
+
+export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/pdn.tcl
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc
new file mode 100644
index 0000000000..95787b8df0
--- /dev/null
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc
@@ -0,0 +1,22 @@
+current_design I2cDeviceCtrl/I2cDeviceCtrl
+set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA
+set_max_fanout 8 [current_design]
+set_max_capacitance 0.5 [current_design]
+set_max_transition 3 [current_design]
+set_max_area 0
+
+create_clock [get_ports clock] -name clock -period 20.0 -waveform {0 10.0}
+set_ideal_network [get_ports clock]
+set_clock_uncertainty 0.15 [get_clocks clock]
+set_clock_transition 0.25 [get_clocks clock]
+set input_delay_value_clock 4.0
+set output_delay_value_clock 4.0
+set clk_indx_clock [lsearch [all_inputs] [get_port clock]]
+set all_inputs_wo_clk_rst_clock [lreplace [all_inputs] $clk_indx_clock $clk_indx_clock ""]
+set_input_delay $input_delay_value_clock -clock [get_clocks clock] $all_inputs_wo_clk_rst_clock
+set_output_delay $output_delay_value_clock -clock [get_clocks clock] [all_outputs]
+
+set_load -pin_load 5 [all_inputs]
+set_load -pin_load 5 [all_outputs]
+set_timing_derate -early 0.95
+set_timing_derate -late 1.05
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl
new file mode 100644
index 0000000000..fd105772b5
--- /dev/null
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl
@@ -0,0 +1,34 @@
+# standard cells
+add_global_connection -net {VDD} -pin_pattern {^VDD$} -power
+add_global_connection -net {VDD} -pin_pattern {^VDDPE$}
+add_global_connection -net {VDD} -pin_pattern {^VDDCE$}
+add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground
+add_global_connection -net {VSS} -pin_pattern {^VSSE$}
+
+# macros
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power
+add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
+add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
+
+# padframe core power pins
+add_global_connection -net {VDD} -pin_pattern {^vdd$} -power
+add_global_connection -net {VSS} -pin_pattern {^vss$} -ground
+
+# padframe io power pins
+add_global_connection -net {IOVDD} -pin_pattern {^iovdd$} -power
+add_global_connection -net {IOVSS} -pin_pattern {^iovss$} -ground
+
+global_connect
+
+# core voltage domain
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+
+# stdcell grid
+define_pdn_grid -name {grid} -voltage_domains {CORE}
+add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring
+add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads
+add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring
+add_pdn_connect -grid {grid} -layers {Metal1 Metal3}
+add_pdn_connect -grid {grid} -layers {Metal3 Metal4}
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk
index c6c45aba0f..f46620b481 100644
--- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk
@@ -9,7 +9,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz
export DIE_AREA = 0.0 0.0 1050.0 1050.0
-export CORE_AREA = 425.28 427.16 631.2 630.24
+export CORE_AREA = 351.36 351.54 699.84 699.3
export MAX_ROUTING_LAYER = TopMetal2
@@ -20,3 +20,5 @@ export CORNERS = slow fast
export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl
export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.tcl
+
+export BLOCKS = I2cDeviceCtrl
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc
index 02aff71773..7f9b71f07d 100644
--- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc
@@ -24,7 +24,7 @@ set clk_core_inout_16mA_ports [get_ports {
io_gpio_5_PAD
io_gpio_6_PAD
io_gpio_7_PAD
-}]
+}]
set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports
set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports
set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports
@@ -32,7 +32,7 @@ set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports
set clk_core_inout_4mA_ports [get_ports {
io_i2c_scl_PAD
io_i2c_sda_PAD
-}]
+}]
set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports
set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports
set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports
@@ -42,13 +42,13 @@ set clk_core_input_ports [get_ports {
io_address_0_PAD
io_address_1_PAD
io_address_2_PAD
-}]
+}]
set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports
set_input_delay 8 -clock clk_core $clk_core_input_ports
set clk_core_output_4mA_ports [get_ports {
io_i2c_interrupt_PAD
-}]
+}]
set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports
set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json
new file mode 100644
index 0000000000..0cfab656d7
--- /dev/null
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json
@@ -0,0 +1,399 @@
+{
+ "constraints__clocks__count": 1,
+ "constraints__clocks__details": [
+ "clk_core: 20.0000"
+ ],
+ "cts__clock__skew__hold": 0.416925,
+ "cts__clock__skew__setup": 0.416925,
+ "cts__cpu__total": 1.74,
+ "cts__design__core__area": 121187,
+ "cts__design__die__area": 1102500.0,
+ "cts__design__instance__area": 36578.3,
+ "cts__design__instance__area__cover": 98000,
+ "cts__design__instance__area__macros": 21794.6,
+ "cts__design__instance__area__padcells": 424800,
+ "cts__design__instance__area__stdcell": 14783.7,
+ "cts__design__instance__count": 985,
+ "cts__design__instance__count__cover": 20,
+ "cts__design__instance__count__hold_buffer": 0,
+ "cts__design__instance__count__macros": 1,
+ "cts__design__instance__count__padcells": 48,
+ "cts__design__instance__count__setup_buffer": 0,
+ "cts__design__instance__count__stdcell": 916,
+ "cts__design__instance__displacement__max": 0,
+ "cts__design__instance__displacement__mean": 0,
+ "cts__design__instance__displacement__total": 0,
+ "cts__design__instance__utilization": 0.301833,
+ "cts__design__instance__utilization__stdcell": 0.14874,
+ "cts__design__io": 20,
+ "cts__design__rows": 133,
+ "cts__design__rows:CoreSite": 133,
+ "cts__design__sites": 53754,
+ "cts__design__sites:CoreSite": 53754,
+ "cts__design__violations": 0,
+ "cts__flow__errors__count": 0,
+ "cts__flow__warnings__count": 1,
+ "cts__mem__peak": 223804.0,
+ "cts__power__internal__total": 6.36515e-05,
+ "cts__power__leakage__total": 6.15849e-07,
+ "cts__power__switching__total": 1.14976e-05,
+ "cts__power__total": 7.5765e-05,
+ "cts__route__wirelength__estimated": 32399.4,
+ "cts__runtime__total": "0:01.36",
+ "cts__timing__drv__hold_violation_count": 0,
+ "cts__timing__drv__max_cap": 27,
+ "cts__timing__drv__max_cap_limit": -9.58431,
+ "cts__timing__drv__max_fanout": 0,
+ "cts__timing__drv__max_fanout_limit": 8,
+ "cts__timing__drv__max_slew": 25,
+ "cts__timing__drv__max_slew_limit": -5.32153,
+ "cts__timing__drv__setup_violation_count": 0,
+ "cts__timing__hold__tns": 0,
+ "cts__timing__hold__ws": 0.0665765,
+ "cts__timing__setup__tns": 0,
+ "cts__timing__setup__ws": 3.44505,
+ "design__violations": 0,
+ "detailedplace__cpu__total": 0.94,
+ "detailedplace__design__core__area": 121187,
+ "detailedplace__design__die__area": 1102500.0,
+ "detailedplace__design__instance__area": 34050.8,
+ "detailedplace__design__instance__area__cover": 98000,
+ "detailedplace__design__instance__area__macros": 21794.6,
+ "detailedplace__design__instance__area__padcells": 424800,
+ "detailedplace__design__instance__area__stdcell": 12256.3,
+ "detailedplace__design__instance__count": 924,
+ "detailedplace__design__instance__count__cover": 20,
+ "detailedplace__design__instance__count__macros": 1,
+ "detailedplace__design__instance__count__padcells": 48,
+ "detailedplace__design__instance__count__stdcell": 855,
+ "detailedplace__design__instance__displacement__max": 13.101,
+ "detailedplace__design__instance__displacement__mean": 3.157,
+ "detailedplace__design__instance__displacement__total": 2702.6,
+ "detailedplace__design__instance__utilization": 0.280977,
+ "detailedplace__design__instance__utilization__stdcell": 0.123311,
+ "detailedplace__design__io": 20,
+ "detailedplace__design__rows": 133,
+ "detailedplace__design__rows:CoreSite": 133,
+ "detailedplace__design__sites": 53754,
+ "detailedplace__design__sites:CoreSite": 53754,
+ "detailedplace__design__violations": 0,
+ "detailedplace__flow__errors__count": 0,
+ "detailedplace__flow__warnings__count": 1,
+ "detailedplace__mem__peak": 126980.0,
+ "detailedplace__power__internal__total": 3.34988e-05,
+ "detailedplace__power__leakage__total": 3.57528e-07,
+ "detailedplace__power__switching__total": 6.76419e-06,
+ "detailedplace__power__total": 4.06205e-05,
+ "detailedplace__route__wirelength__estimated": 27769.5,
+ "detailedplace__runtime__total": "0:00.70",
+ "detailedplace__timing__drv__hold_violation_count": 0,
+ "detailedplace__timing__drv__max_cap": 27,
+ "detailedplace__timing__drv__max_cap_limit": -9.58431,
+ "detailedplace__timing__drv__max_fanout": 0,
+ "detailedplace__timing__drv__max_fanout_limit": 8,
+ "detailedplace__timing__drv__max_slew": 25,
+ "detailedplace__timing__drv__max_slew_limit": -5.32153,
+ "detailedplace__timing__drv__setup_violation_count": 0,
+ "detailedplace__timing__hold__tns": 0,
+ "detailedplace__timing__hold__ws": 0.0614673,
+ "detailedplace__timing__setup__tns": 0,
+ "detailedplace__timing__setup__ws": 3.44505,
+ "detailedroute__antenna__violating__nets": 0,
+ "detailedroute__antenna__violating__pins": 0,
+ "detailedroute__antenna_diodes_count": 2,
+ "detailedroute__flow__errors__count": 0,
+ "detailedroute__flow__warnings__count": 11,
+ "detailedroute__route__drc_errors": 0,
+ "detailedroute__route__drc_errors__iter:0": 6,
+ "detailedroute__route__drc_errors__iter:1": 1,
+ "detailedroute__route__drc_errors__iter:2": 0,
+ "detailedroute__route__drc_errors__iter:3": 27,
+ "detailedroute__route__drc_errors__iter:4": 3,
+ "detailedroute__route__drc_errors__iter:5": 0,
+ "detailedroute__route__net": 1062,
+ "detailedroute__route__net__special": 24,
+ "detailedroute__route__vias": 6330,
+ "detailedroute__route__vias__multicut": 0,
+ "detailedroute__route__vias__singlecut": 6330,
+ "detailedroute__route__wirelength": 37033,
+ "detailedroute__route__wirelength__iter:0": 37038,
+ "detailedroute__route__wirelength__iter:1": 37035,
+ "detailedroute__route__wirelength__iter:2": 37033,
+ "detailedroute__route__wirelength__iter:3": 37018,
+ "detailedroute__route__wirelength__iter:4": 37007,
+ "detailedroute__route__wirelength__iter:5": 37012,
+ "finish__clock__skew__hold": 0.48647,
+ "finish__clock__skew__setup": 0.462837,
+ "finish__cpu__total": 4.47,
+ "finish__design__core__area": 121187,
+ "finish__design__die__area": 1102500.0,
+ "finish__design__instance__area": 118272,
+ "finish__design__instance__area__class:antenna_cell": 576.979,
+ "finish__design__instance__area__class:clock_buffer": 2494.8,
+ "finish__design__instance__area__class:clock_inverter": 32.6592,
+ "finish__design__instance__area__class:cover": 98000,
+ "finish__design__instance__area__class:input_output_pad": 144000,
+ "finish__design__instance__area__class:input_pad": 72000,
+ "finish__design__instance__area__class:inverter": 154.224,
+ "finish__design__instance__area__class:macro": 21794.6,
+ "finish__design__instance__area__class:multi_input_combinational_cell": 5889.54,
+ "finish__design__instance__area__class:output_pad": 14400,
+ "finish__design__instance__area__class:pad_spacer": 136800,
+ "finish__design__instance__area__class:power_pad": 57600,
+ "finish__design__instance__area__class:sequential_cell": 5755.28,
+ "finish__design__instance__area__class:timing_repair_buffer": 457.229,
+ "finish__design__instance__area__cover": 98000,
+ "finish__design__instance__area__macros": 21794.6,
+ "finish__design__instance__area__padcells": 424800,
+ "finish__design__instance__area__stdcell": 96477.1,
+ "finish__design__instance__count": 7518,
+ "finish__design__instance__count__class:antenna_cell": 106,
+ "finish__design__instance__count__class:clock_buffer": 55,
+ "finish__design__instance__count__class:clock_inverter": 6,
+ "finish__design__instance__count__class:cover": 20,
+ "finish__design__instance__count__class:input_output_pad": 10,
+ "finish__design__instance__count__class:input_pad": 5,
+ "finish__design__instance__count__class:inverter": 28,
+ "finish__design__instance__count__class:macro": 1,
+ "finish__design__instance__count__class:multi_input_combinational_cell": 642,
+ "finish__design__instance__count__class:output_pad": 1,
+ "finish__design__instance__count__class:pad_spacer": 28,
+ "finish__design__instance__count__class:power_pad": 4,
+ "finish__design__instance__count__class:sequential_cell": 122,
+ "finish__design__instance__count__class:timing_repair_buffer": 63,
+ "finish__design__instance__count__cover": 20,
+ "finish__design__instance__count__macros": 1,
+ "finish__design__instance__count__padcells": 48,
+ "finish__design__instance__count__stdcell": 7449,
+ "finish__design__instance__utilization": 0.97594,
+ "finish__design__instance__utilization__stdcell": 0.970664,
+ "finish__design__io": 20,
+ "finish__design__rows": 133,
+ "finish__design__rows:CoreSite": 133,
+ "finish__design__sites": 53754,
+ "finish__design__sites:CoreSite": 53754,
+ "finish__design_powergrid__drop__average__net:VDD__corner:fast": 1.19999,
+ "finish__design_powergrid__drop__average__net:VSS__corner:fast": 5.72021e-06,
+ "finish__design_powergrid__drop__worst__net:VDD__corner:fast": 3.33034e-05,
+ "finish__design_powergrid__drop__worst__net:VSS__corner:fast": 2.81877e-05,
+ "finish__design_powergrid__voltage__worst__net:VDD__corner:fast": 1.19997,
+ "finish__design_powergrid__voltage__worst__net:VSS__corner:fast": 2.81877e-05,
+ "finish__flow__errors__count": 0,
+ "finish__flow__warnings__count": 2,
+ "finish__mem__peak": 266520.0,
+ "finish__power__internal__total": 5.79117e-05,
+ "finish__power__leakage__total": 1.87494e-06,
+ "finish__power__switching__total": 1.32977e-05,
+ "finish__power__total": 7.30843e-05,
+ "finish__runtime__total": "0:04.06",
+ "finish__timing__drv__hold_violation_count": 0,
+ "finish__timing__drv__max_cap": 27,
+ "finish__timing__drv__max_cap_limit": -9.58431,
+ "finish__timing__drv__max_fanout": 3,
+ "finish__timing__drv__max_fanout_limit": 8,
+ "finish__timing__drv__max_slew": 25,
+ "finish__timing__drv__max_slew_limit": -5.32041,
+ "finish__timing__drv__setup_violation_count": 0,
+ "finish__timing__hold__tns": 0,
+ "finish__timing__hold__ws": 0.033864,
+ "finish__timing__setup__tns": 0,
+ "finish__timing__setup__ws": 3.88761,
+ "finish__timing__wns_percent_delay": 48.824475,
+ "finish_merge__cpu__total": 1.38,
+ "finish_merge__mem__peak": 473592.0,
+ "finish_merge__runtime__total": "0:01.53",
+ "floorplan__cpu__total": 0.63,
+ "floorplan__design__core__area": 121187,
+ "floorplan__design__die__area": 1102500.0,
+ "floorplan__design__instance__area": 33045.7,
+ "floorplan__design__instance__area__cover": 98000,
+ "floorplan__design__instance__area__macros": 21794.6,
+ "floorplan__design__instance__area__padcells": 424800,
+ "floorplan__design__instance__area__stdcell": 11251.1,
+ "floorplan__design__instance__count": 754,
+ "floorplan__design__instance__count__cover": 20,
+ "floorplan__design__instance__count__hold_buffer": 0,
+ "floorplan__design__instance__count__macros": 1,
+ "floorplan__design__instance__count__padcells": 48,
+ "floorplan__design__instance__count__setup_buffer": 0,
+ "floorplan__design__instance__count__stdcell": 685,
+ "floorplan__design__instance__utilization": 0.272682,
+ "floorplan__design__instance__utilization__stdcell": 0.113198,
+ "floorplan__design__io": 20,
+ "floorplan__design__rows": 92,
+ "floorplan__design__rows:CoreSite": 92,
+ "floorplan__design__sites": 66792,
+ "floorplan__design__sites:CoreSite": 66792,
+ "floorplan__flow__errors__count": 0,
+ "floorplan__flow__warnings__count": 7,
+ "floorplan__mem__peak": 116856.0,
+ "floorplan__power__internal__total": 3.26237e-05,
+ "floorplan__power__leakage__total": 3.66049e-07,
+ "floorplan__power__switching__total": 4.05039e-06,
+ "floorplan__power__total": 3.70401e-05,
+ "floorplan__runtime__total": "0:00.45",
+ "floorplan__timing__hold__tns": 0,
+ "floorplan__timing__hold__ws": 0.0483089,
+ "floorplan__timing__setup__tns": 0,
+ "floorplan__timing__setup__ws": 3.57371,
+ "flow__errors__count": 0,
+ "flow__warnings__count": 1,
+ "globalplace__cpu__total": 14.31,
+ "globalplace__design__core__area": 121187,
+ "globalplace__design__die__area": 1102500.0,
+ "globalplace__design__instance__area": 32911.4,
+ "globalplace__design__instance__area__cover": 98000,
+ "globalplace__design__instance__area__macros": 21794.6,
+ "globalplace__design__instance__area__padcells": 424800,
+ "globalplace__design__instance__area__stdcell": 11116.8,
+ "globalplace__design__instance__count": 767,
+ "globalplace__design__instance__count__cover": 20,
+ "globalplace__design__instance__count__macros": 1,
+ "globalplace__design__instance__count__padcells": 48,
+ "globalplace__design__instance__count__stdcell": 698,
+ "globalplace__design__instance__utilization": 0.271574,
+ "globalplace__design__instance__utilization__stdcell": 0.111847,
+ "globalplace__design__io": 20,
+ "globalplace__design__rows": 133,
+ "globalplace__design__rows:CoreSite": 133,
+ "globalplace__design__sites": 53754,
+ "globalplace__design__sites:CoreSite": 53754,
+ "globalplace__flow__errors__count": 0,
+ "globalplace__flow__warnings__count": 1,
+ "globalplace__mem__peak": 701500.0,
+ "globalplace__power__internal__total": 3.35075e-05,
+ "globalplace__power__leakage__total": 3.55326e-07,
+ "globalplace__power__switching__total": 6.72037e-06,
+ "globalplace__power__total": 4.05832e-05,
+ "globalplace__runtime__total": "0:02.59",
+ "globalplace__timing__hold__tns": 0,
+ "globalplace__timing__hold__ws": 0.0627901,
+ "globalplace__timing__setup__tns": 0,
+ "globalplace__timing__setup__ws": 3.44505,
+ "globalplace_io__cpu__total": 0.09,
+ "globalplace_io__mem__peak": 98292.0,
+ "globalplace_io__runtime__total": "0:00.12",
+ "globalplace_skip_io__cpu__total": 8.01,
+ "globalplace_skip_io__mem__peak": 114176.0,
+ "globalplace_skip_io__runtime__total": "0:00.70",
+ "globalroute__antenna__violating__nets": 2,
+ "globalroute__antenna__violating__pins": 4,
+ "globalroute__antenna_diodes_count": 104,
+ "globalroute__clock__skew__hold": 0.507695,
+ "globalroute__clock__skew__setup": 0.471571,
+ "globalroute__cpu__total": 40.2,
+ "globalroute__design__core__area": 121187,
+ "globalroute__design__die__area": 1102500.0,
+ "globalroute__design__instance__area": 37144.4,
+ "globalroute__design__instance__area__cover": 98000,
+ "globalroute__design__instance__area__macros": 21794.6,
+ "globalroute__design__instance__area__padcells": 424800,
+ "globalroute__design__instance__area__stdcell": 15349.8,
+ "globalroute__design__instance__count": 1089,
+ "globalroute__design__instance__count__cover": 20,
+ "globalroute__design__instance__count__hold_buffer": 0,
+ "globalroute__design__instance__count__macros": 1,
+ "globalroute__design__instance__count__padcells": 48,
+ "globalroute__design__instance__count__setup_buffer": 0,
+ "globalroute__design__instance__count__stdcell": 1020,
+ "globalroute__design__instance__displacement__max": 0,
+ "globalroute__design__instance__displacement__mean": 0,
+ "globalroute__design__instance__displacement__total": 0,
+ "globalroute__design__instance__utilization": 0.306504,
+ "globalroute__design__instance__utilization__stdcell": 0.154436,
+ "globalroute__design__io": 20,
+ "globalroute__design__rows": 133,
+ "globalroute__design__rows:CoreSite": 133,
+ "globalroute__design__sites": 53754,
+ "globalroute__design__sites:CoreSite": 53754,
+ "globalroute__design__violations": 0,
+ "globalroute__flow__errors__count": 0,
+ "globalroute__flow__warnings__count": 11,
+ "globalroute__mem__peak": 751424.0,
+ "globalroute__power__internal__total": 5.83437e-05,
+ "globalroute__power__leakage__total": 6.16393e-07,
+ "globalroute__power__switching__total": 1.5735e-05,
+ "globalroute__power__total": 7.46951e-05,
+ "globalroute__route__net": 1062,
+ "globalroute__route__net__special": 24,
+ "globalroute__route__wirelength__estimated": 32399.4,
+ "globalroute__runtime__total": "0:05.61",
+ "globalroute__timing__clock__slack": 3.812,
+ "globalroute__timing__drv__hold_violation_count": 0,
+ "globalroute__timing__drv__max_cap": 27,
+ "globalroute__timing__drv__max_cap_limit": -9.58431,
+ "globalroute__timing__drv__max_fanout": 3,
+ "globalroute__timing__drv__max_fanout_limit": 8,
+ "globalroute__timing__drv__max_slew": 25,
+ "globalroute__timing__drv__max_slew_limit": -5.32154,
+ "globalroute__timing__drv__setup_violation_count": 0,
+ "globalroute__timing__hold__tns": 0,
+ "globalroute__timing__hold__ws": 0.0494376,
+ "globalroute__timing__setup__tns": 0,
+ "globalroute__timing__setup__ws": 3.81203,
+ "placeopt__cpu__total": 1.15,
+ "placeopt__design__core__area": 121187,
+ "placeopt__design__die__area": 1102500.0,
+ "placeopt__design__instance__area": 34050.8,
+ "placeopt__design__instance__area__cover": 98000,
+ "placeopt__design__instance__area__macros": 21794.6,
+ "placeopt__design__instance__area__padcells": 424800,
+ "placeopt__design__instance__area__stdcell": 12256.3,
+ "placeopt__design__instance__count": 924,
+ "placeopt__design__instance__count__cover": 20,
+ "placeopt__design__instance__count__macros": 1,
+ "placeopt__design__instance__count__padcells": 48,
+ "placeopt__design__instance__count__stdcell": 855,
+ "placeopt__design__instance__utilization": 0.280977,
+ "placeopt__design__instance__utilization__stdcell": 0.123311,
+ "placeopt__design__io": 20,
+ "placeopt__design__rows": 133,
+ "placeopt__design__rows:CoreSite": 133,
+ "placeopt__design__sites": 53754,
+ "placeopt__design__sites:CoreSite": 53754,
+ "placeopt__flow__errors__count": 0,
+ "placeopt__flow__warnings__count": 2,
+ "placeopt__mem__peak": 641056.0,
+ "placeopt__power__internal__total": 3.35075e-05,
+ "placeopt__power__leakage__total": 3.57528e-07,
+ "placeopt__power__switching__total": 1.18703e-05,
+ "placeopt__power__total": 4.57353e-05,
+ "placeopt__runtime__total": "0:00.88",
+ "placeopt__timing__drv__floating__nets": 4,
+ "placeopt__timing__drv__floating__pins": 0,
+ "placeopt__timing__drv__hold_violation_count": 0,
+ "placeopt__timing__drv__max_cap": 27,
+ "placeopt__timing__drv__max_cap_limit": -9.58431,
+ "placeopt__timing__drv__max_fanout": 0,
+ "placeopt__timing__drv__max_fanout_limit": 8,
+ "placeopt__timing__drv__max_slew": 25,
+ "placeopt__timing__drv__max_slew_limit": -5.32153,
+ "placeopt__timing__drv__setup_violation_count": 0,
+ "placeopt__timing__hold__tns": 0,
+ "placeopt__timing__hold__ws": 0.0627901,
+ "placeopt__timing__setup__tns": 0,
+ "placeopt__timing__setup__ws": 3.44505,
+ "run__flow__design": "i2c-gpio-expander",
+ "run__flow__generate_date": "2025-06-27 17:15",
+ "run__flow__metrics_version": "Metrics_2.1.2",
+ "run__flow__openroad_commit": "N/A",
+ "run__flow__openroad_version": "v2.0-18663-g4a7c6dd8f",
+ "run__flow__platform": "ihp-sg13g2",
+ "run__flow__platform__capacitance_units": "1pF",
+ "run__flow__platform__current_units": "1uA",
+ "run__flow__platform__distance_units": "1um",
+ "run__flow__platform__power_units": "1pW",
+ "run__flow__platform__resistance_units": "1kohm",
+ "run__flow__platform__time_units": "1ns",
+ "run__flow__platform__voltage_units": "1v",
+ "run__flow__platform_commit": "2b92477257a655e1c3d56c83372e3ea6262fc7e1",
+ "run__flow__scripts_commit": "2b92477257a655e1c3d56c83372e3ea6262fc7e1",
+ "run__flow__uuid": "a55e4f22-7f3b-48eb-84a6-b10f6fde9a2a",
+ "run__flow__variant": "base",
+ "synth__cpu__total": 0.88,
+ "synth__design__instance__area__stdcell": 253699.051,
+ "synth__design__instance__count__stdcell": 702.0,
+ "synth__mem__peak": 26056.0,
+ "synth__runtime__total": "0:00.90",
+ "total_time": "0:00:18.900000"
+}
\ No newline at end of file
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl
index 5ed1a981fa..2e2773ec98 100644
--- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl
@@ -2,45 +2,46 @@ set IO_LENGTH 180
set IO_WIDTH 80
set BONDPAD_SIZE 70
set SEALRING_OFFSET 70
+set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }]
-proc calc_horizontal_pad_location {index total} {
- global IO_LENGTH
- global IO_WIDTH
- global BONDPAD_SIZE
- global SEALRING_OFFSET
+proc calc_horizontal_pad_location { index total } {
+ global IO_LENGTH
+ global IO_WIDTH
+ global BONDPAD_SIZE
+ global SEALRING_OFFSET
- set DIE_WIDTH [expr {[lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0]}]
- set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}]
- set PAD_AREA_WIDTH [expr {$DIE_WIDTH - ($PAD_OFFSET * 2)}]
- set HORIZONTAL_PAD_DISTANCE [expr {($PAD_AREA_WIDTH / $total) - $IO_WIDTH}]
+ set DIE_WIDTH [expr { [lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0] }]
+ set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }]
+ set PAD_AREA_WIDTH [expr { $DIE_WIDTH - ($PAD_OFFSET * 2) }]
+ set HORIZONTAL_PAD_DISTANCE [expr { ($PAD_AREA_WIDTH / $total) - $IO_WIDTH }]
- return [expr {$PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2)}]
+ return [expr { $PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2) }]
}
-proc calc_vertical_pad_location {index total} {
- global IO_LENGTH
- global IO_WIDTH
- global BONDPAD_SIZE
- global SEALRING_OFFSET
+proc calc_vertical_pad_location { index total } {
+ global IO_LENGTH
+ global IO_WIDTH
+ global BONDPAD_SIZE
+ global SEALRING_OFFSET
- set DIE_HEIGHT [expr {[lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1]}]
- set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}]
- set PAD_AREA_HEIGHT [expr {$DIE_HEIGHT - ($PAD_OFFSET * 2)}]
- set VERTICAL_PAD_DISTANCE [expr {($PAD_AREA_HEIGHT / $total) - $IO_WIDTH}]
+ set DIE_HEIGHT [expr { [lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1] }]
+ set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }]
+ set PAD_AREA_HEIGHT [expr { $DIE_HEIGHT - ($PAD_OFFSET * 2) }]
+ set VERTICAL_PAD_DISTANCE [expr { ($PAD_AREA_HEIGHT / $total) - $IO_WIDTH }]
- return [expr {$PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2)}]
+ return [expr { $PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2) }]
}
make_fake_io_site -name IOLibSite -width 1 -height $IO_LENGTH
make_fake_io_site -name IOLibCSite -width $IO_LENGTH -height $IO_LENGTH
-set IO_OFFSET [expr {$BONDPAD_SIZE + $SEALRING_OFFSET}]
+set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }]
# Create IO Rows
make_io_sites \
- -horizontal_site IOLibSite \
- -vertical_site IOLibSite \
- -corner_site IOLibCSite \
- -offset $IO_OFFSET
+ -horizontal_site IOLibSite \
+ -vertical_site IOLibSite \
+ -corner_site IOLibCSite \
+ -offset $IO_OFFSET
# Place Pads\n# IO pin io_clock
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0 5] {sg13g2_IOPad_io_clock} -master sg13g2_IOPadIn
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl
index 0534bb5bde..8e205d1c13 100644
--- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl
@@ -1,12 +1,16 @@
-
-# stdcell power pins
+# standard cells
add_global_connection -net {VDD} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -pin_pattern {^VDDCE$}
-
add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -pin_pattern {^VSSE$}
+# macros
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power
+add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
+add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
+
# padframe core power pins
add_global_connection -net {VDD} -pin_pattern {^vdd$} -power
add_global_connection -net {VSS} -pin_pattern {^vss$} -ground
@@ -22,43 +26,15 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
# stdcell grid
define_pdn_grid -name {grid} -voltage_domains {CORE}
-add_pdn_ring \
- -grid {grid} \
- -layers {Metal5 TopMetal1} \
- -widths {30.0} \
- -spacings {5.0} \
- -core_offsets {4.5} \
- -connect_to_pads
-add_pdn_stripe \
- -grid {grid} \
- -layer {Metal1} \
- -width {0.44} \
- -pitch {7.56} \
- -offset {0} \
- -followpins \
- -extend_to_core_ring
-add_pdn_stripe \
- -grid {grid} \
- -layer {Metal5} \
- -width {2.200} \
- -pitch {75.6} \
- -offset {13.600} \
- -extend_to_core_ring
-add_pdn_stripe \
- -grid {grid} \
- -layer {TopMetal1} \
- -width {2.200} \
- -pitch {75.6} \
- -offset {13.600} \
- -extend_to_core_ring
-add_pdn_stripe \
- -grid {grid} \
- -layer {TopMetal2} \
- -width {2.200} \
- -pitch {75.6} \
- -offset {13.600} \
- -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring
+add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} -core_offsets {4.5} -connect_to_pads
+add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} -extend_to_core_ring
add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2}
add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2}
+
+define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -cells {I2cDeviceCtrl} -grid_over_boundary
+add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal3 TopMetal1}
+add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal4 TopMetal1}
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json
index e3879ba092..0d62bb9a3a 100644
--- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json
+++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 23061,
+ "value": 39158,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 1601,
+ "value": 983,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,19 +20,19 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 139,
+ "value": 86,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 139,
+ "value": 86,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 2,
+ "value": 156,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 60953,
+ "value": 42588,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 44275,
+ "value": 136013,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 70,
+ "value": 43,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc
index a4faf836eb..979e0b0b28 100644
--- a/flow/designs/ihp-sg13g2/ibex/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/ibex/constraint.sdc
@@ -1,6 +1,6 @@
current_design ibex_core
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 10.0
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc
index e169d10114..31ddde31d7 100644
--- a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc
+++ b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc
@@ -1,5 +1,5 @@
set uncertainty 1.0
-set io_delay 7.0
+set io_delay 7.0
set clock_port clk_i
@@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl
set_clock_uncertainty $uncertainty [all_clocks]
#
-set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs]
-set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs]
+set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs]
+set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json
index 8b520ea9ec..36f121e565 100644
--- a/flow/designs/ihp-sg13g2/ibex/rules-base.json
+++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 0,
+ "value": 3,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1194089,
+ "value": 1072557,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,7 +44,7 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 51,
+ "value": 32,
"compare": "<="
},
"finish__timing__setup__ws": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 986,
+ "value": 906,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc
index 879a3ef4b4..923cf1199f 100644
--- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc
@@ -1,8 +1,8 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 8.0
+set clk_period 8.0
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json
index bf2a834c15..913c3fa3c8 100644
--- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json
+++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 87671,
+ "value": 86736,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 27,
+ "value": 4,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 3188482,
+ "value": 3140459,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,7 +44,7 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 160,
+ "value": 134,
"compare": "<="
},
"finish__timing__setup__ws": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 3812,
+ "value": 3771,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc
index 72adf7e57f..5b0a6f1b4e 100644
--- a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc
@@ -1,4 +1,4 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 6.0
set clk_io_pct 0.2
@@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [list]
foreach input [all_inputs] {
- if {$clk_port != $input} {
- lappend $non_clock_inputs $input
- }
+ if { $clk_port != $input } {
+ lappend $non_clock_inputs $input
+ }
}
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json
index d782c9d2ef..4a5905cd8e 100644
--- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json
+++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 177178,
+ "value": 171401,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 770173,
+ "value": 534072,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,11 +44,11 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 33,
+ "value": 5,
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.4,
+ "value": 0.0,
"compare": ">="
},
"finish__design__instance__area": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 523,
+ "value": 478,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -12.48,
+ "value": -10.0,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc
index 5c7d8643e9..225f73938c 100644
--- a/flow/designs/ihp-sg13g2/spi/constraint.sdc
+++ b/flow/designs/ihp-sg13g2/spi/constraint.sdc
@@ -1,6 +1,6 @@
current_design spi
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
set clk_period 0.9
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json
index cd53421bf4..48f784b4d5 100644
--- a/flow/designs/ihp-sg13g2/spi/rules-base.json
+++ b/flow/designs/ihp-sg13g2/spi/rules-base.json
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 5088,
+ "value": 4888,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.25,
+ "value": -0.09,
"compare": ">="
},
"finish__design__instance__area": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 17,
+ "value": 10,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -21.65,
+ "value": -15.68,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/aes/config.mk b/flow/designs/nangate45/aes/config.mk
index f653445292..7008a46a9f 100644
--- a/flow/designs/nangate45/aes/config.mk
+++ b/flow/designs/nangate45/aes/config.mk
@@ -11,3 +11,5 @@ export PLACE_DENSITY_LB_ADDON = 0.20
export TNS_END_PERCENT = 100
export REMOVE_CELLS_FOR_EQY = TAPCELL*
+# workaround for high congestion in post-grt repair
+export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc
index 6bf0879d5b..d7b8414c8e 100644
--- a/flow/designs/nangate45/aes/constraint.sdc
+++ b/flow/designs/nangate45/aes/constraint.sdc
@@ -1,8 +1,8 @@
current_design aes_cipher_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 0.82
+set clk_period 0.82
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/aes/rules-base.json b/flow/designs/nangate45/aes/rules-base.json
index a927b19b33..65c5fac049 100644
--- a/flow/designs/nangate45/aes/rules-base.json
+++ b/flow/designs/nangate45/aes/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 27558,
+ "value": 26514,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 351027,
+ "value": 298800,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.11,
+ "value": -0.06,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 30793,
+ "value": 27064,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -18.58,
+ "value": -13.22,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json
index 4c7ede902a..00369c0887 100644
--- a/flow/designs/nangate45/ariane133/rules-base.json
+++ b/flow/designs/nangate45/ariane133/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 872735,
+ "value": 871517,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 9590764,
+ "value": 8921456,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.26,
+ "value": -0.22,
"compare": ">="
},
"finish__design__instance__area": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -11.6,
+ "value": -10.68,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/ariane136/constraint.sdc b/flow/designs/nangate45/ariane136/constraint.sdc
index e0f4e320df..34dd047647 100644
--- a/flow/designs/nangate45/ariane136/constraint.sdc
+++ b/flow/designs/nangate45/ariane136/constraint.sdc
@@ -1,496 +1,496 @@
-create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3}
-set_input_delay -clock core_clock 0 [get_ports clk_i]
-set_input_delay -clock core_clock 0 [get_ports rst_ni]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}]
-set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}]
-set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}]
-set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}]
-set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}]
-set_input_delay -clock core_clock 0 [get_ports ipi_i]
-set_input_delay -clock core_clock 0 [get_ports time_irq_i]
-set_input_delay -clock core_clock 0 [get_ports debug_req_i]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}]
-set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}]
-set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}]
+create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3}
+set_input_delay -clock core_clock 0 [get_ports clk_i]
+set_input_delay -clock core_clock 0 [get_ports rst_ni]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}]
+set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}]
+set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}]
+set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}]
+set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}]
+set_input_delay -clock core_clock 0 [get_ports ipi_i]
+set_input_delay -clock core_clock 0 [get_ports time_irq_i]
+set_input_delay -clock core_clock 0 [get_ports debug_req_i]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}]
+set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}]
+set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}]
diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json
index 15c6bdf6f2..8f69cae835 100644
--- a/flow/designs/nangate45/ariane136/rules-base.json
+++ b/flow/designs/nangate45/ariane136/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 897767,
+ "value": 889812,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 9221377,
+ "value": 8032745,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -52,7 +52,7 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 904162,
+ "value": 902506,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 178,
+ "value": 106,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
diff --git a/flow/designs/nangate45/black_parrot/constraint.sdc b/flow/designs/nangate45/black_parrot/constraint.sdc
index d6a53ebbd8..a5514ffe49 100644
--- a/flow/designs/nangate45/black_parrot/constraint.sdc
+++ b/flow/designs/nangate45/black_parrot/constraint.sdc
@@ -1,4 +1,4 @@
-set clk_name CLK
+set clk_name CLK
set clk_port_name clk_i
set clk_period 6.0
set clk_io_pct 0.2
@@ -9,2397 +9,2397 @@ set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port
-set_input_delay -clock CLK -max 3.42 [get_ports reset_i]
-set_input_delay -clock CLK -min $min_arrival [get_ports reset_i]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}]
-set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}]
-set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}]
-set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}]
-set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}]
+set_input_delay -clock CLK -max 3.42 [get_ports reset_i]
+set_input_delay -clock CLK -min $min_arrival [get_ports reset_i]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}]
+set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}]
+set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}]
+set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}]
+set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}]
diff --git a/flow/designs/nangate45/black_parrot/rules-base.json b/flow/designs/nangate45/black_parrot/rules-base.json
index 525c71aac8..2ff95a60b1 100644
--- a/flow/designs/nangate45/black_parrot/rules-base.json
+++ b/flow/designs/nangate45/black_parrot/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 857876,
+ "value": 816555,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 299499,
+ "value": 280905,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 26043,
+ "value": 24426,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 26043,
+ "value": 24426,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 8591633,
+ "value": 7165555,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -3.63,
+ "value": -3.58,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 870913,
+ "value": 832384,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 13022,
+ "value": 12213,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/nangate45/bp_be_top/constraint.sdc b/flow/designs/nangate45/bp_be_top/constraint.sdc
index 632222055a..3df6fe408f 100644
--- a/flow/designs/nangate45/bp_be_top/constraint.sdc
+++ b/flow/designs/nangate45/bp_be_top/constraint.sdc
@@ -1,6058 +1,6057 @@
-
-create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3}
-set_input_delay -clock CLK -max 0.6 [get_ports reset_i]
-set_input_delay -clock CLK -min 0.6 [get_ports reset_i]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}]
-set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i]
-set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i]
-set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i]
-set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i]
-set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i]
-set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i]
-set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}]
-set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o]
-set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o]
-set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o]
-set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o]
-set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o]
-set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o]
-set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o]
-set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o]
-set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o]
-set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}]
-set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}]
+create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3}
+set_input_delay -clock CLK -max 0.6 [get_ports reset_i]
+set_input_delay -clock CLK -min 0.6 [get_ports reset_i]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}]
+set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i]
+set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i]
+set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i]
+set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i]
+set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i]
+set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i]
+set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}]
+set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o]
+set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o]
+set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o]
+set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o]
+set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o]
+set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o]
+set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o]
+set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o]
+set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o]
+set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}]
+set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}]
diff --git a/flow/designs/nangate45/bp_be_top/io.tcl b/flow/designs/nangate45/bp_be_top/io.tcl
index b3bbef4631..713f1d0db0 100644
--- a/flow/designs/nangate45/bp_be_top/io.tcl
+++ b/flow/designs/nangate45/bp_be_top/io.tcl
@@ -1 +1 @@
-exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:*
\ No newline at end of file
+exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:*
diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json
index f69d95f09a..f886e74244 100644
--- a/flow/designs/nangate45/bp_be_top/rules-base.json
+++ b/flow/designs/nangate45/bp_be_top/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 298541,
+ "value": 288926,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 63823,
+ "value": 62588,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 5550,
+ "value": 5442,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 5550,
+ "value": 5442,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.51,
+ "value": -0.35,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 302367,
+ "value": 290373,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 2775,
+ "value": 2721,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -29.19,
+ "value": -22.31,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/bp_fe_top/constraint.sdc b/flow/designs/nangate45/bp_fe_top/constraint.sdc
index b2d5405cf1..7428491fbe 100644
--- a/flow/designs/nangate45/bp_fe_top/constraint.sdc
+++ b/flow/designs/nangate45/bp_fe_top/constraint.sdc
@@ -1,4 +1,3 @@
-
set clk_period 1.8
create_clock [get_ports clk_i] -name CLK -period $clk_period
set io_delay [expr $clk_period * .2]
diff --git a/flow/designs/nangate45/bp_fe_top/io.tcl b/flow/designs/nangate45/bp_fe_top/io.tcl
index 8e24fc28ea..82d99e921d 100644
--- a/flow/designs/nangate45/bp_fe_top/io.tcl
+++ b/flow/designs/nangate45/bp_fe_top/io.tcl
@@ -1 +1 @@
-exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:*
\ No newline at end of file
+exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:*
diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json
index aff5af09fd..c5bec52251 100644
--- a/flow/designs/nangate45/bp_fe_top/rules-base.json
+++ b/flow/designs/nangate45/bp_fe_top/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 261584,
+ "value": 252534,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 40888,
+ "value": 39729,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 3556,
+ "value": 3455,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 3556,
+ "value": 3455,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 2466638,
+ "value": 2081448,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 263398,
+ "value": 254470,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 1778,
+ "value": 1727,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/nangate45/bp_multi_top/constraint.sdc b/flow/designs/nangate45/bp_multi_top/constraint.sdc
index f9be728c02..24d87fe369 100644
--- a/flow/designs/nangate45/bp_multi_top/constraint.sdc
+++ b/flow/designs/nangate45/bp_multi_top/constraint.sdc
@@ -1,2906 +1,2905 @@
-
-create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4}
-set_input_delay -clock CLK -max 1.8 [get_ports reset_i]
-set_input_delay -clock CLK -min 0.6 [get_ports reset_i]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}]
-set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}]
-set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}]
-set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}]
+create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4}
+set_input_delay -clock CLK -max 1.8 [get_ports reset_i]
+set_input_delay -clock CLK -min 0.6 [get_ports reset_i]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}]
+set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}]
+set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}]
+set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}]
diff --git a/flow/designs/nangate45/bp_multi_top/io.tcl b/flow/designs/nangate45/bp_multi_top/io.tcl
index b2bdd9fce6..46c1375a1d 100644
--- a/flow/designs/nangate45/bp_multi_top/io.tcl
+++ b/flow/designs/nangate45/bp_multi_top/io.tcl
@@ -1 +1 @@
-exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:*
\ No newline at end of file
+exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:*
diff --git a/flow/designs/nangate45/bp_multi_top/rules-base.json b/flow/designs/nangate45/bp_multi_top/rules-base.json
index 0d705fc6c7..0f31b3dbc0 100644
--- a/flow/designs/nangate45/bp_multi_top/rules-base.json
+++ b/flow/designs/nangate45/bp_multi_top/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 622260,
+ "value": 607245,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 150268,
+ "value": 143977,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 13067,
+ "value": 12520,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 13067,
+ "value": 12520,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 4806328,
+ "value": 4291357,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -4.29,
+ "value": -4.2,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 629703,
+ "value": 616495,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 6533,
+ "value": 6260,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/nangate45/bp_quad/bsg_chip.sdc b/flow/designs/nangate45/bp_quad/bsg_chip.sdc
index 69ce39fe4b..ea9a593ed0 100644
--- a/flow/designs/nangate45/bp_quad/bsg_chip.sdc
+++ b/flow/designs/nangate45/bp_quad/bsg_chip.sdc
@@ -17,132 +17,132 @@ set mx_delay2 [expr ${l_clk_p2}*0.28]
set mn_delay1 [expr ${l_clk_p1}*0.02]
-set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \
--current uA
-create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3
-set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk]
-create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1
-set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk]
-create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1
-set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk]
-create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1
-set_clock_uncertainty $clk_uncertainty [get_clocks router_clk]
-create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2
-set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk]
-create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2
-set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk]
-create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2
-set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk]
-create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2
-set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk]
+set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \
+ -current uA
+create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3
+set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk]
+create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1
+set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk]
+create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1
+set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk]
+create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1
+set_clock_uncertainty $clk_uncertainty [get_clocks router_clk]
+create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2
+set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk]
+create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2
+set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk]
+create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2
+set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk]
+create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2
+set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk]
#
-set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \
-p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
-[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
-p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
-set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \
-p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
-[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
-p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
-set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \
-p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
-[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
-p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
-set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \
-p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
-[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
-p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
-set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk]
-set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i]
-set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i]
-set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i]
-set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i]
-set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i]
-set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i]
-set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i]
-set_timing_derate -early -cell_delay 0.97 [get_cells \
-{bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]
+set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \
+ p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
+ [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
+ p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
+set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \
+ p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \
+ [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \
+ p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]]
+set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \
+ p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
+ [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
+ p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
+set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \
+ p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \
+ [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \
+ p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]]
+set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk]
+set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i]
+set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i]
+set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i]
+set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i]
+set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i]
+set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i]
+set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i]
+set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i]
+set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i]
+set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i]
+set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i]
+set_timing_derate -early -cell_delay 0.97 [get_cells \
+ {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]
diff --git a/flow/designs/nangate45/bp_quad/io.tcl b/flow/designs/nangate45/bp_quad/io.tcl
index c368ed9bf9..c9e50c4b0a 100644
--- a/flow/designs/nangate45/bp_quad/io.tcl
+++ b/flow/designs/nangate45/bp_quad/io.tcl
@@ -1 +1 @@
-exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-1000 -region bottom:2400-3600
\ No newline at end of file
+exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-1000 -region bottom:2400-3600
diff --git a/flow/designs/nangate45/dynamic_node/rules-base.json b/flow/designs/nangate45/dynamic_node/rules-base.json
index bf896023ad..bdc31d60f5 100644
--- a/flow/designs/nangate45/dynamic_node/rules-base.json
+++ b/flow/designs/nangate45/dynamic_node/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 28233,
+ "value": 27551,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 13523,
+ "value": 12798,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 1176,
+ "value": 1113,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1176,
+ "value": 1113,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 261214,
+ "value": 354277,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 29582,
+ "value": 28843,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 588,
+ "value": 556,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc
index 57be8eb9c6..852fef6395 100644
--- a/flow/designs/nangate45/gcd/constraint.sdc
+++ b/flow/designs/nangate45/gcd/constraint.sdc
@@ -1,8 +1,8 @@
current_design gcd
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
-set clk_period 0.46
+set clk_period 0.46
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/gcd/rules-base.json b/flow/designs/nangate45/gcd/rules-base.json
index 94f99b2fc3..0e91d99a8e 100644
--- a/flow/designs/nangate45/gcd/rules-base.json
+++ b/flow/designs/nangate45/gcd/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 747,
+ "value": 743,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 6853,
+ "value": 5050,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.09,
+ "value": -0.08,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 1069,
+ "value": 898,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc
index 625bba41ec..210d591716 100644
--- a/flow/designs/nangate45/ibex/constraint.sdc
+++ b/flow/designs/nangate45/ibex/constraint.sdc
@@ -1,6 +1,6 @@
current_design ibex_core
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 2.2
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/ibex/rules-base.json b/flow/designs/nangate45/ibex/rules-base.json
index 6a0b8c87f1..966130b95e 100644
--- a/flow/designs/nangate45/ibex/rules-base.json
+++ b/flow/designs/nangate45/ibex/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 36863,
+ "value": 35998,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 18834,
+ "value": 17800,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 1638,
+ "value": 1548,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 1638,
+ "value": 1548,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 363762,
+ "value": 325819,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.19,
+ "value": -0.14,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 39536,
+ "value": 37049,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 825,
+ "value": 774,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -15.31,
+ "value": -11.47,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc
index af18e2d682..4548cad10c 100644
--- a/flow/designs/nangate45/jpeg/constraint.sdc
+++ b/flow/designs/nangate45/jpeg/constraint.sdc
@@ -1,6 +1,6 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 1.2
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json
index 4f11d20d1f..ffa598e023 100644
--- a/flow/designs/nangate45/jpeg/rules-base.json
+++ b/flow/designs/nangate45/jpeg/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 110453,
+ "value": 104372,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 71206,
+ "value": 69094,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 6192,
+ "value": 6008,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 6192,
+ "value": 6008,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 1209350,
+ "value": 687679,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.07,
+ "value": -0.05,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 112296,
+ "value": 106338,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 3096,
+ "value": 3004,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/nangate45/mempool_group/mempool_group.sdc b/flow/designs/nangate45/mempool_group/mempool_group.sdc
index 87e865fbac..3d6bf172ca 100755
--- a/flow/designs/nangate45/mempool_group/mempool_group.sdc
+++ b/flow/designs/nangate45/mempool_group/mempool_group.sdc
@@ -29,22 +29,21 @@ set_case_analysis 0 [get_ports scan_enable_i]
set_max_fanout $maxFanout [current_design]
-
# False path some of the quasi-static signals.
#set_false_path -from tile_id_i
# TCDM Master
-set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}]
+set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}]
-set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}]
+set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}]
# TCDM Slave
#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}]
-set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}]
+set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}]
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}]
# Refill port
@@ -52,7 +51,7 @@ set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name
#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}]
# Reset
-set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
+set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
# Critical range
# Depending on the synthesis tool used, this can be helpful.
diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc
index 9fd406be5e..be7426a1a2 100644
--- a/flow/designs/nangate45/swerv/constraint.sdc
+++ b/flow/designs/nangate45/swerv/constraint.sdc
@@ -1,6 +1,6 @@
current_design swerv
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
set clk_period 2.0
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json
index 7a4e713281..26b84e8c90 100644
--- a/flow/designs/nangate45/swerv/rules-base.json
+++ b/flow/designs/nangate45/swerv/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 213238,
+ "value": 201974,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 106074,
+ "value": 99342,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 9224,
+ "value": 8638,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 9224,
+ "value": 8638,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.3,
+ "value": -0.27,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 218848,
+ "value": 206802,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 4612,
+ "value": 4319,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -22.51,
+ "value": -21.98,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk
index 6d45062af7..2ce3c88234 100644
--- a/flow/designs/nangate45/swerv_wrapper/config.mk
+++ b/flow/designs/nangate45/swerv_wrapper/config.mk
@@ -23,5 +23,3 @@ export PLACE_DENSITY_LB_ADDON = 0.08
export TNS_END_PERCENT = 100
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl
-
-export GPL_KEEP_OVERFLOW = 0
diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc
index 308fd50a14..4ccc054acb 100644
--- a/flow/designs/nangate45/swerv_wrapper/constraint.sdc
+++ b/flow/designs/nangate45/swerv_wrapper/constraint.sdc
@@ -1,6 +1,6 @@
current_design swerv_wrapper
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
set clk_period 2.0
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json
index 5fe8593bb9..4d68fe18d5 100644
--- a/flow/designs/nangate45/swerv_wrapper/rules-base.json
+++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 115300,
+ "value": 113069,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 10026,
+ "value": 9832,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 10026,
+ "value": 9832,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 5096058,
+ "value": 5365759,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.33,
+ "value": -0.32,
"compare": ">="
},
"finish__design__instance__area": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 5013,
+ "value": 4916,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -20.07,
+ "value": -19.88,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json
index eaaba9cf90..c4e298e189 100644
--- a/flow/designs/nangate45/tinyRocket/rules-base.json
+++ b/flow/designs/nangate45/tinyRocket/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 66186,
+ "value": 64635,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -48,11 +48,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.32,
+ "value": -0.13,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 68441,
+ "value": 67327,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -20.85,
+ "value": -15.79,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc
index 7fa2a489d8..f32c9be836 100644
--- a/flow/designs/sky130hd/aes/constraint.sdc
+++ b/flow/designs/sky130hd/aes/constraint.sdc
@@ -1,8 +1,8 @@
current_design aes_cipher_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 4.5
+set clk_period 4.5
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/aes/fastroute.tcl b/flow/designs/sky130hd/aes/fastroute.tcl
index 66eb939e6f..80e4274ee2 100644
--- a/flow/designs/sky130hd/aes/fastroute.tcl
+++ b/flow/designs/sky130hd/aes/fastroute.tcl
@@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING
set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/designs/sky130hd/aes/rules-base.json b/flow/designs/sky130hd/aes/rules-base.json
index 949929c08f..8427199c0d 100644
--- a/flow/designs/sky130hd/aes/rules-base.json
+++ b/flow/designs/sky130hd/aes/rules-base.json
@@ -28,7 +28,7 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 180,
+ "value": 442,
"compare": "<="
},
"detailedroute__route__wirelength": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.54,
+ "value": -0.61,
"compare": ">="
},
"finish__design__instance__area": {
diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc
index 6dcc28d927..da65f16f66 100644
--- a/flow/designs/sky130hd/chameleon/constraint.sdc
+++ b/flow/designs/sky130hd/chameleon/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name core_clock
-set clk_port_name HCLK
-set clk_period 7.0
+set clk_name core_clock
+set clk_port_name HCLK
+set clk_period 7.0
set clk_io_pct 0.1
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json
index e183d8c443..de98b6d05b 100644
--- a/flow/designs/sky130hd/chameleon/rules-base.json
+++ b/flow/designs/sky130hd/chameleon/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 69796,
+ "value": 69712,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,15 +20,15 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 6069,
+ "value": 6062,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 6069,
+ "value": 6062,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 200,
+ "value": 196,
"compare": "<="
},
"detailedroute__route__wirelength": {
@@ -44,7 +44,7 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 189,
+ "value": 174,
"compare": "<="
},
"finish__timing__setup__ws": {
@@ -56,7 +56,7 @@
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 3035,
+ "value": 3031,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc
index 7177c71e7b..d3fcca89a9 100644
--- a/flow/designs/sky130hd/gcd/constraint.sdc
+++ b/flow/designs/sky130hd/gcd/constraint.sdc
@@ -1,6 +1,6 @@
current_design gcd
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
set clk_period 1.1
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json
index 3e70838254..eda2d1a286 100644
--- a/flow/designs/sky130hd/gcd/rules-base.json
+++ b/flow/designs/sky130hd/gcd/rules-base.json
@@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 481,
+ "value": 581,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,7 +20,7 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 65,
+ "value": 50,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel
index 7203d88313..08f7adc3e6 100644
--- a/flow/designs/sky130hd/ibex/BUILD.bazel
+++ b/flow/designs/sky130hd/ibex/BUILD.bazel
@@ -5,11 +5,13 @@ orfs_flow(
arguments = {
"ADDER_MAP_FILE": "",
"CORE_UTILIZATION": "45",
- "PLACE_DENSITY_LB_ADDON": "0.2",
+ "PLACE_DENSITY_LB_ADDON": "0.25",
"TNS_END_PERCENT": "100",
"REMOVE_ABC_BUFFERS": "1",
"SYNTH_HDL_FRONTEND": "slang",
"VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl",
+ "CTS_CLUSTER_SIZE": "20",
+ "CTS_CLUSTER_DIAMETER": "50",
},
pdk = "@docker_orfs//:sky130hd",
sources = {
diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc
index a4faf836eb..979e0b0b28 100644
--- a/flow/designs/sky130hd/ibex/constraint.sdc
+++ b/flow/designs/sky130hd/ibex/constraint.sdc
@@ -1,6 +1,6 @@
current_design ibex_core
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 10.0
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/ibex/constraint_doe.sdc b/flow/designs/sky130hd/ibex/constraint_doe.sdc
index e169d10114..31ddde31d7 100644
--- a/flow/designs/sky130hd/ibex/constraint_doe.sdc
+++ b/flow/designs/sky130hd/ibex/constraint_doe.sdc
@@ -1,5 +1,5 @@
set uncertainty 1.0
-set io_delay 7.0
+set io_delay 7.0
set clock_port clk_i
@@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl
set_clock_uncertainty $uncertainty [all_clocks]
#
-set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs]
-set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs]
+set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs]
+set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs]
diff --git a/flow/designs/sky130hd/ibex/fastroute.tcl b/flow/designs/sky130hd/ibex/fastroute.tcl
index 24af379c99..76f9321967 100644
--- a/flow/designs/sky130hd/ibex/fastroute.tcl
+++ b/flow/designs/sky130hd/ibex/fastroute.tcl
@@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING
set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json
index a3e84be8d1..9176116e5a 100644
--- a/flow/designs/sky130hd/ibex/rules-base.json
+++ b/flow/designs/sky130hd/ibex/rules-base.json
@@ -28,7 +28,7 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 24,
+ "value": 62,
"compare": "<="
},
"detailedroute__route__wirelength": {
@@ -44,15 +44,15 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 57,
+ "value": 64,
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.94,
+ "value": -0.98,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 204248,
+ "value": 204569,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -16.35,
+ "value": -16.91,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk
index dced6f2bca..995fbeda5f 100644
--- a/flow/designs/sky130hd/jpeg/config.mk
+++ b/flow/designs/sky130hd/jpeg/config.mk
@@ -13,3 +13,6 @@ export TNS_END_PERCENT = 100
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
export REMOVE_ABC_BUFFERS = 1
+
+# workaround for density growing to 0.91 from adjustments on TD/RD iterations
+export GPL_ROUTABILITY_DRIVEN = 0
diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc
index 28aa0cc7ca..5ac34a1acf 100644
--- a/flow/designs/sky130hd/jpeg/constraint.sdc
+++ b/flow/designs/sky130hd/jpeg/constraint.sdc
@@ -1,6 +1,6 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 5.5
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/jpeg/fastroute.tcl b/flow/designs/sky130hd/jpeg/fastroute.tcl
index 80a2ca181e..e795f5e820 100644
--- a/flow/designs/sky130hd/jpeg/fastroute.tcl
+++ b/flow/designs/sky130hd/jpeg/fastroute.tcl
@@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING
set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json
index c6f18384b8..780a6ec5bd 100644
--- a/flow/designs/sky130hd/jpeg/rules-base.json
+++ b/flow/designs/sky130hd/jpeg/rules-base.json
@@ -28,7 +28,7 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 268,
+ "value": 220,
"compare": "<="
},
"detailedroute__route__wirelength": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.42,
+ "value": -0.25,
"compare": ">="
},
"finish__design__instance__area": {
diff --git a/flow/designs/sky130hd/microwatt/constraint.sdc b/flow/designs/sky130hd/microwatt/constraint.sdc
index cc9dbbe523..30f2da4808 100644
--- a/flow/designs/sky130hd/microwatt/constraint.sdc
+++ b/flow/designs/sky130hd/microwatt/constraint.sdc
@@ -49,8 +49,8 @@ set jtag_clk_port [get_ports $jtag_clk_port_name]
create_clock -name $jtag_clk_name -period $jtag_clk_period $jtag_clk_port
set_clock_groups -name group1 -logically_exclusive \
- -group [get_clocks $jtag_clk_name]\
- -group [get_clocks $clk_name]
+ -group [get_clocks $jtag_clk_name] \
+ -group [get_clocks $clk_name]
set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdi]
set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tms]
diff --git a/flow/designs/sky130hd/microwatt/fastroute.tcl b/flow/designs/sky130hd/microwatt/fastroute.tcl
index b39791ca0e..e1ea87c701 100644
--- a/flow/designs/sky130hd/microwatt/fastroute.tcl
+++ b/flow/designs/sky130hd/microwatt/fastroute.tcl
@@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING
set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json
index c9c30f9494..3d00501a44 100644
--- a/flow/designs/sky130hd/microwatt/rules-base.json
+++ b/flow/designs/sky130hd/microwatt/rules-base.json
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 5627882,
+ "value": 5621142,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 3606,
+ "value": 4257,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 11745555,
+ "value": 10026505,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -40,15 +40,15 @@
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
- "value": 9,
+ "value": 1,
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 3412,
+ "value": 1618,
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -2.11,
+ "value": -3.13,
"compare": ">="
},
"finish__design__instance__area": {
@@ -60,11 +60,11 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
- "value": 104,
+ "value": 262,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -18.62,
+ "value": -17.68,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/sky130hd/riscv32i/constraint.sdc b/flow/designs/sky130hd/riscv32i/constraint.sdc
index 70a1fcf751..5b0a6f1b4e 100644
--- a/flow/designs/sky130hd/riscv32i/constraint.sdc
+++ b/flow/designs/sky130hd/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
-set clk_period 6.0
+set clk_period 6.0
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [list]
foreach input [all_inputs] {
- if {$clk_port != $input} {
- lappend $non_clock_inputs $input
- }
+ if { $clk_port != $input } {
+ lappend $non_clock_inputs $input
+ }
}
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json
index 6fc2d11613..c1df764f6c 100644
--- a/flow/designs/sky130hd/riscv32i/rules-base.json
+++ b/flow/designs/sky130hd/riscv32i/rules-base.json
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
- "value": 70856.21,
+ "value": 70778.51,
"compare": "<="
},
"constraints__clocks__count": {
@@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 83236,
+ "value": 81702,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 36,
+ "value": 10,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 309557,
+ "value": 301382,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,15 +44,15 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 10,
+ "value": 18,
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -1.36,
+ "value": -1.17,
"compare": ">="
},
"finish__design__instance__area": {
- "value": 103720,
+ "value": 94909,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
- "value": -30.94,
+ "value": -28.53,
"compare": ">="
}
}
\ No newline at end of file
diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc
index 09f157ee3d..f99ac98b46 100644
--- a/flow/designs/sky130hs/aes/constraint.sdc
+++ b/flow/designs/sky130hs/aes/constraint.sdc
@@ -1,6 +1,6 @@
current_design aes_cipher_top
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 3.1
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json
index 2155ca377d..27ade127bb 100644
--- a/flow/designs/sky130hs/aes/rules-base.json
+++ b/flow/designs/sky130hs/aes/rules-base.json
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 9,
+ "value": 182,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 737983,
+ "value": 722796,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,7 +44,7 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 24,
+ "value": 54,
"compare": "<="
},
"finish__timing__setup__ws": {
@@ -52,7 +52,7 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 193310,
+ "value": 184400,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc
index f347111b34..71ddb64d28 100644
--- a/flow/designs/sky130hs/gcd/constraint.sdc
+++ b/flow/designs/sky130hs/gcd/constraint.sdc
@@ -1,8 +1,8 @@
current_design gcd
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk
-set clk_period 2.2
+set clk_period 2.2
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/gcd/rules-base.json b/flow/designs/sky130hs/gcd/rules-base.json
index 6e33b6ad11..f8939b236d 100644
--- a/flow/designs/sky130hs/gcd/rules-base.json
+++ b/flow/designs/sky130hs/gcd/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 5424,
+ "value": 5423,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 631,
+ "value": 622,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,11 +20,11 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 55,
+ "value": 54,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 55,
+ "value": 54,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
@@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 10496,
+ "value": 12530,
"compare": "<="
},
"detailedroute__route__drc_errors": {
diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc
index 72bc0ce1a3..a844a0dba6 100644
--- a/flow/designs/sky130hs/ibex/constraint.sdc
+++ b/flow/designs/sky130hs/ibex/constraint.sdc
@@ -1,6 +1,6 @@
current_design ibex_core
-set clk_name core_clock
+set clk_name core_clock
set clk_port_name clk_i
set clk_period 9.0
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json
index d55bd63edf..ab9f01be3f 100644
--- a/flow/designs/sky130hs/ibex/rules-base.json
+++ b/flow/designs/sky130hs/ibex/rules-base.json
@@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 12,
+ "value": 45,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 911447,
+ "value": 908310,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
- "value": -0.34,
+ "value": -0.19,
"compare": ">="
},
"finish__design__instance__area": {
diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc
index d9420273eb..d150e21e15 100644
--- a/flow/designs/sky130hs/jpeg/constraint.sdc
+++ b/flow/designs/sky130hs/jpeg/constraint.sdc
@@ -1,6 +1,6 @@
current_design jpeg_encoder
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 6.0
set clk_io_pct 0.2
@@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json
index ce7d4fa25d..181da8a088 100644
--- a/flow/designs/sky130hs/jpeg/rules-base.json
+++ b/flow/designs/sky130hs/jpeg/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 749317,
+ "value": 723127,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 63909,
+ "value": 63375,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,19 +20,19 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 5557,
+ "value": 5511,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 5557,
+ "value": 5511,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 712,
+ "value": 60,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 2481556,
+ "value": 1619030,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -40,11 +40,11 @@
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
- "value": 1,
+ "value": 0,
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 699,
+ "value": 164,
"compare": "<="
},
"finish__timing__setup__ws": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 779230,
+ "value": 760037,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 2779,
+ "value": 2755,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc
index 4be7147ef9..a598e70954 100644
--- a/flow/designs/sky130hs/riscv32i/constraint.sdc
+++ b/flow/designs/sky130hs/riscv32i/constraint.sdc
@@ -1,4 +1,4 @@
-set clk_name clk
+set clk_name clk
set clk_port_name clk
set clk_period 5.2
set clk_io_pct 0.2
@@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [list]
foreach input [all_inputs] {
- if {$clk_port != $input} {
- lappend $non_clock_inputs $input
- }
+ if { $clk_port != $input } {
+ lappend $non_clock_inputs $input
+ }
}
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json
index c5fe338cb5..0b81614fcc 100644
--- a/flow/designs/sky130hs/riscv32i/rules-base.json
+++ b/flow/designs/sky130hs/riscv32i/rules-base.json
@@ -8,11 +8,11 @@
"compare": "=="
},
"placeopt__design__instance__area": {
- "value": 118571,
+ "value": 116710,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
- "value": 7591,
+ "value": 7538,
"compare": "<="
},
"detailedplace__design__violations": {
@@ -20,19 +20,19 @@
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
- "value": 660,
+ "value": 656,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
- "value": 660,
+ "value": 656,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
- "value": 3,
+ "value": 26,
"compare": "<="
},
"detailedroute__route__wirelength": {
- "value": 378010,
+ "value": 369598,
"compare": "<="
},
"detailedroute__route__drc_errors": {
@@ -44,7 +44,7 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
- "value": 9,
+ "value": 5,
"compare": "<="
},
"finish__timing__setup__ws": {
@@ -52,11 +52,11 @@
"compare": ">="
},
"finish__design__instance__area": {
- "value": 141659,
+ "value": 134164,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
- "value": 330,
+ "value": 328,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/src/cva6/README.md b/flow/designs/src/cva6/README.md
index 0726796f5c..cd27453e1c 100644
--- a/flow/designs/src/cva6/README.md
+++ b/flow/designs/src/cva6/README.md
@@ -1 +1,3 @@
Extracted from https://github.com/openhwgroup/cva6
+
+Based on commit 3a389af with some changes for the RAMs
diff --git a/flow/designs/src/cva6/common/local/util/sram_cache.sv b/flow/designs/src/cva6/common/local/util/sram_cache.sv
index 9b3cf8d89b..799c63afcd 100644
--- a/flow/designs/src/cva6/common/local/util/sram_cache.sv
+++ b/flow/designs/src/cva6/common/local/util/sram_cache.sv
@@ -52,7 +52,7 @@ module sram_cache #(
rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH];
ruser_o = rdata_user[USER_WIDTH-1:0];
end
- fakeram7_256x256 i_tc_sram_wrapper(
+ fakeram7_64x256 i_tc_sram_wrapper(
.clk ( clk_i ),
.ce_in ( req_i ),
.we_in ( we_i ),
@@ -91,7 +91,7 @@ module sram_cache #(
rdata_o = rdata_user;
ruser_o = '0;
end
- fakeram7_256x256 i_tc_sram_wrapper(
+ fakeram7_64x25 i_tc_sram_wrapper(
.clk ( clk_i ),
.ce_in ( req_i ),
.we_in ( we_i ),
diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv
index bc6668a1e9..d078555ac4 100644
--- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv
+++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv
@@ -39,7 +39,7 @@ module hpdcache_sram
output logic [DATA_SIZE-1:0] rdata
);
- fakeram7_256x256 ram_i (
+ fakeram7_64x28 ram_i (
.clk(clk),
.ce_in(cs),
.we_in(we),
diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv
index b78cd44a81..d0cf76a389 100644
--- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv
+++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv
@@ -39,7 +39,7 @@ module hpdcache_sram_wbyteenable
input logic [DATA_SIZE/8-1:0] wbyteenable,
output logic [DATA_SIZE-1:0] rdata
);
- fakeram7_256x256 ram_i (
+ fakeram7_128x64 ram_i (
.clk (clk),
.ce_in(cs),
.we_in(we),
diff --git a/flow/designs/src/mock-array/util.tcl b/flow/designs/src/mock-array/util.tcl
index 960a3dffdb..6f3e9624c8 100644
--- a/flow/designs/src/mock-array/util.tcl
+++ b/flow/designs/src/mock-array/util.tcl
@@ -1,56 +1,56 @@
# Helper function to split a string into a list of strings and numbers
-proc split_strings_and_numbers {str} {
- set result {}
- foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] {
- if {$letters ne ""} {
- lappend result $letters
- }
- if {$numbers ne ""} {
- lappend result [expr {$numbers + 0}] ;# Convert to integer
- }
+proc split_strings_and_numbers { str } {
+ set result {}
+ foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] {
+ if { $letters ne "" } {
+ lappend result $letters
}
- return $result
+ if { $numbers ne "" } {
+ lappend result [expr { $numbers + 0 }] ;# Convert to integer
+ }
+ }
+ return $result
}
# Custom comparison function
-proc natural_compare {str1 str2} {
- set list1 [split_strings_and_numbers $str1]
- set list2 [split_strings_and_numbers $str2]
- set len [expr {min([llength $list1], [llength $list2])}]
- for {set i 0} {$i < $len} {incr i} {
- set part1 [lindex $list1 $i]
- set part2 [lindex $list2 $i]
- if {$part1 ne $part2} {
- if {[string is integer -strict $part1] && [string is integer -strict $part2]} {
- return [expr {$part1 - $part2}]
- } else {
- return [string compare $part1 $part2]
- }
- }
+proc natural_compare { str1 str2 } {
+ set list1 [split_strings_and_numbers $str1]
+ set list2 [split_strings_and_numbers $str2]
+ set len [expr { min([llength $list1], [llength $list2]) }]
+ for { set i 0 } { $i < $len } { incr i } {
+ set part1 [lindex $list1 $i]
+ set part2 [lindex $list2 $i]
+ if { $part1 ne $part2 } {
+ if { [string is integer -strict $part1] && [string is integer -strict $part2] } {
+ return [expr { $part1 - $part2 }]
+ } else {
+ return [string compare $part1 $part2]
+ }
}
- return [expr {[llength $list1] - [llength $list2]}] ;# If all parts are equal, compare by length
+ }
+ return [expr { [llength $list1] - [llength $list2] }] ;# If all parts are equal, compare by length
}
-proc natural_sort {list} {
- return [lsort -command natural_compare $list]
+proc natural_sort { list } {
+ return [lsort -command natural_compare $list]
}
-proc match_pins { regex {direction .*} {is_clock 0}} {
- set pins {}
- # The regex for get_ports is not the tcl regex
- foreach pin [get_ports -regex .*] {
- set input [get_property $pin name]
- # We want the Tcl regex
- if {![regexp $regex $input]} {
- continue
- }
- if {![regexp $direction [get_property $pin direction]]} {
- continue
- }
- if {[expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]]} {
- continue
- }
- lappend pins [get_property $pin name]
+proc match_pins { regex { direction .* } { is_clock 0 } } {
+ set pins {}
+ # The regex for get_ports is not the tcl regex
+ foreach pin [get_ports -regex .*] {
+ set input [get_property $pin name]
+ # We want the Tcl regex
+ if { ![regexp $regex $input] } {
+ continue
+ }
+ if { ![regexp $direction [get_property $pin direction]] } {
+ continue
+ }
+ if { [expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]] } {
+ continue
}
- return [natural_sort $pins]
+ lappend pins [get_property $pin name]
+ }
+ return [natural_sort $pins]
}
diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk
index 7e89ec9638..2ecb360eb8 100644
--- a/flow/platforms/asap7/config.mk
+++ b/flow/platforms/asap7/config.mk
@@ -80,87 +80,91 @@ export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/asap7.lydrc
# OpenRCX extRules
export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules
-# XS - defining function for using LVT
-ifeq ($(ASAP7_USE_VT), LVT)
- export VT_TAG = L
-else ifeq ($(ASAP7_USE_VT), SLVT)
- export VT_TAG = SL
-else
- # Default to RVT
- export VT_TAG = R
-endif
-
+# PLACEHOLDER gets replaced with the appropriate VT tag in the following templates
+export BC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib
+export BC_CCS_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib
+export WC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib
+export TC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib
+export BC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_nldm_220122.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib
+export BC_CCS_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_ccs_220122.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib
+export WC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_SS_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_SS_nldm_220122.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_SS_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib \
+ $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_SS_nldm_211120.lib.gz
+export TC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_TT_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_TT_nldm_220122.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_TT_nldm_211120.lib.gz \
+ $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib \
+ $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_TT_nldm_211120.lib.gz
+export FILL_CELLS_T = FILLERxp5_ASAP7_75t_ \
+ FILLER_ASAP7_75t_ \
+ DECAPx1_ASAP7_75t_ \
+ DECAPx2_ASAP7_75t_ \
+ DECAPx4_ASAP7_75t_ \
+ DECAPx6_ASAP7_75t_ \
+ DECAPx10_ASAP7_75t_
+
+# Default to RVT if unset
+export VT_LIST = $(if $(strip $(ASAP7_USE_VT)), $(ASAP7_USE_VT), RVT)
+
+# # The first VT in the ASAP7_USE_VT list is the primary VT. The others get added to OTHER_VT
+export PRIMARY_VT = $(word 1, $(VT_LIST))
+export PRIMARY_VT_TAG = $(strip $(patsubst %VT, %, $(PRIMARY_VT)))
+export OTHER_VT = $(wordlist 2, $(words $(VT_LIST)), $(VT_LIST))
+
+## Set cells based on the primary VT first
# Set the TIEHI/TIELO cells
# These are used in yosys synthesis to avoid logical 1/0's in the netlist
-export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(VT_TAG) H
-export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(VT_TAG) L
+export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(PRIMARY_VT_TAG) H
+export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(PRIMARY_VT_TAG) L
# Used in synthesis
-export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(VT_TAG) A Y
+export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) A Y
-export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG)
+export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG)
-export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG)
+export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG)
# Fill cells used in fill cell insertion
-export FILL_CELLS ?= FILLERxp5_ASAP7_75t_$(VT_TAG) \
- FILLER_ASAP7_75t_$(VT_TAG) \
- DECAPx1_ASAP7_75t_$(VT_TAG) \
- DECAPx2_ASAP7_75t_$(VT_TAG) \
- DECAPx4_ASAP7_75t_$(VT_TAG) \
- DECAPx6_ASAP7_75t_$(VT_TAG) \
- DECAPx10_ASAP7_75t_$(VT_TAG)
+export FILL_CELLS ?= $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))
-export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(VT_TAG)
+export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(PRIMARY_VT_TAG)
# GDS_FILES has to be = vs. ?= because GDS_FILES gets set in the ORFS Makefile
-export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(VT_TAG)_220121a.gds \
- $(ADDITIONAL_GDS)
+export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_220121a.gds
-export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(VT_TAG)_1x_220121a.lef
+export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_1x_220121a.lef
# Yosys mapping files
-export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(VT_TAG).v
-export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(VT_TAG).v
-export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(VT_TAG).v
-
-export BC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib
-
-export BC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_nldm_220122.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib
-
-export BC_CCS_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_ccs_220122.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib \
- $(BC_ADDITIONAL_LIBS)
+export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(PRIMARY_VT_TAG).v
+export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(PRIMARY_VT_TAG).v
+export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(PRIMARY_VT_TAG).v
-export BC_CCS_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib
-
-export WC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib
-
-export WC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_SS_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_SS_nldm_220122.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_SS_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib \
- $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_SS_nldm_211120.lib.gz
+export BC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))
+export BC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_LIB_FILES_T))
+export BC_CCS_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_LIB_FILES_T)) \
+ $(BC_ADDITIONAL_LIBS)
+export BC_CCS_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))
-export TC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib
+export WC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))
+export WC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_LIB_FILES_T))
-export TC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_TT_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_TT_nldm_220122.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_TT_nldm_211120.lib.gz \
- $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib \
- $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_TT_nldm_211120.lib.gz
+export TC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))
+export TC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_LIB_FILES_T))
ifeq ($(CLUSTER_FLOPS),1)
# Add the multi-bit FF for clustering. These are single corner libraries.
- export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(VT_TAG)VT_TT_nldm_FAKE.lib \
- $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(VT_TAG)VT_TT_nldm_FAKE.lib
+ export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib \
+ $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \
$(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef
@@ -168,6 +172,22 @@ ifeq ($(CLUSTER_FLOPS),1)
export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].*
endif
+### Add additional files to the variables based on the OTHER_VT list
+$(foreach vt_type,$(OTHER_VT),\
+ $(eval OTHER_VT_TAG = $(strip $(patsubst %VT, %, $(vt_type)))) \
+ $(eval ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(OTHER_VT_TAG)_1x_220121a.lef) \
+ $(eval BC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))) \
+ $(eval BC_CCS_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))) \
+ $(eval WC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))) \
+ $(eval TC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))) \
+ $(eval BC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_LIB_FILES_T))) \
+ $(eval BC_CCS_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_LIB_FILES_T))) \
+ $(eval WC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_LIB_FILES_T))) \
+ $(eval TC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_LIB_FILES_T))) \
+ $(eval GDS_FILES += $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(OTHER_VT_TAG)_220121a.gds) \
+ $(eval FILL_CELLS += $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))) \
+)
+
# Dont use SC library based on CORNER selection
#
# BC - Best case, fastest
@@ -176,6 +196,7 @@ endif
export CORNER ?= BC
export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES)
export LIB_FILES += $(ADDITIONAL_LIBS)
+export GDS_FILES += $(ADDITIONAL_GDS)
export DB_FILES += $(realpath $($(CORNER)_DB_FILES))
export TEMPERATURE = $($(CORNER)_TEMPERATURE)
export VOLTAGE = $($(CORNER)_VOLTAGE)
diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc
index e7ca24cb2b..b08b9fa596 100644
--- a/flow/platforms/asap7/constraints.sdc
+++ b/flow/platforms/asap7/constraints.sdc
@@ -69,7 +69,7 @@ set sdc_version 2.0
set clk_port [get_ports $clk_port_name]
create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
-set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
# Optimization targets: overconstrain by default and
@@ -77,9 +77,9 @@ set all_register_outputs [get_pins -of_objects [all_registers] -filter {directio
#
# Minimum time for io-io, io-reg, reg-io paths in macro is on
# the order of 80ps for a small macro on ASAP7.
-set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers]
-set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs]
-set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs]
+set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs -to [all_registers]
+set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from $all_register_outputs -to [all_outputs]
+set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs -to [all_outputs]
# This allows us to view the different groups
# in the histogram in the GUI and also includes these
diff --git a/flow/platforms/asap7/lef/fakeram7_128x64.lef b/flow/platforms/asap7/lef/fakeram7_128x64.lef
new file mode 100644
index 0000000000..8b0977f4b9
--- /dev/null
+++ b/flow/platforms/asap7/lef/fakeram7_128x64.lef
@@ -0,0 +1,1341 @@
+# Generated by FakeRAM 2.0
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+PROPERTYDEFINITIONS
+ MACRO width INTEGER ;
+ MACRO depth INTEGER ;
+ MACRO banks INTEGER ;
+END PROPERTYDEFINITIONS
+MACRO fakeram7_128x64
+ PROPERTY width 64 ;
+ PROPERTY depth 128 ;
+ PROPERTY banks 2 ;
+ FOREIGN fakeram7_128x64 0 0 ;
+ SYMMETRY X Y R90 ;
+ SIZE 16.720 BY 21.600 ;
+ CLASS BLOCK ;
+ PIN rd_out[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.048 0.024 0.072 ;
+ END
+ END rd_out[0]
+ PIN rd_out[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.192 0.024 0.216 ;
+ END
+ END rd_out[1]
+ PIN rd_out[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.336 0.024 0.360 ;
+ END
+ END rd_out[2]
+ PIN rd_out[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.480 0.024 0.504 ;
+ END
+ END rd_out[3]
+ PIN rd_out[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.624 0.024 0.648 ;
+ END
+ END rd_out[4]
+ PIN rd_out[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.768 0.024 0.792 ;
+ END
+ END rd_out[5]
+ PIN rd_out[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.912 0.024 0.936 ;
+ END
+ END rd_out[6]
+ PIN rd_out[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.056 0.024 1.080 ;
+ END
+ END rd_out[7]
+ PIN rd_out[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.200 0.024 1.224 ;
+ END
+ END rd_out[8]
+ PIN rd_out[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.344 0.024 1.368 ;
+ END
+ END rd_out[9]
+ PIN rd_out[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.488 0.024 1.512 ;
+ END
+ END rd_out[10]
+ PIN rd_out[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.632 0.024 1.656 ;
+ END
+ END rd_out[11]
+ PIN rd_out[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.776 0.024 1.800 ;
+ END
+ END rd_out[12]
+ PIN rd_out[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.920 0.024 1.944 ;
+ END
+ END rd_out[13]
+ PIN rd_out[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.064 0.024 2.088 ;
+ END
+ END rd_out[14]
+ PIN rd_out[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.208 0.024 2.232 ;
+ END
+ END rd_out[15]
+ PIN rd_out[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.352 0.024 2.376 ;
+ END
+ END rd_out[16]
+ PIN rd_out[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.496 0.024 2.520 ;
+ END
+ END rd_out[17]
+ PIN rd_out[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.640 0.024 2.664 ;
+ END
+ END rd_out[18]
+ PIN rd_out[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.784 0.024 2.808 ;
+ END
+ END rd_out[19]
+ PIN rd_out[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.928 0.024 2.952 ;
+ END
+ END rd_out[20]
+ PIN rd_out[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.072 0.024 3.096 ;
+ END
+ END rd_out[21]
+ PIN rd_out[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.216 0.024 3.240 ;
+ END
+ END rd_out[22]
+ PIN rd_out[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.360 0.024 3.384 ;
+ END
+ END rd_out[23]
+ PIN rd_out[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.504 0.024 3.528 ;
+ END
+ END rd_out[24]
+ PIN rd_out[25]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.648 0.024 3.672 ;
+ END
+ END rd_out[25]
+ PIN rd_out[26]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.792 0.024 3.816 ;
+ END
+ END rd_out[26]
+ PIN rd_out[27]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.936 0.024 3.960 ;
+ END
+ END rd_out[27]
+ PIN rd_out[28]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.080 0.024 4.104 ;
+ END
+ END rd_out[28]
+ PIN rd_out[29]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.224 0.024 4.248 ;
+ END
+ END rd_out[29]
+ PIN rd_out[30]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.368 0.024 4.392 ;
+ END
+ END rd_out[30]
+ PIN rd_out[31]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.512 0.024 4.536 ;
+ END
+ END rd_out[31]
+ PIN rd_out[32]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.656 0.024 4.680 ;
+ END
+ END rd_out[32]
+ PIN rd_out[33]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.800 0.024 4.824 ;
+ END
+ END rd_out[33]
+ PIN rd_out[34]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.944 0.024 4.968 ;
+ END
+ END rd_out[34]
+ PIN rd_out[35]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.088 0.024 5.112 ;
+ END
+ END rd_out[35]
+ PIN rd_out[36]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.232 0.024 5.256 ;
+ END
+ END rd_out[36]
+ PIN rd_out[37]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.376 0.024 5.400 ;
+ END
+ END rd_out[37]
+ PIN rd_out[38]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.520 0.024 5.544 ;
+ END
+ END rd_out[38]
+ PIN rd_out[39]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.664 0.024 5.688 ;
+ END
+ END rd_out[39]
+ PIN rd_out[40]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.808 0.024 5.832 ;
+ END
+ END rd_out[40]
+ PIN rd_out[41]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.952 0.024 5.976 ;
+ END
+ END rd_out[41]
+ PIN rd_out[42]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.096 0.024 6.120 ;
+ END
+ END rd_out[42]
+ PIN rd_out[43]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.240 0.024 6.264 ;
+ END
+ END rd_out[43]
+ PIN rd_out[44]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.384 0.024 6.408 ;
+ END
+ END rd_out[44]
+ PIN rd_out[45]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.528 0.024 6.552 ;
+ END
+ END rd_out[45]
+ PIN rd_out[46]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.672 0.024 6.696 ;
+ END
+ END rd_out[46]
+ PIN rd_out[47]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.816 0.024 6.840 ;
+ END
+ END rd_out[47]
+ PIN rd_out[48]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.960 0.024 6.984 ;
+ END
+ END rd_out[48]
+ PIN rd_out[49]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.104 0.024 7.128 ;
+ END
+ END rd_out[49]
+ PIN rd_out[50]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.248 0.024 7.272 ;
+ END
+ END rd_out[50]
+ PIN rd_out[51]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.392 0.024 7.416 ;
+ END
+ END rd_out[51]
+ PIN rd_out[52]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.536 0.024 7.560 ;
+ END
+ END rd_out[52]
+ PIN rd_out[53]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.680 0.024 7.704 ;
+ END
+ END rd_out[53]
+ PIN rd_out[54]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.824 0.024 7.848 ;
+ END
+ END rd_out[54]
+ PIN rd_out[55]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.968 0.024 7.992 ;
+ END
+ END rd_out[55]
+ PIN rd_out[56]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.112 0.024 8.136 ;
+ END
+ END rd_out[56]
+ PIN rd_out[57]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.256 0.024 8.280 ;
+ END
+ END rd_out[57]
+ PIN rd_out[58]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.400 0.024 8.424 ;
+ END
+ END rd_out[58]
+ PIN rd_out[59]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.544 0.024 8.568 ;
+ END
+ END rd_out[59]
+ PIN rd_out[60]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.688 0.024 8.712 ;
+ END
+ END rd_out[60]
+ PIN rd_out[61]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.832 0.024 8.856 ;
+ END
+ END rd_out[61]
+ PIN rd_out[62]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.976 0.024 9.000 ;
+ END
+ END rd_out[62]
+ PIN rd_out[63]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.120 0.024 9.144 ;
+ END
+ END rd_out[63]
+ PIN wd_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.792 0.024 9.816 ;
+ END
+ END wd_in[0]
+ PIN wd_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.936 0.024 9.960 ;
+ END
+ END wd_in[1]
+ PIN wd_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.080 0.024 10.104 ;
+ END
+ END wd_in[2]
+ PIN wd_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.224 0.024 10.248 ;
+ END
+ END wd_in[3]
+ PIN wd_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.368 0.024 10.392 ;
+ END
+ END wd_in[4]
+ PIN wd_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.512 0.024 10.536 ;
+ END
+ END wd_in[5]
+ PIN wd_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.656 0.024 10.680 ;
+ END
+ END wd_in[6]
+ PIN wd_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.800 0.024 10.824 ;
+ END
+ END wd_in[7]
+ PIN wd_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.944 0.024 10.968 ;
+ END
+ END wd_in[8]
+ PIN wd_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.088 0.024 11.112 ;
+ END
+ END wd_in[9]
+ PIN wd_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.232 0.024 11.256 ;
+ END
+ END wd_in[10]
+ PIN wd_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.376 0.024 11.400 ;
+ END
+ END wd_in[11]
+ PIN wd_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.520 0.024 11.544 ;
+ END
+ END wd_in[12]
+ PIN wd_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.664 0.024 11.688 ;
+ END
+ END wd_in[13]
+ PIN wd_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.808 0.024 11.832 ;
+ END
+ END wd_in[14]
+ PIN wd_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.952 0.024 11.976 ;
+ END
+ END wd_in[15]
+ PIN wd_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.096 0.024 12.120 ;
+ END
+ END wd_in[16]
+ PIN wd_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.240 0.024 12.264 ;
+ END
+ END wd_in[17]
+ PIN wd_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.384 0.024 12.408 ;
+ END
+ END wd_in[18]
+ PIN wd_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.528 0.024 12.552 ;
+ END
+ END wd_in[19]
+ PIN wd_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.672 0.024 12.696 ;
+ END
+ END wd_in[20]
+ PIN wd_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.816 0.024 12.840 ;
+ END
+ END wd_in[21]
+ PIN wd_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.960 0.024 12.984 ;
+ END
+ END wd_in[22]
+ PIN wd_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.104 0.024 13.128 ;
+ END
+ END wd_in[23]
+ PIN wd_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.248 0.024 13.272 ;
+ END
+ END wd_in[24]
+ PIN wd_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.392 0.024 13.416 ;
+ END
+ END wd_in[25]
+ PIN wd_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.536 0.024 13.560 ;
+ END
+ END wd_in[26]
+ PIN wd_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.680 0.024 13.704 ;
+ END
+ END wd_in[27]
+ PIN wd_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.824 0.024 13.848 ;
+ END
+ END wd_in[28]
+ PIN wd_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 13.968 0.024 13.992 ;
+ END
+ END wd_in[29]
+ PIN wd_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.112 0.024 14.136 ;
+ END
+ END wd_in[30]
+ PIN wd_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.256 0.024 14.280 ;
+ END
+ END wd_in[31]
+ PIN wd_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.400 0.024 14.424 ;
+ END
+ END wd_in[32]
+ PIN wd_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.544 0.024 14.568 ;
+ END
+ END wd_in[33]
+ PIN wd_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.688 0.024 14.712 ;
+ END
+ END wd_in[34]
+ PIN wd_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.832 0.024 14.856 ;
+ END
+ END wd_in[35]
+ PIN wd_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 14.976 0.024 15.000 ;
+ END
+ END wd_in[36]
+ PIN wd_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.120 0.024 15.144 ;
+ END
+ END wd_in[37]
+ PIN wd_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.264 0.024 15.288 ;
+ END
+ END wd_in[38]
+ PIN wd_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.408 0.024 15.432 ;
+ END
+ END wd_in[39]
+ PIN wd_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.552 0.024 15.576 ;
+ END
+ END wd_in[40]
+ PIN wd_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.696 0.024 15.720 ;
+ END
+ END wd_in[41]
+ PIN wd_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.840 0.024 15.864 ;
+ END
+ END wd_in[42]
+ PIN wd_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 15.984 0.024 16.008 ;
+ END
+ END wd_in[43]
+ PIN wd_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.128 0.024 16.152 ;
+ END
+ END wd_in[44]
+ PIN wd_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.272 0.024 16.296 ;
+ END
+ END wd_in[45]
+ PIN wd_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.416 0.024 16.440 ;
+ END
+ END wd_in[46]
+ PIN wd_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.560 0.024 16.584 ;
+ END
+ END wd_in[47]
+ PIN wd_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.704 0.024 16.728 ;
+ END
+ END wd_in[48]
+ PIN wd_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.848 0.024 16.872 ;
+ END
+ END wd_in[49]
+ PIN wd_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 16.992 0.024 17.016 ;
+ END
+ END wd_in[50]
+ PIN wd_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 17.136 0.024 17.160 ;
+ END
+ END wd_in[51]
+ PIN wd_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 17.280 0.024 17.304 ;
+ END
+ END wd_in[52]
+ PIN wd_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 17.424 0.024 17.448 ;
+ END
+ END wd_in[53]
+ PIN wd_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 17.568 0.024 17.592 ;
+ END
+ END wd_in[54]
+ PIN wd_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 17.712 0.024 17.736 ;
+ END
+ END wd_in[55]
+ PIN wd_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 17.856 0.024 17.880 ;
+ END
+ END wd_in[56]
+ PIN wd_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.000 0.024 18.024 ;
+ END
+ END wd_in[57]
+ PIN wd_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.144 0.024 18.168 ;
+ END
+ END wd_in[58]
+ PIN wd_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.288 0.024 18.312 ;
+ END
+ END wd_in[59]
+ PIN wd_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.432 0.024 18.456 ;
+ END
+ END wd_in[60]
+ PIN wd_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.576 0.024 18.600 ;
+ END
+ END wd_in[61]
+ PIN wd_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.720 0.024 18.744 ;
+ END
+ END wd_in[62]
+ PIN wd_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 18.864 0.024 18.888 ;
+ END
+ END wd_in[63]
+ PIN addr_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.536 0.024 19.560 ;
+ END
+ END addr_in[0]
+ PIN addr_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.680 0.024 19.704 ;
+ END
+ END addr_in[1]
+ PIN addr_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.824 0.024 19.848 ;
+ END
+ END addr_in[2]
+ PIN addr_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.968 0.024 19.992 ;
+ END
+ END addr_in[3]
+ PIN addr_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.112 0.024 20.136 ;
+ END
+ END addr_in[4]
+ PIN addr_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.256 0.024 20.280 ;
+ END
+ END addr_in[5]
+ PIN addr_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.400 0.024 20.424 ;
+ END
+ END addr_in[6]
+ PIN we_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.072 0.024 21.096 ;
+ END
+ END we_in
+ PIN ce_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.216 0.024 21.240 ;
+ END
+ END ce_in
+ PIN clk
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.360 0.024 21.384 ;
+ END
+ END clk
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER M4 ;
+ RECT 0.048 0.000 16.672 0.096 ;
+ RECT 0.048 0.768 16.672 0.864 ;
+ RECT 0.048 1.536 16.672 1.632 ;
+ RECT 0.048 2.304 16.672 2.400 ;
+ RECT 0.048 3.072 16.672 3.168 ;
+ RECT 0.048 3.840 16.672 3.936 ;
+ RECT 0.048 4.608 16.672 4.704 ;
+ RECT 0.048 5.376 16.672 5.472 ;
+ RECT 0.048 6.144 16.672 6.240 ;
+ RECT 0.048 6.912 16.672 7.008 ;
+ RECT 0.048 7.680 16.672 7.776 ;
+ RECT 0.048 8.448 16.672 8.544 ;
+ RECT 0.048 9.216 16.672 9.312 ;
+ RECT 0.048 9.984 16.672 10.080 ;
+ RECT 0.048 10.752 16.672 10.848 ;
+ RECT 0.048 11.520 16.672 11.616 ;
+ RECT 0.048 12.288 16.672 12.384 ;
+ RECT 0.048 13.056 16.672 13.152 ;
+ RECT 0.048 13.824 16.672 13.920 ;
+ RECT 0.048 14.592 16.672 14.688 ;
+ RECT 0.048 15.360 16.672 15.456 ;
+ RECT 0.048 16.128 16.672 16.224 ;
+ RECT 0.048 16.896 16.672 16.992 ;
+ RECT 0.048 17.664 16.672 17.760 ;
+ RECT 0.048 18.432 16.672 18.528 ;
+ RECT 0.048 19.200 16.672 19.296 ;
+ RECT 0.048 19.968 16.672 20.064 ;
+ RECT 0.048 20.736 16.672 20.832 ;
+ END
+ END VSS
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER M4 ;
+ RECT 0.048 0.384 16.672 0.480 ;
+ RECT 0.048 1.152 16.672 1.248 ;
+ RECT 0.048 1.920 16.672 2.016 ;
+ RECT 0.048 2.688 16.672 2.784 ;
+ RECT 0.048 3.456 16.672 3.552 ;
+ RECT 0.048 4.224 16.672 4.320 ;
+ RECT 0.048 4.992 16.672 5.088 ;
+ RECT 0.048 5.760 16.672 5.856 ;
+ RECT 0.048 6.528 16.672 6.624 ;
+ RECT 0.048 7.296 16.672 7.392 ;
+ RECT 0.048 8.064 16.672 8.160 ;
+ RECT 0.048 8.832 16.672 8.928 ;
+ RECT 0.048 9.600 16.672 9.696 ;
+ RECT 0.048 10.368 16.672 10.464 ;
+ RECT 0.048 11.136 16.672 11.232 ;
+ RECT 0.048 11.904 16.672 12.000 ;
+ RECT 0.048 12.672 16.672 12.768 ;
+ RECT 0.048 13.440 16.672 13.536 ;
+ RECT 0.048 14.208 16.672 14.304 ;
+ RECT 0.048 14.976 16.672 15.072 ;
+ RECT 0.048 15.744 16.672 15.840 ;
+ RECT 0.048 16.512 16.672 16.608 ;
+ RECT 0.048 17.280 16.672 17.376 ;
+ RECT 0.048 18.048 16.672 18.144 ;
+ RECT 0.048 18.816 16.672 18.912 ;
+ RECT 0.048 19.584 16.672 19.680 ;
+ RECT 0.048 20.352 16.672 20.448 ;
+ RECT 0.048 21.120 16.672 21.216 ;
+ END
+ END VDD
+ OBS
+ LAYER M1 ;
+ RECT 0 0 16.720 21.600 ;
+ LAYER M2 ;
+ RECT 0 0 16.720 21.600 ;
+ LAYER M3 ;
+ RECT 0 0 16.720 21.600 ;
+ LAYER M4 ;
+ RECT 0 0 16.720 21.600 ;
+ END
+END fakeram7_128x64
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/fakeram7_64x25.lef b/flow/platforms/asap7/lef/fakeram7_64x25.lef
new file mode 100644
index 0000000000..70cb255428
--- /dev/null
+++ b/flow/platforms/asap7/lef/fakeram7_64x25.lef
@@ -0,0 +1,590 @@
+# Generated by FakeRAM 2.0
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+PROPERTYDEFINITIONS
+ MACRO width INTEGER ;
+ MACRO depth INTEGER ;
+ MACRO banks INTEGER ;
+END PROPERTYDEFINITIONS
+MACRO fakeram7_64x25
+ PROPERTY width 25 ;
+ PROPERTY depth 64 ;
+ PROPERTY banks 4 ;
+ FOREIGN fakeram7_64x25 0 0 ;
+ SYMMETRY X Y R90 ;
+ SIZE 13.110 BY 6.000 ;
+ CLASS BLOCK ;
+ PIN rd_out[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.048 0.024 0.072 ;
+ END
+ END rd_out[0]
+ PIN rd_out[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.144 0.024 0.168 ;
+ END
+ END rd_out[1]
+ PIN rd_out[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.240 0.024 0.264 ;
+ END
+ END rd_out[2]
+ PIN rd_out[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.336 0.024 0.360 ;
+ END
+ END rd_out[3]
+ PIN rd_out[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.432 0.024 0.456 ;
+ END
+ END rd_out[4]
+ PIN rd_out[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.528 0.024 0.552 ;
+ END
+ END rd_out[5]
+ PIN rd_out[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.624 0.024 0.648 ;
+ END
+ END rd_out[6]
+ PIN rd_out[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.720 0.024 0.744 ;
+ END
+ END rd_out[7]
+ PIN rd_out[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.816 0.024 0.840 ;
+ END
+ END rd_out[8]
+ PIN rd_out[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.912 0.024 0.936 ;
+ END
+ END rd_out[9]
+ PIN rd_out[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.008 0.024 1.032 ;
+ END
+ END rd_out[10]
+ PIN rd_out[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.104 0.024 1.128 ;
+ END
+ END rd_out[11]
+ PIN rd_out[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.200 0.024 1.224 ;
+ END
+ END rd_out[12]
+ PIN rd_out[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.296 0.024 1.320 ;
+ END
+ END rd_out[13]
+ PIN rd_out[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.392 0.024 1.416 ;
+ END
+ END rd_out[14]
+ PIN rd_out[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.488 0.024 1.512 ;
+ END
+ END rd_out[15]
+ PIN rd_out[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.584 0.024 1.608 ;
+ END
+ END rd_out[16]
+ PIN rd_out[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.680 0.024 1.704 ;
+ END
+ END rd_out[17]
+ PIN rd_out[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.776 0.024 1.800 ;
+ END
+ END rd_out[18]
+ PIN rd_out[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.872 0.024 1.896 ;
+ END
+ END rd_out[19]
+ PIN rd_out[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.968 0.024 1.992 ;
+ END
+ END rd_out[20]
+ PIN rd_out[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.064 0.024 2.088 ;
+ END
+ END rd_out[21]
+ PIN rd_out[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.160 0.024 2.184 ;
+ END
+ END rd_out[22]
+ PIN rd_out[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.256 0.024 2.280 ;
+ END
+ END rd_out[23]
+ PIN rd_out[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.352 0.024 2.376 ;
+ END
+ END rd_out[24]
+ PIN wd_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.496 0.024 2.520 ;
+ END
+ END wd_in[0]
+ PIN wd_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.592 0.024 2.616 ;
+ END
+ END wd_in[1]
+ PIN wd_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.688 0.024 2.712 ;
+ END
+ END wd_in[2]
+ PIN wd_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.784 0.024 2.808 ;
+ END
+ END wd_in[3]
+ PIN wd_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.880 0.024 2.904 ;
+ END
+ END wd_in[4]
+ PIN wd_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.976 0.024 3.000 ;
+ END
+ END wd_in[5]
+ PIN wd_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.072 0.024 3.096 ;
+ END
+ END wd_in[6]
+ PIN wd_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.168 0.024 3.192 ;
+ END
+ END wd_in[7]
+ PIN wd_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.264 0.024 3.288 ;
+ END
+ END wd_in[8]
+ PIN wd_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.360 0.024 3.384 ;
+ END
+ END wd_in[9]
+ PIN wd_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.456 0.024 3.480 ;
+ END
+ END wd_in[10]
+ PIN wd_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.552 0.024 3.576 ;
+ END
+ END wd_in[11]
+ PIN wd_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.648 0.024 3.672 ;
+ END
+ END wd_in[12]
+ PIN wd_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.744 0.024 3.768 ;
+ END
+ END wd_in[13]
+ PIN wd_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.840 0.024 3.864 ;
+ END
+ END wd_in[14]
+ PIN wd_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.936 0.024 3.960 ;
+ END
+ END wd_in[15]
+ PIN wd_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.032 0.024 4.056 ;
+ END
+ END wd_in[16]
+ PIN wd_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.128 0.024 4.152 ;
+ END
+ END wd_in[17]
+ PIN wd_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.224 0.024 4.248 ;
+ END
+ END wd_in[18]
+ PIN wd_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.320 0.024 4.344 ;
+ END
+ END wd_in[19]
+ PIN wd_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.416 0.024 4.440 ;
+ END
+ END wd_in[20]
+ PIN wd_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.512 0.024 4.536 ;
+ END
+ END wd_in[21]
+ PIN wd_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.608 0.024 4.632 ;
+ END
+ END wd_in[22]
+ PIN wd_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.704 0.024 4.728 ;
+ END
+ END wd_in[23]
+ PIN wd_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.800 0.024 4.824 ;
+ END
+ END wd_in[24]
+ PIN addr_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.944 0.024 4.968 ;
+ END
+ END addr_in[0]
+ PIN addr_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.040 0.024 5.064 ;
+ END
+ END addr_in[1]
+ PIN addr_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.136 0.024 5.160 ;
+ END
+ END addr_in[2]
+ PIN addr_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.232 0.024 5.256 ;
+ END
+ END addr_in[3]
+ PIN addr_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.328 0.024 5.352 ;
+ END
+ END addr_in[4]
+ PIN addr_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.424 0.024 5.448 ;
+ END
+ END addr_in[5]
+ PIN we_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.568 0.024 5.592 ;
+ END
+ END we_in
+ PIN ce_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.664 0.024 5.688 ;
+ END
+ END ce_in
+ PIN clk
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.760 0.024 5.784 ;
+ END
+ END clk
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER M4 ;
+ RECT 0.048 0.000 13.062 0.096 ;
+ RECT 0.048 0.768 13.062 0.864 ;
+ RECT 0.048 1.536 13.062 1.632 ;
+ RECT 0.048 2.304 13.062 2.400 ;
+ RECT 0.048 3.072 13.062 3.168 ;
+ RECT 0.048 3.840 13.062 3.936 ;
+ RECT 0.048 4.608 13.062 4.704 ;
+ RECT 0.048 5.376 13.062 5.472 ;
+ END
+ END VSS
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER M4 ;
+ RECT 0.048 0.384 13.062 0.480 ;
+ RECT 0.048 1.152 13.062 1.248 ;
+ RECT 0.048 1.920 13.062 2.016 ;
+ RECT 0.048 2.688 13.062 2.784 ;
+ RECT 0.048 3.456 13.062 3.552 ;
+ RECT 0.048 4.224 13.062 4.320 ;
+ RECT 0.048 4.992 13.062 5.088 ;
+ RECT 0.048 5.760 13.062 5.856 ;
+ END
+ END VDD
+ OBS
+ LAYER M1 ;
+ RECT 0 0 13.110 6.000 ;
+ LAYER M2 ;
+ RECT 0 0 13.110 6.000 ;
+ LAYER M3 ;
+ RECT 0 0 13.110 6.000 ;
+ LAYER M4 ;
+ RECT 0 0 13.110 6.000 ;
+ END
+END fakeram7_64x25
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/fakeram7_64x256.lef b/flow/platforms/asap7/lef/fakeram7_64x256.lef
new file mode 100644
index 0000000000..d1b8f95fee
--- /dev/null
+++ b/flow/platforms/asap7/lef/fakeram7_64x256.lef
@@ -0,0 +1,4854 @@
+# Generated by FakeRAM 2.0
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+PROPERTYDEFINITIONS
+ MACRO width INTEGER ;
+ MACRO depth INTEGER ;
+ MACRO banks INTEGER ;
+END PROPERTYDEFINITIONS
+MACRO fakeram7_64x256
+ PROPERTY width 256 ;
+ PROPERTY depth 64 ;
+ PROPERTY banks 1 ;
+ FOREIGN fakeram7_64x256 0 0 ;
+ SYMMETRY X Y R90 ;
+ SIZE 33.250 BY 46.800 ;
+ CLASS BLOCK ;
+ PIN rd_out[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.048 0.036 0.072 ;
+ END
+ END rd_out[0]
+ PIN rd_out[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.096 0.036 0.120 ;
+ END
+ END rd_out[1]
+ PIN rd_out[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.144 0.036 0.168 ;
+ END
+ END rd_out[2]
+ PIN rd_out[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.192 0.036 0.216 ;
+ END
+ END rd_out[3]
+ PIN rd_out[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.240 0.036 0.264 ;
+ END
+ END rd_out[4]
+ PIN rd_out[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.288 0.036 0.312 ;
+ END
+ END rd_out[5]
+ PIN rd_out[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.336 0.036 0.360 ;
+ END
+ END rd_out[6]
+ PIN rd_out[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.384 0.036 0.408 ;
+ END
+ END rd_out[7]
+ PIN rd_out[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.432 0.036 0.456 ;
+ END
+ END rd_out[8]
+ PIN rd_out[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.480 0.036 0.504 ;
+ END
+ END rd_out[9]
+ PIN rd_out[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.528 0.036 0.552 ;
+ END
+ END rd_out[10]
+ PIN rd_out[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.576 0.036 0.600 ;
+ END
+ END rd_out[11]
+ PIN rd_out[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.624 0.036 0.648 ;
+ END
+ END rd_out[12]
+ PIN rd_out[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.672 0.036 0.696 ;
+ END
+ END rd_out[13]
+ PIN rd_out[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.720 0.036 0.744 ;
+ END
+ END rd_out[14]
+ PIN rd_out[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.768 0.036 0.792 ;
+ END
+ END rd_out[15]
+ PIN rd_out[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.816 0.036 0.840 ;
+ END
+ END rd_out[16]
+ PIN rd_out[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.864 0.036 0.888 ;
+ END
+ END rd_out[17]
+ PIN rd_out[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.912 0.036 0.936 ;
+ END
+ END rd_out[18]
+ PIN rd_out[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.960 0.036 0.984 ;
+ END
+ END rd_out[19]
+ PIN rd_out[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.008 0.036 1.032 ;
+ END
+ END rd_out[20]
+ PIN rd_out[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.056 0.036 1.080 ;
+ END
+ END rd_out[21]
+ PIN rd_out[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.104 0.036 1.128 ;
+ END
+ END rd_out[22]
+ PIN rd_out[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.152 0.036 1.176 ;
+ END
+ END rd_out[23]
+ PIN rd_out[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.200 0.036 1.224 ;
+ END
+ END rd_out[24]
+ PIN rd_out[25]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.248 0.036 1.272 ;
+ END
+ END rd_out[25]
+ PIN rd_out[26]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.296 0.036 1.320 ;
+ END
+ END rd_out[26]
+ PIN rd_out[27]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.344 0.036 1.368 ;
+ END
+ END rd_out[27]
+ PIN rd_out[28]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.392 0.036 1.416 ;
+ END
+ END rd_out[28]
+ PIN rd_out[29]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.440 0.036 1.464 ;
+ END
+ END rd_out[29]
+ PIN rd_out[30]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.488 0.036 1.512 ;
+ END
+ END rd_out[30]
+ PIN rd_out[31]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.536 0.036 1.560 ;
+ END
+ END rd_out[31]
+ PIN rd_out[32]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.584 0.036 1.608 ;
+ END
+ END rd_out[32]
+ PIN rd_out[33]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.632 0.036 1.656 ;
+ END
+ END rd_out[33]
+ PIN rd_out[34]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.680 0.036 1.704 ;
+ END
+ END rd_out[34]
+ PIN rd_out[35]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.728 0.036 1.752 ;
+ END
+ END rd_out[35]
+ PIN rd_out[36]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.776 0.036 1.800 ;
+ END
+ END rd_out[36]
+ PIN rd_out[37]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.824 0.036 1.848 ;
+ END
+ END rd_out[37]
+ PIN rd_out[38]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.872 0.036 1.896 ;
+ END
+ END rd_out[38]
+ PIN rd_out[39]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.920 0.036 1.944 ;
+ END
+ END rd_out[39]
+ PIN rd_out[40]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.968 0.036 1.992 ;
+ END
+ END rd_out[40]
+ PIN rd_out[41]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.016 0.036 2.040 ;
+ END
+ END rd_out[41]
+ PIN rd_out[42]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.064 0.036 2.088 ;
+ END
+ END rd_out[42]
+ PIN rd_out[43]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.112 0.036 2.136 ;
+ END
+ END rd_out[43]
+ PIN rd_out[44]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.160 0.036 2.184 ;
+ END
+ END rd_out[44]
+ PIN rd_out[45]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.208 0.036 2.232 ;
+ END
+ END rd_out[45]
+ PIN rd_out[46]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.256 0.036 2.280 ;
+ END
+ END rd_out[46]
+ PIN rd_out[47]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.304 0.036 2.328 ;
+ END
+ END rd_out[47]
+ PIN rd_out[48]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.352 0.036 2.376 ;
+ END
+ END rd_out[48]
+ PIN rd_out[49]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.400 0.036 2.424 ;
+ END
+ END rd_out[49]
+ PIN rd_out[50]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.448 0.036 2.472 ;
+ END
+ END rd_out[50]
+ PIN rd_out[51]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.496 0.036 2.520 ;
+ END
+ END rd_out[51]
+ PIN rd_out[52]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.544 0.036 2.568 ;
+ END
+ END rd_out[52]
+ PIN rd_out[53]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.592 0.036 2.616 ;
+ END
+ END rd_out[53]
+ PIN rd_out[54]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.640 0.036 2.664 ;
+ END
+ END rd_out[54]
+ PIN rd_out[55]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.688 0.036 2.712 ;
+ END
+ END rd_out[55]
+ PIN rd_out[56]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.736 0.036 2.760 ;
+ END
+ END rd_out[56]
+ PIN rd_out[57]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.784 0.036 2.808 ;
+ END
+ END rd_out[57]
+ PIN rd_out[58]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.832 0.036 2.856 ;
+ END
+ END rd_out[58]
+ PIN rd_out[59]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.880 0.036 2.904 ;
+ END
+ END rd_out[59]
+ PIN rd_out[60]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.928 0.036 2.952 ;
+ END
+ END rd_out[60]
+ PIN rd_out[61]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.976 0.036 3.000 ;
+ END
+ END rd_out[61]
+ PIN rd_out[62]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.024 0.036 3.048 ;
+ END
+ END rd_out[62]
+ PIN rd_out[63]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.072 0.036 3.096 ;
+ END
+ END rd_out[63]
+ PIN rd_out[64]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.120 0.036 3.144 ;
+ END
+ END rd_out[64]
+ PIN rd_out[65]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.168 0.036 3.192 ;
+ END
+ END rd_out[65]
+ PIN rd_out[66]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.216 0.036 3.240 ;
+ END
+ END rd_out[66]
+ PIN rd_out[67]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.264 0.036 3.288 ;
+ END
+ END rd_out[67]
+ PIN rd_out[68]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.312 0.036 3.336 ;
+ END
+ END rd_out[68]
+ PIN rd_out[69]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.360 0.036 3.384 ;
+ END
+ END rd_out[69]
+ PIN rd_out[70]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.408 0.036 3.432 ;
+ END
+ END rd_out[70]
+ PIN rd_out[71]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.456 0.036 3.480 ;
+ END
+ END rd_out[71]
+ PIN rd_out[72]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.504 0.036 3.528 ;
+ END
+ END rd_out[72]
+ PIN rd_out[73]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.552 0.036 3.576 ;
+ END
+ END rd_out[73]
+ PIN rd_out[74]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.600 0.036 3.624 ;
+ END
+ END rd_out[74]
+ PIN rd_out[75]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.648 0.036 3.672 ;
+ END
+ END rd_out[75]
+ PIN rd_out[76]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.696 0.036 3.720 ;
+ END
+ END rd_out[76]
+ PIN rd_out[77]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.744 0.036 3.768 ;
+ END
+ END rd_out[77]
+ PIN rd_out[78]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.792 0.036 3.816 ;
+ END
+ END rd_out[78]
+ PIN rd_out[79]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.840 0.036 3.864 ;
+ END
+ END rd_out[79]
+ PIN rd_out[80]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.888 0.036 3.912 ;
+ END
+ END rd_out[80]
+ PIN rd_out[81]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.936 0.036 3.960 ;
+ END
+ END rd_out[81]
+ PIN rd_out[82]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.984 0.036 4.008 ;
+ END
+ END rd_out[82]
+ PIN rd_out[83]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.032 0.036 4.056 ;
+ END
+ END rd_out[83]
+ PIN rd_out[84]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.080 0.036 4.104 ;
+ END
+ END rd_out[84]
+ PIN rd_out[85]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.128 0.036 4.152 ;
+ END
+ END rd_out[85]
+ PIN rd_out[86]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.176 0.036 4.200 ;
+ END
+ END rd_out[86]
+ PIN rd_out[87]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.224 0.036 4.248 ;
+ END
+ END rd_out[87]
+ PIN rd_out[88]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.272 0.036 4.296 ;
+ END
+ END rd_out[88]
+ PIN rd_out[89]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.320 0.036 4.344 ;
+ END
+ END rd_out[89]
+ PIN rd_out[90]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.368 0.036 4.392 ;
+ END
+ END rd_out[90]
+ PIN rd_out[91]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.416 0.036 4.440 ;
+ END
+ END rd_out[91]
+ PIN rd_out[92]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.464 0.036 4.488 ;
+ END
+ END rd_out[92]
+ PIN rd_out[93]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.512 0.036 4.536 ;
+ END
+ END rd_out[93]
+ PIN rd_out[94]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.560 0.036 4.584 ;
+ END
+ END rd_out[94]
+ PIN rd_out[95]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.608 0.036 4.632 ;
+ END
+ END rd_out[95]
+ PIN rd_out[96]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.656 0.036 4.680 ;
+ END
+ END rd_out[96]
+ PIN rd_out[97]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.704 0.036 4.728 ;
+ END
+ END rd_out[97]
+ PIN rd_out[98]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.752 0.036 4.776 ;
+ END
+ END rd_out[98]
+ PIN rd_out[99]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.800 0.036 4.824 ;
+ END
+ END rd_out[99]
+ PIN rd_out[100]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.848 0.036 4.872 ;
+ END
+ END rd_out[100]
+ PIN rd_out[101]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.896 0.036 4.920 ;
+ END
+ END rd_out[101]
+ PIN rd_out[102]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.944 0.036 4.968 ;
+ END
+ END rd_out[102]
+ PIN rd_out[103]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.992 0.036 5.016 ;
+ END
+ END rd_out[103]
+ PIN rd_out[104]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.040 0.036 5.064 ;
+ END
+ END rd_out[104]
+ PIN rd_out[105]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.088 0.036 5.112 ;
+ END
+ END rd_out[105]
+ PIN rd_out[106]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.136 0.036 5.160 ;
+ END
+ END rd_out[106]
+ PIN rd_out[107]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.184 0.036 5.208 ;
+ END
+ END rd_out[107]
+ PIN rd_out[108]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.232 0.036 5.256 ;
+ END
+ END rd_out[108]
+ PIN rd_out[109]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.280 0.036 5.304 ;
+ END
+ END rd_out[109]
+ PIN rd_out[110]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.328 0.036 5.352 ;
+ END
+ END rd_out[110]
+ PIN rd_out[111]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.376 0.036 5.400 ;
+ END
+ END rd_out[111]
+ PIN rd_out[112]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.424 0.036 5.448 ;
+ END
+ END rd_out[112]
+ PIN rd_out[113]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.472 0.036 5.496 ;
+ END
+ END rd_out[113]
+ PIN rd_out[114]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.520 0.036 5.544 ;
+ END
+ END rd_out[114]
+ PIN rd_out[115]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.568 0.036 5.592 ;
+ END
+ END rd_out[115]
+ PIN rd_out[116]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.616 0.036 5.640 ;
+ END
+ END rd_out[116]
+ PIN rd_out[117]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.664 0.036 5.688 ;
+ END
+ END rd_out[117]
+ PIN rd_out[118]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.712 0.036 5.736 ;
+ END
+ END rd_out[118]
+ PIN rd_out[119]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.760 0.036 5.784 ;
+ END
+ END rd_out[119]
+ PIN rd_out[120]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.808 0.036 5.832 ;
+ END
+ END rd_out[120]
+ PIN rd_out[121]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.856 0.036 5.880 ;
+ END
+ END rd_out[121]
+ PIN rd_out[122]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.904 0.036 5.928 ;
+ END
+ END rd_out[122]
+ PIN rd_out[123]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.952 0.036 5.976 ;
+ END
+ END rd_out[123]
+ PIN rd_out[124]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.000 0.036 6.024 ;
+ END
+ END rd_out[124]
+ PIN rd_out[125]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.048 0.036 6.072 ;
+ END
+ END rd_out[125]
+ PIN rd_out[126]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.096 0.036 6.120 ;
+ END
+ END rd_out[126]
+ PIN rd_out[127]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.144 0.036 6.168 ;
+ END
+ END rd_out[127]
+ PIN rd_out[128]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.192 0.036 6.216 ;
+ END
+ END rd_out[128]
+ PIN rd_out[129]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.240 0.036 6.264 ;
+ END
+ END rd_out[129]
+ PIN rd_out[130]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.288 0.036 6.312 ;
+ END
+ END rd_out[130]
+ PIN rd_out[131]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.336 0.036 6.360 ;
+ END
+ END rd_out[131]
+ PIN rd_out[132]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.384 0.036 6.408 ;
+ END
+ END rd_out[132]
+ PIN rd_out[133]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.432 0.036 6.456 ;
+ END
+ END rd_out[133]
+ PIN rd_out[134]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.480 0.036 6.504 ;
+ END
+ END rd_out[134]
+ PIN rd_out[135]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.528 0.036 6.552 ;
+ END
+ END rd_out[135]
+ PIN rd_out[136]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.576 0.036 6.600 ;
+ END
+ END rd_out[136]
+ PIN rd_out[137]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.624 0.036 6.648 ;
+ END
+ END rd_out[137]
+ PIN rd_out[138]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.672 0.036 6.696 ;
+ END
+ END rd_out[138]
+ PIN rd_out[139]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.720 0.036 6.744 ;
+ END
+ END rd_out[139]
+ PIN rd_out[140]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.768 0.036 6.792 ;
+ END
+ END rd_out[140]
+ PIN rd_out[141]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.816 0.036 6.840 ;
+ END
+ END rd_out[141]
+ PIN rd_out[142]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.864 0.036 6.888 ;
+ END
+ END rd_out[142]
+ PIN rd_out[143]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.912 0.036 6.936 ;
+ END
+ END rd_out[143]
+ PIN rd_out[144]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 6.960 0.036 6.984 ;
+ END
+ END rd_out[144]
+ PIN rd_out[145]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.008 0.036 7.032 ;
+ END
+ END rd_out[145]
+ PIN rd_out[146]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.056 0.036 7.080 ;
+ END
+ END rd_out[146]
+ PIN rd_out[147]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.104 0.036 7.128 ;
+ END
+ END rd_out[147]
+ PIN rd_out[148]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.152 0.036 7.176 ;
+ END
+ END rd_out[148]
+ PIN rd_out[149]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.200 0.036 7.224 ;
+ END
+ END rd_out[149]
+ PIN rd_out[150]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.248 0.036 7.272 ;
+ END
+ END rd_out[150]
+ PIN rd_out[151]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.296 0.036 7.320 ;
+ END
+ END rd_out[151]
+ PIN rd_out[152]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.344 0.036 7.368 ;
+ END
+ END rd_out[152]
+ PIN rd_out[153]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.392 0.036 7.416 ;
+ END
+ END rd_out[153]
+ PIN rd_out[154]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.440 0.036 7.464 ;
+ END
+ END rd_out[154]
+ PIN rd_out[155]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.488 0.036 7.512 ;
+ END
+ END rd_out[155]
+ PIN rd_out[156]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.536 0.036 7.560 ;
+ END
+ END rd_out[156]
+ PIN rd_out[157]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.584 0.036 7.608 ;
+ END
+ END rd_out[157]
+ PIN rd_out[158]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.632 0.036 7.656 ;
+ END
+ END rd_out[158]
+ PIN rd_out[159]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.680 0.036 7.704 ;
+ END
+ END rd_out[159]
+ PIN rd_out[160]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.728 0.036 7.752 ;
+ END
+ END rd_out[160]
+ PIN rd_out[161]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.776 0.036 7.800 ;
+ END
+ END rd_out[161]
+ PIN rd_out[162]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.824 0.036 7.848 ;
+ END
+ END rd_out[162]
+ PIN rd_out[163]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.872 0.036 7.896 ;
+ END
+ END rd_out[163]
+ PIN rd_out[164]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.920 0.036 7.944 ;
+ END
+ END rd_out[164]
+ PIN rd_out[165]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 7.968 0.036 7.992 ;
+ END
+ END rd_out[165]
+ PIN rd_out[166]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.016 0.036 8.040 ;
+ END
+ END rd_out[166]
+ PIN rd_out[167]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.064 0.036 8.088 ;
+ END
+ END rd_out[167]
+ PIN rd_out[168]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.112 0.036 8.136 ;
+ END
+ END rd_out[168]
+ PIN rd_out[169]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.160 0.036 8.184 ;
+ END
+ END rd_out[169]
+ PIN rd_out[170]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.208 0.036 8.232 ;
+ END
+ END rd_out[170]
+ PIN rd_out[171]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.256 0.036 8.280 ;
+ END
+ END rd_out[171]
+ PIN rd_out[172]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.304 0.036 8.328 ;
+ END
+ END rd_out[172]
+ PIN rd_out[173]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.352 0.036 8.376 ;
+ END
+ END rd_out[173]
+ PIN rd_out[174]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.400 0.036 8.424 ;
+ END
+ END rd_out[174]
+ PIN rd_out[175]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.448 0.036 8.472 ;
+ END
+ END rd_out[175]
+ PIN rd_out[176]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.496 0.036 8.520 ;
+ END
+ END rd_out[176]
+ PIN rd_out[177]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.544 0.036 8.568 ;
+ END
+ END rd_out[177]
+ PIN rd_out[178]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.592 0.036 8.616 ;
+ END
+ END rd_out[178]
+ PIN rd_out[179]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.640 0.036 8.664 ;
+ END
+ END rd_out[179]
+ PIN rd_out[180]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.688 0.036 8.712 ;
+ END
+ END rd_out[180]
+ PIN rd_out[181]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.736 0.036 8.760 ;
+ END
+ END rd_out[181]
+ PIN rd_out[182]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.784 0.036 8.808 ;
+ END
+ END rd_out[182]
+ PIN rd_out[183]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.832 0.036 8.856 ;
+ END
+ END rd_out[183]
+ PIN rd_out[184]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.880 0.036 8.904 ;
+ END
+ END rd_out[184]
+ PIN rd_out[185]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.928 0.036 8.952 ;
+ END
+ END rd_out[185]
+ PIN rd_out[186]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 8.976 0.036 9.000 ;
+ END
+ END rd_out[186]
+ PIN rd_out[187]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.024 0.036 9.048 ;
+ END
+ END rd_out[187]
+ PIN rd_out[188]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.072 0.036 9.096 ;
+ END
+ END rd_out[188]
+ PIN rd_out[189]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.120 0.036 9.144 ;
+ END
+ END rd_out[189]
+ PIN rd_out[190]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.168 0.036 9.192 ;
+ END
+ END rd_out[190]
+ PIN rd_out[191]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.216 0.036 9.240 ;
+ END
+ END rd_out[191]
+ PIN rd_out[192]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.264 0.036 9.288 ;
+ END
+ END rd_out[192]
+ PIN rd_out[193]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.312 0.036 9.336 ;
+ END
+ END rd_out[193]
+ PIN rd_out[194]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.360 0.036 9.384 ;
+ END
+ END rd_out[194]
+ PIN rd_out[195]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.408 0.036 9.432 ;
+ END
+ END rd_out[195]
+ PIN rd_out[196]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.456 0.036 9.480 ;
+ END
+ END rd_out[196]
+ PIN rd_out[197]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.504 0.036 9.528 ;
+ END
+ END rd_out[197]
+ PIN rd_out[198]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.552 0.036 9.576 ;
+ END
+ END rd_out[198]
+ PIN rd_out[199]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.600 0.036 9.624 ;
+ END
+ END rd_out[199]
+ PIN rd_out[200]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.648 0.036 9.672 ;
+ END
+ END rd_out[200]
+ PIN rd_out[201]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.696 0.036 9.720 ;
+ END
+ END rd_out[201]
+ PIN rd_out[202]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.744 0.036 9.768 ;
+ END
+ END rd_out[202]
+ PIN rd_out[203]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.792 0.036 9.816 ;
+ END
+ END rd_out[203]
+ PIN rd_out[204]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.840 0.036 9.864 ;
+ END
+ END rd_out[204]
+ PIN rd_out[205]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.888 0.036 9.912 ;
+ END
+ END rd_out[205]
+ PIN rd_out[206]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.936 0.036 9.960 ;
+ END
+ END rd_out[206]
+ PIN rd_out[207]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 9.984 0.036 10.008 ;
+ END
+ END rd_out[207]
+ PIN rd_out[208]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.032 0.036 10.056 ;
+ END
+ END rd_out[208]
+ PIN rd_out[209]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.080 0.036 10.104 ;
+ END
+ END rd_out[209]
+ PIN rd_out[210]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.128 0.036 10.152 ;
+ END
+ END rd_out[210]
+ PIN rd_out[211]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.176 0.036 10.200 ;
+ END
+ END rd_out[211]
+ PIN rd_out[212]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.224 0.036 10.248 ;
+ END
+ END rd_out[212]
+ PIN rd_out[213]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.272 0.036 10.296 ;
+ END
+ END rd_out[213]
+ PIN rd_out[214]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.320 0.036 10.344 ;
+ END
+ END rd_out[214]
+ PIN rd_out[215]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.368 0.036 10.392 ;
+ END
+ END rd_out[215]
+ PIN rd_out[216]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.416 0.036 10.440 ;
+ END
+ END rd_out[216]
+ PIN rd_out[217]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.464 0.036 10.488 ;
+ END
+ END rd_out[217]
+ PIN rd_out[218]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.512 0.036 10.536 ;
+ END
+ END rd_out[218]
+ PIN rd_out[219]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.560 0.036 10.584 ;
+ END
+ END rd_out[219]
+ PIN rd_out[220]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.608 0.036 10.632 ;
+ END
+ END rd_out[220]
+ PIN rd_out[221]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.656 0.036 10.680 ;
+ END
+ END rd_out[221]
+ PIN rd_out[222]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.704 0.036 10.728 ;
+ END
+ END rd_out[222]
+ PIN rd_out[223]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.752 0.036 10.776 ;
+ END
+ END rd_out[223]
+ PIN rd_out[224]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.800 0.036 10.824 ;
+ END
+ END rd_out[224]
+ PIN rd_out[225]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.848 0.036 10.872 ;
+ END
+ END rd_out[225]
+ PIN rd_out[226]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.896 0.036 10.920 ;
+ END
+ END rd_out[226]
+ PIN rd_out[227]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.944 0.036 10.968 ;
+ END
+ END rd_out[227]
+ PIN rd_out[228]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 10.992 0.036 11.016 ;
+ END
+ END rd_out[228]
+ PIN rd_out[229]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.040 0.036 11.064 ;
+ END
+ END rd_out[229]
+ PIN rd_out[230]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.088 0.036 11.112 ;
+ END
+ END rd_out[230]
+ PIN rd_out[231]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.136 0.036 11.160 ;
+ END
+ END rd_out[231]
+ PIN rd_out[232]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.184 0.036 11.208 ;
+ END
+ END rd_out[232]
+ PIN rd_out[233]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.232 0.036 11.256 ;
+ END
+ END rd_out[233]
+ PIN rd_out[234]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.280 0.036 11.304 ;
+ END
+ END rd_out[234]
+ PIN rd_out[235]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.328 0.036 11.352 ;
+ END
+ END rd_out[235]
+ PIN rd_out[236]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.376 0.036 11.400 ;
+ END
+ END rd_out[236]
+ PIN rd_out[237]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.424 0.036 11.448 ;
+ END
+ END rd_out[237]
+ PIN rd_out[238]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.472 0.036 11.496 ;
+ END
+ END rd_out[238]
+ PIN rd_out[239]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.520 0.036 11.544 ;
+ END
+ END rd_out[239]
+ PIN rd_out[240]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.568 0.036 11.592 ;
+ END
+ END rd_out[240]
+ PIN rd_out[241]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.616 0.036 11.640 ;
+ END
+ END rd_out[241]
+ PIN rd_out[242]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.664 0.036 11.688 ;
+ END
+ END rd_out[242]
+ PIN rd_out[243]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.712 0.036 11.736 ;
+ END
+ END rd_out[243]
+ PIN rd_out[244]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.760 0.036 11.784 ;
+ END
+ END rd_out[244]
+ PIN rd_out[245]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.808 0.036 11.832 ;
+ END
+ END rd_out[245]
+ PIN rd_out[246]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.856 0.036 11.880 ;
+ END
+ END rd_out[246]
+ PIN rd_out[247]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.904 0.036 11.928 ;
+ END
+ END rd_out[247]
+ PIN rd_out[248]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 11.952 0.036 11.976 ;
+ END
+ END rd_out[248]
+ PIN rd_out[249]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.000 0.036 12.024 ;
+ END
+ END rd_out[249]
+ PIN rd_out[250]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.048 0.036 12.072 ;
+ END
+ END rd_out[250]
+ PIN rd_out[251]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.096 0.036 12.120 ;
+ END
+ END rd_out[251]
+ PIN rd_out[252]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.144 0.036 12.168 ;
+ END
+ END rd_out[252]
+ PIN rd_out[253]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.192 0.036 12.216 ;
+ END
+ END rd_out[253]
+ PIN rd_out[254]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.240 0.036 12.264 ;
+ END
+ END rd_out[254]
+ PIN rd_out[255]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 12.288 0.036 12.312 ;
+ END
+ END rd_out[255]
+ PIN wd_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.536 0.036 19.560 ;
+ END
+ END wd_in[0]
+ PIN wd_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.584 0.036 19.608 ;
+ END
+ END wd_in[1]
+ PIN wd_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.632 0.036 19.656 ;
+ END
+ END wd_in[2]
+ PIN wd_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.680 0.036 19.704 ;
+ END
+ END wd_in[3]
+ PIN wd_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.728 0.036 19.752 ;
+ END
+ END wd_in[4]
+ PIN wd_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.776 0.036 19.800 ;
+ END
+ END wd_in[5]
+ PIN wd_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.824 0.036 19.848 ;
+ END
+ END wd_in[6]
+ PIN wd_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.872 0.036 19.896 ;
+ END
+ END wd_in[7]
+ PIN wd_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.920 0.036 19.944 ;
+ END
+ END wd_in[8]
+ PIN wd_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 19.968 0.036 19.992 ;
+ END
+ END wd_in[9]
+ PIN wd_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.016 0.036 20.040 ;
+ END
+ END wd_in[10]
+ PIN wd_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.064 0.036 20.088 ;
+ END
+ END wd_in[11]
+ PIN wd_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.112 0.036 20.136 ;
+ END
+ END wd_in[12]
+ PIN wd_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.160 0.036 20.184 ;
+ END
+ END wd_in[13]
+ PIN wd_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.208 0.036 20.232 ;
+ END
+ END wd_in[14]
+ PIN wd_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.256 0.036 20.280 ;
+ END
+ END wd_in[15]
+ PIN wd_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.304 0.036 20.328 ;
+ END
+ END wd_in[16]
+ PIN wd_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.352 0.036 20.376 ;
+ END
+ END wd_in[17]
+ PIN wd_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.400 0.036 20.424 ;
+ END
+ END wd_in[18]
+ PIN wd_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.448 0.036 20.472 ;
+ END
+ END wd_in[19]
+ PIN wd_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.496 0.036 20.520 ;
+ END
+ END wd_in[20]
+ PIN wd_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.544 0.036 20.568 ;
+ END
+ END wd_in[21]
+ PIN wd_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.592 0.036 20.616 ;
+ END
+ END wd_in[22]
+ PIN wd_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.640 0.036 20.664 ;
+ END
+ END wd_in[23]
+ PIN wd_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.688 0.036 20.712 ;
+ END
+ END wd_in[24]
+ PIN wd_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.736 0.036 20.760 ;
+ END
+ END wd_in[25]
+ PIN wd_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.784 0.036 20.808 ;
+ END
+ END wd_in[26]
+ PIN wd_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.832 0.036 20.856 ;
+ END
+ END wd_in[27]
+ PIN wd_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.880 0.036 20.904 ;
+ END
+ END wd_in[28]
+ PIN wd_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.928 0.036 20.952 ;
+ END
+ END wd_in[29]
+ PIN wd_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 20.976 0.036 21.000 ;
+ END
+ END wd_in[30]
+ PIN wd_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.024 0.036 21.048 ;
+ END
+ END wd_in[31]
+ PIN wd_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.072 0.036 21.096 ;
+ END
+ END wd_in[32]
+ PIN wd_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.120 0.036 21.144 ;
+ END
+ END wd_in[33]
+ PIN wd_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.168 0.036 21.192 ;
+ END
+ END wd_in[34]
+ PIN wd_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.216 0.036 21.240 ;
+ END
+ END wd_in[35]
+ PIN wd_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.264 0.036 21.288 ;
+ END
+ END wd_in[36]
+ PIN wd_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.312 0.036 21.336 ;
+ END
+ END wd_in[37]
+ PIN wd_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.360 0.036 21.384 ;
+ END
+ END wd_in[38]
+ PIN wd_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.408 0.036 21.432 ;
+ END
+ END wd_in[39]
+ PIN wd_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.456 0.036 21.480 ;
+ END
+ END wd_in[40]
+ PIN wd_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.504 0.036 21.528 ;
+ END
+ END wd_in[41]
+ PIN wd_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.552 0.036 21.576 ;
+ END
+ END wd_in[42]
+ PIN wd_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.600 0.036 21.624 ;
+ END
+ END wd_in[43]
+ PIN wd_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.648 0.036 21.672 ;
+ END
+ END wd_in[44]
+ PIN wd_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.696 0.036 21.720 ;
+ END
+ END wd_in[45]
+ PIN wd_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.744 0.036 21.768 ;
+ END
+ END wd_in[46]
+ PIN wd_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.792 0.036 21.816 ;
+ END
+ END wd_in[47]
+ PIN wd_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.840 0.036 21.864 ;
+ END
+ END wd_in[48]
+ PIN wd_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.888 0.036 21.912 ;
+ END
+ END wd_in[49]
+ PIN wd_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.936 0.036 21.960 ;
+ END
+ END wd_in[50]
+ PIN wd_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 21.984 0.036 22.008 ;
+ END
+ END wd_in[51]
+ PIN wd_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.032 0.036 22.056 ;
+ END
+ END wd_in[52]
+ PIN wd_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.080 0.036 22.104 ;
+ END
+ END wd_in[53]
+ PIN wd_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.128 0.036 22.152 ;
+ END
+ END wd_in[54]
+ PIN wd_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.176 0.036 22.200 ;
+ END
+ END wd_in[55]
+ PIN wd_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.224 0.036 22.248 ;
+ END
+ END wd_in[56]
+ PIN wd_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.272 0.036 22.296 ;
+ END
+ END wd_in[57]
+ PIN wd_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.320 0.036 22.344 ;
+ END
+ END wd_in[58]
+ PIN wd_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.368 0.036 22.392 ;
+ END
+ END wd_in[59]
+ PIN wd_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.416 0.036 22.440 ;
+ END
+ END wd_in[60]
+ PIN wd_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.464 0.036 22.488 ;
+ END
+ END wd_in[61]
+ PIN wd_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.512 0.036 22.536 ;
+ END
+ END wd_in[62]
+ PIN wd_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.560 0.036 22.584 ;
+ END
+ END wd_in[63]
+ PIN wd_in[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.608 0.036 22.632 ;
+ END
+ END wd_in[64]
+ PIN wd_in[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.656 0.036 22.680 ;
+ END
+ END wd_in[65]
+ PIN wd_in[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.704 0.036 22.728 ;
+ END
+ END wd_in[66]
+ PIN wd_in[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.752 0.036 22.776 ;
+ END
+ END wd_in[67]
+ PIN wd_in[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.800 0.036 22.824 ;
+ END
+ END wd_in[68]
+ PIN wd_in[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.848 0.036 22.872 ;
+ END
+ END wd_in[69]
+ PIN wd_in[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.896 0.036 22.920 ;
+ END
+ END wd_in[70]
+ PIN wd_in[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.944 0.036 22.968 ;
+ END
+ END wd_in[71]
+ PIN wd_in[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 22.992 0.036 23.016 ;
+ END
+ END wd_in[72]
+ PIN wd_in[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.040 0.036 23.064 ;
+ END
+ END wd_in[73]
+ PIN wd_in[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.088 0.036 23.112 ;
+ END
+ END wd_in[74]
+ PIN wd_in[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.136 0.036 23.160 ;
+ END
+ END wd_in[75]
+ PIN wd_in[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.184 0.036 23.208 ;
+ END
+ END wd_in[76]
+ PIN wd_in[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.232 0.036 23.256 ;
+ END
+ END wd_in[77]
+ PIN wd_in[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.280 0.036 23.304 ;
+ END
+ END wd_in[78]
+ PIN wd_in[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.328 0.036 23.352 ;
+ END
+ END wd_in[79]
+ PIN wd_in[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.376 0.036 23.400 ;
+ END
+ END wd_in[80]
+ PIN wd_in[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.424 0.036 23.448 ;
+ END
+ END wd_in[81]
+ PIN wd_in[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.472 0.036 23.496 ;
+ END
+ END wd_in[82]
+ PIN wd_in[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.520 0.036 23.544 ;
+ END
+ END wd_in[83]
+ PIN wd_in[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.568 0.036 23.592 ;
+ END
+ END wd_in[84]
+ PIN wd_in[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.616 0.036 23.640 ;
+ END
+ END wd_in[85]
+ PIN wd_in[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.664 0.036 23.688 ;
+ END
+ END wd_in[86]
+ PIN wd_in[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.712 0.036 23.736 ;
+ END
+ END wd_in[87]
+ PIN wd_in[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.760 0.036 23.784 ;
+ END
+ END wd_in[88]
+ PIN wd_in[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.808 0.036 23.832 ;
+ END
+ END wd_in[89]
+ PIN wd_in[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.856 0.036 23.880 ;
+ END
+ END wd_in[90]
+ PIN wd_in[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.904 0.036 23.928 ;
+ END
+ END wd_in[91]
+ PIN wd_in[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 23.952 0.036 23.976 ;
+ END
+ END wd_in[92]
+ PIN wd_in[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.000 0.036 24.024 ;
+ END
+ END wd_in[93]
+ PIN wd_in[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.048 0.036 24.072 ;
+ END
+ END wd_in[94]
+ PIN wd_in[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.096 0.036 24.120 ;
+ END
+ END wd_in[95]
+ PIN wd_in[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.144 0.036 24.168 ;
+ END
+ END wd_in[96]
+ PIN wd_in[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.192 0.036 24.216 ;
+ END
+ END wd_in[97]
+ PIN wd_in[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.240 0.036 24.264 ;
+ END
+ END wd_in[98]
+ PIN wd_in[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.288 0.036 24.312 ;
+ END
+ END wd_in[99]
+ PIN wd_in[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.336 0.036 24.360 ;
+ END
+ END wd_in[100]
+ PIN wd_in[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.384 0.036 24.408 ;
+ END
+ END wd_in[101]
+ PIN wd_in[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.432 0.036 24.456 ;
+ END
+ END wd_in[102]
+ PIN wd_in[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.480 0.036 24.504 ;
+ END
+ END wd_in[103]
+ PIN wd_in[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.528 0.036 24.552 ;
+ END
+ END wd_in[104]
+ PIN wd_in[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.576 0.036 24.600 ;
+ END
+ END wd_in[105]
+ PIN wd_in[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.624 0.036 24.648 ;
+ END
+ END wd_in[106]
+ PIN wd_in[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.672 0.036 24.696 ;
+ END
+ END wd_in[107]
+ PIN wd_in[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.720 0.036 24.744 ;
+ END
+ END wd_in[108]
+ PIN wd_in[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.768 0.036 24.792 ;
+ END
+ END wd_in[109]
+ PIN wd_in[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.816 0.036 24.840 ;
+ END
+ END wd_in[110]
+ PIN wd_in[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.864 0.036 24.888 ;
+ END
+ END wd_in[111]
+ PIN wd_in[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.912 0.036 24.936 ;
+ END
+ END wd_in[112]
+ PIN wd_in[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 24.960 0.036 24.984 ;
+ END
+ END wd_in[113]
+ PIN wd_in[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.008 0.036 25.032 ;
+ END
+ END wd_in[114]
+ PIN wd_in[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.056 0.036 25.080 ;
+ END
+ END wd_in[115]
+ PIN wd_in[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.104 0.036 25.128 ;
+ END
+ END wd_in[116]
+ PIN wd_in[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.152 0.036 25.176 ;
+ END
+ END wd_in[117]
+ PIN wd_in[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.200 0.036 25.224 ;
+ END
+ END wd_in[118]
+ PIN wd_in[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.248 0.036 25.272 ;
+ END
+ END wd_in[119]
+ PIN wd_in[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.296 0.036 25.320 ;
+ END
+ END wd_in[120]
+ PIN wd_in[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.344 0.036 25.368 ;
+ END
+ END wd_in[121]
+ PIN wd_in[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.392 0.036 25.416 ;
+ END
+ END wd_in[122]
+ PIN wd_in[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.440 0.036 25.464 ;
+ END
+ END wd_in[123]
+ PIN wd_in[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.488 0.036 25.512 ;
+ END
+ END wd_in[124]
+ PIN wd_in[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.536 0.036 25.560 ;
+ END
+ END wd_in[125]
+ PIN wd_in[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.584 0.036 25.608 ;
+ END
+ END wd_in[126]
+ PIN wd_in[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.632 0.036 25.656 ;
+ END
+ END wd_in[127]
+ PIN wd_in[128]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.680 0.036 25.704 ;
+ END
+ END wd_in[128]
+ PIN wd_in[129]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.728 0.036 25.752 ;
+ END
+ END wd_in[129]
+ PIN wd_in[130]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.776 0.036 25.800 ;
+ END
+ END wd_in[130]
+ PIN wd_in[131]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.824 0.036 25.848 ;
+ END
+ END wd_in[131]
+ PIN wd_in[132]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.872 0.036 25.896 ;
+ END
+ END wd_in[132]
+ PIN wd_in[133]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.920 0.036 25.944 ;
+ END
+ END wd_in[133]
+ PIN wd_in[134]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 25.968 0.036 25.992 ;
+ END
+ END wd_in[134]
+ PIN wd_in[135]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.016 0.036 26.040 ;
+ END
+ END wd_in[135]
+ PIN wd_in[136]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.064 0.036 26.088 ;
+ END
+ END wd_in[136]
+ PIN wd_in[137]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.112 0.036 26.136 ;
+ END
+ END wd_in[137]
+ PIN wd_in[138]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.160 0.036 26.184 ;
+ END
+ END wd_in[138]
+ PIN wd_in[139]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.208 0.036 26.232 ;
+ END
+ END wd_in[139]
+ PIN wd_in[140]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.256 0.036 26.280 ;
+ END
+ END wd_in[140]
+ PIN wd_in[141]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.304 0.036 26.328 ;
+ END
+ END wd_in[141]
+ PIN wd_in[142]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.352 0.036 26.376 ;
+ END
+ END wd_in[142]
+ PIN wd_in[143]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.400 0.036 26.424 ;
+ END
+ END wd_in[143]
+ PIN wd_in[144]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.448 0.036 26.472 ;
+ END
+ END wd_in[144]
+ PIN wd_in[145]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.496 0.036 26.520 ;
+ END
+ END wd_in[145]
+ PIN wd_in[146]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.544 0.036 26.568 ;
+ END
+ END wd_in[146]
+ PIN wd_in[147]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.592 0.036 26.616 ;
+ END
+ END wd_in[147]
+ PIN wd_in[148]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.640 0.036 26.664 ;
+ END
+ END wd_in[148]
+ PIN wd_in[149]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.688 0.036 26.712 ;
+ END
+ END wd_in[149]
+ PIN wd_in[150]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.736 0.036 26.760 ;
+ END
+ END wd_in[150]
+ PIN wd_in[151]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.784 0.036 26.808 ;
+ END
+ END wd_in[151]
+ PIN wd_in[152]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.832 0.036 26.856 ;
+ END
+ END wd_in[152]
+ PIN wd_in[153]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.880 0.036 26.904 ;
+ END
+ END wd_in[153]
+ PIN wd_in[154]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.928 0.036 26.952 ;
+ END
+ END wd_in[154]
+ PIN wd_in[155]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 26.976 0.036 27.000 ;
+ END
+ END wd_in[155]
+ PIN wd_in[156]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.024 0.036 27.048 ;
+ END
+ END wd_in[156]
+ PIN wd_in[157]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.072 0.036 27.096 ;
+ END
+ END wd_in[157]
+ PIN wd_in[158]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.120 0.036 27.144 ;
+ END
+ END wd_in[158]
+ PIN wd_in[159]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.168 0.036 27.192 ;
+ END
+ END wd_in[159]
+ PIN wd_in[160]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.216 0.036 27.240 ;
+ END
+ END wd_in[160]
+ PIN wd_in[161]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.264 0.036 27.288 ;
+ END
+ END wd_in[161]
+ PIN wd_in[162]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.312 0.036 27.336 ;
+ END
+ END wd_in[162]
+ PIN wd_in[163]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.360 0.036 27.384 ;
+ END
+ END wd_in[163]
+ PIN wd_in[164]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.408 0.036 27.432 ;
+ END
+ END wd_in[164]
+ PIN wd_in[165]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.456 0.036 27.480 ;
+ END
+ END wd_in[165]
+ PIN wd_in[166]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.504 0.036 27.528 ;
+ END
+ END wd_in[166]
+ PIN wd_in[167]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.552 0.036 27.576 ;
+ END
+ END wd_in[167]
+ PIN wd_in[168]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.600 0.036 27.624 ;
+ END
+ END wd_in[168]
+ PIN wd_in[169]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.648 0.036 27.672 ;
+ END
+ END wd_in[169]
+ PIN wd_in[170]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.696 0.036 27.720 ;
+ END
+ END wd_in[170]
+ PIN wd_in[171]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.744 0.036 27.768 ;
+ END
+ END wd_in[171]
+ PIN wd_in[172]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.792 0.036 27.816 ;
+ END
+ END wd_in[172]
+ PIN wd_in[173]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.840 0.036 27.864 ;
+ END
+ END wd_in[173]
+ PIN wd_in[174]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.888 0.036 27.912 ;
+ END
+ END wd_in[174]
+ PIN wd_in[175]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.936 0.036 27.960 ;
+ END
+ END wd_in[175]
+ PIN wd_in[176]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 27.984 0.036 28.008 ;
+ END
+ END wd_in[176]
+ PIN wd_in[177]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.032 0.036 28.056 ;
+ END
+ END wd_in[177]
+ PIN wd_in[178]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.080 0.036 28.104 ;
+ END
+ END wd_in[178]
+ PIN wd_in[179]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.128 0.036 28.152 ;
+ END
+ END wd_in[179]
+ PIN wd_in[180]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.176 0.036 28.200 ;
+ END
+ END wd_in[180]
+ PIN wd_in[181]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.224 0.036 28.248 ;
+ END
+ END wd_in[181]
+ PIN wd_in[182]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.272 0.036 28.296 ;
+ END
+ END wd_in[182]
+ PIN wd_in[183]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.320 0.036 28.344 ;
+ END
+ END wd_in[183]
+ PIN wd_in[184]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.368 0.036 28.392 ;
+ END
+ END wd_in[184]
+ PIN wd_in[185]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.416 0.036 28.440 ;
+ END
+ END wd_in[185]
+ PIN wd_in[186]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.464 0.036 28.488 ;
+ END
+ END wd_in[186]
+ PIN wd_in[187]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.512 0.036 28.536 ;
+ END
+ END wd_in[187]
+ PIN wd_in[188]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.560 0.036 28.584 ;
+ END
+ END wd_in[188]
+ PIN wd_in[189]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.608 0.036 28.632 ;
+ END
+ END wd_in[189]
+ PIN wd_in[190]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.656 0.036 28.680 ;
+ END
+ END wd_in[190]
+ PIN wd_in[191]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.704 0.036 28.728 ;
+ END
+ END wd_in[191]
+ PIN wd_in[192]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.752 0.036 28.776 ;
+ END
+ END wd_in[192]
+ PIN wd_in[193]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.800 0.036 28.824 ;
+ END
+ END wd_in[193]
+ PIN wd_in[194]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.848 0.036 28.872 ;
+ END
+ END wd_in[194]
+ PIN wd_in[195]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.896 0.036 28.920 ;
+ END
+ END wd_in[195]
+ PIN wd_in[196]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.944 0.036 28.968 ;
+ END
+ END wd_in[196]
+ PIN wd_in[197]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 28.992 0.036 29.016 ;
+ END
+ END wd_in[197]
+ PIN wd_in[198]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.040 0.036 29.064 ;
+ END
+ END wd_in[198]
+ PIN wd_in[199]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.088 0.036 29.112 ;
+ END
+ END wd_in[199]
+ PIN wd_in[200]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.136 0.036 29.160 ;
+ END
+ END wd_in[200]
+ PIN wd_in[201]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.184 0.036 29.208 ;
+ END
+ END wd_in[201]
+ PIN wd_in[202]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.232 0.036 29.256 ;
+ END
+ END wd_in[202]
+ PIN wd_in[203]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.280 0.036 29.304 ;
+ END
+ END wd_in[203]
+ PIN wd_in[204]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.328 0.036 29.352 ;
+ END
+ END wd_in[204]
+ PIN wd_in[205]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.376 0.036 29.400 ;
+ END
+ END wd_in[205]
+ PIN wd_in[206]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.424 0.036 29.448 ;
+ END
+ END wd_in[206]
+ PIN wd_in[207]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.472 0.036 29.496 ;
+ END
+ END wd_in[207]
+ PIN wd_in[208]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.520 0.036 29.544 ;
+ END
+ END wd_in[208]
+ PIN wd_in[209]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.568 0.036 29.592 ;
+ END
+ END wd_in[209]
+ PIN wd_in[210]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.616 0.036 29.640 ;
+ END
+ END wd_in[210]
+ PIN wd_in[211]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.664 0.036 29.688 ;
+ END
+ END wd_in[211]
+ PIN wd_in[212]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.712 0.036 29.736 ;
+ END
+ END wd_in[212]
+ PIN wd_in[213]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.760 0.036 29.784 ;
+ END
+ END wd_in[213]
+ PIN wd_in[214]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.808 0.036 29.832 ;
+ END
+ END wd_in[214]
+ PIN wd_in[215]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.856 0.036 29.880 ;
+ END
+ END wd_in[215]
+ PIN wd_in[216]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.904 0.036 29.928 ;
+ END
+ END wd_in[216]
+ PIN wd_in[217]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 29.952 0.036 29.976 ;
+ END
+ END wd_in[217]
+ PIN wd_in[218]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.000 0.036 30.024 ;
+ END
+ END wd_in[218]
+ PIN wd_in[219]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.048 0.036 30.072 ;
+ END
+ END wd_in[219]
+ PIN wd_in[220]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.096 0.036 30.120 ;
+ END
+ END wd_in[220]
+ PIN wd_in[221]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.144 0.036 30.168 ;
+ END
+ END wd_in[221]
+ PIN wd_in[222]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.192 0.036 30.216 ;
+ END
+ END wd_in[222]
+ PIN wd_in[223]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.240 0.036 30.264 ;
+ END
+ END wd_in[223]
+ PIN wd_in[224]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.288 0.036 30.312 ;
+ END
+ END wd_in[224]
+ PIN wd_in[225]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.336 0.036 30.360 ;
+ END
+ END wd_in[225]
+ PIN wd_in[226]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.384 0.036 30.408 ;
+ END
+ END wd_in[226]
+ PIN wd_in[227]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.432 0.036 30.456 ;
+ END
+ END wd_in[227]
+ PIN wd_in[228]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.480 0.036 30.504 ;
+ END
+ END wd_in[228]
+ PIN wd_in[229]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.528 0.036 30.552 ;
+ END
+ END wd_in[229]
+ PIN wd_in[230]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.576 0.036 30.600 ;
+ END
+ END wd_in[230]
+ PIN wd_in[231]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.624 0.036 30.648 ;
+ END
+ END wd_in[231]
+ PIN wd_in[232]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.672 0.036 30.696 ;
+ END
+ END wd_in[232]
+ PIN wd_in[233]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.720 0.036 30.744 ;
+ END
+ END wd_in[233]
+ PIN wd_in[234]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.768 0.036 30.792 ;
+ END
+ END wd_in[234]
+ PIN wd_in[235]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.816 0.036 30.840 ;
+ END
+ END wd_in[235]
+ PIN wd_in[236]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.864 0.036 30.888 ;
+ END
+ END wd_in[236]
+ PIN wd_in[237]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.912 0.036 30.936 ;
+ END
+ END wd_in[237]
+ PIN wd_in[238]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 30.960 0.036 30.984 ;
+ END
+ END wd_in[238]
+ PIN wd_in[239]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.008 0.036 31.032 ;
+ END
+ END wd_in[239]
+ PIN wd_in[240]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.056 0.036 31.080 ;
+ END
+ END wd_in[240]
+ PIN wd_in[241]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.104 0.036 31.128 ;
+ END
+ END wd_in[241]
+ PIN wd_in[242]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.152 0.036 31.176 ;
+ END
+ END wd_in[242]
+ PIN wd_in[243]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.200 0.036 31.224 ;
+ END
+ END wd_in[243]
+ PIN wd_in[244]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.248 0.036 31.272 ;
+ END
+ END wd_in[244]
+ PIN wd_in[245]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.296 0.036 31.320 ;
+ END
+ END wd_in[245]
+ PIN wd_in[246]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.344 0.036 31.368 ;
+ END
+ END wd_in[246]
+ PIN wd_in[247]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.392 0.036 31.416 ;
+ END
+ END wd_in[247]
+ PIN wd_in[248]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.440 0.036 31.464 ;
+ END
+ END wd_in[248]
+ PIN wd_in[249]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.488 0.036 31.512 ;
+ END
+ END wd_in[249]
+ PIN wd_in[250]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.536 0.036 31.560 ;
+ END
+ END wd_in[250]
+ PIN wd_in[251]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.584 0.036 31.608 ;
+ END
+ END wd_in[251]
+ PIN wd_in[252]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.632 0.036 31.656 ;
+ END
+ END wd_in[252]
+ PIN wd_in[253]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.680 0.036 31.704 ;
+ END
+ END wd_in[253]
+ PIN wd_in[254]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.728 0.036 31.752 ;
+ END
+ END wd_in[254]
+ PIN wd_in[255]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 31.776 0.036 31.800 ;
+ END
+ END wd_in[255]
+ PIN addr_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 39.024 0.036 39.048 ;
+ END
+ END addr_in[0]
+ PIN addr_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 39.072 0.036 39.096 ;
+ END
+ END addr_in[1]
+ PIN addr_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 39.120 0.036 39.144 ;
+ END
+ END addr_in[2]
+ PIN addr_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 39.168 0.036 39.192 ;
+ END
+ END addr_in[3]
+ PIN addr_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 39.216 0.036 39.240 ;
+ END
+ END addr_in[4]
+ PIN addr_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 39.264 0.036 39.288 ;
+ END
+ END addr_in[5]
+ PIN we_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 46.512 0.036 46.536 ;
+ END
+ END we_in
+ PIN ce_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 46.560 0.036 46.584 ;
+ END
+ END ce_in
+ PIN clk
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 46.608 0.036 46.632 ;
+ END
+ END clk
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER M4 ;
+ RECT 0.096 0.000 33.154 0.096 ;
+ RECT 0.096 0.768 33.154 0.864 ;
+ RECT 0.096 1.536 33.154 1.632 ;
+ RECT 0.096 2.304 33.154 2.400 ;
+ RECT 0.096 3.072 33.154 3.168 ;
+ RECT 0.096 3.840 33.154 3.936 ;
+ RECT 0.096 4.608 33.154 4.704 ;
+ RECT 0.096 5.376 33.154 5.472 ;
+ RECT 0.096 6.144 33.154 6.240 ;
+ RECT 0.096 6.912 33.154 7.008 ;
+ RECT 0.096 7.680 33.154 7.776 ;
+ RECT 0.096 8.448 33.154 8.544 ;
+ RECT 0.096 9.216 33.154 9.312 ;
+ RECT 0.096 9.984 33.154 10.080 ;
+ RECT 0.096 10.752 33.154 10.848 ;
+ RECT 0.096 11.520 33.154 11.616 ;
+ RECT 0.096 12.288 33.154 12.384 ;
+ RECT 0.096 13.056 33.154 13.152 ;
+ RECT 0.096 13.824 33.154 13.920 ;
+ RECT 0.096 14.592 33.154 14.688 ;
+ RECT 0.096 15.360 33.154 15.456 ;
+ RECT 0.096 16.128 33.154 16.224 ;
+ RECT 0.096 16.896 33.154 16.992 ;
+ RECT 0.096 17.664 33.154 17.760 ;
+ RECT 0.096 18.432 33.154 18.528 ;
+ RECT 0.096 19.200 33.154 19.296 ;
+ RECT 0.096 19.968 33.154 20.064 ;
+ RECT 0.096 20.736 33.154 20.832 ;
+ RECT 0.096 21.504 33.154 21.600 ;
+ RECT 0.096 22.272 33.154 22.368 ;
+ RECT 0.096 23.040 33.154 23.136 ;
+ RECT 0.096 23.808 33.154 23.904 ;
+ RECT 0.096 24.576 33.154 24.672 ;
+ RECT 0.096 25.344 33.154 25.440 ;
+ RECT 0.096 26.112 33.154 26.208 ;
+ RECT 0.096 26.880 33.154 26.976 ;
+ RECT 0.096 27.648 33.154 27.744 ;
+ RECT 0.096 28.416 33.154 28.512 ;
+ RECT 0.096 29.184 33.154 29.280 ;
+ RECT 0.096 29.952 33.154 30.048 ;
+ RECT 0.096 30.720 33.154 30.816 ;
+ RECT 0.096 31.488 33.154 31.584 ;
+ RECT 0.096 32.256 33.154 32.352 ;
+ RECT 0.096 33.024 33.154 33.120 ;
+ RECT 0.096 33.792 33.154 33.888 ;
+ RECT 0.096 34.560 33.154 34.656 ;
+ RECT 0.096 35.328 33.154 35.424 ;
+ RECT 0.096 36.096 33.154 36.192 ;
+ RECT 0.096 36.864 33.154 36.960 ;
+ RECT 0.096 37.632 33.154 37.728 ;
+ RECT 0.096 38.400 33.154 38.496 ;
+ RECT 0.096 39.168 33.154 39.264 ;
+ RECT 0.096 39.936 33.154 40.032 ;
+ RECT 0.096 40.704 33.154 40.800 ;
+ RECT 0.096 41.472 33.154 41.568 ;
+ RECT 0.096 42.240 33.154 42.336 ;
+ RECT 0.096 43.008 33.154 43.104 ;
+ RECT 0.096 43.776 33.154 43.872 ;
+ RECT 0.096 44.544 33.154 44.640 ;
+ RECT 0.096 45.312 33.154 45.408 ;
+ RECT 0.096 46.080 33.154 46.176 ;
+ END
+ END VSS
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER M4 ;
+ RECT 0.096 0.384 33.154 0.480 ;
+ RECT 0.096 1.152 33.154 1.248 ;
+ RECT 0.096 1.920 33.154 2.016 ;
+ RECT 0.096 2.688 33.154 2.784 ;
+ RECT 0.096 3.456 33.154 3.552 ;
+ RECT 0.096 4.224 33.154 4.320 ;
+ RECT 0.096 4.992 33.154 5.088 ;
+ RECT 0.096 5.760 33.154 5.856 ;
+ RECT 0.096 6.528 33.154 6.624 ;
+ RECT 0.096 7.296 33.154 7.392 ;
+ RECT 0.096 8.064 33.154 8.160 ;
+ RECT 0.096 8.832 33.154 8.928 ;
+ RECT 0.096 9.600 33.154 9.696 ;
+ RECT 0.096 10.368 33.154 10.464 ;
+ RECT 0.096 11.136 33.154 11.232 ;
+ RECT 0.096 11.904 33.154 12.000 ;
+ RECT 0.096 12.672 33.154 12.768 ;
+ RECT 0.096 13.440 33.154 13.536 ;
+ RECT 0.096 14.208 33.154 14.304 ;
+ RECT 0.096 14.976 33.154 15.072 ;
+ RECT 0.096 15.744 33.154 15.840 ;
+ RECT 0.096 16.512 33.154 16.608 ;
+ RECT 0.096 17.280 33.154 17.376 ;
+ RECT 0.096 18.048 33.154 18.144 ;
+ RECT 0.096 18.816 33.154 18.912 ;
+ RECT 0.096 19.584 33.154 19.680 ;
+ RECT 0.096 20.352 33.154 20.448 ;
+ RECT 0.096 21.120 33.154 21.216 ;
+ RECT 0.096 21.888 33.154 21.984 ;
+ RECT 0.096 22.656 33.154 22.752 ;
+ RECT 0.096 23.424 33.154 23.520 ;
+ RECT 0.096 24.192 33.154 24.288 ;
+ RECT 0.096 24.960 33.154 25.056 ;
+ RECT 0.096 25.728 33.154 25.824 ;
+ RECT 0.096 26.496 33.154 26.592 ;
+ RECT 0.096 27.264 33.154 27.360 ;
+ RECT 0.096 28.032 33.154 28.128 ;
+ RECT 0.096 28.800 33.154 28.896 ;
+ RECT 0.096 29.568 33.154 29.664 ;
+ RECT 0.096 30.336 33.154 30.432 ;
+ RECT 0.096 31.104 33.154 31.200 ;
+ RECT 0.096 31.872 33.154 31.968 ;
+ RECT 0.096 32.640 33.154 32.736 ;
+ RECT 0.096 33.408 33.154 33.504 ;
+ RECT 0.096 34.176 33.154 34.272 ;
+ RECT 0.096 34.944 33.154 35.040 ;
+ RECT 0.096 35.712 33.154 35.808 ;
+ RECT 0.096 36.480 33.154 36.576 ;
+ RECT 0.096 37.248 33.154 37.344 ;
+ RECT 0.096 38.016 33.154 38.112 ;
+ RECT 0.096 38.784 33.154 38.880 ;
+ RECT 0.096 39.552 33.154 39.648 ;
+ RECT 0.096 40.320 33.154 40.416 ;
+ RECT 0.096 41.088 33.154 41.184 ;
+ RECT 0.096 41.856 33.154 41.952 ;
+ RECT 0.096 42.624 33.154 42.720 ;
+ RECT 0.096 43.392 33.154 43.488 ;
+ RECT 0.096 44.160 33.154 44.256 ;
+ RECT 0.096 44.928 33.154 45.024 ;
+ RECT 0.096 45.696 33.154 45.792 ;
+ RECT 0.096 46.464 33.154 46.560 ;
+ END
+ END VDD
+ OBS
+ LAYER M1 ;
+ RECT 0 0 33.250 46.800 ;
+ LAYER M2 ;
+ RECT 0 0 33.250 46.800 ;
+ LAYER M3 ;
+ RECT 0 0 33.250 46.800 ;
+ LAYER M4 ;
+ RECT 0 0 33.250 46.800 ;
+ END
+END fakeram7_64x256
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/fakeram7_64x28.lef b/flow/platforms/asap7/lef/fakeram7_64x28.lef
new file mode 100644
index 0000000000..725ac02163
--- /dev/null
+++ b/flow/platforms/asap7/lef/fakeram7_64x28.lef
@@ -0,0 +1,644 @@
+# Generated by FakeRAM 2.0
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+PROPERTYDEFINITIONS
+ MACRO width INTEGER ;
+ MACRO depth INTEGER ;
+ MACRO banks INTEGER ;
+END PROPERTYDEFINITIONS
+MACRO fakeram7_64x28
+ PROPERTY width 28 ;
+ PROPERTY depth 64 ;
+ PROPERTY banks 4 ;
+ FOREIGN fakeram7_64x28 0 0 ;
+ SYMMETRY X Y R90 ;
+ SIZE 14.630 BY 6.000 ;
+ CLASS BLOCK ;
+ PIN rd_out[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.048 0.036 0.072 ;
+ END
+ END rd_out[0]
+ PIN rd_out[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.096 0.036 0.120 ;
+ END
+ END rd_out[1]
+ PIN rd_out[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.144 0.036 0.168 ;
+ END
+ END rd_out[2]
+ PIN rd_out[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.192 0.036 0.216 ;
+ END
+ END rd_out[3]
+ PIN rd_out[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.240 0.036 0.264 ;
+ END
+ END rd_out[4]
+ PIN rd_out[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.288 0.036 0.312 ;
+ END
+ END rd_out[5]
+ PIN rd_out[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.336 0.036 0.360 ;
+ END
+ END rd_out[6]
+ PIN rd_out[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.384 0.036 0.408 ;
+ END
+ END rd_out[7]
+ PIN rd_out[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.432 0.036 0.456 ;
+ END
+ END rd_out[8]
+ PIN rd_out[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.480 0.036 0.504 ;
+ END
+ END rd_out[9]
+ PIN rd_out[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.528 0.036 0.552 ;
+ END
+ END rd_out[10]
+ PIN rd_out[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.576 0.036 0.600 ;
+ END
+ END rd_out[11]
+ PIN rd_out[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.624 0.036 0.648 ;
+ END
+ END rd_out[12]
+ PIN rd_out[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.672 0.036 0.696 ;
+ END
+ END rd_out[13]
+ PIN rd_out[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.720 0.036 0.744 ;
+ END
+ END rd_out[14]
+ PIN rd_out[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.768 0.036 0.792 ;
+ END
+ END rd_out[15]
+ PIN rd_out[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.816 0.036 0.840 ;
+ END
+ END rd_out[16]
+ PIN rd_out[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.864 0.036 0.888 ;
+ END
+ END rd_out[17]
+ PIN rd_out[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.912 0.036 0.936 ;
+ END
+ END rd_out[18]
+ PIN rd_out[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 0.960 0.036 0.984 ;
+ END
+ END rd_out[19]
+ PIN rd_out[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.008 0.036 1.032 ;
+ END
+ END rd_out[20]
+ PIN rd_out[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.056 0.036 1.080 ;
+ END
+ END rd_out[21]
+ PIN rd_out[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.104 0.036 1.128 ;
+ END
+ END rd_out[22]
+ PIN rd_out[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.152 0.036 1.176 ;
+ END
+ END rd_out[23]
+ PIN rd_out[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.200 0.036 1.224 ;
+ END
+ END rd_out[24]
+ PIN rd_out[25]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.248 0.036 1.272 ;
+ END
+ END rd_out[25]
+ PIN rd_out[26]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.296 0.036 1.320 ;
+ END
+ END rd_out[26]
+ PIN rd_out[27]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 1.344 0.036 1.368 ;
+ END
+ END rd_out[27]
+ PIN wd_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.304 0.036 2.328 ;
+ END
+ END wd_in[0]
+ PIN wd_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.352 0.036 2.376 ;
+ END
+ END wd_in[1]
+ PIN wd_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.400 0.036 2.424 ;
+ END
+ END wd_in[2]
+ PIN wd_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.448 0.036 2.472 ;
+ END
+ END wd_in[3]
+ PIN wd_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.496 0.036 2.520 ;
+ END
+ END wd_in[4]
+ PIN wd_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.544 0.036 2.568 ;
+ END
+ END wd_in[5]
+ PIN wd_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.592 0.036 2.616 ;
+ END
+ END wd_in[6]
+ PIN wd_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.640 0.036 2.664 ;
+ END
+ END wd_in[7]
+ PIN wd_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.688 0.036 2.712 ;
+ END
+ END wd_in[8]
+ PIN wd_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.736 0.036 2.760 ;
+ END
+ END wd_in[9]
+ PIN wd_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.784 0.036 2.808 ;
+ END
+ END wd_in[10]
+ PIN wd_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.832 0.036 2.856 ;
+ END
+ END wd_in[11]
+ PIN wd_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.880 0.036 2.904 ;
+ END
+ END wd_in[12]
+ PIN wd_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.928 0.036 2.952 ;
+ END
+ END wd_in[13]
+ PIN wd_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 2.976 0.036 3.000 ;
+ END
+ END wd_in[14]
+ PIN wd_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.024 0.036 3.048 ;
+ END
+ END wd_in[15]
+ PIN wd_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.072 0.036 3.096 ;
+ END
+ END wd_in[16]
+ PIN wd_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.120 0.036 3.144 ;
+ END
+ END wd_in[17]
+ PIN wd_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.168 0.036 3.192 ;
+ END
+ END wd_in[18]
+ PIN wd_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.216 0.036 3.240 ;
+ END
+ END wd_in[19]
+ PIN wd_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.264 0.036 3.288 ;
+ END
+ END wd_in[20]
+ PIN wd_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.312 0.036 3.336 ;
+ END
+ END wd_in[21]
+ PIN wd_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.360 0.036 3.384 ;
+ END
+ END wd_in[22]
+ PIN wd_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.408 0.036 3.432 ;
+ END
+ END wd_in[23]
+ PIN wd_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.456 0.036 3.480 ;
+ END
+ END wd_in[24]
+ PIN wd_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.504 0.036 3.528 ;
+ END
+ END wd_in[25]
+ PIN wd_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.552 0.036 3.576 ;
+ END
+ END wd_in[26]
+ PIN wd_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 3.600 0.036 3.624 ;
+ END
+ END wd_in[27]
+ PIN addr_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.560 0.036 4.584 ;
+ END
+ END addr_in[0]
+ PIN addr_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.608 0.036 4.632 ;
+ END
+ END addr_in[1]
+ PIN addr_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.656 0.036 4.680 ;
+ END
+ END addr_in[2]
+ PIN addr_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.704 0.036 4.728 ;
+ END
+ END addr_in[3]
+ PIN addr_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.752 0.036 4.776 ;
+ END
+ END addr_in[4]
+ PIN addr_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 4.800 0.036 4.824 ;
+ END
+ END addr_in[5]
+ PIN we_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.760 0.036 5.784 ;
+ END
+ END we_in
+ PIN ce_in
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.808 0.036 5.832 ;
+ END
+ END ce_in
+ PIN clk
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER M4 ;
+ RECT 0.000 5.856 0.036 5.880 ;
+ END
+ END clk
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER M4 ;
+ RECT 0.096 0.000 14.534 0.096 ;
+ RECT 0.096 0.768 14.534 0.864 ;
+ RECT 0.096 1.536 14.534 1.632 ;
+ RECT 0.096 2.304 14.534 2.400 ;
+ RECT 0.096 3.072 14.534 3.168 ;
+ RECT 0.096 3.840 14.534 3.936 ;
+ RECT 0.096 4.608 14.534 4.704 ;
+ RECT 0.096 5.376 14.534 5.472 ;
+ END
+ END VSS
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER M4 ;
+ RECT 0.096 0.384 14.534 0.480 ;
+ RECT 0.096 1.152 14.534 1.248 ;
+ RECT 0.096 1.920 14.534 2.016 ;
+ RECT 0.096 2.688 14.534 2.784 ;
+ RECT 0.096 3.456 14.534 3.552 ;
+ RECT 0.096 4.224 14.534 4.320 ;
+ RECT 0.096 4.992 14.534 5.088 ;
+ RECT 0.096 5.760 14.534 5.856 ;
+ END
+ END VDD
+ OBS
+ LAYER M1 ;
+ RECT 0 0 14.630 6.000 ;
+ LAYER M2 ;
+ RECT 0 0 14.630 6.000 ;
+ LAYER M3 ;
+ RECT 0 0 14.630 6.000 ;
+ LAYER M4 ;
+ RECT 0 0 14.630 6.000 ;
+ END
+END fakeram7_64x28
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib
new file mode 100644
index 0000000000..8bcf2d6ae7
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib
@@ -0,0 +1,389 @@
+library(fakeram7_128x64) {
+ technology (cmos);
+ delay_model : table_lookup;
+ revision : 1.0;
+ date : "2025-06-10 17:10:26Z";
+ comment : "SRAM";
+ time_unit : "1ns";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+ leakage_power_unit : "1uW";
+ nom_process : 1;
+ nom_temperature : 25.000;
+ nom_voltage : 0.7;
+ capacitive_load_unit (1,pf);
+
+ pulling_resistance_unit : "1kohm";
+
+ operating_conditions(tt_1.0_25.0) {
+ process : 1;
+ temperature : 25.000;
+ voltage : 0.7;
+ tree_type : balanced_tree;
+ }
+
+ /* default attributes */
+ default_cell_leakage_power : 0;
+ default_fanout_load : 1;
+ default_inout_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_output_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_max_transition : 0.227;
+
+ default_operating_conditions : tt_1.0_25.0;
+ default_leakage_power_density : 0.0;
+
+ /* additional header data */
+ slew_derate_from_library : 1.000;
+ slew_lower_threshold_pct_fall : 20.000;
+ slew_upper_threshold_pct_fall : 80.000;
+ slew_lower_threshold_pct_rise : 20.000;
+ slew_upper_threshold_pct_rise : 80.000;
+ input_threshold_pct_fall : 50.000;
+ input_threshold_pct_rise : 50.000;
+ output_threshold_pct_fall : 50.000;
+ output_threshold_pct_rise : 50.000;
+
+
+ lu_table_template(fakeram7_128x64_mem_out_delay_template) {
+ variable_1 : input_net_transition;
+ variable_2 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_128x64_mem_out_slew_template) {
+ variable_1 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_128x64_constraint_template) {
+ variable_1 : related_pin_transition;
+ variable_2 : constrained_pin_transition;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_128x64_energy_template_clkslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_128x64_energy_template_sigslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ library_features(report_delay_calculation);
+ type (fakeram7_128x64_DATA) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 64;
+ bit_from : 63;
+ bit_to : 0 ;
+ downto : true ;
+ }
+ type (fakeram7_128x64_ADDRESS) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 7;
+ bit_from : 6;
+ bit_to : 0 ;
+ downto : true ;
+ }
+cell(fakeram7_128x64) {
+ area : 343.985;
+ interface_timing : true;
+ memory() {
+ type : ram;
+ address_width : 7;
+ word_width : 64;
+ }
+ pin(clk) {
+ direction : input;
+ capacitance : 0.025;
+ clock : true;
+ min_period : 0.157 ;
+ internal_power(){
+ rise_power(fakeram7_128x64_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ fall_power(fakeram7_128x64_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ }
+ }
+
+ bus(rd_out) {
+ bus_type : fakeram7_128x64_DATA;
+ direction : output;
+ max_capacitance : 0.500;
+ memory_read() {
+ address : addr_in;
+ }
+ timing() {
+ related_pin : "clk" ;
+ timing_type : rising_edge;
+ timing_sense : non_unate;
+ cell_rise(fakeram7_128x64_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ cell_fall(fakeram7_128x64_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ rise_transition(fakeram7_128x64_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ fall_transition(fakeram7_128x64_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ }
+ }
+ pin(we_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ pin(ce_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(addr_in) {
+ bus_type : fakeram7_128x64_ADDRESS;
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(wd_in) {
+ bus_type : fakeram7_128x64_DATA;
+ memory_write() {
+ address : addr_in;
+ clocked_on : "clk";
+ }
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_128x64_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ when : "(! (we_in) )";
+ rise_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ internal_power(){
+ when : "(we_in)";
+ rise_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_128x64_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ cell_leakage_power : 128.900;
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib
new file mode 100644
index 0000000000..1afa95f09b
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib
@@ -0,0 +1,389 @@
+library(fakeram7_64x25) {
+ technology (cmos);
+ delay_model : table_lookup;
+ revision : 1.0;
+ date : "2025-06-10 17:10:26Z";
+ comment : "SRAM";
+ time_unit : "1ns";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+ leakage_power_unit : "1uW";
+ nom_process : 1;
+ nom_temperature : 25.000;
+ nom_voltage : 0.7;
+ capacitive_load_unit (1,pf);
+
+ pulling_resistance_unit : "1kohm";
+
+ operating_conditions(tt_1.0_25.0) {
+ process : 1;
+ temperature : 25.000;
+ voltage : 0.7;
+ tree_type : balanced_tree;
+ }
+
+ /* default attributes */
+ default_cell_leakage_power : 0;
+ default_fanout_load : 1;
+ default_inout_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_output_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_max_transition : 0.227;
+
+ default_operating_conditions : tt_1.0_25.0;
+ default_leakage_power_density : 0.0;
+
+ /* additional header data */
+ slew_derate_from_library : 1.000;
+ slew_lower_threshold_pct_fall : 20.000;
+ slew_upper_threshold_pct_fall : 80.000;
+ slew_lower_threshold_pct_rise : 20.000;
+ slew_upper_threshold_pct_rise : 80.000;
+ input_threshold_pct_fall : 50.000;
+ input_threshold_pct_rise : 50.000;
+ output_threshold_pct_fall : 50.000;
+ output_threshold_pct_rise : 50.000;
+
+
+ lu_table_template(fakeram7_64x25_mem_out_delay_template) {
+ variable_1 : input_net_transition;
+ variable_2 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_64x25_mem_out_slew_template) {
+ variable_1 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_64x25_constraint_template) {
+ variable_1 : related_pin_transition;
+ variable_2 : constrained_pin_transition;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_64x25_energy_template_clkslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_64x25_energy_template_sigslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ library_features(report_delay_calculation);
+ type (fakeram7_64x25_DATA) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 25;
+ bit_from : 24;
+ bit_to : 0 ;
+ downto : true ;
+ }
+ type (fakeram7_64x25_ADDRESS) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 6;
+ bit_from : 5;
+ bit_to : 0 ;
+ downto : true ;
+ }
+cell(fakeram7_64x25) {
+ area : 67.185;
+ interface_timing : true;
+ memory() {
+ type : ram;
+ address_width : 6;
+ word_width : 25;
+ }
+ pin(clk) {
+ direction : input;
+ capacitance : 0.025;
+ clock : true;
+ min_period : 0.157 ;
+ internal_power(){
+ rise_power(fakeram7_64x25_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ fall_power(fakeram7_64x25_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ }
+ }
+
+ bus(rd_out) {
+ bus_type : fakeram7_64x25_DATA;
+ direction : output;
+ max_capacitance : 0.500;
+ memory_read() {
+ address : addr_in;
+ }
+ timing() {
+ related_pin : "clk" ;
+ timing_type : rising_edge;
+ timing_sense : non_unate;
+ cell_rise(fakeram7_64x25_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ cell_fall(fakeram7_64x25_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ rise_transition(fakeram7_64x25_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ fall_transition(fakeram7_64x25_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ }
+ }
+ pin(we_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ pin(ce_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(addr_in) {
+ bus_type : fakeram7_64x25_ADDRESS;
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(wd_in) {
+ bus_type : fakeram7_64x25_DATA;
+ memory_write() {
+ address : addr_in;
+ clocked_on : "clk";
+ }
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x25_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ when : "(! (we_in) )";
+ rise_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ internal_power(){
+ when : "(we_in)";
+ rise_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x25_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ cell_leakage_power : 128.900;
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib
new file mode 100644
index 0000000000..8282373b44
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib
@@ -0,0 +1,389 @@
+library(fakeram7_64x256) {
+ technology (cmos);
+ delay_model : table_lookup;
+ revision : 1.0;
+ date : "2025-06-12 00:08:06Z";
+ comment : "SRAM";
+ time_unit : "1ns";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+ leakage_power_unit : "1uW";
+ nom_process : 1;
+ nom_temperature : 25.000;
+ nom_voltage : 0.7;
+ capacitive_load_unit (1,pf);
+
+ pulling_resistance_unit : "1kohm";
+
+ operating_conditions(tt_1.0_25.0) {
+ process : 1;
+ temperature : 25.000;
+ voltage : 0.7;
+ tree_type : balanced_tree;
+ }
+
+ /* default attributes */
+ default_cell_leakage_power : 0;
+ default_fanout_load : 1;
+ default_inout_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_output_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_max_transition : 0.227;
+
+ default_operating_conditions : tt_1.0_25.0;
+ default_leakage_power_density : 0.0;
+
+ /* additional header data */
+ slew_derate_from_library : 1.000;
+ slew_lower_threshold_pct_fall : 20.000;
+ slew_upper_threshold_pct_fall : 80.000;
+ slew_lower_threshold_pct_rise : 20.000;
+ slew_upper_threshold_pct_rise : 80.000;
+ input_threshold_pct_fall : 50.000;
+ input_threshold_pct_rise : 50.000;
+ output_threshold_pct_fall : 50.000;
+ output_threshold_pct_rise : 50.000;
+
+
+ lu_table_template(fakeram7_64x256_mem_out_delay_template) {
+ variable_1 : input_net_transition;
+ variable_2 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_64x256_mem_out_slew_template) {
+ variable_1 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_64x256_constraint_template) {
+ variable_1 : related_pin_transition;
+ variable_2 : constrained_pin_transition;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_64x256_energy_template_clkslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_64x256_energy_template_sigslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ library_features(report_delay_calculation);
+ type (fakeram7_64x256_DATA) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 256;
+ bit_from : 255;
+ bit_to : 0 ;
+ downto : true ;
+ }
+ type (fakeram7_64x256_ADDRESS) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 6;
+ bit_from : 5;
+ bit_to : 0 ;
+ downto : true ;
+ }
+cell(fakeram7_64x256) {
+ area : 1517.411;
+ interface_timing : true;
+ memory() {
+ type : ram;
+ address_width : 6;
+ word_width : 256;
+ }
+ pin(clk) {
+ direction : input;
+ capacitance : 0.025;
+ clock : true;
+ min_period : 0.157 ;
+ internal_power(){
+ rise_power(fakeram7_64x256_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ fall_power(fakeram7_64x256_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ }
+ }
+
+ bus(rd_out) {
+ bus_type : fakeram7_64x256_DATA;
+ direction : output;
+ max_capacitance : 0.500;
+ memory_read() {
+ address : addr_in;
+ }
+ timing() {
+ related_pin : "clk" ;
+ timing_type : rising_edge;
+ timing_sense : non_unate;
+ cell_rise(fakeram7_64x256_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ cell_fall(fakeram7_64x256_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ rise_transition(fakeram7_64x256_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ fall_transition(fakeram7_64x256_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ }
+ }
+ pin(we_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ pin(ce_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(addr_in) {
+ bus_type : fakeram7_64x256_ADDRESS;
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(wd_in) {
+ bus_type : fakeram7_64x256_DATA;
+ memory_write() {
+ address : addr_in;
+ clocked_on : "clk";
+ }
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x256_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ when : "(! (we_in) )";
+ rise_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ internal_power(){
+ when : "(we_in)";
+ rise_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x256_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ cell_leakage_power : 128.900;
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib
new file mode 100644
index 0000000000..1681b2bf1f
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib
@@ -0,0 +1,389 @@
+library(fakeram7_64x28) {
+ technology (cmos);
+ delay_model : table_lookup;
+ revision : 1.0;
+ date : "2025-06-10 17:10:26Z";
+ comment : "SRAM";
+ time_unit : "1ns";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+ leakage_power_unit : "1uW";
+ nom_process : 1;
+ nom_temperature : 25.000;
+ nom_voltage : 0.7;
+ capacitive_load_unit (1,pf);
+
+ pulling_resistance_unit : "1kohm";
+
+ operating_conditions(tt_1.0_25.0) {
+ process : 1;
+ temperature : 25.000;
+ voltage : 0.7;
+ tree_type : balanced_tree;
+ }
+
+ /* default attributes */
+ default_cell_leakage_power : 0;
+ default_fanout_load : 1;
+ default_inout_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_output_pin_cap : 0.0;
+ default_input_pin_cap : 0.0;
+ default_max_transition : 0.227;
+
+ default_operating_conditions : tt_1.0_25.0;
+ default_leakage_power_density : 0.0;
+
+ /* additional header data */
+ slew_derate_from_library : 1.000;
+ slew_lower_threshold_pct_fall : 20.000;
+ slew_upper_threshold_pct_fall : 80.000;
+ slew_lower_threshold_pct_rise : 20.000;
+ slew_upper_threshold_pct_rise : 80.000;
+ input_threshold_pct_fall : 50.000;
+ input_threshold_pct_rise : 50.000;
+ output_threshold_pct_fall : 50.000;
+ output_threshold_pct_rise : 50.000;
+
+
+ lu_table_template(fakeram7_64x28_mem_out_delay_template) {
+ variable_1 : input_net_transition;
+ variable_2 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_64x28_mem_out_slew_template) {
+ variable_1 : total_output_net_capacitance;
+ index_1 ("1000, 1001");
+ }
+ lu_table_template(fakeram7_64x28_constraint_template) {
+ variable_1 : related_pin_transition;
+ variable_2 : constrained_pin_transition;
+ index_1 ("1000, 1001");
+ index_2 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_64x28_energy_template_clkslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ power_lut_template(fakeram7_64x28_energy_template_sigslew) {
+ variable_1 : input_transition_time;
+ index_1 ("1000, 1001");
+ }
+ library_features(report_delay_calculation);
+ type (fakeram7_64x28_DATA) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 28;
+ bit_from : 27;
+ bit_to : 0 ;
+ downto : true ;
+ }
+ type (fakeram7_64x28_ADDRESS) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 6;
+ bit_from : 5;
+ bit_to : 0 ;
+ downto : true ;
+ }
+cell(fakeram7_64x28) {
+ area : 75.247;
+ interface_timing : true;
+ memory() {
+ type : ram;
+ address_width : 6;
+ word_width : 28;
+ }
+ pin(clk) {
+ direction : input;
+ capacitance : 0.025;
+ clock : true;
+ min_period : 0.157 ;
+ internal_power(){
+ rise_power(fakeram7_64x28_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ fall_power(fakeram7_64x28_energy_template_clkslew) {
+ index_1 ("0.009, 0.227");
+ values ("1.345, 1.345")
+ }
+ }
+ }
+
+ bus(rd_out) {
+ bus_type : fakeram7_64x28_DATA;
+ direction : output;
+ max_capacitance : 0.500;
+ memory_read() {
+ address : addr_in;
+ }
+ timing() {
+ related_pin : "clk" ;
+ timing_type : rising_edge;
+ timing_sense : non_unate;
+ cell_rise(fakeram7_64x28_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ cell_fall(fakeram7_64x28_mem_out_delay_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.005, 0.500");
+ values ( \
+ "0.218, 0.218", \
+ "0.218, 0.218" \
+ )
+ }
+ rise_transition(fakeram7_64x28_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ fall_transition(fakeram7_64x28_mem_out_slew_template) {
+ index_1 ("0.005, 0.500");
+ values ("0.009, 0.227")
+ }
+ }
+ }
+ pin(we_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ pin(ce_in){
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(addr_in) {
+ bus_type : fakeram7_64x28_ADDRESS;
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ rise_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ bus(wd_in) {
+ bus_type : fakeram7_64x28_DATA;
+ memory_write() {
+ address : addr_in;
+ clocked_on : "clk";
+ }
+ direction : input;
+ capacitance : 0.005;
+ timing() {
+ related_pin : clk;
+ timing_type : setup_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ timing() {
+ related_pin : clk;
+ timing_type : hold_rising ;
+ rise_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ fall_constraint(fakeram7_64x28_constraint_template) {
+ index_1 ("0.009, 0.227");
+ index_2 ("0.009, 0.227");
+ values ( \
+ "0.050, 0.050", \
+ "0.050, 0.050" \
+ )
+ }
+ }
+ internal_power(){
+ when : "(! (we_in) )";
+ rise_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ internal_power(){
+ when : "(we_in)";
+ rise_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ fall_power(fakeram7_64x28_energy_template_sigslew) {
+ index_1 ("0.009, 0.227");
+ values ("0.013, 0.013")
+ }
+ }
+ }
+ cell_leakage_power : 128.900;
+}
+
+}
diff --git a/flow/platforms/asap7/openRoad/make_tracks.tcl b/flow/platforms/asap7/openRoad/make_tracks.tcl
index f404ab2209..ffd85fc94b 100644
--- a/flow/platforms/asap7/openRoad/make_tracks.tcl
+++ b/flow/platforms/asap7/openRoad/make_tracks.tcl
@@ -1,18 +1,18 @@
make_tracks Pad -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
-make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
-make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
-make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064
-make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064
-make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
-make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048
-make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
+make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
+make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
+make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064
+make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064
+make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
+make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048
+make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270
-make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270
-make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
+make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl
index bd7977d717..02d76cdcec 100644
--- a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl
+++ b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl
@@ -18,9 +18,9 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
define_pdn_grid -name {top} -voltage_domains {CORE}
add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
-add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504}
+add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504}
-add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring
add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} -offset {1.504} -extend_to_core_ring
add_pdn_connect -grid {top} -layers {M1 M2}
@@ -41,7 +41,7 @@ foreach macro [find_macros] {
set macro_names [dict keys $macro_names]
define_pdn_grid -macro -cells $macro_names \
- -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \
- -voltage_domains {CORE} -name ElementGrid
+ -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \
+ -voltage_domains {CORE} -name ElementGrid
add_pdn_connect -grid {ElementGrid} -layers {M5 M6}
diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
index 26234aae64..b8d6c4d392 100644
--- a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
+++ b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
@@ -20,14 +20,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
####################################
define_pdn_grid -name {top} -voltage_domains {CORE}
-add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084}
+add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084}
-add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
-add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
-add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring
add_pdn_connect -grid {top} -layers {M1 M2}
add_pdn_connect -grid {top} -layers {M2 M5}
add_pdn_connect -grid {top} -layers {M4 M5}
-
diff --git a/flow/platforms/asap7/openRoad/tapcell.tcl b/flow/platforms/asap7/openRoad/tapcell.tcl
index 9526ba83d0..809d6952aa 100644
--- a/flow/platforms/asap7/openRoad/tapcell.tcl
+++ b/flow/platforms/asap7/openRoad/tapcell.tcl
@@ -9,6 +9,6 @@ puts " TAP Cell Distance : 25"
tapcell \
-distance 25 \
-tapcell_master "$::env(TAP_CELL_NAME)" \
- -endcap_master "$::env(TAP_CELL_NAME)" \
+ -endcap_master "$::env(TAP_CELL_NAME)" \
-halo_width_x $::env(MACRO_ROWS_HALO_X) \
-halo_width_y $::env(MACRO_ROWS_HALO_Y)
diff --git a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl
index 28c2da3eed..9e23b6d0bd 100644
--- a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl
+++ b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl
@@ -11,9 +11,9 @@ set ::env(LIB_SLOWEST) ""
set lib_path "$libs_ref/lib"
foreach lib {"AO" "INVBUF" "OA" "SEQ" "SIMPLE"} {
- append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib "
- append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib "
- append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib "
+ append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib "
+ append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib "
+ append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib "
}
set ::env(LIB_SYNTH) $::env(LIB_TYPICAL)
@@ -36,7 +36,7 @@ set ::env(FP_ENDCAP_CELL) "TAPCELL_ASAP7_75t_R"
# defaults (can be overridden by designs):
set ::env(SYNTH_DRIVING_CELL) "BUFx2_ASAP7_75t_R"
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "4.61057" ; # femtofarad INVx8_ASAP7_75t_R pin A cap
+set ::env(SYNTH_CAP_LOAD) "4.61057" ;# femtofarad INVx8_ASAP7_75t_R pin A cap
set ::env(SYNTH_MIN_BUF_PORT) "BUFx2_ASAP7_75t_R A Y"
set ::env(SYNTH_TIEHI_PORT) "TIEHIx1_ASAP7_75t_R H"
set ::env(SYNTH_TIELO_PORT) "TIELOx1_ASAP7_75t_R L"
diff --git a/flow/platforms/asap7/openlane/config.tcl b/flow/platforms/asap7/openlane/config.tcl
index d7a4ee0bd1..ac404b4e2f 100755
--- a/flow/platforms/asap7/openlane/config.tcl
+++ b/flow/platforms/asap7/openlane/config.tcl
@@ -15,7 +15,7 @@ set ::env(STD_CELL_GROUND_PINS) "VSS"
set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/asap7_tech_1x_201209.lef"
set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]
set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"]
-set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl"
+set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl"
set ::env(GPIO_PADS_LEF) ""
@@ -25,7 +25,7 @@ set ::env(GPIO_PADS_VERILOG) ""
set ::env(TECH_LEF_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/techlef/$::env(STD_CELL_LIBRARY_OPT).tlef"
set ::env(CELLS_LEF_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/lef/*.lef"]
set ::env(GDS_FILES_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/gds/*.gds"]
-set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl"
+set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl"
# Optimization library slowest corner
diff --git a/flow/platforms/asap7/ram/cva6.cfg b/flow/platforms/asap7/ram/cva6.cfg
new file mode 100644
index 0000000000..a7d378fa0e
--- /dev/null
+++ b/flow/platforms/asap7/ram/cva6.cfg
@@ -0,0 +1,50 @@
+#SAMPLE INPUT FILE; VALUES NOT REALISTIC
+{
+ # The process node.
+ "tech_nm": 7,
+
+ # The operating voltage.
+ "voltage": 0.7,
+
+ # String to add in front of every metal layer number for the layer name.
+ "metal_prefix": "M",
+
+ # Horizontal Metal layer for macro pins
+ "metal_layer": "M4",
+
+ # The pin width for signal pins.
+ "pin_width_nm": 24,
+
+ # The minimum pin pitch for signal pins
+ "pin_pitch_nm": 48,
+
+ # Metal track pitch
+ "metal_track_pitch_nm": 48,
+
+ # Manufacturing Grid
+ "manufacturing_grid_nm": 1,
+
+ # Contacted Poly Pitch
+ "contacted_poly_pitch_nm": 54,
+
+ #column mux factor
+ "column_mux_factor": 1,
+
+ # Fin pitch
+ "fin_pitch_nm" : 27,
+
+ # Optional snap the width and height of the sram to a multiple value.
+ "snap_width_nm": 190,
+ "snap_height_nm": 1200,
+
+ # List of SRAM configurations (name width depth and banks)
+ "srams": [
+ {"name": "fakeram7_64x28", "width": 28, "depth": 64, "banks": 4},
+ {"name": "fakeram7_128x64", "width": 64, "depth": 128, "banks": 2},
+ {"name": "fakeram7_64x25", "width": 25, "depth": 64, "banks": 4},
+ {"name": "fakeram7_64x256", "width": 256, "depth": 64, "banks": 1,
+ "additional_height": 25}
+ ]
+
+ # TENTATIVE PARAMETERS
+}
diff --git a/flow/platforms/asap7/verilog/fakeram7_128x64.sv b/flow/platforms/asap7/verilog/fakeram7_128x64.sv
new file mode 100644
index 0000000000..d7353e1c65
--- /dev/null
+++ b/flow/platforms/asap7/verilog/fakeram7_128x64.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module fakeram7_128x64 (
+ output reg [63:0] rd_out,
+ input [6:0] addr_in,
+ input we_in,
+ input [63:0] wd_in,
+ input clk,
+ input ce_in
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/fakeram7_64x25.sv b/flow/platforms/asap7/verilog/fakeram7_64x25.sv
new file mode 100644
index 0000000000..4d2c60724d
--- /dev/null
+++ b/flow/platforms/asap7/verilog/fakeram7_64x25.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module fakeram7_64x25 (
+ output reg [24:0] rd_out,
+ input [5:0] addr_in,
+ input we_in,
+ input [24:0] wd_in,
+ input clk,
+ input ce_in
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/fakeram7_64x256.sv b/flow/platforms/asap7/verilog/fakeram7_64x256.sv
new file mode 100644
index 0000000000..b87ffae7d7
--- /dev/null
+++ b/flow/platforms/asap7/verilog/fakeram7_64x256.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module fakeram7_64x256 (
+ output reg [255:0] rd_out,
+ input [5:0] addr_in,
+ input we_in,
+ input [255:0] wd_in,
+ input clk,
+ input ce_in
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/fakeram7_64x28.sv b/flow/platforms/asap7/verilog/fakeram7_64x28.sv
new file mode 100644
index 0000000000..7ed704addd
--- /dev/null
+++ b/flow/platforms/asap7/verilog/fakeram7_64x28.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module fakeram7_64x28 (
+ output reg [27:0] rd_out,
+ input [5:0] addr_in,
+ input we_in,
+ input [27:0] wd_in,
+ input clk,
+ input ce_in
+);
+endmodule
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v
new file mode 100644
index 0000000000..67002d6142
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v
@@ -0,0 +1,3627 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_LVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module A2O1A1Ixp33_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0, C__bar);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module A2O1A1O1Ixp25_ASAP7_75t_L (Y, A1, A2, B, C, D);
+ output Y;
+ input A1, A2, B, C, D;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, D__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ and (int_fwire_0, C__bar, D__bar);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar, D__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar, D__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO211x2_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2);
+ or (Y, int_fwire_0, B, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO21x1_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2);
+ or (Y, int_fwire_0, B);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO21x2_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2);
+ or (Y, int_fwire_0, B);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO221x1_ASAP7_75t_L (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO221x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO222x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2);
+ and (int_fwire_2, A1, A2);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO22x1_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO22x2_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO31x2_ASAP7_75t_L (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2, A3);
+ or (Y, int_fwire_0, B);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO322x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO32x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO32x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO331x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2, B3);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO331x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2, B3);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO332x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO332x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO333x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2, C3);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO333x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2, C3);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO33x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2, B3);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI211x1_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI211xp5_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI21x1_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ if ((~A1 & ~A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI21xp33_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ if ((~A1 & ~A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI21xp5_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ if ((~A1 & ~A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI221x1_ASAP7_75t_L (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar, C__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar, C__bar);
+ and (int_fwire_3, A1__bar, B1__bar, C__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI221xp5_ASAP7_75t_L (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar, C__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar, C__bar);
+ and (int_fwire_3, A1__bar, B1__bar, C__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI222xp33_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C1__bar, C2__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7;
+
+ not (C2__bar, C2);
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_1, A2__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_3, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_4, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_5, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_6, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_7, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI22x1_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3;
+
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar);
+ and (int_fwire_3, A1__bar, B1__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI22xp33_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3;
+
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar);
+ and (int_fwire_3, A1__bar, B1__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI22xp5_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3;
+
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar);
+ and (int_fwire_3, A1__bar, B1__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI311xp33_ASAP7_75t_L (Y, A1, A2, A3, B, C);
+ output Y;
+ input A1, A2, A3, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, C__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B__bar, C__bar);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar, C__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~C))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI31xp33_ASAP7_75t_L (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B__bar);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI31xp67_ASAP7_75t_L (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B__bar);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI321xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C);
+ output Y;
+ input A1, A2, A3, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B2__bar, C__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A3__bar, B1__bar, C__bar);
+ not (A2__bar, A2);
+ and (int_fwire_2, A2__bar, B2__bar, C__bar);
+ and (int_fwire_3, A2__bar, B1__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_4, A1__bar, B2__bar, C__bar);
+ and (int_fwire_5, A1__bar, B1__bar, C__bar);
+ or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI322xp5_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C1__bar;
+ wire C2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3, int_fwire_4;
+ wire int_fwire_5, int_fwire_6, int_fwire_7;
+ wire int_fwire_8, int_fwire_9, int_fwire_10;
+ wire int_fwire_11;
+
+ not (C2__bar, C2);
+ not (B2__bar, B2);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B2__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_1, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A3__bar, B1__bar, C2__bar);
+ and (int_fwire_3, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_4, A2__bar, B2__bar, C2__bar);
+ and (int_fwire_5, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_6, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_7, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_8, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_9, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_10, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_11, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI32xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+ wire int_fwire_4, int_fwire_5;
+
+ not (B2__bar, B2);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A3__bar, B1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_2, A2__bar, B2__bar);
+ and (int_fwire_3, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_4, A1__bar, B2__bar);
+ and (int_fwire_5, A1__bar, B1__bar);
+ or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI331xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3, int_fwire_4;
+ wire int_fwire_5, int_fwire_6, int_fwire_7;
+ wire int_fwire_8;
+
+ not (C1__bar, C1);
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar, C1__bar);
+ not (B2__bar, B2);
+ and (int_fwire_1, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_3, A2__bar, B3__bar, C1__bar);
+ and (int_fwire_4, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_5, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_6, A1__bar, B3__bar, C1__bar);
+ and (int_fwire_7, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_8, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI332xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+ wire int_fwire_4, int_fwire_5, int_fwire_6;
+ wire int_fwire_7, int_fwire_8, int_fwire_9;
+ wire int_fwire_10, int_fwire_11, int_fwire_12;
+ wire int_fwire_13, int_fwire_14, int_fwire_15;
+ wire int_fwire_16, int_fwire_17;
+
+ not (C2__bar, C2);
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_1, A3__bar, B3__bar, C1__bar);
+ not (B2__bar, B2);
+ and (int_fwire_2, A3__bar, B2__bar, C2__bar);
+ and (int_fwire_3, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_4, A3__bar, B1__bar, C2__bar);
+ and (int_fwire_5, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_6, A2__bar, B3__bar, C2__bar);
+ and (int_fwire_7, A2__bar, B3__bar, C1__bar);
+ and (int_fwire_8, A2__bar, B2__bar, C2__bar);
+ and (int_fwire_9, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_10, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_11, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_12, A1__bar, B3__bar, C2__bar);
+ and (int_fwire_13, A1__bar, B3__bar, C1__bar);
+ and (int_fwire_14, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_15, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_16, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_17, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI333xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, C3__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+ wire int_fwire_18, int_fwire_19, int_fwire_20;
+ wire int_fwire_21, int_fwire_22, int_fwire_23;
+ wire int_fwire_24, int_fwire_25, int_fwire_26;
+
+ not (C3__bar, C3);
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar, C3__bar);
+ not (C2__bar, C2);
+ and (int_fwire_1, A3__bar, B3__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_2, A3__bar, B3__bar, C1__bar);
+ not (B2__bar, B2);
+ and (int_fwire_3, A3__bar, B2__bar, C3__bar);
+ and (int_fwire_4, A3__bar, B2__bar, C2__bar);
+ and (int_fwire_5, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_6, A3__bar, B1__bar, C3__bar);
+ and (int_fwire_7, A3__bar, B1__bar, C2__bar);
+ and (int_fwire_8, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_9, A2__bar, B3__bar, C3__bar);
+ and (int_fwire_10, A2__bar, B3__bar, C2__bar);
+ and (int_fwire_11, A2__bar, B3__bar, C1__bar);
+ and (int_fwire_12, A2__bar, B2__bar, C3__bar);
+ and (int_fwire_13, A2__bar, B2__bar, C2__bar);
+ and (int_fwire_14, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_15, A2__bar, B1__bar, C3__bar);
+ and (int_fwire_16, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_17, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_18, A1__bar, B3__bar, C3__bar);
+ and (int_fwire_19, A1__bar, B3__bar, C2__bar);
+ and (int_fwire_20, A1__bar, B3__bar, C1__bar);
+ and (int_fwire_21, A1__bar, B2__bar, C3__bar);
+ and (int_fwire_22, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_23, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_24, A1__bar, B1__bar, C3__bar);
+ and (int_fwire_25, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_26, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI33xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar);
+ not (B2__bar, B2);
+ and (int_fwire_1, A3__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A3__bar, B1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_3, A2__bar, B3__bar);
+ and (int_fwire_4, A2__bar, B2__bar);
+ and (int_fwire_5, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_6, A1__bar, B3__bar);
+ and (int_fwire_7, A1__bar, B2__bar);
+ and (int_fwire_8, A1__bar, B1__bar);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v
new file mode 100644
index 0000000000..b33fb13e52
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v
@@ -0,0 +1,3627 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_SLVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module A2O1A1Ixp33_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0, C__bar);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module A2O1A1O1Ixp25_ASAP7_75t_SL (Y, A1, A2, B, C, D);
+ output Y;
+ input A1, A2, B, C, D;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, D__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ and (int_fwire_0, C__bar, D__bar);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar, D__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar, D__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO211x2_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2);
+ or (Y, int_fwire_0, B, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO21x1_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2);
+ or (Y, int_fwire_0, B);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO21x2_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2);
+ or (Y, int_fwire_0, B);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO221x1_ASAP7_75t_SL (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO221x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO222x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2);
+ and (int_fwire_2, A1, A2);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO22x2_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO31x2_ASAP7_75t_SL (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire int_fwire_0;
+
+ and (int_fwire_0, A1, A2, A3);
+ or (Y, int_fwire_0, B);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO322x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO32x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO32x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO331x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2, B3);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO331x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2, B3);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0, C);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO332x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO332x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO333x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2, C3);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO333x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, C1, C2, C3);
+ and (int_fwire_1, B1, B2, B3);
+ and (int_fwire_2, A1, A2, A3);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AO33x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, B1, B2, B3);
+ and (int_fwire_1, A1, A2, A3);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI211x1_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI211xp5_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI21x1_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ if ((~A1 & ~A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI21xp33_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ if ((~A1 & ~A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI21xp5_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ if ((~A1 & ~A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI221x1_ASAP7_75t_SL (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar, C__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar, C__bar);
+ and (int_fwire_3, A1__bar, B1__bar, C__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI221xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar, C__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar, C__bar);
+ and (int_fwire_3, A1__bar, B1__bar, C__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI222xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C1__bar, C2__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7;
+
+ not (C2__bar, C2);
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_1, A2__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_3, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_4, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_5, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_6, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_7, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3;
+
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar);
+ and (int_fwire_3, A1__bar, B1__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI22xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3;
+
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar);
+ and (int_fwire_3, A1__bar, B1__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI22xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3;
+
+ not (B2__bar, B2);
+ not (A2__bar, A2);
+ and (int_fwire_0, A2__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B2__bar);
+ and (int_fwire_3, A1__bar, B1__bar);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI311xp33_ASAP7_75t_SL (Y, A1, A2, A3, B, C);
+ output Y;
+ input A1, A2, A3, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, C__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B__bar, C__bar);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar, C__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~C))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI31xp33_ASAP7_75t_SL (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B__bar);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI31xp67_ASAP7_75t_SL (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B__bar);
+ not (A2__bar, A2);
+ and (int_fwire_1, A2__bar, B__bar);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, B__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI321xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C);
+ output Y;
+ input A1, A2, A3, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B2__bar, C__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A3__bar, B1__bar, C__bar);
+ not (A2__bar, A2);
+ and (int_fwire_2, A2__bar, B2__bar, C__bar);
+ and (int_fwire_3, A2__bar, B1__bar, C__bar);
+ not (A1__bar, A1);
+ and (int_fwire_4, A1__bar, B2__bar, C__bar);
+ and (int_fwire_5, A1__bar, B1__bar, C__bar);
+ or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~C))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~C))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & ~C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI322xp5_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C1__bar;
+ wire C2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3, int_fwire_4;
+ wire int_fwire_5, int_fwire_6, int_fwire_7;
+ wire int_fwire_8, int_fwire_9, int_fwire_10;
+ wire int_fwire_11;
+
+ not (C2__bar, C2);
+ not (B2__bar, B2);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B2__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_1, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A3__bar, B1__bar, C2__bar);
+ and (int_fwire_3, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_4, A2__bar, B2__bar, C2__bar);
+ and (int_fwire_5, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_6, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_7, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_8, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_9, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_10, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_11, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI32xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+ wire int_fwire_4, int_fwire_5;
+
+ not (B2__bar, B2);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_1, A3__bar, B1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_2, A2__bar, B2__bar);
+ and (int_fwire_3, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_4, A1__bar, B2__bar);
+ and (int_fwire_5, A1__bar, B1__bar);
+ or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI331xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2, int_fwire_3, int_fwire_4;
+ wire int_fwire_5, int_fwire_6, int_fwire_7;
+ wire int_fwire_8;
+
+ not (C1__bar, C1);
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar, C1__bar);
+ not (B2__bar, B2);
+ and (int_fwire_1, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_3, A2__bar, B3__bar, C1__bar);
+ and (int_fwire_4, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_5, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_6, A1__bar, B3__bar, C1__bar);
+ and (int_fwire_7, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_8, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI332xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2, int_fwire_3;
+ wire int_fwire_4, int_fwire_5, int_fwire_6;
+ wire int_fwire_7, int_fwire_8, int_fwire_9;
+ wire int_fwire_10, int_fwire_11, int_fwire_12;
+ wire int_fwire_13, int_fwire_14, int_fwire_15;
+ wire int_fwire_16, int_fwire_17;
+
+ not (C2__bar, C2);
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_1, A3__bar, B3__bar, C1__bar);
+ not (B2__bar, B2);
+ and (int_fwire_2, A3__bar, B2__bar, C2__bar);
+ and (int_fwire_3, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_4, A3__bar, B1__bar, C2__bar);
+ and (int_fwire_5, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_6, A2__bar, B3__bar, C2__bar);
+ and (int_fwire_7, A2__bar, B3__bar, C1__bar);
+ and (int_fwire_8, A2__bar, B2__bar, C2__bar);
+ and (int_fwire_9, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_10, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_11, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_12, A1__bar, B3__bar, C2__bar);
+ and (int_fwire_13, A1__bar, B3__bar, C1__bar);
+ and (int_fwire_14, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_15, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_16, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_17, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI333xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, C3__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+ wire int_fwire_18, int_fwire_19, int_fwire_20;
+ wire int_fwire_21, int_fwire_22, int_fwire_23;
+ wire int_fwire_24, int_fwire_25, int_fwire_26;
+
+ not (C3__bar, C3);
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar, C3__bar);
+ not (C2__bar, C2);
+ and (int_fwire_1, A3__bar, B3__bar, C2__bar);
+ not (C1__bar, C1);
+ and (int_fwire_2, A3__bar, B3__bar, C1__bar);
+ not (B2__bar, B2);
+ and (int_fwire_3, A3__bar, B2__bar, C3__bar);
+ and (int_fwire_4, A3__bar, B2__bar, C2__bar);
+ and (int_fwire_5, A3__bar, B2__bar, C1__bar);
+ not (B1__bar, B1);
+ and (int_fwire_6, A3__bar, B1__bar, C3__bar);
+ and (int_fwire_7, A3__bar, B1__bar, C2__bar);
+ and (int_fwire_8, A3__bar, B1__bar, C1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_9, A2__bar, B3__bar, C3__bar);
+ and (int_fwire_10, A2__bar, B3__bar, C2__bar);
+ and (int_fwire_11, A2__bar, B3__bar, C1__bar);
+ and (int_fwire_12, A2__bar, B2__bar, C3__bar);
+ and (int_fwire_13, A2__bar, B2__bar, C2__bar);
+ and (int_fwire_14, A2__bar, B2__bar, C1__bar);
+ and (int_fwire_15, A2__bar, B1__bar, C3__bar);
+ and (int_fwire_16, A2__bar, B1__bar, C2__bar);
+ and (int_fwire_17, A2__bar, B1__bar, C1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_18, A1__bar, B3__bar, C3__bar);
+ and (int_fwire_19, A1__bar, B3__bar, C2__bar);
+ and (int_fwire_20, A1__bar, B3__bar, C1__bar);
+ and (int_fwire_21, A1__bar, B2__bar, C3__bar);
+ and (int_fwire_22, A1__bar, B2__bar, C2__bar);
+ and (int_fwire_23, A1__bar, B2__bar, C1__bar);
+ and (int_fwire_24, A1__bar, B1__bar, C3__bar);
+ and (int_fwire_25, A1__bar, B1__bar, C2__bar);
+ and (int_fwire_26, A1__bar, B1__bar, C1__bar);
+ or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AOI33xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ not (B3__bar, B3);
+ not (A3__bar, A3);
+ and (int_fwire_0, A3__bar, B3__bar);
+ not (B2__bar, B2);
+ and (int_fwire_1, A3__bar, B2__bar);
+ not (B1__bar, B1);
+ and (int_fwire_2, A3__bar, B1__bar);
+ not (A2__bar, A2);
+ and (int_fwire_3, A2__bar, B3__bar);
+ and (int_fwire_4, A2__bar, B2__bar);
+ and (int_fwire_5, A2__bar, B1__bar);
+ not (A1__bar, A1);
+ and (int_fwire_6, A1__bar, B3__bar);
+ and (int_fwire_7, A1__bar, B2__bar);
+ and (int_fwire_8, A1__bar, B1__bar);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((A2 & A3 & B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((A2 & A3 & ~B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((A1 & A3 & B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((A1 & A3 & ~B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B2 & B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & ~A3 & B1 & B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v
new file mode 100644
index 0000000000..8d929214e2
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v
@@ -0,0 +1,663 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_LVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx10_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx12_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx12f_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx16f_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx24_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx2_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx3_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx4_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx4f_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx5_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx6f_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx8_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx10_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx11_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx12_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx14_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx16_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx20_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx5p33_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx6p67_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx8_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx9p33_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB1xp67_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB2xp67_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB3xp67_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB4xp67_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx11_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx13_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx1_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx2_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx3_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx4_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx5_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx6_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx8_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVxp33_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVxp67_ASAP7_75t_L (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v
new file mode 100644
index 0000000000..7a29306535
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v
@@ -0,0 +1,664 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx10_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx12_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx12f_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx16f_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx24_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx2_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx3_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx4_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx4f_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx5_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx6f_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module BUFx8_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx10_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx11_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx12_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx14_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx16_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx20_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx5p33_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx6p67_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx8_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module CKINVDCx9p33_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB1xp67_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB2xp67_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB3xp67_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HB4xp67_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx11_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx13_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx1_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx2_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx3_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx4_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx5_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx6_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVx8_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVxp33_ASAP7_75t_SL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module INVxp67_ASAP7_75t_SL
+ (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v
new file mode 100644
index 0000000000..65fc6836e8
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v
@@ -0,0 +1,5243 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_LVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module O2A1O1Ixp33_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, C__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module O2A1O1Ixp5_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, C__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A2 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA211x2_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, A2, B, C);
+ and (int_fwire_1, A1, B, C);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & A2 & B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA21x2_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, A2, B);
+ and (int_fwire_1, A1, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA221x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3;
+
+ and (int_fwire_0, A2, B2, C);
+ and (int_fwire_1, A2, B1, C);
+ and (int_fwire_2, A1, B2, C);
+ and (int_fwire_3, A1, B1, C);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA222x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7;
+
+ and (int_fwire_0, A2, B2, C2);
+ and (int_fwire_1, A2, B2, C1);
+ and (int_fwire_2, A2, B1, C2);
+ and (int_fwire_3, A2, B1, C1);
+ and (int_fwire_4, A1, B2, C2);
+ and (int_fwire_5, A1, B2, C1);
+ and (int_fwire_6, A1, B1, C2);
+ and (int_fwire_7, A1, B1, C1);
+ or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA22x2_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3;
+
+ and (int_fwire_0, A2, B2);
+ and (int_fwire_1, A2, B1);
+ and (int_fwire_2, A1, B2);
+ and (int_fwire_3, A1, B1);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA31x2_ASAP7_75t_L (Y, A1, A2, A3, B1);
+ output Y;
+ input A1, A2, A3, B1;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, A3, B1);
+ and (int_fwire_1, A2, B1);
+ and (int_fwire_2, A1, B1);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3) | (~A1 & A2 & A3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3))
+ (B1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA331x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ and (int_fwire_0, A3, B3, C1);
+ and (int_fwire_1, A3, B2, C1);
+ and (int_fwire_2, A3, B1, C1);
+ and (int_fwire_3, A2, B3, C1);
+ and (int_fwire_4, A2, B2, C1);
+ and (int_fwire_5, A2, B1, C1);
+ and (int_fwire_6, A1, B3, C1);
+ and (int_fwire_7, A1, B2, C1);
+ and (int_fwire_8, A1, B1, C1);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA331x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ and (int_fwire_0, A3, B3, C1);
+ and (int_fwire_1, A3, B2, C1);
+ and (int_fwire_2, A3, B1, C1);
+ and (int_fwire_3, A2, B3, C1);
+ and (int_fwire_4, A2, B2, C1);
+ and (int_fwire_5, A2, B1, C1);
+ and (int_fwire_6, A1, B3, C1);
+ and (int_fwire_7, A1, B2, C1);
+ and (int_fwire_8, A1, B1, C1);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA332x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+
+ and (int_fwire_0, A3, B3, C2);
+ and (int_fwire_1, A3, B3, C1);
+ and (int_fwire_2, A3, B2, C2);
+ and (int_fwire_3, A3, B2, C1);
+ and (int_fwire_4, A3, B1, C2);
+ and (int_fwire_5, A3, B1, C1);
+ and (int_fwire_6, A2, B3, C2);
+ and (int_fwire_7, A2, B3, C1);
+ and (int_fwire_8, A2, B2, C2);
+ and (int_fwire_9, A2, B2, C1);
+ and (int_fwire_10, A2, B1, C2);
+ and (int_fwire_11, A2, B1, C1);
+ and (int_fwire_12, A1, B3, C2);
+ and (int_fwire_13, A1, B3, C1);
+ and (int_fwire_14, A1, B2, C2);
+ and (int_fwire_15, A1, B2, C1);
+ and (int_fwire_16, A1, B1, C2);
+ and (int_fwire_17, A1, B1, C1);
+ or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA332x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+
+ and (int_fwire_0, A3, B3, C2);
+ and (int_fwire_1, A3, B3, C1);
+ and (int_fwire_2, A3, B2, C2);
+ and (int_fwire_3, A3, B2, C1);
+ and (int_fwire_4, A3, B1, C2);
+ and (int_fwire_5, A3, B1, C1);
+ and (int_fwire_6, A2, B3, C2);
+ and (int_fwire_7, A2, B3, C1);
+ and (int_fwire_8, A2, B2, C2);
+ and (int_fwire_9, A2, B2, C1);
+ and (int_fwire_10, A2, B1, C2);
+ and (int_fwire_11, A2, B1, C1);
+ and (int_fwire_12, A1, B3, C2);
+ and (int_fwire_13, A1, B3, C1);
+ and (int_fwire_14, A1, B2, C2);
+ and (int_fwire_15, A1, B2, C1);
+ and (int_fwire_16, A1, B1, C2);
+ and (int_fwire_17, A1, B1, C1);
+ or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA333x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+ wire int_fwire_18, int_fwire_19, int_fwire_20;
+ wire int_fwire_21, int_fwire_22, int_fwire_23;
+ wire int_fwire_24, int_fwire_25, int_fwire_26;
+
+ and (int_fwire_0, A3, B3, C3);
+ and (int_fwire_1, A3, B3, C2);
+ and (int_fwire_2, A3, B3, C1);
+ and (int_fwire_3, A3, B2, C3);
+ and (int_fwire_4, A3, B2, C2);
+ and (int_fwire_5, A3, B2, C1);
+ and (int_fwire_6, A3, B1, C3);
+ and (int_fwire_7, A3, B1, C2);
+ and (int_fwire_8, A3, B1, C1);
+ and (int_fwire_9, A2, B3, C3);
+ and (int_fwire_10, A2, B3, C2);
+ and (int_fwire_11, A2, B3, C1);
+ and (int_fwire_12, A2, B2, C3);
+ and (int_fwire_13, A2, B2, C2);
+ and (int_fwire_14, A2, B2, C1);
+ and (int_fwire_15, A2, B1, C3);
+ and (int_fwire_16, A2, B1, C2);
+ and (int_fwire_17, A2, B1, C1);
+ and (int_fwire_18, A1, B3, C3);
+ and (int_fwire_19, A1, B3, C2);
+ and (int_fwire_20, A1, B3, C1);
+ and (int_fwire_21, A1, B2, C3);
+ and (int_fwire_22, A1, B2, C2);
+ and (int_fwire_23, A1, B2, C1);
+ and (int_fwire_24, A1, B1, C3);
+ and (int_fwire_25, A1, B1, C2);
+ and (int_fwire_26, A1, B1, C1);
+ or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA333x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+ wire int_fwire_18, int_fwire_19, int_fwire_20;
+ wire int_fwire_21, int_fwire_22, int_fwire_23;
+ wire int_fwire_24, int_fwire_25, int_fwire_26;
+
+ and (int_fwire_0, A3, B3, C3);
+ and (int_fwire_1, A3, B3, C2);
+ and (int_fwire_2, A3, B3, C1);
+ and (int_fwire_3, A3, B2, C3);
+ and (int_fwire_4, A3, B2, C2);
+ and (int_fwire_5, A3, B2, C1);
+ and (int_fwire_6, A3, B1, C3);
+ and (int_fwire_7, A3, B1, C2);
+ and (int_fwire_8, A3, B1, C1);
+ and (int_fwire_9, A2, B3, C3);
+ and (int_fwire_10, A2, B3, C2);
+ and (int_fwire_11, A2, B3, C1);
+ and (int_fwire_12, A2, B2, C3);
+ and (int_fwire_13, A2, B2, C2);
+ and (int_fwire_14, A2, B2, C1);
+ and (int_fwire_15, A2, B1, C3);
+ and (int_fwire_16, A2, B1, C2);
+ and (int_fwire_17, A2, B1, C1);
+ and (int_fwire_18, A1, B3, C3);
+ and (int_fwire_19, A1, B3, C2);
+ and (int_fwire_20, A1, B3, C1);
+ and (int_fwire_21, A1, B2, C3);
+ and (int_fwire_22, A1, B2, C2);
+ and (int_fwire_23, A1, B2, C1);
+ and (int_fwire_24, A1, B1, C3);
+ and (int_fwire_25, A1, B1, C2);
+ and (int_fwire_26, A1, B1, C1);
+ or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA33x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ and (int_fwire_0, A3, B3);
+ and (int_fwire_1, A3, B2);
+ and (int_fwire_2, A3, B1);
+ and (int_fwire_3, A2, B3);
+ and (int_fwire_4, A2, B2);
+ and (int_fwire_5, A2, B1);
+ and (int_fwire_6, A1, B3);
+ and (int_fwire_7, A1, B2);
+ and (int_fwire_8, A1, B1);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI211xp5_ASAP7_75t_L (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & A2 & B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI21x1_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI21xp33_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI21xp5_ASAP7_75t_L (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI221xp5_ASAP7_75t_L (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0, C__bar);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI222xp33_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C1__bar, C2__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI22x1_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI22xp33_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI22xp5_ASAP7_75t_L (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI311xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, C1);
+ output Y;
+ input A1, A2, A3, B1, C1;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, C1__bar, int_fwire_0;
+
+ not (C1__bar, C1);
+ not (B1__bar, B1);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_0, B1__bar, C1__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI31xp33_ASAP7_75t_L (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI31xp67_ASAP7_75t_L (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI321xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C);
+ output Y;
+ input A1, A2, A3, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0, C__bar);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & C))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI322xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C1__bar;
+ wire C2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2;
+
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI32xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI331xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, int_fwire_0, int_fwire_1;
+
+ not (C1__bar, C1);
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0, C1__bar);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI332xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2;
+
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar);
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI333xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, C3__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ not (C3__bar, C3);
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar, C3__bar);
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI33xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v
new file mode 100644
index 0000000000..c737d3b31c
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v
@@ -0,0 +1,5243 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_SLVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module O2A1O1Ixp33_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, C__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module O2A1O1Ixp5_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, C__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, C__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~C))
+ (B => Y) = 0;
+ if ((A2 & ~B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & ~B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA211x2_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, A2, B, C);
+ and (int_fwire_1, A1, B, C);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & A2 & B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA21x2_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire int_fwire_0, int_fwire_1;
+
+ and (int_fwire_0, A2, B);
+ and (int_fwire_1, A1, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA221x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3;
+
+ and (int_fwire_0, A2, B2, C);
+ and (int_fwire_1, A2, B1, C);
+ and (int_fwire_2, A1, B2, C);
+ and (int_fwire_3, A1, B1, C);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA222x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7;
+
+ and (int_fwire_0, A2, B2, C2);
+ and (int_fwire_1, A2, B2, C1);
+ and (int_fwire_2, A2, B1, C2);
+ and (int_fwire_3, A2, B1, C1);
+ and (int_fwire_4, A1, B2, C2);
+ and (int_fwire_5, A1, B2, C1);
+ and (int_fwire_6, A1, B1, C2);
+ and (int_fwire_7, A1, B1, C1);
+ or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA22x2_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3;
+
+ and (int_fwire_0, A2, B2);
+ and (int_fwire_1, A2, B1);
+ and (int_fwire_2, A1, B2);
+ and (int_fwire_3, A1, B1);
+ or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA31x2_ASAP7_75t_SL (Y, A1, A2, A3, B1);
+ output Y;
+ input A1, A2, A3, B1;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, A3, B1);
+ and (int_fwire_1, A2, B1);
+ and (int_fwire_2, A1, B1);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3) | (~A1 & A2 & A3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3))
+ (B1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA331x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ and (int_fwire_0, A3, B3, C1);
+ and (int_fwire_1, A3, B2, C1);
+ and (int_fwire_2, A3, B1, C1);
+ and (int_fwire_3, A2, B3, C1);
+ and (int_fwire_4, A2, B2, C1);
+ and (int_fwire_5, A2, B1, C1);
+ and (int_fwire_6, A1, B3, C1);
+ and (int_fwire_7, A1, B2, C1);
+ and (int_fwire_8, A1, B1, C1);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA331x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ and (int_fwire_0, A3, B3, C1);
+ and (int_fwire_1, A3, B2, C1);
+ and (int_fwire_2, A3, B1, C1);
+ and (int_fwire_3, A2, B3, C1);
+ and (int_fwire_4, A2, B2, C1);
+ and (int_fwire_5, A2, B1, C1);
+ and (int_fwire_6, A1, B3, C1);
+ and (int_fwire_7, A1, B2, C1);
+ and (int_fwire_8, A1, B1, C1);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA332x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+
+ and (int_fwire_0, A3, B3, C2);
+ and (int_fwire_1, A3, B3, C1);
+ and (int_fwire_2, A3, B2, C2);
+ and (int_fwire_3, A3, B2, C1);
+ and (int_fwire_4, A3, B1, C2);
+ and (int_fwire_5, A3, B1, C1);
+ and (int_fwire_6, A2, B3, C2);
+ and (int_fwire_7, A2, B3, C1);
+ and (int_fwire_8, A2, B2, C2);
+ and (int_fwire_9, A2, B2, C1);
+ and (int_fwire_10, A2, B1, C2);
+ and (int_fwire_11, A2, B1, C1);
+ and (int_fwire_12, A1, B3, C2);
+ and (int_fwire_13, A1, B3, C1);
+ and (int_fwire_14, A1, B2, C2);
+ and (int_fwire_15, A1, B2, C1);
+ and (int_fwire_16, A1, B1, C2);
+ and (int_fwire_17, A1, B1, C1);
+ or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA332x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+
+ and (int_fwire_0, A3, B3, C2);
+ and (int_fwire_1, A3, B3, C1);
+ and (int_fwire_2, A3, B2, C2);
+ and (int_fwire_3, A3, B2, C1);
+ and (int_fwire_4, A3, B1, C2);
+ and (int_fwire_5, A3, B1, C1);
+ and (int_fwire_6, A2, B3, C2);
+ and (int_fwire_7, A2, B3, C1);
+ and (int_fwire_8, A2, B2, C2);
+ and (int_fwire_9, A2, B2, C1);
+ and (int_fwire_10, A2, B1, C2);
+ and (int_fwire_11, A2, B1, C1);
+ and (int_fwire_12, A1, B3, C2);
+ and (int_fwire_13, A1, B3, C1);
+ and (int_fwire_14, A1, B2, C2);
+ and (int_fwire_15, A1, B2, C1);
+ and (int_fwire_16, A1, B1, C2);
+ and (int_fwire_17, A1, B1, C1);
+ or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA333x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+ wire int_fwire_18, int_fwire_19, int_fwire_20;
+ wire int_fwire_21, int_fwire_22, int_fwire_23;
+ wire int_fwire_24, int_fwire_25, int_fwire_26;
+
+ and (int_fwire_0, A3, B3, C3);
+ and (int_fwire_1, A3, B3, C2);
+ and (int_fwire_2, A3, B3, C1);
+ and (int_fwire_3, A3, B2, C3);
+ and (int_fwire_4, A3, B2, C2);
+ and (int_fwire_5, A3, B2, C1);
+ and (int_fwire_6, A3, B1, C3);
+ and (int_fwire_7, A3, B1, C2);
+ and (int_fwire_8, A3, B1, C1);
+ and (int_fwire_9, A2, B3, C3);
+ and (int_fwire_10, A2, B3, C2);
+ and (int_fwire_11, A2, B3, C1);
+ and (int_fwire_12, A2, B2, C3);
+ and (int_fwire_13, A2, B2, C2);
+ and (int_fwire_14, A2, B2, C1);
+ and (int_fwire_15, A2, B1, C3);
+ and (int_fwire_16, A2, B1, C2);
+ and (int_fwire_17, A2, B1, C1);
+ and (int_fwire_18, A1, B3, C3);
+ and (int_fwire_19, A1, B3, C2);
+ and (int_fwire_20, A1, B3, C1);
+ and (int_fwire_21, A1, B2, C3);
+ and (int_fwire_22, A1, B2, C2);
+ and (int_fwire_23, A1, B2, C1);
+ and (int_fwire_24, A1, B1, C3);
+ and (int_fwire_25, A1, B1, C2);
+ and (int_fwire_26, A1, B1, C1);
+ or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA333x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+ wire int_fwire_9, int_fwire_10, int_fwire_11;
+ wire int_fwire_12, int_fwire_13, int_fwire_14;
+ wire int_fwire_15, int_fwire_16, int_fwire_17;
+ wire int_fwire_18, int_fwire_19, int_fwire_20;
+ wire int_fwire_21, int_fwire_22, int_fwire_23;
+ wire int_fwire_24, int_fwire_25, int_fwire_26;
+
+ and (int_fwire_0, A3, B3, C3);
+ and (int_fwire_1, A3, B3, C2);
+ and (int_fwire_2, A3, B3, C1);
+ and (int_fwire_3, A3, B2, C3);
+ and (int_fwire_4, A3, B2, C2);
+ and (int_fwire_5, A3, B2, C1);
+ and (int_fwire_6, A3, B1, C3);
+ and (int_fwire_7, A3, B1, C2);
+ and (int_fwire_8, A3, B1, C1);
+ and (int_fwire_9, A2, B3, C3);
+ and (int_fwire_10, A2, B3, C2);
+ and (int_fwire_11, A2, B3, C1);
+ and (int_fwire_12, A2, B2, C3);
+ and (int_fwire_13, A2, B2, C2);
+ and (int_fwire_14, A2, B2, C1);
+ and (int_fwire_15, A2, B1, C3);
+ and (int_fwire_16, A2, B1, C2);
+ and (int_fwire_17, A2, B1, C1);
+ and (int_fwire_18, A1, B3, C3);
+ and (int_fwire_19, A1, B3, C2);
+ and (int_fwire_20, A1, B3, C1);
+ and (int_fwire_21, A1, B2, C3);
+ and (int_fwire_22, A1, B2, C2);
+ and (int_fwire_23, A1, B2, C1);
+ and (int_fwire_24, A1, B1, C3);
+ and (int_fwire_25, A1, B1, C2);
+ and (int_fwire_26, A1, B1, C1);
+ or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OA33x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6, int_fwire_7, int_fwire_8;
+
+ and (int_fwire_0, A3, B3);
+ and (int_fwire_1, A3, B2);
+ and (int_fwire_2, A3, B1);
+ and (int_fwire_3, A2, B3);
+ and (int_fwire_4, A2, B2);
+ and (int_fwire_5, A2, B1);
+ and (int_fwire_6, A1, B3);
+ and (int_fwire_7, A1, B2);
+ and (int_fwire_8, A1, B1);
+ or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI211xp5_ASAP7_75t_SL (Y, A1, A2, B, C);
+ output Y;
+ input A1, A2, B, C;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire C__bar, int_fwire_0;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & C))
+ (B => Y) = 0;
+ if ((~A1 & A2 & C))
+ (B => Y) = 0;
+ if ((A1 & A2 & B))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI21x1_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI21xp33_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI21xp5_ASAP7_75t_SL (Y, A1, A2, B);
+ output Y;
+ input A1, A2, B;
+
+ // Function
+ wire A1__bar, A2__bar, B__bar;
+ wire int_fwire_0;
+
+ not (B__bar, B);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ if ((A1 & A2))
+ (B => Y) = 0;
+ if ((A1 & ~A2))
+ (B => Y) = 0;
+ if ((~A1 & A2))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI221xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2, C);
+ output Y;
+ input A1, A2, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0, C__bar);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI222xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, C1__bar, C2__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI22xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI22xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2);
+ output Y;
+ input A1, A2, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, B1__bar;
+ wire B2__bar, int_fwire_0, int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI311xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, C1);
+ output Y;
+ input A1, A2, A3, B1, C1;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, C1__bar, int_fwire_0;
+
+ not (C1__bar, C1);
+ not (B1__bar, B1);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_0, B1__bar, C1__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI31xp33_ASAP7_75t_SL (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI31xp67_ASAP7_75t_SL (Y, A1, A2, A3, B);
+ output Y;
+ input A1, A2, A3, B;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B__bar, int_fwire_0;
+
+ not (B__bar, B);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_0, B__bar);
+
+ // Timing
+ specify
+ (A1 => Y) = 0;
+ (A2 => Y) = 0;
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3))
+ (B => Y) = 0;
+ if ((A1 & ~A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & A3))
+ (B => Y) = 0;
+ if ((~A1 & A2 & ~A3))
+ (B => Y) = 0;
+ if ((~A1 & ~A2 & A3))
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI321xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C);
+ output Y;
+ input A1, A2, A3, B1, B2, C;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (C__bar, C);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0, C__bar);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & C))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & C))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & C))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & C))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & C))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & C))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2))
+ (C => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2))
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI322xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, C1__bar;
+ wire C2__bar, int_fwire_0, int_fwire_1;
+ wire int_fwire_2;
+
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI32xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2);
+ output Y;
+ input A1, A2, A3, B1, B2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1))
+ (B2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI331xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, int_fwire_0, int_fwire_1;
+
+ not (C1__bar, C1);
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0, C1__bar);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3))
+ (C1 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI332xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, int_fwire_0;
+ wire int_fwire_1, int_fwire_2;
+
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar);
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1))
+ (C2 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI333xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3, C1, C2, C3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire C1__bar, C2__bar, C3__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ not (C3__bar, C3);
+ not (C2__bar, C2);
+ not (C1__bar, C1);
+ and (int_fwire_0, C1__bar, C2__bar, C3__bar);
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_1, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_2, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3))
+ (C1 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3))
+ (C2 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2))
+ (C3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OAI33xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3);
+ output Y;
+ input A1, A2, A3, B1, B2, B3;
+
+ // Function
+ wire A1__bar, A2__bar, A3__bar;
+ wire B1__bar, B2__bar, B3__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B3__bar, B3);
+ not (B2__bar, B2);
+ not (B1__bar, B1);
+ and (int_fwire_0, B1__bar, B2__bar, B3__bar);
+ not (A3__bar, A3);
+ not (A2__bar, A2);
+ not (A1__bar, A1);
+ and (int_fwire_1, A1__bar, A2__bar, A3__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if ((~A2 & ~A3 & B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & B1 & ~B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & B2 & ~B3))
+ (A1 => Y) = 0;
+ if ((~A2 & ~A3 & ~B1 & ~B2 & B3))
+ (A1 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & B1 & ~B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & B2 & ~B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A3 & ~B1 & ~B2 & B3))
+ (A2 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & B1 & ~B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & B2 & ~B3))
+ (A3 => Y) = 0;
+ if ((~A1 & ~A2 & ~B1 & ~B2 & B3))
+ (A3 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B2 & ~B3))
+ (B1 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B3))
+ (B2 => Y) = 0;
+ if ((A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((A1 & ~A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & A2 & ~A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ if ((~A1 & ~A2 & A3 & ~B1 & ~B2))
+ (B3 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v
new file mode 100644
index 0000000000..a04bc82c17
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v
@@ -0,0 +1,1173 @@
+// BSD 3-Clause License
+//
+// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_LVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFASRHQNx1_ASAP7_75t_L (QN, D, RESETN, SETN, CLK);
+ output QN;
+ input D, RESETN, SETN, CLK;
+ reg notifier;
+ wire delayed_D, delayed_LESETN, delayed_SETN, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, int_fwire_r;
+ wire int_fwire_s, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_s, delayed_LESETN);
+ not (int_fwire_r, delayed_SETN);
+ //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r);
+ // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, adacond8;
+ wire CLK__bar, D__bar;
+
+
+ // Additional timing gates
+ and (adacond0, RESETN, SETN);
+ and (adacond1, D, SETN);
+ and (adacond2, CLK, SETN);
+ not (CLK__bar, CLK);
+ and (adacond3, CLK__bar, SETN);
+ not (D__bar, D);
+ and (adacond4, D__bar, RESETN);
+ and (adacond5, CLK, RESETN);
+ and (adacond6, CLK__bar, RESETN);
+ and (adacond7, D, RESETN, SETN);
+ and (adacond8, D__bar, RESETN, SETN);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQNx1_ASAP7_75t_L (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQNx2_ASAP7_75t_L (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQNx3_ASAP7_75t_L (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQx4_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ, xcr_0;
+
+ //altos_dff_err (xcr_0, delayed_CLK, delayed_D);
+ //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQNx1_ASAP7_75t_L (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQNx2_ASAP7_75t_L (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQNx3_ASAP7_75t_L (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQx4_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, xcr_0;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, delayed_D);
+ //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DHLx1_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ;
+
+ //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DHLx2_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ;
+
+ //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DHLx3_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ;
+
+ //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DLLx1_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DLLx2_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DLLx3_ASAP7_75t_L (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx1_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx2_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx2p67DC_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx3_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx4DC_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx4_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx5_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx5p33DC_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx6p67DC_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx8DC_ASAP7_75t_L (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx1_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx2_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx3_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx4_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx1_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx2_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx3_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx4_ASAP7_75t_L (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v
new file mode 100644
index 0000000000..86b817a386
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v
@@ -0,0 +1,1173 @@
+// BSD 3-Clause License
+//
+// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_SLVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFASRHQNx1_ASAP7_75t_SL (QN, D, RESETN, SETN, CLK);
+ output QN;
+ input D, RESETN, SETN, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SLESETN, delayed_SETN, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, int_fwire_r;
+ wire int_fwire_s, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_s, delayed_SLESETN);
+ not (int_fwire_r, delayed_SETN);
+ //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r);
+ // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, adacond8;
+ wire CLK__bar, D__bar;
+
+
+ // Additional timing gates
+ and (adacond0, RESETN, SETN);
+ and (adacond1, D, SETN);
+ and (adacond2, CLK, SETN);
+ not (CLK__bar, CLK);
+ and (adacond3, CLK__bar, SETN);
+ not (D__bar, D);
+ and (adacond4, D__bar, RESETN);
+ and (adacond5, CLK, RESETN);
+ and (adacond6, CLK__bar, RESETN);
+ and (adacond7, D, RESETN, SETN);
+ and (adacond8, D__bar, RESETN, SETN);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQNx1_ASAP7_75t_SL (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQNx2_ASAP7_75t_SL (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQNx3_ASAP7_75t_SL (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFHQx4_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ, xcr_0;
+
+ //altos_dff_err (xcr_0, delayed_CLK, delayed_D);
+ //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQNx1_ASAP7_75t_SL (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQNx2_ASAP7_75t_SL (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQNx3_ASAP7_75t_SL (QN, D, CLK);
+ output QN;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_d, delayed_D);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DFFLQx4_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, xcr_0;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, delayed_D);
+ //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DHLx1_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ;
+
+ //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DHLx2_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ;
+
+ //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DHLx3_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_IQ;
+
+ //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DLLx1_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DLLx2_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module DLLx3_ASAP7_75t_SL (Q, D, CLK);
+ output Q;
+ input D, CLK;
+ reg notifier;
+ wire delayed_D, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ;
+
+ not (int_fwire_clk, delayed_CLK);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D);
+ buf (Q, int_fwire_IQ);
+
+ // Timing
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx1_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx2_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx2p67DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx3_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx4DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx4_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx5_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx5p33DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx6p67DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module ICGx8DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK);
+ output GCLK;
+ input ENA, SE, CLK;
+ reg notifier;
+ wire delayed_ENA, delayed_SE, delayed_CLK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_test;
+
+ not (int_fwire_clk, delayed_CLK);
+ or (int_fwire_test, delayed_ENA, delayed_SE);
+ //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test);
+ and (GCLK, delayed_CLK, int_fwire_IQ);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, ENA__bar;
+ wire int_twire_0, SE__bar;
+
+
+ // Additional timing gates
+ not (ENA__bar, ENA);
+ and (int_twire_0, ENA__bar, SE);
+ or (adacond0, ENA, int_twire_0);
+ not (SE__bar, SE);
+ and (adacond1, ENA__bar, SE__bar);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx1_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx2_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx3_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFHx4_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_d, int_fwire_IQN, xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx1_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx2_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx3_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module SDFLx4_ASAP7_75t_SL (QN, D, SE, SI, CLK);
+ output QN;
+ input D, SE, SI, CLK;
+ reg notifier;
+ wire delayed_D, delayed_SE, delayed_SI, delayed_CLK;
+
+ // Function
+ wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_clk, int_fwire_d, int_fwire_IQN;
+ wire xcr_0;
+
+ not (delayed_SI__bar, delayed_SI);
+ and (int_fwire_0, delayed_SE, delayed_SI__bar);
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_1, delayed_D__bar, delayed_SI__bar);
+ not (delayed_SE__bar, delayed_SE);
+ and (int_fwire_2, delayed_D__bar, delayed_SE__bar);
+ or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (int_fwire_clk, delayed_CLK);
+ //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d);
+ //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, adacond2;
+ wire adacond3, adacond4, adacond5;
+ wire adacond6, adacond7, D__bar;
+ wire int_twire_0, int_twire_1, int_twire_2;
+ wire int_twire_3, int_twire_4, int_twire_5;
+ wire SE__bar, SI__bar;
+
+
+ // Additional timing gates
+ not (SE__bar, SE);
+ and (adacond0, SE__bar, SI);
+ not (SI__bar, SI);
+ and (adacond1, SE__bar, SI__bar);
+ and (adacond2, D, SI__bar);
+ not (D__bar, D);
+ and (adacond3, D__bar, SI);
+ and (adacond4, D, SE);
+ and (adacond5, D__bar, SE);
+ and (int_twire_0, D__bar, SE, SI);
+ and (int_twire_1, D, SE__bar);
+ and (int_twire_2, D, SE, SI);
+ or (adacond6, int_twire_2, int_twire_1, int_twire_0);
+ and (int_twire_3, D__bar, SE__bar);
+ and (int_twire_4, D__bar, SE, SI__bar);
+ and (int_twire_5, D, SE, SI__bar);
+ or (adacond7, int_twire_5, int_twire_4, int_twire_3);
+
+endmodule
+`endcelldefine
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v
new file mode 100644
index 0000000000..ce741d6cfa
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v
@@ -0,0 +1,1303 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND2x2_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND2x4_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND2x6_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND3x1_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ and (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND3x2_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ and (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND3x4_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ and (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND4x1_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ and (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND4x2_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ and (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND5x1_ASAP7_75t_L (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ and (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND5x2_ASAP7_75t_L (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ and (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module FAx1_ASAP7_75t_L (CON, SN, A, B, CI);
+ output CON, SN;
+ input A, B, CI;
+
+ // Function
+ wire A__bar, B__bar, CI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6;
+
+ not (CI__bar, CI);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, CI__bar);
+ not (A__bar, A);
+ and (int_fwire_1, A__bar, CI__bar);
+ and (int_fwire_2, A__bar, B__bar);
+ or (CON, int_fwire_2, int_fwire_1, int_fwire_0);
+ and (int_fwire_3, A__bar, B__bar, CI__bar);
+ and (int_fwire_4, A__bar, B, CI);
+ and (int_fwire_5, A, B__bar, CI);
+ and (int_fwire_6, A, B, CI__bar);
+ or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HAxp5_ASAP7_75t_L (CON, SN, A, B);
+ output CON, SN;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (CON, A__bar, B__bar);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (SN, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A => CON) = 0;
+ (B => CON) = 0;
+ if (B)
+ (A => SN) = 0;
+ if (~B)
+ (A => SN) = 0;
+ if (A)
+ (B => SN) = 0;
+ if (~A)
+ (B => SN) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module MAJIxp5_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, C__bar);
+ not (A__bar, A);
+ and (int_fwire_1, A__bar, C__bar);
+ and (int_fwire_2, A__bar, B__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module MAJx2_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, B, C);
+ and (int_fwire_1, A, C);
+ and (int_fwire_2, A, B);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module MAJx3_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, B, C);
+ and (int_fwire_1, A, C);
+ and (int_fwire_2, A, B);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2x1_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2x1p5_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2x2_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2xp33_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2xp5_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2xp67_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND3x1_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND3x2_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND3xp33_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND4xp25_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND4xp75_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND5xp2_ASAP7_75t_L (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar, E__bar;
+
+ not (E__bar, E);
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar, D__bar, E__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2x1_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2x1p5_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2x2_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2xp33_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2xp67_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR3x1_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR3x2_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR3xp33_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR4xp25_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR4xp75_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR5xp2_ASAP7_75t_L (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar, E__bar;
+
+ not (E__bar, E);
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar, D__bar, E__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR2x2_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR2x4_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR2x6_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR3x1_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ or (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR3x2_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ or (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR3x4_ASAP7_75t_L (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ or (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR4x1_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ or (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR4x2_ASAP7_75t_L (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ or (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR5x1_ASAP7_75t_L (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ or (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR5x2_ASAP7_75t_L (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ or (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module TIEHIx1_ASAP7_75t_L (H);
+ output H;
+
+ // Function
+ buf (H, 1'b1);
+
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module TIELOx1_ASAP7_75t_L (L);
+ output L;
+
+ // Function
+ buf (L, 1'b0);
+
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XNOR2x1_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XNOR2x2_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XNOR2xp5_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XOR2x1_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (~B)
+ (A => Y) = 0;
+ if (B)
+ (A => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XOR2x2_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (~B)
+ (A => Y) = 0;
+ if (B)
+ (A => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XOR2xp5_ASAP7_75t_L (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (~B)
+ (A => Y) = 0;
+ if (B)
+ (A => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v
new file mode 100644
index 0000000000..abdd8249e8
--- /dev/null
+++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v
@@ -0,0 +1,1303 @@
+// BSD 3-Clause License
+//
+// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State
+// University
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND2x2_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND2x4_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND2x6_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND3x1_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ and (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND3x2_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ and (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND3x4_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ and (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND4x1_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ and (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND4x2_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ and (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND5x1_ASAP7_75t_SL (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ and (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module AND5x2_ASAP7_75t_SL (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ and (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module FAx1_ASAP7_75t_SL (CON, SN, A, B, CI);
+ output CON, SN;
+ input A, B, CI;
+
+ // Function
+ wire A__bar, B__bar, CI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6;
+
+ not (CI__bar, CI);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, CI__bar);
+ not (A__bar, A);
+ and (int_fwire_1, A__bar, CI__bar);
+ and (int_fwire_2, A__bar, B__bar);
+ or (CON, int_fwire_2, int_fwire_1, int_fwire_0);
+ and (int_fwire_3, A__bar, B__bar, CI__bar);
+ and (int_fwire_4, A__bar, B, CI);
+ and (int_fwire_5, A, B__bar, CI);
+ and (int_fwire_6, A, B, CI__bar);
+ or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module HAxp5_ASAP7_75t_SL (CON, SN, A, B);
+ output CON, SN;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (CON, A__bar, B__bar);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (SN, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A => CON) = 0;
+ (B => CON) = 0;
+ if (B)
+ (A => SN) = 0;
+ if (~B)
+ (A => SN) = 0;
+ if (A)
+ (B => SN) = 0;
+ if (~A)
+ (B => SN) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module MAJIxp5_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ and (int_fwire_0, B__bar, C__bar);
+ not (A__bar, A);
+ and (int_fwire_1, A__bar, C__bar);
+ and (int_fwire_2, A__bar, B__bar);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module MAJx2_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, B, C);
+ and (int_fwire_1, A, C);
+ and (int_fwire_2, A, B);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module MAJx3_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+
+ and (int_fwire_0, B, C);
+ and (int_fwire_1, A, C);
+ and (int_fwire_2, A, B);
+ or (Y, int_fwire_2, int_fwire_1, int_fwire_0);
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2x1_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2x1p5_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2x2_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2xp33_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2xp5_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND2xp67_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND3x1_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND3x2_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND3xp33_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND4xp25_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND4xp75_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NAND5xp2_ASAP7_75t_SL (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar, E__bar;
+
+ not (E__bar, E);
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar, D__bar, E__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2x1_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2x1p5_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2x2_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2xp33_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR2xp67_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR3x1_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR3x2_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR3xp33_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR4xp25_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR4xp75_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar;
+
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar, D__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module NOR5xp2_ASAP7_75t_SL (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+ wire D__bar, E__bar;
+
+ not (E__bar, E);
+ not (D__bar, D);
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar, C__bar, D__bar, E__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR2x2_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR2x4_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR2x6_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR3x1_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ or (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR3x2_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ or (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR3x4_ASAP7_75t_SL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ or (Y, A, B, C);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR4x1_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ or (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR4x2_ASAP7_75t_SL (Y, A, B, C, D);
+ output Y;
+ input A, B, C, D;
+
+ // Function
+ or (Y, A, B, C, D);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR5x1_ASAP7_75t_SL (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ or (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module OR5x2_ASAP7_75t_SL (Y, A, B, C, D, E);
+ output Y;
+ input A, B, C, D, E;
+
+ // Function
+ or (Y, A, B, C, D, E);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ (D => Y) = 0;
+ (E => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module TIEHIx1_ASAP7_75t_SL (H);
+ output H;
+
+ // Function
+ buf (H, 1'b1);
+
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module TIELOx1_ASAP7_75t_SL (L);
+ output L;
+
+ // Function
+ buf (L, 1'b0);
+
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XNOR2x1_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XNOR2x2_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XNOR2xp5_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XOR2x1_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (~B)
+ (A => Y) = 0;
+ if (B)
+ (A => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XOR2x2_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (~B)
+ (A => Y) = 0;
+ if (B)
+ (A => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+// type:
+`timescale 1ns/10ps
+`celldefine
+module XOR2xp5_ASAP7_75t_SL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (~B)
+ (A => Y) = 0;
+ if (B)
+ (A => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
diff --git a/flow/platforms/gf180/fastroute.tcl b/flow/platforms/gf180/fastroute.tcl
index d91e3b4dcc..42e6b5996b 100644
--- a/flow/platforms/gf180/fastroute.tcl
+++ b/flow/platforms/gf180/fastroute.tcl
@@ -1,3 +1,2 @@
set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.25
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/platforms/gf180/openROAD/tapcell.tcl b/flow/platforms/gf180/openROAD/tapcell.tcl
index fecbde985a..24ebce5587 100644
--- a/flow/platforms/gf180/openROAD/tapcell.tcl
+++ b/flow/platforms/gf180/openROAD/tapcell.tcl
@@ -1,5 +1,5 @@
- tapcell \
- -endcap_cpp "12" \
- -distance 100 \
- -tapcell_master $::env(TIE_CELL) \
- -endcap_master $::env(ENDCAP_CELL)
+tapcell \
+ -endcap_cpp "12" \
+ -distance 100 \
+ -tapcell_master $::env(TIE_CELL) \
+ -endcap_master $::env(ENDCAP_CELL)
diff --git a/flow/platforms/gf180/setRC.tcl b/flow/platforms/gf180/setRC.tcl
index 7c6828b1de..33ae86856a 100644
--- a/flow/platforms/gf180/setRC.tcl
+++ b/flow/platforms/gf180/setRC.tcl
@@ -17,14 +17,12 @@ set_layer_rc -layer Metal5 -resistance 7.92778E-05 -capacitance 1.55595E-04
regexp {(\d+)} $::env(METAL_OPTION) metal
if { $metal == "6" } {
-
set_wire_rc -signal -layer Metal2
- set_wire_rc -clock -layer Metal5
-
-} elseif { $metal == "5" } {
+ set_wire_rc -clock -layer Metal5
+} elseif { $metal == "5" } {
# TC matches LEF. These are the temperature adjusted values.
# The other stacks are likely similar but I haven't checked yet.
- if {$::env(CORNER) == "WC"} {
+ if { $::env(CORNER) == "WC" } {
set_layer_rc -via Via1 -resistance 16.845
set_layer_rc -via Via2 -resistance 16.845
set_layer_rc -via Via3 -resistance 16.845
@@ -32,11 +30,11 @@ if { $metal == "6" } {
set tech [ord::get_db_tech]
foreach via [$tech getVias] {
- if {[$via getResistance] == 4.5} {
+ if { [$via getResistance] == 4.5 } {
$via setResistance 16.845
}
}
- } elseif {$::env(CORNER) == "BC"} {
+ } elseif { $::env(CORNER) == "BC" } {
set_layer_rc -via Via1 -resistance 4.23
set_layer_rc -via Via2 -resistance 4.23
set_layer_rc -via Via3 -resistance 4.23
@@ -44,27 +42,21 @@ if { $metal == "6" } {
set tech [ord::get_db_tech]
foreach via [$tech getVias] {
- if {[$via getResistance] == 4.5} {
+ if { [$via getResistance] == 4.5 } {
$via setResistance 4.23
}
}
}
-
- set_wire_rc -signal -layer Metal2
- set_wire_rc -clock -layer Metal4
-
-} elseif { $metal == "4" } {
set_wire_rc -signal -layer Metal2
- set_wire_rc -clock -layer Metal3
-
-} elseif { $metal == "3" } {
-
+ set_wire_rc -clock -layer Metal4
+} elseif { $metal == "4" } {
set_wire_rc -signal -layer Metal2
- set_wire_rc -clock -layer Metal2
-
-} elseif { $metal == "2" } {
-
+ set_wire_rc -clock -layer Metal3
+} elseif { $metal == "3" } {
+ set_wire_rc -signal -layer Metal2
+ set_wire_rc -clock -layer Metal2
+} elseif { $metal == "2" } {
set_wire_rc -signal -layer Metal2
- set_wire_rc -clock -layer Metal2
+ set_wire_rc -clock -layer Metal2
}
diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk
index 4f2440675c..caea89b76c 100644
--- a/flow/platforms/ihp-sg13g2/config.mk
+++ b/flow/platforms/ihp-sg13g2/config.mk
@@ -6,17 +6,17 @@ export PROCESS = ihp-sg13g2
# ----------------------------------------------------
# Add IO related files when a TCL script is assigned to 'FOOTPRINT_TCL'.
# This variable is used to pass IO information.
-export LOAD_ADDITIONAL_FILES ?= yes
-ifdef FOOTPRINT_TCL
-ifdef LOAD_ADDITIONAL_FILES
- export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \
- $(PLATFORM_DIR)/lef/bondpad_70x70.lef
- export ADDITIONAL_SLOW_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
- export ADDITIONAL_FAST_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib
- export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
- export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \
- $(PLATFORM_DIR)/gds/bondpad_70x70.gds
-endif
+export LOAD_ADDITIONAL_FILES ?= 1
+ifneq ($(FOOTPRINT_TCL),)
+ ifeq ($(LOAD_ADDITIONAL_FILES),1)
+ export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \
+ $(PLATFORM_DIR)/lef/bondpad_70x70.lef
+ export ADDITIONAL_SLOW_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
+ export ADDITIONAL_FAST_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib
+ export ADDITIONAL_TYP_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
+ export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \
+ $(PLATFORM_DIR)/gds/bondpad_70x70.gds
+ endif
endif
export TECH_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_tech.lef
export SC_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_stdcell.lef
@@ -25,8 +25,9 @@ export SLOW_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_slow_1p08V_125C.lib
$(ADDITIONAL_SLOW_LIBS)
export FAST_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_fast_1p32V_m40C.lib \
$(ADDITIONAL_FAST_LIBS)
-export LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \
- $(ADDITIONAL_LIBS)
+export TYP_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \
+ $(ADDITIONAL_TYP_LIBS)
+export LIB_FILES ?= $(TYP_LIB_FILES)
export GDS_FILES ?= $(PLATFORM_DIR)/gds/sg13g2_stdcell.gds \
$(ADDITIONAL_GDS)
@@ -63,8 +64,12 @@ export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v
# Define ABC driver and load
export ABC_DRIVER_CELL = sg13g2_buf_4
export ABC_LOAD_IN_FF = 6.0
-# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file
-export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}')
+ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined)
+ ifneq ($(wildcard $(SDC_FILE)),)
+ # Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file
+ export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}')
+ endif
+endif
# -----------------------------------------------------
# Sizing
diff --git a/flow/platforms/ihp-sg13g2/fastroute.tcl b/flow/platforms/ihp-sg13g2/fastroute.tcl
index 079fa662e8..e386fefda4 100644
--- a/flow/platforms/ihp-sg13g2/fastroute.tcl
+++ b/flow/platforms/ihp-sg13g2/fastroute.tcl
@@ -1,4 +1,3 @@
set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.05
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/platforms/ihp-sg13g2/make_tracks.tcl b/flow/platforms/ihp-sg13g2/make_tracks.tcl
index 4b6c63fd52..b3380eb7ef 100644
--- a/flow/platforms/ihp-sg13g2/make_tracks.tcl
+++ b/flow/platforms/ihp-sg13g2/make_tracks.tcl
@@ -1,7 +1,7 @@
-make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48
-make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42
-make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48
-make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42
-make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48
+make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48
+make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42
+make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48
+make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42
+make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48
make_tracks TopMetal1 -x_offset 1.46 -x_pitch 2.28 -y_offset 1.46 -y_pitch 2.28
-make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0
+make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0
diff --git a/flow/platforms/ihp-sg13g2/pdn.tcl b/flow/platforms/ihp-sg13g2/pdn.tcl
index 99d911feae..27c506046a 100644
--- a/flow/platforms/ihp-sg13g2/pdn.tcl
+++ b/flow/platforms/ihp-sg13g2/pdn.tcl
@@ -20,9 +20,9 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
####################################
define_pdn_grid -name {grid} -voltage_domains {CORE}
add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads
-add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring
-add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring
-add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring
add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
# I/O pads
diff --git a/flow/platforms/ihp-sg13g2/setRC.tcl b/flow/platforms/ihp-sg13g2/setRC.tcl
index 65ea6cc833..35bfff7693 100644
--- a/flow/platforms/ihp-sg13g2/setRC.tcl
+++ b/flow/platforms/ihp-sg13g2/setRC.tcl
@@ -8,9 +8,9 @@ set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05
set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04
set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04
-set_layer_rc -via Via1 -resistance 2.0E-3
-set_layer_rc -via Via2 -resistance 2.0E-3
-set_layer_rc -via Via3 -resistance 2.0E-3
-set_layer_rc -via Via4 -resistance 2.0E-3
+set_layer_rc -via Via1 -resistance 2.0E-3
+set_layer_rc -via Via2 -resistance 2.0E-3
+set_layer_rc -via Via3 -resistance 2.0E-3
+set_layer_rc -via Via4 -resistance 2.0E-3
set_layer_rc -via TopVia1 -resistance 0.4E-3
set_layer_rc -via TopVia2 -resistance 0.22E-3
diff --git a/flow/platforms/ihp-sg13g2/sg13g2.map b/flow/platforms/ihp-sg13g2/sg13g2.map
index 2614374122..fbb201c83d 100644
--- a/flow/platforms/ihp-sg13g2/sg13g2.map
+++ b/flow/platforms/ihp-sg13g2/sg13g2.map
@@ -29,13 +29,10 @@
#EDI Layer Name EDI Layer Type GDS Layer Number GDS Layer Type
#============== ============== ================ ==============
-Metal1 NET 8 0
-Metal1 SPNET 8 0
-Metal1 PIN 8 2
-Metal1 LEFPIN 8 2
-Metal1 FILL 8 22
-Metal1 LEFOBS 8 4
-Metal1 VIA 8 0
+Metal1 NET,SPNET,PIN,LEFPIN,VIA 8 0
+Metal1 PIN,LEFPIN 8 2
+Metal1 FILL 8 22
+Metal1 LEFOBS 8 4
#NAME Metal1/NET 20 0
#NAME Metal1/SPNET 20 0
@@ -46,13 +43,10 @@ Via1 PIN 19 0
Via1 LEFPIN 19 0
Via1 VIA 19 0
-Metal2 NET 10 0
-Metal2 SPNET 10 0
-Metal2 PIN 10 2
-Metal2 LEFPIN 10 2
-Metal2 FILL 10 22
-Metal2 VIA 10 0
-Metal2 LEFOBS 10 4
+Metal2 NET,SPNET,PIN,LEFPIN,VIA 10 0
+Metal2 PIN,LEFPIN 10 2
+Metal2 FILL 10 22
+Metal2 LEFOBS 10 4
#NAME Metal2/NET 21 0
#NAME Metal2/SPNET 21 0
@@ -64,13 +58,10 @@ Via2 LEFPIN 29 0
Via2 VIA 29 0
-Metal3 NET 30 0
-Metal3 SPNET 30 0
-Metal3 PIN 30 2
-Metal3 LEFPIN 30 2
-Metal3 FILL 30 22
-Metal3 VIA 30 0
-Metal3 LEFOBS 30 4
+Metal3 NET,SPNET,PIN,LEFPIN,VIA 30 0
+Metal3 PIN,LEFPIN 30 2
+Metal3 FILL 30 22
+Metal3 LEFOBS 30 4
#NAME Metal3/NET 22 0
#NAME Metal3/SPNET 22 0
@@ -82,13 +73,10 @@ Via3 LEFPIN 49 0
Via3 VIA 49 0
-Metal4 NET 50 0
-Metal4 SPNET 50 0
-Metal4 PIN 50 2
-Metal4 LEFPIN 50 2
-Metal4 FILL 50 22
-Metal4 VIA 50 0
-Metal4 LEFOBS 50 4
+Metal4 NET,SPNET,PIN,LEFPIN,VIA 50 0
+Metal4 PIN,LEFPIN 50 2
+Metal4 FILL 50 22
+Metal4 LEFOBS 50 4
#NAME Metal4/NET 23 0
#NAME Metal4/SPNET 23 0
@@ -100,13 +88,10 @@ Via4 LEFPIN 66 0
Via4 VIA 66 0
-Metal5 NET 67 0
-Metal5 SPNET 67 0
-Metal5 PIN 67 2
-Metal5 LEFPIN 67 2
-Metal5 FILL 67 22
-Metal5 VIA 67 0
-Metal5 LEFOBS 67 4
+Metal5 NET,SPNET,PIN,LEFPIN,VIA 67 0
+Metal5 PIN,LEFPIN 67 2
+Metal5 FILL 67 22
+Metal5 LEFOBS 67 4
#NAME Metal5/NET 70 0
#NAME Metal5/SPNET 70 0
@@ -117,13 +102,10 @@ TopVia1 PIN 125 0
TopVia1 LEFPIN 125 0
TopVia1 VIA 125 0
-TopMetal1 NET 126 0
-TopMetal1 SPNET 126 0
-TopMetal1 PIN 126 2
-TopMetal1 LEFPIN 126 2
-TopMetal1 FILL 126 22
-TopMetal1 VIA 126 0
-TopMetal1 LEFOBS 126 4
+TopMetal1 NET,SPNET,PIN,LEFPIN,VIA 126 0
+TopMetal1 PIN,LEFPIN 126 2
+TopMetal1 FILL 126 22
+TopMetal1 LEFOBS 126 4
#NAME TopMetal1/NET 130 0
#NAME TopMetal1/SPNET 130 0
@@ -134,13 +116,10 @@ TopVia2 PIN 133 0
TopVia2 LEFPIN 133 0
TopVia2 VIA 133 0
-TopMetal2 NET 134 0
-TopMetal2 SPNET 134 0
-TopMetal2 PIN 134 2
-TopMetal2 LEFPIN 134 2
-TopMetal2 FILL 134 22
-TopMetal2 VIA 134 0
-TopMetal2 LEFOBS 135 4
+TopMetal2 NET,SPNET,PIN,LEFPIN,VIA 134 0
+TopMetal2 PIN,LEFPIN 134 2
+TopMetal2 FILL 134 22
+TopMetal2 LEFOBS 134 4
#NAME TopMetal2/NET 137 0
#NAME TopMetal2/SPNET 137 0
@@ -149,6 +128,6 @@ NAME TopMetal2/PIN 134 25
NAME COMP 63 0
-COMP ALL 235 0
+COMP ALL 189 0
-DIEAREA ALL 235 4
+DIEAREA ALL 189 4
diff --git a/flow/platforms/nangate45/fakeram.tcl b/flow/platforms/nangate45/fakeram.tcl
index 4c8f9997e6..d4706cbe1a 100644
--- a/flow/platforms/nangate45/fakeram.tcl
+++ b/flow/platforms/nangate45/fakeram.tcl
@@ -1,4 +1,3 @@
-
set design_rams {
swerv {2048x39 256x34 64x21}
bp_be_top {64x96 512x64 64x15}
@@ -11,7 +10,7 @@ set design_rams {
set results_dir "~/import/fakeram/results"
set flow_dir "~/import/flow/flow/platforms/nangate45"
-proc make_fakeram_links {} {
+proc make_fakeram_links { } {
global design_rams flow_dir
foreach {design sizes} $design_rams {
@@ -27,7 +26,7 @@ proc make_fakeram_links {} {
}
}
-proc copy_fakeram_results {} {
+proc copy_fakeram_results { } {
global design_rams results_dir flow_dir
foreach {design sizes} $design_rams {
diff --git a/flow/platforms/nangate45/make_tracks.tcl b/flow/platforms/nangate45/make_tracks.tcl
index 923d6a1fda..0411a74b72 100644
--- a/flow/platforms/nangate45/make_tracks.tcl
+++ b/flow/platforms/nangate45/make_tracks.tcl
@@ -1,10 +1,10 @@
make_tracks metal1 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
-make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
-make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
-make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
-make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
-make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
-make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8
-make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8
-make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6
+make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
+make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
+make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
+make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
+make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
+make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8
+make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8
+make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6
make_tracks metal10 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6
diff --git a/flow/platforms/nangate45/setRC.tcl b/flow/platforms/nangate45/setRC.tcl
index d52baaa67d..f39d456de7 100644
--- a/flow/platforms/nangate45/setRC.tcl
+++ b/flow/platforms/nangate45/setRC.tcl
@@ -12,4 +12,4 @@ set_layer_rc -layer metal8 -resistance 1.8750e-04 -capacitance 9.69714E-02
#set_layer_rc -layer metal10 -resistance 3.7500e-05 -capacitance 2.8042e-02
set_wire_rc -signal -layer metal3
-set_wire_rc -clock -layer metal5
+set_wire_rc -clock -layer metal5
diff --git a/flow/platforms/nangate45/tapcell.tcl b/flow/platforms/nangate45/tapcell.tcl
index 9057b795cd..edd4e1d15b 100644
--- a/flow/platforms/nangate45/tapcell.tcl
+++ b/flow/platforms/nangate45/tapcell.tcl
@@ -2,4 +2,3 @@ tapcell \
-distance 120 \
-tapcell_master "$::env(TAP_CELL_NAME)" \
-endcap_master "$::env(TAP_CELL_NAME)"
-
diff --git a/flow/platforms/sky130hd/fastroute.tcl b/flow/platforms/sky130hd/fastroute.tcl
index 24af379c99..76f9321967 100644
--- a/flow/platforms/sky130hd/fastroute.tcl
+++ b/flow/platforms/sky130hd/fastroute.tcl
@@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING
set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-
diff --git a/flow/scripts/add_routing_blk.tcl b/flow/scripts/add_routing_blk.tcl
index 7fc079f446..f4aadedbe7 100644
--- a/flow/scripts/add_routing_blk.tcl
+++ b/flow/scripts/add_routing_blk.tcl
@@ -22,19 +22,19 @@ foreach inst $allInsts {
set loc_llx [lindex [$inst getLocation] 0]
set loc_lly [lindex [$inst getLocation] 1]
- if {[string match "*gf12*" $name]||[string match "IN12LP*" $name]} {
+ if { [string match "*gf12*" $name] || [string match "IN12LP*" $name] } {
set w [$master getWidth]
set h [$master getHeight]
- set llx_Mx [expr $loc_llx - (128*$numTrack)]
- set lly_Mx [expr $loc_lly - (128*$numTrack)]
- set urx_Mx [expr $loc_llx + $w + (128*$numTrack)]
- set ury_Mx [expr $loc_lly + $h + (128*$numTrack)]
+ set llx_Mx [expr $loc_llx - (128*$numTrack)]
+ set lly_Mx [expr $loc_lly - (128*$numTrack)]
+ set urx_Mx [expr $loc_llx + $w + (128*$numTrack)]
+ set ury_Mx [expr $loc_lly + $h + (128*$numTrack)]
- set llx_Cx $loc_llx
- set lly_Cx [expr $loc_lly - (160*$numTrack)]
- set urx_Cx [expr $loc_llx + $w]
- set ury_Cx [expr $loc_lly + $h + (160*$numTrack)]
+ set llx_Cx $loc_llx
+ set lly_Cx [expr $loc_lly - (160*$numTrack)]
+ set urx_Cx [expr $loc_llx + $w]
+ set ury_Cx [expr $loc_lly + $h + (160*$numTrack)]
set obs_M2 [odb::dbObstruction_create $block $layer_M2 $llx_Mx $lly_Mx $urx_Mx $ury_Mx]
set obs_M3 [odb::dbObstruction_create $block $layer_M3 $llx_Mx $lly_Mx $urx_Mx $ury_Mx]
@@ -44,6 +44,6 @@ foreach inst $allInsts {
}
}
-if {$cnt != 0} {
+if { $cnt != 0 } {
puts "Created $cnt routing blockages over macros"
}
diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl
index 5350eaa3eb..5865a19485 100644
--- a/flow/scripts/cts.tcl
+++ b/flow/scripts/cts.tcl
@@ -7,7 +7,7 @@ load_design 3_place.odb 3_place.sdc
# so cts does not try to buffer the inverted clocks.
repair_clock_inverters
-proc save_progress {stage} {
+proc save_progress { stage } {
puts "Run 'make gui_$stage.odb' to load progress snapshot"
write_db $::env(RESULTS_DIR)/$stage.odb
write_sdc -no_timestamp $::env(RESULTS_DIR)/$stage.sdc
@@ -15,9 +15,9 @@ proc save_progress {stage} {
# Run CTS
set cts_args [list \
- -sink_clustering_enable \
- -balance_levels \
- -repair_clock_nets]
+ -sink_clustering_enable \
+ -balance_levels \
+ -repair_clock_nets]
append_env_var cts_args CTS_BUF_DISTANCE -distance_between_buffers 1
append_env_var cts_args CTS_CLUSTER_SIZE -sink_clustering_size 1
@@ -26,7 +26,7 @@ append_env_var cts_args CTS_BUF_LIST -buf_list 1
append_env_var cts_args CTS_LIB_NAME -library 1
-if {[env_var_exists_and_non_empty CTS_ARGS]} {
+if { [env_var_exists_and_non_empty CTS_ARGS] } {
set cts_args $::env(CTS_ARGS)
}
@@ -42,29 +42,29 @@ if { $::env(DETAILED_METRICS) } {
utl::pop_metrics_stage
set_placement_padding -global \
- -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
- -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
+ -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
+ -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
detailed_placement
estimate_parasitics -placement
-if {[env_var_equals CTS_SNAPSHOTS 1]} {
+if { [env_var_equals CTS_SNAPSHOTS 1] } {
save_progress 4_1_pre_repair_hold_setup
}
-if {![env_var_equals SKIP_CTS_REPAIR_TIMING 1]} {
- if {$::env(EQUIVALENCE_CHECK)} {
- write_eqy_verilog 4_before_rsz.v
+if { ![env_var_equals SKIP_CTS_REPAIR_TIMING 1] } {
+ if { $::env(EQUIVALENCE_CHECK) } {
+ write_eqy_verilog 4_before_rsz.v
}
repair_timing_helper
- if {$::env(EQUIVALENCE_CHECK)} {
- run_equivalence_test
+ if { $::env(EQUIVALENCE_CHECK) } {
+ run_equivalence_test
}
- set result [catch {detailed_placement} msg]
- if {$result != 0} {
+ set result [catch { detailed_placement } msg]
+ if { $result != 0 } {
save_progress 4_1_error
puts "Detailed placement failed in CTS: $msg"
exit $result
diff --git a/flow/scripts/deleteNonClkNets.tcl b/flow/scripts/deleteNonClkNets.tcl
index 0a6e80bb3c..bad10a4772 100644
--- a/flow/scripts/deleteNonClkNets.tcl
+++ b/flow/scripts/deleteNonClkNets.tcl
@@ -1,6 +1,6 @@
read_lef $::env(TECH_LEF)
read_lef $::env(SC_LEF)
-if {[info exist ::env(ADDITIONAL_LEFS)]} {
+if { [info exist ::env(ADDITIONAL_LEFS)] } {
foreach lef $::env(ADDITIONAL_LEFS) {
read_lef $lef
}
@@ -13,24 +13,26 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl
read_def $::env(RESULTS_DIR)/6_final.def
set block [[[ord::get_db] getChip] getBlock]
-set nets [$block getNets]
+set nets [$block getNets]
set insts [$block getInsts]
# Delete all non-clock nets
foreach net $nets {
set sigType [$net getSigType]
set wire [$net getWire]
- if {"$sigType" eq "SIGNAL" && "$wire" ne "NULL"} {
+ if { "$sigType" eq "SIGNAL" && "$wire" ne "NULL" } {
odb::dbWire_destroy $wire
- } elseif {"$sigType" eq "POWER" ||
- "$sigType" eq "GROUND"} {
+ } elseif {
+ "$sigType" eq "POWER" ||
+ "$sigType" eq "GROUND"
+ } {
$net destroySWires
}
}
# Delete fill cells to clean up screenshot
foreach inst $insts {
- if {"[[$inst getMaster] getType]" eq "CORE_SPACER"} {
+ if { "[[$inst getMaster] getType]" eq "CORE_SPACER" } {
odb::dbInst_destroy $inst
}
}
diff --git a/flow/scripts/deletePowerNets.tcl b/flow/scripts/deletePowerNets.tcl
index 74120d50b3..e1e6def4e1 100644
--- a/flow/scripts/deletePowerNets.tcl
+++ b/flow/scripts/deletePowerNets.tcl
@@ -1,6 +1,6 @@
read_lef $::env(TECH_LEF)
read_lef $::env(SC_LEF)
-if {[info exist ::env(ADDITIONAL_LEFS)]} {
+if { [info exist ::env(ADDITIONAL_LEFS)] } {
foreach lef $::env(ADDITIONAL_LEFS) {
read_lef $lef
}
@@ -12,7 +12,7 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl
# Read def and sdc
read_def $::env(RESULTS_DIR)/6_final.def
-proc deleteNetByName {name} {
+proc deleteNetByName { name } {
set db [ord::get_db]
set chip [$db getChip]
set block [$chip getBlock]
diff --git a/flow/scripts/deleteRoutingObstructions.tcl b/flow/scripts/deleteRoutingObstructions.tcl
index 5f78de4e06..2743009338 100644
--- a/flow/scripts/deleteRoutingObstructions.tcl
+++ b/flow/scripts/deleteRoutingObstructions.tcl
@@ -1,4 +1,4 @@
-proc deleteRoutingObstructions {} {
+proc deleteRoutingObstructions { } {
set db [ord::get_db]
set chip [$db getChip]
set block [$chip getBlock]
diff --git a/flow/scripts/density_fill.tcl b/flow/scripts/density_fill.tcl
index 3709a447d3..0c4e10585e 100644
--- a/flow/scripts/density_fill.tcl
+++ b/flow/scripts/density_fill.tcl
@@ -2,7 +2,7 @@ source $::env(SCRIPTS_DIR)/load.tcl
erase_non_stage_variables final
load_design 5_route.odb 5_route.sdc
-if {[env_var_equals USE_FILL 1]} {
+if { [env_var_equals USE_FILL 1] } {
set_propagated_clock [all_clocks]
density_fill -rules $::env(FILL_CONFIG)
# The .v file is just for debugging purposes, not a result of
diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl
index a92a5ae800..c093b162fe 100644
--- a/flow/scripts/detail_place.tcl
+++ b/flow/scripts/detail_place.tcl
@@ -5,19 +5,19 @@ load_design 3_4_place_resized.odb 2_floorplan.sdc
source $::env(PLATFORM_DIR)/setRC.tcl
-proc do_dpl {} {
+proc do_dpl { } {
# Only for use with hybrid rows
- if {[env_var_equals BALANCE_ROWS 1]} {
+ if { [env_var_equals BALANCE_ROWS 1] } {
balance_row_usage
}
-
+
set_placement_padding -global \
- -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
- -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
+ -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
+ -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
detailed_placement
-
- if {[env_var_equals ENABLE_DPO 1]} {
- if {[env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT]} {
+
+ if { [env_var_equals ENABLE_DPO 1] } {
+ if { [env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT] } {
improve_placement -max_displacement $::env(DPO_MAX_DISPLACEMENT)
} else {
improve_placement
@@ -26,12 +26,12 @@ proc do_dpl {} {
optimize_mirroring
utl::info FLW 12 "Placement violations [check_placement -verbose]."
-
+
estimate_parasitics -placement
}
-set result [catch {do_dpl} errMsg]
-if {$result != 0} {
+set result [catch { do_dpl } errMsg]
+if { $result != 0 } {
write_db $::env(RESULTS_DIR)/3_5_place_dp-failed.odb
error $errMsg
}
diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl
index df1bdc1999..0ec28b2135 100644
--- a/flow/scripts/detail_route.tcl
+++ b/flow/scripts/detail_route.tcl
@@ -1,7 +1,7 @@
utl::set_metrics_stage "detailedroute__{}"
source $::env(SCRIPTS_DIR)/load.tcl
load_design 5_1_grt.odb 5_1_grt.sdc
-if {![grt::have_routes]} {
+if { ![grt::have_routes] } {
error "Global routing failed, run `make gui_grt` and load $::global_route_congestion_report \
in DRC viewer to view congestion"
}
@@ -36,8 +36,10 @@ append additional_args " -verbose 1"
# having to go spelunking in Tcl or modify configuration scripts, while
# not having to wait too long or generating large useless reports.
-set arguments [expr {[env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : \
- [concat $additional_args {-drc_report_iter_step 5}]}]
+set arguments [expr {
+ [env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) :
+ [concat $additional_args {-drc_report_iter_step 5}]
+}]
set all_args [concat [list \
-output_drc $::env(REPORTS_DIR)/5_route_drc.rpt \
@@ -46,12 +48,12 @@ set all_args [concat [list \
log_cmd detailed_route {*}$all_args
-if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} {
+if { ![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1] } {
set repair_antennas_iters 1
- if {[repair_antennas]} {
+ if { [repair_antennas] } {
detailed_route {*}$all_args
}
- while {[check_antennas] && $repair_antennas_iters < 5} {
+ while { [check_antennas] && $repair_antennas_iters < 5 } {
repair_antennas
detailed_route {*}$all_args
incr repair_antennas_iters
@@ -66,7 +68,7 @@ if { [env_var_exists_and_non_empty POST_DETAIL_ROUTE_TCL] } {
check_antennas -report_file $env(REPORTS_DIR)/drt_antennas.log
-if {![design_is_routed]} {
+if { ![design_is_routed] } {
error "Design has unrouted nets."
}
diff --git a/flow/scripts/fillcell.tcl b/flow/scripts/fillcell.tcl
index 293f69ac83..ea23e5b24f 100644
--- a/flow/scripts/fillcell.tcl
+++ b/flow/scripts/fillcell.tcl
@@ -1,6 +1,6 @@
source $::env(SCRIPTS_DIR)/load.tcl
erase_non_stage_variables route
-if {[env_var_exists_and_non_empty FILL_CELLS]} {
+if { [env_var_exists_and_non_empty FILL_CELLS] } {
load_design 5_2_route.odb 5_1_grt.sdc
set_propagated_clock [all_clocks]
diff --git a/flow/scripts/final_report.tcl b/flow/scripts/final_report.tcl
index d5c8d98e6a..a843d6dad6 100644
--- a/flow/scripts/final_report.tcl
+++ b/flow/scripts/final_report.tcl
@@ -18,11 +18,10 @@ write_def $::env(RESULTS_DIR)/6_final.def
write_verilog $::env(RESULTS_DIR)/6_final.v
# Run extraction and STA
-if {[env_var_exists_and_non_empty RCX_RULES]} {
-
+if { [env_var_exists_and_non_empty RCX_RULES] } {
# Set RC corner for RCX
# Set in config.mk
- if {[env_var_exists_and_non_empty RCX_RC_CORNER]} {
+ if { [env_var_exists_and_non_empty RCX_RC_CORNER] } {
set rc_corner $::env(RCX_RC_CORNER)
}
@@ -38,25 +37,24 @@ if {[env_var_exists_and_non_empty RCX_RULES]} {
read_spef $::env(RESULTS_DIR)/6_final.spef
# Static IR drop analysis
- if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} {
+ if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } {
dict for {pwrNetName pwrNetVoltage} $::env(PWR_NETS_VOLTAGES) {
- set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage}
- analyze_power_grid -net ${pwrNetName} \
- -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt
+ set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage}
+ analyze_power_grid -net ${pwrNetName} \
+ -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt
}
} else {
puts "IR drop analysis for power nets is skipped because PWR_NETS_VOLTAGES is undefined"
}
- if {[env_var_exists_and_non_empty GND_NETS_VOLTAGES]} {
+ if { [env_var_exists_and_non_empty GND_NETS_VOLTAGES] } {
dict for {gndNetName gndNetVoltage} $::env(GND_NETS_VOLTAGES) {
- set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage}
- analyze_power_grid -net ${gndNetName} \
- -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt
+ set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage}
+ analyze_power_grid -net ${gndNetName} \
+ -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt
}
} else {
puts "IR drop analysis for ground nets is skipped because GND_NETS_VOLTAGES is undefined"
}
-
} else {
puts "OpenRCX is not enabled for this platform."
}
@@ -66,6 +64,6 @@ report_cell_usage
report_metrics 6 "finish"
# Save a final image if openroad is compiled with the gui
-if {[ord::openroad_gui_compiled]} {
- gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false
+if { [ord::openroad_gui_compiled] } {
+ gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false
}
diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl
index 259e97d57f..7e58e3fd9f 100644
--- a/flow/scripts/floorplan.tcl
+++ b/flow/scripts/floorplan.tcl
@@ -3,14 +3,14 @@ source $::env(SCRIPTS_DIR)/load.tcl
erase_non_stage_variables floorplan
load_design 1_synth.v 1_synth.sdc
-proc report_unused_masters {} {
+proc report_unused_masters { } {
set db [ord::get_db]
set libs [$db getLibs]
set masters ""
foreach lib $libs {
foreach master [$lib getMasters] {
# filter out non-block masters, or you can remove this conditional to detect any unused master
- if {[$master getType] == "BLOCK"} {
+ if { [$master getType] == "BLOCK" } {
lappend masters $master
}
}
@@ -45,61 +45,53 @@ append_env_var additional_args ADDITIONAL_SITES -additional_sites 1
set use_floorplan_def [env_var_exists_and_non_empty FLOORPLAN_DEF]
set use_footprint [env_var_exists_and_non_empty FOOTPRINT]
-set use_die_and_core_area [expr {[env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA]}]
+set use_die_and_core_area [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }]
set use_core_utilization [env_var_exists_and_non_empty CORE_UTILIZATION]
-set methods_defined [expr {$use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization}]
-if {$methods_defined > 1} {
- puts "Error: Floorplan initialization methods are mutually exclusive, pick one."
- exit 1
+set methods_defined [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }]
+if { $methods_defined > 1 } {
+ puts "Error: Floorplan initialization methods are mutually exclusive, pick one."
+ exit 1
}
-if {$use_floorplan_def} {
- # Initialize floorplan by reading in floorplan DEF
- log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF)
-} elseif {$use_footprint} {
- # Initialize floorplan using ICeWall FOOTPRINT
- ICeWall load_footprint $env(FOOTPRINT)
-
- initialize_floorplan \
- -die_area [ICeWall get_die_area] \
- -core_area [ICeWall get_core_area] \
- -site $::env(PLACE_SITE)
-
- ICeWall init_footprint $env(SIG_MAP_FILE)
-} elseif {$use_die_and_core_area} {
- initialize_floorplan -die_area $::env(DIE_AREA) \
- -core_area $::env(CORE_AREA) \
- -site $::env(PLACE_SITE) \
- {*}$additional_args
-} elseif {$use_core_utilization} {
- set aspect_ratio 1.0
- if {[env_var_exists_and_non_empty "CORE_ASPECT_RATIO"]} {
- set aspect_ratio $::env(CORE_ASPECT_RATIO)
- }
- set core_margin 1.0
- if {[env_var_exists_and_non_empty "CORE_MARGIN"]} {
- set core_margin $::env(CORE_MARGIN)
- }
- initialize_floorplan -utilization $::env(CORE_UTILIZATION) \
- -aspect_ratio $aspect_ratio \
- -core_space $core_margin \
- -site $::env(PLACE_SITE) \
- {*}$additional_args
+if { $use_floorplan_def } {
+ # Initialize floorplan by reading in floorplan DEF
+ log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF)
+} elseif { $use_footprint } {
+ # Initialize floorplan using ICeWall FOOTPRINT
+ ICeWall load_footprint $env(FOOTPRINT)
+
+ initialize_floorplan \
+ -die_area [ICeWall get_die_area] \
+ -core_area [ICeWall get_core_area] \
+ -site $::env(PLACE_SITE)
+
+ ICeWall init_footprint $env(SIG_MAP_FILE)
+} elseif { $use_die_and_core_area } {
+ initialize_floorplan -die_area $::env(DIE_AREA) \
+ -core_area $::env(CORE_AREA) \
+ -site $::env(PLACE_SITE) \
+ {*}$additional_args
+} elseif { $use_core_utilization } {
+ initialize_floorplan -utilization $::env(CORE_UTILIZATION) \
+ -aspect_ratio $::env(CORE_ASPECT_RATIO) \
+ -core_space $::env(CORE_MARGIN) \
+ -site $::env(PLACE_SITE) \
+ {*}$additional_args
} else {
- puts "Error: No floorplan initialization method specified"
- exit 1
+ puts "Error: No floorplan initialization method specified"
+ exit 1
}
if { [env_var_exists_and_non_empty MAKE_TRACKS] } {
log_cmd source $::env(MAKE_TRACKS)
-} elseif {[file exists $::env(PLATFORM_DIR)/make_tracks.tcl]} {
+} elseif { [file exists $::env(PLATFORM_DIR)/make_tracks.tcl] } {
log_cmd source $::env(PLATFORM_DIR)/make_tracks.tcl
} else {
make_tracks
}
-if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} {
+if { [env_var_exists_and_non_empty FOOTPRINT_TCL] } {
log_cmd source $::env(FOOTPRINT_TCL)
}
@@ -107,93 +99,23 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
# remove buffers inserted by yosys/abc
remove_buffers
} else {
- repair_timing_helper 0
-}
-
-##### Restructure for timing #########
-if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
- repair_design_helper
- repair_timing_helper
- # pre restructure area/timing report (ideal clocks)
- puts "Post synth-opt area"
- report_design_area
- report_worst_slack -min -digits 3
- puts "Post synth-opt wns"
- report_worst_slack -max -digits 3
- puts "Post synth-opt tns"
- report_tns -digits 3
-
- write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v
-
- restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \
- -work_dir $::env(RESULTS_DIR)
-
- write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v
-
- # post restructure area/timing report (ideal clocks)
- remove_buffers
- repair_design_helper
- repair_timing_helper
-
- puts "Post restructure-opt wns"
- report_worst_slack -max -digits 3
- puts "Post restructure-opt tns"
- report_tns -digits 3
-
- # remove buffers inserted by optimization
- remove_buffers
+ # Skip clone & split
+ set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer"
+ set ::env(SKIP_LAST_GASP) 1
+ repair_timing_helper -setup
}
-
puts "Default units for flow"
report_units
report_units_metric
report_metrics 2 "floorplan final" false false
-if { [env_var_equals RESYNTH_AREA_RECOVER 1] } {
-
- utl::push_metrics_stage "floorplan__{}__pre_restruct"
- set num_instances [llength [get_cells -hier *]]
- puts "number instances before restructure is $num_instances"
- puts "Design Area before restructure"
- report_design_area
- report_design_area_metrics
- utl::pop_metrics_stage
-
- write_verilog $::env(RESULTS_DIR)/2_pre_abc.v
-
- set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0]
- set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
- set tielo_port $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1]
-
- set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0]
- set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
- set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1]
-
- restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \
- -tiehi_port $tiehi_port \
- -tielo_port $tielo_port \
- -work_dir $::env(RESULTS_DIR)
-
- # remove buffers inserted by abc
- remove_buffers
-
- write_verilog $::env(RESULTS_DIR)/2_post_abc.v
- utl::push_metrics_stage "floorplan__{}__post_restruct"
- set num_instances [llength [get_cells -hier *]]
- puts "number instances after restructure is $num_instances"
- puts "Design Area after restructure"
- report_design_area
- report_design_area_metrics
- utl::pop_metrics_stage
-}
-
if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } {
log_cmd source $::env(POST_FLOORPLAN_TCL)
}
-if {[env_var_exists_and_non_empty IO_CONSTRAINTS]} {
+if { [env_var_exists_and_non_empty IO_CONSTRAINTS] } {
log_cmd source $::env(IO_CONSTRAINTS)
}
diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py
index 241edeb245..75a38d6f4f 100755
--- a/flow/scripts/generate-variables-docs.py
+++ b/flow/scripts/generate-variables-docs.py
@@ -26,8 +26,8 @@
markdown_table += "## Variables in alphabetic order\n\n"
table_header = """
-| Variable | Description | Default | Deprecated |
-| --- | --- | --- | --- |
+| Variable | Description | Default |
+| --- | --- | --- |
"""
table_rows = ""
for key in sorted(data):
@@ -35,9 +35,9 @@
description = value.get("description", "").replace("\n", " ").strip()
table_rows += (
f'| {key}'
+ + f'{" (deprecated)" if value.get("deprecated", 0) == 1 else ""}'
+ f"| {description}"
+ f'| {value.get("default", "")}'
- + f'| {"yes" if value.get("deprecated", 0) == 1 else ""}'
+ "|\n"
)
diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl
index 8ba73b46f5..6fc76b693a 100644
--- a/flow/scripts/generate_abstract.tcl
+++ b/flow/scripts/generate_abstract.tcl
@@ -1,7 +1,7 @@
source $::env(SCRIPTS_DIR)/load.tcl
erase_non_stage_variables generate_abstract
-set stem [expr {[env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final"}]
+set stem [expr { [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final" }]
set result [find_sdc_file $stem.odb]
set design_stage [lindex $result 0]
@@ -9,19 +9,19 @@ set sdc_file [lindex $result 1]
log_cmd load_design $stem.odb [file tail $sdc_file]
-if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} {
+if { $design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef] } {
log_cmd read_spef $::env(RESULTS_DIR)/$stem.spef
-} elseif {$design_stage >= 3} {
+} elseif { $design_stage >= 3 } {
log_cmd estimate_parasitics -placement
}
-if {$design_stage >= 4} {
+if { $design_stage >= 4 } {
set_propagated_clock [all_clocks]
}
# write_timing_model includes the source latency in the model
set_clock_latency -source 0 [all_clocks]
puts "Generating abstract views"
-if {[env_var_exists_and_non_empty CORNERS]} {
+if { [env_var_exists_and_non_empty CORNERS] } {
# corners
foreach corner $::env(CORNERS) {
log_cmd write_timing_model -corner $corner $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_$corner.lib
@@ -32,7 +32,7 @@ if {[env_var_exists_and_non_empty CORNERS]} {
}
log_cmd write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef
-if {[env_var_exists_and_non_empty CDL_FILES]} {
+if { [env_var_exists_and_non_empty CDL_FILES] } {
cdl read_masters $::env(CDL_FILES)
cdl out $::env(RESULTS_DIR)/$stem.cdl
}
diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl
index 5969c9e9d8..ac9d5c6722 100644
--- a/flow/scripts/global_place.tcl
+++ b/flow/scripts/global_place.tcl
@@ -5,6 +5,19 @@ load_design 3_2_place_iop.odb 2_floorplan.sdc
set_dont_use $::env(DONT_USE_CELLS)
+remove_buffers
+
+# Do not buffer chip-level designs
+# by default, IO ports will be buffered
+# to not buffer IO ports, set environment variable
+# DONT_BUFFER_PORT = 1
+if { ![env_var_exists_and_non_empty FOOTPRINT] } {
+ if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
+ puts "Perform port buffering..."
+ buffer_ports
+ }
+}
+
fast_route
set global_placement_args {}
@@ -13,33 +26,33 @@ set global_placement_args {}
append_env_var global_placement_args GPL_ROUTABILITY_DRIVEN -routability_driven 0
# Parameters for timing driven mode in global placement
-if {$::env(GPL_TIMING_DRIVEN)} {
+if { $::env(GPL_TIMING_DRIVEN) } {
lappend global_placement_args {-timing_driven}
- if {[info exists ::env(GPL_KEEP_OVERFLOW)]} {
+ if { [info exists ::env(GPL_KEEP_OVERFLOW)] } {
lappend global_placement_args -keep_resize_below_overflow $::env(GPL_KEEP_OVERFLOW)
}
}
-proc do_placement {global_placement_args} {
+proc do_placement { global_placement_args } {
set all_args [concat [list -density [place_density_with_lb_addon] \
-pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
-pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \
$global_placement_args]
- lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS)
+ lappend all_args {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS]
log_cmd global_placement {*}$all_args
}
-set result [catch {do_placement $global_placement_args} errMsg]
-if {$result != 0} {
+set result [catch { do_placement $global_placement_args } errMsg]
+if { $result != 0 } {
write_db $::env(RESULTS_DIR)/3_3_place_gp-failed.odb
error $errMsg
}
estimate_parasitics -placement
-if {[env_var_equals CLUSTER_FLOPS 1]} {
+if { [env_var_equals CLUSTER_FLOPS 1] } {
cluster_flops
estimate_parasitics -placement
}
diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl
index fa9a53d537..ff05f363f6 100644
--- a/flow/scripts/global_place_skip_io.tcl
+++ b/flow/scripts/global_place_skip_io.tcl
@@ -6,9 +6,9 @@ if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } {
puts "FLOORPLAN_DEF is set. Skipping global placement without IOs"
} else {
log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \
- -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
- -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
- {*}$::env(GLOBAL_PLACEMENT_ARGS)
+ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
+ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
+ {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS]
}
write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb
diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl
index ecbf18109f..360a0067cc 100644
--- a/flow/scripts/global_route.tcl
+++ b/flow/scripts/global_route.tcl
@@ -5,12 +5,12 @@ load_design 4_cts.odb 4_cts.sdc
# This proc is here to allow us to use 'return' to return early from this
# file which is sourced
-proc global_route_helper {} {
- if {[env_var_exists_and_non_empty PRE_GLOBAL_ROUTE]} {
+proc global_route_helper { } {
+ if { [env_var_exists_and_non_empty PRE_GLOBAL_ROUTE] } {
source $::env(PRE_GLOBAL_ROUTE)
}
- proc do_global_route {} {
+ proc do_global_route { } {
set all_args [concat [list \
-congestion_report_file $::global_route_congestion_report] \
$::env(GLOBAL_ROUTE_ARGS)]
@@ -19,14 +19,16 @@ proc global_route_helper {} {
}
pin_access -bottom_routing_layer $::env(MIN_ROUTING_LAYER) \
- -top_routing_layer $::env(MAX_ROUTING_LAYER)
+ -top_routing_layer $::env(MAX_ROUTING_LAYER)
- set result [catch {do_global_route} errMsg]
+ set result [catch { do_global_route } errMsg]
- if {$result != 0} {
- if {[expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \
+ if { $result != 0 } {
+ if {
+ [expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \
![file exists $::global_route_congestion_report] || \
- [file size $::global_route_congestion_report] == 0]} {
+ [file size $::global_route_congestion_report] == 0]
+ } {
write_db $::env(RESULTS_DIR)/5_1_grt-failed.odb
error $errMsg
}
@@ -36,13 +38,13 @@ proc global_route_helper {} {
}
set_placement_padding -global \
- -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
- -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
+ -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
+ -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
set_propagated_clock [all_clocks]
estimate_parasitics -global_routing
- if {[env_var_exists_and_non_empty DONT_USE_CELLS]} {
+ if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
set_dont_use $::env(DONT_USE_CELLS)
}
@@ -88,7 +90,7 @@ proc global_route_helper {} {
# Route the modified nets by rsz journal restore
log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt
- if {![env_var_equals SKIP_ANTENNA_REPAIR 1]} {
+ if { ![env_var_equals SKIP_ANTENNA_REPAIR 1] } {
puts "Repair antennas..."
repair_antennas -iterations 5
check_placement -verbose
diff --git a/flow/scripts/io_placement.tcl b/flow/scripts/io_placement.tcl
index dc29acc671..e4f61e0983 100644
--- a/flow/scripts/io_placement.tcl
+++ b/flow/scripts/io_placement.tcl
@@ -1,14 +1,16 @@
source $::env(SCRIPTS_DIR)/load.tcl
erase_non_stage_variables place
-if {![env_var_exists_and_non_empty FLOORPLAN_DEF] && \
- ![env_var_exists_and_non_empty FOOTPRINT] && \
- ![env_var_exists_and_non_empty FOOTPRINT_TCL]} {
+if {
+ ![env_var_exists_and_non_empty FLOORPLAN_DEF] &&
+ ![env_var_exists_and_non_empty FOOTPRINT] &&
+ ![env_var_exists_and_non_empty FOOTPRINT_TCL]
+} {
load_design 3_1_place_gp_skip_io.odb 2_floorplan.sdc
log_cmd place_pins \
-hor_layers $::env(IO_PLACER_H) \
-ver_layers $::env(IO_PLACER_V) \
- {*}$::env(PLACE_PINS_ARGS)
+ {*}[env_var_or_empty PLACE_PINS_ARGS]
write_db $::env(RESULTS_DIR)/3_2_place_iop.odb
write_pin_placement $::env(RESULTS_DIR)/3_2_place_iop.tcl
} else {
diff --git a/flow/scripts/klayout.tcl b/flow/scripts/klayout.tcl
index 56cc08ad6b..811902d6c7 100644
--- a/flow/scripts/klayout.tcl
+++ b/flow/scripts/klayout.tcl
@@ -1,20 +1,20 @@
-if {[env_var_exists_and_non_empty FILL_CONFIG]} {
- set fill_config $::env(FILL_CONFIG)
+if { [env_var_exists_and_non_empty FILL_CONFIG] } {
+ set fill_config $::env(FILL_CONFIG)
} else {
- set fill_config ""
+ set fill_config ""
}
-if {[env_var_exists_and_non_empty SEAL_GDS]} {
- set seal_gds $::env(SEAL_GDS)
+if { [env_var_exists_and_non_empty SEAL_GDS] } {
+ set seal_gds $::env(SEAL_GDS)
} else {
- set seal_gds ""
+ set seal_gds ""
}
exec klayout -zz -rd design_name=$::env(DESIGN_NAME) \
- -rd in_def=$::env(RESULTS_DIR)/6_final.def \
- -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \
- -rd config_file=$fill_config \
- -rd seal_file=$seal_gds \
- -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \
- -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \
- -rm $::env(UTILS_DIR)/def2stream.py
+ -rd in_def=$::env(RESULTS_DIR)/6_final.def \
+ -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \
+ -rd config_file=$fill_config \
+ -rd seal_file=$seal_gds \
+ -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \
+ -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \
+ -rm $::env(UTILS_DIR)/def2stream.py
diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl
index a8f6f1e642..2134f61dda 100644
--- a/flow/scripts/load.tcl
+++ b/flow/scripts/load.tcl
@@ -2,29 +2,29 @@ source $::env(SCRIPTS_DIR)/util.tcl
source $::env(SCRIPTS_DIR)/report_metrics.tcl
-proc load_design {design_file sdc_file} {
+proc load_design { design_file sdc_file } {
# Source platform-related Tcl command (initially for suppressing Liberty
# warnings
- if {[env_var_exists_and_non_empty PLATFORM_TCL]} {
+ if { [env_var_exists_and_non_empty PLATFORM_TCL] } {
log_cmd source $::env(PLATFORM_TCL)
}
-
+
# Read liberty files
source $::env(SCRIPTS_DIR)/read_liberty.tcl
# Read design files
set ext [file extension $design_file]
- if {$ext == ".v"} {
+ if { $ext == ".v" } {
read_lef $::env(TECH_LEF)
read_lef $::env(SC_LEF)
- if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} {
+ if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } {
foreach lef $::env(ADDITIONAL_LEFS) {
read_lef $lef
}
}
read_verilog $::env(RESULTS_DIR)/$design_file
link_design $::env(DESIGN_NAME)
- } elseif {$ext == ".odb"} {
+ } elseif { $ext == ".odb" } {
read_db $::env(RESULTS_DIR)/$design_file
} else {
error "Unrecognized input file $design_file"
@@ -49,89 +49,89 @@ proc load_design {design_file sdc_file} {
# Routines to run equivalence tests when they are enabled.
proc get_verilog_cells_for_design { } {
- set dir "$::env(PLATFORM_DIR)/work_around_yosys/"
- set cell_files [glob $dir/*.v ]
+ set dir "$::env(PLATFORM_DIR)/work_around_yosys/"
+ set cell_files [glob $dir/*.v]
}
-proc write_eqy_verilog {filename} {
+proc write_eqy_verilog { filename } {
# Filter out cells with no verilog/not needed for equivalence such
# as fillers and tap cells
- if {[env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY]} {
+ if { [env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY] } {
write_verilog -remove_cells $::env(REMOVE_CELLS_FOR_EQY) $::env(RESULTS_DIR)/$filename
} else {
- write_verilog $::env(RESULTS_DIR)/$filename
+ write_verilog $::env(RESULTS_DIR)/$filename
}
}
-proc write_eqy_script_for_sky130hd {} {
- error "this routine is not yet implemented"
- #[gold]
- #read_verilog -sv ./before.v ./formal_pdk.v
+proc write_eqy_script_for_sky130hd { } {
+ error "this routine is not yet implemented"
+ #[gold]
+ #read_verilog -sv ./before.v ./formal_pdk.v
- #[gate]
- #read_verilog -sv ./after.v ./formal_pdk.v
+ #[gate]
+ #read_verilog -sv ./after.v ./formal_pdk.v
- #[script]
- #prep -top aes_cipher_top -flatten
+ #[script]
+ #prep -top aes_cipher_top -flatten
- ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all
- #rename -hide */_*_.*
+ ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all
+ #rename -hide */_*_.*
- ## This removes unused signals before partitioning so no partitions are created for them
- #opt_clean -purge
- #memory_map
+ ## This removes unused signals before partitioning so no partitions are created for them
+ #opt_clean -purge
+ #memory_map
- #[collect *]
- ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index
- #group *[] \1[]
+ #[collect *]
+ ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index
+ #group *[] \1[]
- #[strategy basic]
- #use sat
- #depth 2
+ #[strategy basic]
+ #use sat
+ #depth 2
}
proc write_eqy_script { } {
- set top_cell [current_design]
- set cell_files [get_verilog_cells_for_design]
- set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w]
- # Gold netlist
- puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n"
- puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
- # Modified netlist
- puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n"
- puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
-
- # Recommendation from eqy team on how to speed up a design
- puts $outfile "\[match *]\ngate-nomatch _*_.*"
-
- # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets"
- puts $outfile "gate-nomatch net*"
-
- # Necessary to avoid false positive after Yosys 0.49
- puts $outfile "gate-nomatch clone*\n\n"
-
- # Equivalence check recipe 1
- puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n"
- # Equivalence check recipe 2
- puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n"
-
- close $outfile
+ set top_cell [current_design]
+ set cell_files [get_verilog_cells_for_design]
+ set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w]
+ # Gold netlist
+ puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n"
+ puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
+ # Modified netlist
+ puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n"
+ puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
+
+ # Recommendation from eqy team on how to speed up a design
+ puts $outfile "\[match *]\ngate-nomatch _*_.*"
+
+ # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets"
+ puts $outfile "gate-nomatch net*"
+
+ # Necessary to avoid false positive after Yosys 0.49
+ puts $outfile "gate-nomatch clone*\n\n"
+
+ # Equivalence check recipe 1
+ puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n"
+ # Equivalence check recipe 2
+ puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n"
+
+ close $outfile
}
-proc run_equivalence_test {} {
- write_eqy_verilog 4_after_rsz.v
- write_eqy_script
-
- eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \
- --force \
- --jobs $::env(NUM_CORES) \
- $::env(OBJECTS_DIR)/4_eqy_test.eqy \
- > $::env(LOG_DIR)/4_equivalence_check.log
- set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log]
- if { $count == 0 } {
- error "Repair timing output failed equivalence test"
- } else {
- puts "Repair timing output passed equivalence test"
- }
+proc run_equivalence_test { } {
+ write_eqy_verilog 4_after_rsz.v
+ write_eqy_script
+
+ eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \
+ --force \
+ --jobs $::env(NUM_CORES) \
+ $::env(OBJECTS_DIR)/4_eqy_test.eqy \
+ > $::env(LOG_DIR)/4_equivalence_check.log
+ set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log]
+ if { $count == 0 } {
+ error "Repair timing output failed equivalence test"
+ } else {
+ puts "Repair timing output passed equivalence test"
+ }
}
diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl
index de8c5ff99b..8aa9963ad0 100644
--- a/flow/scripts/macro_place_util.tcl
+++ b/flow/scripts/macro_place_util.tcl
@@ -1,16 +1,16 @@
-if {[find_macros] != ""} {
- if {![env_var_exists_and_non_empty RTLMP_RPT_DIR]} {
+if { [find_macros] != "" } {
+ if { ![env_var_exists_and_non_empty RTLMP_RPT_DIR] } {
set ::env(RTLMP_RPT_DIR) "$::env(OBJECTS_DIR)/rtlmp"
}
- if {![env_var_exists_and_non_empty RTLMP_RPT_FILE]} {
+ if { ![env_var_exists_and_non_empty RTLMP_RPT_FILE] } {
set ::env(RTLMP_RPT_FILE) "partition.txt"
}
- if {![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE]} {
+ if { ![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE] } {
set ::env(RTLMP_BLOCKAGE_FILE) "$::env(OBJECTS_DIR)/rtlmp/partition.txt.blockage"
}
# If wrappers defined replace macros with their wrapped version
- if {[env_var_exists_and_non_empty MACRO_WRAPPERS]} {
+ if { [env_var_exists_and_non_empty MACRO_WRAPPERS] } {
source $::env(MACRO_WRAPPERS)
set wrapped_macros [dict keys [dict get $wrapper around]]
@@ -18,7 +18,7 @@ if {[find_macros] != ""} {
set block [ord::get_db_block]
foreach inst [$block getInsts] {
- if {[lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1} {
+ if { [lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1 } {
set new_master [dict get $wrapper around [[$inst getMaster] getName]]
puts "Replacing [[$inst getMaster] getName] with $new_master for [$inst getName]"
$inst swapMaster [$db findMaster $new_master]
@@ -30,13 +30,13 @@ if {[find_macros] != ""} {
set halo_max [expr max($halo_x, $halo_y)]
set blockage_width $halo_max
- if {[env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO]} {
+ if { [env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO] } {
set blockage_width $::env(MACRO_BLOCKAGE_HALO)
}
- if {[env_var_exists_and_non_empty MACRO_PLACEMENT_TCL]} {
+ if { [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL] } {
log_cmd source $::env(MACRO_PLACEMENT_TCL)
- } elseif {[env_var_exists_and_non_empty MACRO_PLACEMENT]} {
+ } elseif { [env_var_exists_and_non_empty MACRO_PLACEMENT] } {
source $::env(SCRIPTS_DIR)/read_macro_placement.tcl
log_cmd read_macro_placement $::env(MACRO_PLACEMENT)
} else {
@@ -74,7 +74,7 @@ if {[find_macros] != ""} {
}
source $::env(SCRIPTS_DIR)/placement_blockages.tcl
- block_channels $blockage_width
+ block_channels $blockage_width
} else {
puts "No macros found: Skipping macro_placement"
}
diff --git a/flow/scripts/noop.tcl b/flow/scripts/noop.tcl
index e69de29bb2..8b13789179 100644
--- a/flow/scripts/noop.tcl
+++ b/flow/scripts/noop.tcl
@@ -0,0 +1 @@
+
diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl
index 79b8322dfe..36659892e0 100644
--- a/flow/scripts/open.tcl
+++ b/flow/scripts/open.tcl
@@ -3,51 +3,51 @@ source $::env(SCRIPTS_DIR)/util.tcl
source $::env(SCRIPTS_DIR)/read_liberty.tcl
# Read def
-if {[env_var_exists_and_non_empty DEF_FILE]} {
- # Read lef
- log_cmd read_lef $::env(TECH_LEF)
- log_cmd read_lef $::env(SC_LEF)
- if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} {
- foreach lef $::env(ADDITIONAL_LEFS) {
- log_cmd read_lef $lef
- }
+if { [env_var_exists_and_non_empty DEF_FILE] } {
+ # Read lef
+ log_cmd read_lef $::env(TECH_LEF)
+ log_cmd read_lef $::env(SC_LEF)
+ if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } {
+ foreach lef $::env(ADDITIONAL_LEFS) {
+ log_cmd read_lef $lef
}
- set input_file $::env(DEF_FILE)
- log_cmd read_def $input_file
+ }
+ set input_file $::env(DEF_FILE)
+ log_cmd read_def $input_file
} else {
- set input_file $::env(ODB_FILE)
- log_cmd read_db $input_file
+ set input_file $::env(ODB_FILE)
+ log_cmd read_db $input_file
}
-proc read_timing {input_file} {
+proc read_timing { input_file } {
set result [find_sdc_file $input_file]
set design_stage [lindex $result 0]
set sdc_file [lindex $result 1]
- if {$sdc_file == ""} {
+ if { $sdc_file == "" } {
set sdc_file $::env(SDC_FILE)
}
log_cmd read_sdc $sdc_file
if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
source $::env(PLATFORM_DIR)/derate.tcl
}
-
+
source $::env(PLATFORM_DIR)/setRC.tcl
- if {$design_stage >= 4} {
+ if { $design_stage >= 4 } {
# CTS has run, so propagate clocks
set_propagated_clock [all_clocks]
}
-
- if {$design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef]} {
+
+ if { $design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef] } {
log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef
- } elseif {$design_stage >= 5} {
+ } elseif { $design_stage >= 5 } {
if { [log_cmd grt::have_routes] } {
log_cmd estimate_parasitics -global_routing
} else {
puts "No global routing results available, skipping estimate_parasitics"
puts "Load $::global_route_congestion_report for details"
}
- } elseif {$design_stage >= 3} {
+ } elseif { $design_stage >= 3 } {
log_cmd estimate_parasitics -placement
}
@@ -55,17 +55,16 @@ proc read_timing {input_file} {
set _tmp [log_cmd find_timing_paths]
}
-if {[ord::openroad_gui_compiled]} {
+if { [ord::openroad_gui_compiled] } {
set db_basename [file rootname [file tail $input_file]]
gui::set_title "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}"
}
-if {[env_var_equals GUI_TIMING 1]} {
+if { [env_var_equals GUI_TIMING 1] } {
puts "GUI_TIMING=1 reading timing, takes a little while for large designs..."
read_timing $input_file
- if {[gui::enabled]} {
+ if { [gui::enabled] } {
log_cmd gui::select_chart "Endpoint Slack"
log_cmd gui::update_timing_report
}
}
-
diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl
index ea3941177b..628c4727c5 100644
--- a/flow/scripts/pdn.tcl
+++ b/flow/scripts/pdn.tcl
@@ -12,12 +12,12 @@ if { [env_var_exists_and_non_empty POST_PDN_TCL] } {
# Check all supply nets
set block [ord::get_db_block]
foreach net [$block getNets] {
- set type [$net getSigType]
- if {$type == "POWER" || $type == "GROUND"} {
-# Temporarily disable due to CI issues
-# puts "Check supply: [$net getName]"
-# check_power_grid -net [$net getName]
- }
+ set type [$net getSigType]
+ if { $type == "POWER" || $type == "GROUND" } {
+ # Temporarily disable due to CI issues
+ # puts "Check supply: [$net getName]"
+ # check_power_grid -net [$net getName]
+ }
}
write_db $::env(RESULTS_DIR)/2_4_floorplan_pdn.odb
diff --git a/flow/scripts/placement_blockages.tcl b/flow/scripts/placement_blockages.tcl
index 876a01f903..82c306474b 100644
--- a/flow/scripts/placement_blockages.tcl
+++ b/flow/scripts/placement_blockages.tcl
@@ -1,4 +1,4 @@
-proc block_channels {channel_width_in_microns} {
+proc block_channels { channel_width_in_microns } {
set tech [ord::get_db_tech]
set units [$tech getDbUnitsPerMicron]
set block [ord::get_db_block]
@@ -8,7 +8,7 @@ proc block_channels {channel_width_in_microns} {
#
set shapes {}
foreach inst [$block getInsts] {
- if {[[$inst getMaster] getType] == "BLOCK"} {
+ if { [[$inst getMaster] getType] == "BLOCK" } {
set box [$inst getBBox]
lappend shapes [odb::newSetFromRect [$box xMin] [$box yMin] [$box xMax] [$box yMax]]
}
@@ -37,9 +37,8 @@ proc block_channels {channel_width_in_microns} {
#
set rects [odb::getRectangles $shapeSet]
foreach rect $rects {
- set b [odb::dbBlockage_create $block \
- [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]]
- $b setSoft
+ set b [odb::dbBlockage_create $block \
+ [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]]
+ $b setSoft
}
}
-
diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl
index d556c7ff27..89ff2df733 100644
--- a/flow/scripts/read_liberty.tcl
+++ b/flow/scripts/read_liberty.tcl
@@ -1,5 +1,5 @@
#Read Liberty
-if {[env_var_exists_and_non_empty CORNERS]} {
+if { [env_var_exists_and_non_empty CORNERS] } {
# corners
define_corners {*}$::env(CORNERS)
foreach corner $::env(CORNERS) {
diff --git a/flow/scripts/read_macro_placement.tcl b/flow/scripts/read_macro_placement.tcl
index 68c08231a4..bc643c7734 100644
--- a/flow/scripts/read_macro_placement.tcl
+++ b/flow/scripts/read_macro_placement.tcl
@@ -1,19 +1,19 @@
-proc read_macro_placement {macro_placement_file} {
+proc read_macro_placement { macro_placement_file } {
set block [ord::get_db_block]
set units [$block getDefUnits]
set ch [open $macro_placement_file]
- while {![eof $ch]} {
+ while { ![eof $ch] } {
set line [gets $ch]
- if {[llength $line] == 0} {continue}
+ if { [llength $line] == 0 } { continue }
set inst_name [lindex $line 0]
set orientation [lindex $line 1]
set x [expr round([lindex $line 2] * $units)]
set y [expr round([lindex $line 3] * $units)]
- if {[set inst [$block findInst $inst_name]] == "NULL"} {
+ if { [set inst [$block findInst $inst_name]] == "NULL" } {
error "Cannot find instance $inst_name"
}
diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl
index 340de7e629..a1c31864f6 100644
--- a/flow/scripts/report_metrics.tcl
+++ b/flow/scripts/report_metrics.tcl
@@ -1,13 +1,13 @@
proc report_puts { out } {
- upvar 1 when when
- upvar 1 filename filename
- set fileId [open $filename a]
- puts $fileId $out
- close $fileId
+ upvar 1 when when
+ upvar 1 filename filename
+ set fileId [open $filename a]
+ puts $fileId $out
+ close $fileId
}
-proc report_metrics { stage when {include_erc true} {include_clock_skew true} } {
- if {[env_var_equals SKIP_REPORT_METRICS 1]} {
+proc report_metrics { stage when { include_erc true } { include_clock_skew true } } {
+ if { [env_var_equals SKIP_REPORT_METRICS 1] } {
return
}
puts "Report metrics stage $stage, $when..."
@@ -33,7 +33,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_worst_slack_metric >> $filename
report_worst_slack_metric -hold >> $filename
- if {$include_clock_skew && $::env(REPORT_CLOCK_SKEW)} {
+ if { $include_clock_skew && $::env(REPORT_CLOCK_SKEW) } {
report_puts "\n=========================================================================="
report_puts "$when report_clock_skew"
report_puts "--------------------------------------------------------------------------"
@@ -57,7 +57,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_puts "--------------------------------------------------------------------------"
report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded >> $filename
- if {$include_erc} {
+ if { $include_erc } {
report_puts "\n=========================================================================="
report_puts "$when report_check_types -max_slew -max_cap -max_fanout -violators"
report_puts "--------------------------------------------------------------------------"
@@ -75,7 +75,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_puts "--------------------------------------------------------------------------"
report_puts "[sta::max_slew_check_limit]"
- if {[sta::max_slew_check_limit] < 1e30} {
+ if { [sta::max_slew_check_limit] < 1e30 } {
report_puts "\n=========================================================================="
report_puts "$when max_slew_check_slack_limit"
report_puts "--------------------------------------------------------------------------"
@@ -92,7 +92,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_puts "--------------------------------------------------------------------------"
report_puts "[sta::max_fanout_check_limit]"
- if {[sta::max_fanout_check_limit] < 1e30} {
+ if { [sta::max_fanout_check_limit] < 1e30 } {
report_puts "\n=========================================================================="
report_puts "$when max_fanout_check_slack_limit"
report_puts "--------------------------------------------------------------------------"
@@ -109,7 +109,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_puts "--------------------------------------------------------------------------"
report_puts "[sta::max_capacitance_check_limit]"
- if {[sta::max_capacitance_check_limit] < 1e30} {
+ if { [sta::max_capacitance_check_limit] < 1e30 } {
report_puts "\n=========================================================================="
report_puts "$when max_capacitance_check_slack_limit"
report_puts "--------------------------------------------------------------------------"
@@ -142,7 +142,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_puts "hold violation count [sta::endpoint_violation_count min]"
set critical_path [lindex [find_timing_paths -sort_by_slack] 0]
- if {$critical_path != ""} {
+ if { $critical_path != "" } {
set path_delay [sta::format_time [[$critical_path path] arrival] 4]
set path_slack [sta::format_time [[$critical_path path] slack] 4]
} else {
@@ -150,52 +150,52 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
set path_slack 0
}
- if { [llength [all_registers]] != 0} {
- report_puts "\n=========================================================================="
- report_puts "$when report_checks -path_delay max reg to reg"
- report_puts "--------------------------------------------------------------------------"
- report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
- report_puts "\n=========================================================================="
- report_puts "$when report_checks -path_delay min reg to reg"
- report_puts "--------------------------------------------------------------------------"
- report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
+ if { [llength [all_registers]] != 0 } {
+ report_puts "\n=========================================================================="
+ report_puts "$when report_checks -path_delay max reg to reg"
+ report_puts "--------------------------------------------------------------------------"
+ report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
+ report_puts "\n=========================================================================="
+ report_puts "$when report_checks -path_delay min reg to reg"
+ report_puts "--------------------------------------------------------------------------"
+ report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
- set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
- if {$inp_to_reg_critical_path != ""} {
- set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
- } else {
- set target_clock_latency_max 0
- }
+ set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
+ if { $inp_to_reg_critical_path != "" } {
+ set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
+ } else {
+ set target_clock_latency_max 0
+ }
- set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0]
- if {$inp_to_reg_critical_path != ""} {
- set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
- set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4]
- } else {
- set target_clock_latency_min 0
- set source_clock_latency 0
- }
-
- report_puts "\n=========================================================================="
- report_puts "$when critical path target clock latency max path"
- report_puts "--------------------------------------------------------------------------"
- report_puts "$target_clock_latency_max"
+ set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0]
+ if { $inp_to_reg_critical_path != "" } {
+ set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
+ set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4]
+ } else {
+ set target_clock_latency_min 0
+ set source_clock_latency 0
+ }
- report_puts "\n=========================================================================="
- report_puts "$when critical path target clock latency min path"
- report_puts "--------------------------------------------------------------------------"
- report_puts "$target_clock_latency_min"
+ report_puts "\n=========================================================================="
+ report_puts "$when critical path target clock latency max path"
+ report_puts "--------------------------------------------------------------------------"
+ report_puts "$target_clock_latency_max"
- report_puts "\n=========================================================================="
- report_puts "$when critical path source clock latency min path"
- report_puts "--------------------------------------------------------------------------"
- report_puts "$source_clock_latency"
+ report_puts "\n=========================================================================="
+ report_puts "$when critical path target clock latency min path"
+ report_puts "--------------------------------------------------------------------------"
+ report_puts "$target_clock_latency_min"
+
+ report_puts "\n=========================================================================="
+ report_puts "$when critical path source clock latency min path"
+ report_puts "--------------------------------------------------------------------------"
+ report_puts "$source_clock_latency"
} else {
- puts "No registers in design"
+ puts "No registers in design"
}
# end if all_registers
-
+
report_puts "\n=========================================================================="
report_puts "$when critical path delay"
report_puts "--------------------------------------------------------------------------"
@@ -215,7 +215,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
report_puts "\n=========================================================================="
report_puts "$when report_power"
report_puts "--------------------------------------------------------------------------"
- if {[env_var_exists_and_non_empty CORNERS]} {
+ if { [env_var_exists_and_non_empty CORNERS] } {
foreach corner $::env(CORNERS) {
report_puts "Corner: $corner"
report_power -corner $corner >> $filename
diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl
index cb38355043..9e81848921 100644
--- a/flow/scripts/resize.tcl
+++ b/flow/scripts/resize.tcl
@@ -10,15 +10,8 @@ set pin_count_before [sta::network_leaf_pin_count]
set_dont_use $::env(DONT_USE_CELLS)
-# Do not buffer chip-level designs
-# by default, IO ports will be buffered
-# to not buffer IO ports, set environment variable
-# DONT_BUFFER_PORT = 1
-if { ![env_var_exists_and_non_empty FOOTPRINT] } {
- if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
- puts "Perform port buffering..."
- buffer_ports
- }
+if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } {
+ log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO)
}
repair_design_helper
diff --git a/flow/scripts/save_images.tcl b/flow/scripts/save_images.tcl
index 67017a90f9..5dec935009 100644
--- a/flow/scripts/save_images.tcl
+++ b/flow/scripts/save_images.tcl
@@ -7,7 +7,7 @@ set height [ord::dbu_to_microns $height]
set resolution [expr $height / 1000]
set markerdb [[ord::get_db_block] findMarkerCategory DRC]
-if {$markerdb != "NULL" && [$markerdb getMarkerCount] > 0} {
+if { $markerdb != "NULL" && [$markerdb getMarkerCount] > 0 } {
gui::select_marker_category $markerdb
}
@@ -41,7 +41,7 @@ gui::set_display_controls "Instances/Physical/*" visible false
gui::set_display_controls "Misc/Instances/*" visible false
save_image -resolution $resolution $::env(REPORTS_DIR)/final_placement.webp
-if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} {
+if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } {
gui::set_display_controls "Heat Maps/IR Drop" visible true
gui::set_heatmap IRDrop Layer $::env(IR_DROP_LAYER)
gui::set_heatmap IRDrop ShowLegend 1
@@ -66,8 +66,8 @@ foreach clock [get_clocks *] {
if { [llength [get_property $clock sources]] > 0 } {
set clock_name [get_name $clock]
save_clocktree_image -clock $clock_name \
- -width 1024 -height 1024 \
- $::env(REPORTS_DIR)/cts_$clock_name.webp
+ -width 1024 -height 1024 \
+ $::env(REPORTS_DIR)/cts_$clock_name.webp
gui::select_clockviewer_clock $clock_name
save_image -resolution $resolution $::env(REPORTS_DIR)/cts_${clock_name}_layout.webp
}
@@ -81,17 +81,17 @@ gui::set_display_controls "Nets/Ground" visible false
gui::set_display_controls "Shape Types/Routing/*" visible false
gui::set_display_controls "Instances/*" visible true
gui::set_display_controls "Instances/Physical/*" visible false
-select -name "hold*" -type Inst -highlight 0 ;# green
-select -name "input*" -type Inst -highlight 1 ;# yellow
+select -name "hold*" -type Inst -highlight 0 ;# green
+select -name "input*" -type Inst -highlight 1 ;# yellow
select -name "output*" -type Inst -highlight 1
-select -name "repeater*" -type Inst -highlight 3 ;# magenta
+select -name "repeater*" -type Inst -highlight 3 ;# magenta
select -name "fanout*" -type Inst -highlight 3
select -name "load_slew*" -type Inst -highlight 3
select -name "max_cap*" -type Inst -highlight 3
select -name "max_length*" -type Inst -highlight 3
select -name "wire*" -type Inst -highlight 3
-select -name "rebuffer*" -type Inst -highlight 4 ;# red
-select -name "split*" -type Inst -highlight 5 ;# dark green
+select -name "rebuffer*" -type Inst -highlight 4 ;# red
+select -name "split*" -type Inst -highlight 5 ;# dark green
save_image -resolution $resolution $::env(REPORTS_DIR)/final_resizer.webp
diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl
index 1d89beb0ad..9a6b75d0be 100644
--- a/flow/scripts/synth.tcl
+++ b/flow/scripts/synth.tcl
@@ -9,7 +9,7 @@ if { [env_var_equals SYNTH_GUT 1] } {
delete $::env(DESIGN_NAME)/c:*
}
-if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} {
+if { [env_var_exists_and_non_empty SYNTH_KEEP_MODULES] } {
foreach module $::env(SYNTH_KEEP_MODULES) {
select -module $module
setattr -mod -set keep_hierarchy 1
@@ -17,23 +17,26 @@ if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} {
}
}
-set synth_full_args $::env(SYNTH_ARGS)
-if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
+if { [env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR] } {
+ scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
+}
+
+set synth_full_args [env_var_or_empty SYNTH_ARGS]
+if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } {
set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
} else {
set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
}
-if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
+if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
# Perform standard coarse-level synthesis script, flatten right away
- # (-flatten part of $synth_args per default)
- synth -run :fine {*}$synth_full_args
+ synth -flatten -run :fine {*}$synth_full_args
} else {
# Perform standard coarse-level synthesis script,
# defer flattening until we have decided what hierarchy to keep
synth -run :fine
- if {[env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE]} {
+ if { [env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE] } {
set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE)
puts "Keep modules above estimated size of $ungroup_threshold gate equivalents"
@@ -44,14 +47,14 @@ if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
}
# Re-run coarse-level script, this time do pass -flatten
- synth -run coarse:fine {*}$synth_full_args
+ synth -flatten -run coarse:fine {*}$synth_full_args
}
json -o $::env(RESULTS_DIR)/mem.json
# Run report and check here so as to fail early if this synthesis run is doomed
-exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
+exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
-if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
+if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args
} else {
source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl
@@ -70,7 +73,7 @@ renames -wire
opt -purge
# Technology mapping of adders
-if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
+if { [env_var_exists_and_non_empty ADDER_MAP_FILE] } {
# extract the full adders
extract_fa
# map full adders
@@ -81,7 +84,7 @@ if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
}
# Technology mapping of latches
-if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} {
+if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } {
techmap -map $::env(LATCH_MAP_FILE)
}
@@ -92,14 +95,14 @@ foreach cell $::env(DONT_USE_CELLS) {
# Technology mapping of flip-flops
# dfflibmap only supports one liberty file
-if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
+if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
} else {
dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
}
opt
-if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
+if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
log_cmd abc {*}$abc_args
} else {
scratchpad -set abc9.script scripts/abc_speed_gia_only.script
@@ -120,8 +123,8 @@ opt_clean -purge
# Technology mapping of constant hi- and/or lo-drivers
hilomap -singleton \
- -hicell {*}$::env(TIEHI_CELL_AND_PORT) \
- -locell {*}$::env(TIELO_CELL_AND_PORT)
+ -hicell {*}$::env(TIEHI_CELL_AND_PORT) \
+ -locell {*}$::env(TIELO_CELL_AND_PORT)
# Insert buffer cells for pass through wires
insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS)
@@ -132,7 +135,7 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check
tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
# check the design is composed exclusively of target cells, and check for other problems
-if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
+if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
check -assert -mapped
} else {
# Wrapped operator synthesis leaves around $buf cells which `check -mapped`
diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl
index c66d4b58ed..f53ca13219 100644
--- a/flow/scripts/synth_canonicalize.tcl
+++ b/flow/scripts/synth_canonicalize.tcl
@@ -1,7 +1,7 @@
source $::env(SCRIPTS_DIR)/synth_preamble.tcl
read_design_sources
-dict for {key value} $::env(VERILOG_TOP_PARAMS) {
+dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
# Apply toplevel parameters
chparam -set $key $value $::env(DESIGN_NAME)
}
diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl
index 240b292ed6..a148fd9460 100644
--- a/flow/scripts/synth_preamble.tcl
+++ b/flow/scripts/synth_preamble.tcl
@@ -6,8 +6,8 @@ erase_non_stage_variables synth
# If using a cached, gate level netlist, then copy over to the results dir with
# preserve timestamps flag set. If you don't, subsequent runs will cause the
# floorplan step to be re-executed.
-if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} {
- if {[llength $::env(SYNTH_NETLIST_FILES)] == 1} {
+if { [env_var_exists_and_non_empty SYNTH_NETLIST_FILES] } {
+ if { [llength $::env(SYNTH_NETLIST_FILES)] == 1 } {
log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_1_yosys.v
} else {
# The date should be the most recent date of the files, but to
@@ -15,67 +15,69 @@ if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} {
log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_1_yosys.v
}
log_cmd exec cp -p $::env(SDC_FILE) $::env(RESULTS_DIR)/1_synth.sdc
- if {[env_var_exists_and_non_empty CACHED_REPORTS]} {
+ if { [env_var_exists_and_non_empty CACHED_REPORTS] } {
log_cmd exec cp -p {*}$::env(CACHED_REPORTS) $::env(REPORTS_DIR)/.
}
exit
}
-proc read_checkpoint {file} {
+proc read_checkpoint { file } {
# We are reading a Yosys checkpoint
- if {[file extension $file] == ".json"} {
+ if { [file extension $file] == ".json" } {
read_json $file
} else {
read_rtlil $file
- }
+ }
}
-proc read_design_sources {} {
+proc read_design_sources { } {
# We are reading Verilog sources
source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
# Setup verilog include directories
set vIdirsArgs ""
- if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
+ if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } {
foreach dir $::env(VERILOG_INCLUDE_DIRS) {
lappend vIdirsArgs "-I$dir"
}
set vIdirsArgs [join $vIdirsArgs]
}
- if {[env_var_equals SYNTH_HDL_FRONTEND slang]} {
+ if { [env_var_equals SYNTH_HDL_FRONTEND slang] } {
# slang requires all files at once
plugin -i slang
yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \
--ignore-assertions --top $::env(DESIGN_NAME) \
- {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env(VERILOG_DEFINES)
+ {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES]
# Workaround for yosys-slang#119
setattr -unset init
- } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} {
- if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
- verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
+ } elseif { [env_var_equals SYNTH_HDL_FRONTEND verific] } {
+ if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } {
+ verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
}
- if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
- verific -vlog-define {*}$::env(VERILOG_DEFINES)
+ if { [env_var_exists_and_non_empty VERILOG_DEFINES] } {
+ verific -vlog-define {*}$::env(VERILOG_DEFINES)
}
verific -sv2012 {*}$::env(VERILOG_FILES)
- } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} {
+ } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } {
verilog_defaults -push
- verilog_defaults -add {*}$::env(VERILOG_DEFINES)
+ if { [env_var_exists_and_non_empty VERILOG_DEFINES] } {
+ verilog_defaults -add {*}$::env(VERILOG_DEFINES)
+ }
foreach file $::env(VERILOG_FILES) {
read_verilog -defer -sv {*}$vIdirsArgs $file
}
verilog_defaults -pop
} else {
- error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)"
+ error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)"
}
# Read platform specific mapfile for OPENROAD_CLKGATE cells
- if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} {
+ if { [env_var_exists_and_non_empty CLKGATE_MAP_FILE] } {
read_verilog -defer $::env(CLKGATE_MAP_FILE)
}
- if {[env_var_exists_and_non_empty SYNTH_BLACKBOXES]} {
+ if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } {
hierarchy -check -top $::env(DESIGN_NAME)
foreach m $::env(SYNTH_BLACKBOXES) {
blackbox $m
@@ -83,7 +85,7 @@ proc read_design_sources {} {
}
}
-if {$::env(ABC_AREA)} {
+if { $::env(ABC_AREA) } {
puts "Using ABC area script."
set abc_script $::env(SCRIPTS_DIR)/abc_area.script
} else {
@@ -94,22 +96,22 @@ if {$::env(ABC_AREA)} {
# Technology mapping for cells
# ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't
set abc_args [list -script $abc_script \
- -liberty $::env(DONT_USE_SC_LIB) \
- -constr $::env(OBJECTS_DIR)/abc.constr]
+ -liberty $::env(DONT_USE_SC_LIB) \
+ -constr $::env(OBJECTS_DIR)/abc.constr]
# Exclude dont_use cells. This includes macros that are specified via
# LIB_FILES and ADDITIONAL_LIBS that are included in LIB_FILES.
-if {[env_var_exists_and_non_empty DONT_USE_CELLS]} {
+if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
foreach cell $::env(DONT_USE_CELLS) {
lappend abc_args -dont_use $cell
}
}
-if {[env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD]} {
+if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } {
puts "Extracting clock period from SDC file: $::env(SDC_FILE_CLOCK_PERIOD)"
set fp [open $::env(SDC_FILE_CLOCK_PERIOD) r]
set clock_period [string trim [read $fp]]
- if {$clock_period != ""} {
+ if { $clock_period != "" } {
puts "Setting clock period to $clock_period"
lappend abc_args -D $clock_period
}
@@ -127,24 +129,24 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)"
puts $constr "set_load $::env(ABC_LOAD_IN_FF)"
close $constr
-proc convert_liberty_areas {} {
+proc convert_liberty_areas { } {
cellmatch -derive_luts =A:liberty_cell
# find a reference nand2 gate
set found_cell ""
set found_cell_area ""
# iterate over all cells with a nand2 signature
foreach cell [tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m] {
- if {! [rtlil::has_attr -mod $cell area]} {
+ if { ![rtlil::has_attr -mod $cell area] } {
puts "Cell $cell missing area information"
continue
}
set area [rtlil::get_attr -string -mod $cell area]
- if {$found_cell == "" || [expr $area < $found_cell_area]} {
+ if { $found_cell == "" || [expr $area < $found_cell_area] } {
set found_cell $cell
set found_cell_area $area
}
}
- if {$found_cell == ""} {
+ if { $found_cell == "" } {
error "reference nand2 cell not found"
}
diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl
index c9b9ded629..a003aa2e32 100644
--- a/flow/scripts/synth_wrap_operators.tcl
+++ b/flow/scripts/synth_wrap_operators.tcl
@@ -15,7 +15,7 @@ set deferred_cells {
}
}
-techmap {*}[join [lmap cell $deferred_cells {string cat "-dont_map [lindex $cell 0]"}] " "]
+techmap {*}[join [lmap cell $deferred_cells { string cat "-dont_map [lindex $cell 0]" }] " "]
foreach info $deferred_cells {
set type [lindex $info 0]
@@ -53,7 +53,7 @@ foreach info $deferred_cells {
# iterate over all architectures, both the default and non-default
foreach arch [lrange $info 2 end] {
set suffix [lindex $arch 0]
- set extra_map_args [lrange $arch 1 end]
+ set extra_map_args [lrange $arch 1 end]
# map all operator copies which were selected to have this architecture
techmap -map +/techmap.v {*}$extra_map_args A:source_cell=$type A:architecture=$suffix %i
diff --git a/flow/scripts/tapcell.tcl b/flow/scripts/tapcell.tcl
index 16c007c079..eb00d11e23 100644
--- a/flow/scripts/tapcell.tcl
+++ b/flow/scripts/tapcell.tcl
@@ -3,10 +3,10 @@ erase_non_stage_variables floorplan
load_design 2_2_floorplan_macro.odb 2_1_floorplan.sdc
-if {[env_var_exists_and_non_empty TAPCELL_TCL]} {
- source $::env(TAPCELL_TCL)
+if { [env_var_exists_and_non_empty TAPCELL_TCL] } {
+ source $::env(TAPCELL_TCL)
} else {
- cut_rows
+ cut_rows
}
write_db $::env(RESULTS_DIR)/2_3_floorplan_tapcell.odb
diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl
index 972892c1a3..2c0695ef3f 100644
--- a/flow/scripts/util.tcl
+++ b/flow/scripts/util.tcl
@@ -1,11 +1,11 @@
-proc log_cmd {cmd args} {
+proc log_cmd { cmd args } {
# log the command, escape arguments with spaces
- set log_cmd "$cmd[join [lmap arg $args {format " %s" [expr {[string match {* *} $arg] ? "\"$arg\"" : "$arg"}]}] ""]"
+ set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]"
puts $log_cmd
set start [clock seconds]
set result [uplevel 1 [list $cmd {*}$args]]
- set time [expr {[clock seconds] - $start}]
- if {$time >= 5} {
+ set time [expr { [clock seconds] - $start }]
+ if { $time >= 5 } {
# Ideally we'd use a single line, but the command can output text
# and we don't want to mix it with the log, so output the time it took afterwards.
puts "Took $time seconds: $log_cmd"
@@ -13,8 +13,8 @@ proc log_cmd {cmd args} {
return $result
}
-proc fast_route {} {
- if {[env_var_exists_and_non_empty FASTROUTE_TCL]} {
+proc fast_route { } {
+ if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
log_cmd source $::env(FASTROUTE_TCL)
} else {
log_cmd set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT)
@@ -22,10 +22,10 @@ proc fast_route {} {
}
}
-proc repair_timing_helper { {hold_margin 1} } {
- set additional_args "-verbose"
+proc repair_timing_helper { args } {
+ set additional_args "$args -verbose"
append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1
- if {$hold_margin || $::env(HOLD_SLACK_MARGIN) < 0} {
+ if { $::env(HOLD_SLACK_MARGIN) < 0 } {
append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1
}
append_env_var additional_args SETUP_MOVE_SEQUENCE -sequence 1
@@ -38,7 +38,7 @@ proc repair_timing_helper { {hold_margin 1} } {
log_cmd repair_timing {*}$additional_args
}
-proc repair_design_helper {} {
+proc repair_design_helper { } {
puts "Perform buffer insertion and gate resizing..."
set additional_args "-verbose"
@@ -48,7 +48,7 @@ proc repair_design_helper {} {
log_cmd repair_design {*}$additional_args
}
-proc recover_power_helper {} {
+proc recover_power_helper { } {
if { $::env(RECOVER_POWER) == 0 } {
return
}
@@ -66,20 +66,20 @@ proc recover_power_helper {} {
report_power
}
-proc extract_stage {input_file} {
- if {![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2]} {
+proc extract_stage { input_file } {
+ if { ![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2] } {
puts "Error: Could not determine design stage from $input_file"
exit 1
}
lappend number_groups $num1
- if {$num2!=""} {
- lappend number_groups $num2
+ if { $num2 != "" } {
+ lappend number_groups $num2
} else {
lappend number_groups "0"
}
}
-proc find_sdc_file {input_file} {
+proc find_sdc_file { input_file } {
# canonicalize input file, sometimes it is called with an input
# file relative to $::env(RESULTS_DIR), other times with
# an absolute path
@@ -95,9 +95,9 @@ proc find_sdc_file {input_file} {
set exact_sdc [string map {.odb .sdc} $input_file]
set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"]
set sdc_files [lsort -decreasing -dictionary $sdc_files]
- set sdc_files [lmap file $sdc_files {file normalize $file}]
+ set sdc_files [lmap file $sdc_files { file normalize $file }]
foreach name $sdc_files {
- if {[lindex [lsort -decreasing -dictionary [list $name $exact_sdc] ] 0] == $exact_sdc} {
+ if { [lindex [lsort -decreasing -dictionary [list $name $exact_sdc]] 0] == $exact_sdc } {
set sdc_file $name
break
}
@@ -105,26 +105,36 @@ proc find_sdc_file {input_file} {
return [list $design_stage $sdc_file]
}
-proc env_var_equals {env_var value} {
- return [expr {[info exists ::env($env_var)] && $::env($env_var) == $value}]
+proc env_var_equals { env_var value } {
+ return [expr { [info exists ::env($env_var)] && $::env($env_var) == $value }]
}
-proc env_var_exists_and_non_empty {env_var} {
- return [expr {[info exists ::env($env_var)] && ![string equal $::env($env_var) ""]}]
+proc env_var_exists_and_non_empty { env_var } {
+ return [expr { [info exists ::env($env_var)] && ![string equal $::env($env_var) ""] }]
}
-proc append_env_var {list_name var_name prefix has_arg} {
+proc append_env_var { list_name var_name prefix has_arg } {
upvar $list_name list
- if {(!$has_arg && [env_var_equals $var_name 1]) ||
- ($has_arg && [env_var_exists_and_non_empty $var_name])} {
+ if {
+ (!$has_arg && [env_var_equals $var_name 1]) ||
+ ($has_arg && [env_var_exists_and_non_empty $var_name])
+ } {
lappend list $prefix
- if {$has_arg} {
+ if { $has_arg } {
lappend list $::env($var_name)
}
}
}
-proc find_macros {} {
+# Non-empty defaults should go into variables.yaml, generally
+proc env_var_or_empty { env_var } {
+ if { [env_var_exists_and_non_empty $env_var] } {
+ return $::env($env_var)
+ }
+ return ""
+}
+
+proc find_macros { } {
set macros ""
set db [ord::get_db]
@@ -140,7 +150,7 @@ proc find_macros {} {
return $macros
}
-proc erase_non_stage_variables {stage_name} {
+proc erase_non_stage_variables { stage_name } {
# "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of
# variables to erase.
#
@@ -149,7 +159,7 @@ proc erase_non_stage_variables {stage_name} {
# https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875
set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name]
foreach var $variables {
- if {[info exists ::env($var)]} {
+ if { [info exists ::env($var)] } {
unset ::env($var)
}
}
@@ -157,14 +167,14 @@ proc erase_non_stage_variables {stage_name} {
set global_route_congestion_report $::env(REPORTS_DIR)/congestion.rpt
-proc place_density_with_lb_addon {} {
- if {[env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON]} {
+proc place_density_with_lb_addon { } {
+ if { [env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON] } {
# check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON
set place_density_lb [gpl::get_global_placement_uniform_density \
- -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
- -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)]
+ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
+ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)]
set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01]
- if {$place_density > 1.0} {
+ if { $place_density > 1.0 } {
utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99."
}
puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb"
diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk
index 8d0ae89cd4..3f0ea97c3f 100644
--- a/flow/scripts/variables.mk
+++ b/flow/scripts/variables.mk
@@ -3,15 +3,6 @@
# lazy evaluation, conditional code, include statements,
# etc.
-# Setup variables to point to root / head of the OpenROAD directory
-# - the following settings allowed user to point OpenROAD binaries to different
-# location
-# - default is current install / clone directory
-ifeq ($(origin FLOW_HOME), undefined)
-FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))/..)
-endif
-export FLOW_HOME
-
export DESIGN_NICKNAME?=$(DESIGN_NAME)
#-------------------------------------------------------------------------------
@@ -21,7 +12,6 @@ export DESIGN_NICKNAME?=$(DESIGN_NAME)
# - utils, scripts, test - default is under current directory
export DESIGN_HOME ?= $(FLOW_HOME)/designs
export PLATFORM_HOME ?= $(FLOW_HOME)/platforms
-# WORK_HOME is set up in flow/Makefile
export UTILS_DIR ?= $(FLOW_HOME)/util
export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts
@@ -51,7 +41,7 @@ include $(PLATFORM_DIR)/config.mk
# __SPACE__ is a workaround for whitespace hell in "foreach"; there
# is no way to escape space in defaults.py and get "foreach" to work.
-$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
+$(foreach line,$(shell $(PYTHON_EXE) $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
export LOG_DIR = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
@@ -80,6 +70,8 @@ export NUM_CORES
#-------------------------------------------------------------------------------
# setup all commands used within this flow
+export PYTHON_EXE ?= $(shell command -v python3)
+
export TIME_BIN ?= env time
TIME_CMD = $(TIME_BIN) -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.'
TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null)
diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml
index 433085f635..3ac5a8bbe5 100644
--- a/flow/scripts/variables.yaml
+++ b/flow/scripts/variables.yaml
@@ -95,6 +95,7 @@ CORE_UTILIZATION:
stages:
- floorplan
tunable: 1
+ type: float
CORE_AREA:
description: >
The core area specified as a list of lower-left and upper-right corners in
@@ -221,6 +222,16 @@ TIELO_CELL_AND_PORT:
stages:
- synth
- place
+TIE_SEPARATION:
+ description: |
+ Distance separating tie high/low instances from the load.
+ stages:
+ - place
+EARLY_SIZING_CAP_RATIO:
+ description: |
+ Ratio between the input pin capacitance and the output pin load during initial gate sizing.
+ stages:
+ - place
MIN_BUF_CELL_AND_PORTS:
description: |
Used to insert a buffer cell to pass through wires. Used in synthesis.
@@ -328,13 +339,13 @@ IO_CONSTRAINTS:
- place
IO_PLACER_H:
description: >
- The metal layer on which to place the I/O pins horizontally (top and bottom
+ A list of metal layers on which the I/O pins are placed horizontally (top and bottom
of the die).
stages:
- place
IO_PLACER_V:
description: >
- The metal layer on which to place the I/O pins vertically (sides of the
+ A list of metal layers on which the I/O pins are placed vertically (sides of the
die).
stages:
- place
@@ -361,6 +372,7 @@ CELL_PAD_IN_SITES_GLOBAL_PLACEMENT:
- place
- floorplan
default: 0
+ type: int
tunable: 1
CELL_PAD_IN_SITES_DETAIL_PLACEMENT:
description: >
@@ -371,17 +383,24 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT:
- cts
- grt
default: 0
+ type: int
tunable: 1
PLACE_PINS_ARGS:
description: |
Arguments to place_pins
stages:
- place
- default: ""
PLACE_DENSITY:
description: >
- The desired placement density of cells. It reflects how spread the cells
- would be on the core area. 1.0 = closely dense. 0.0 = widely spread.
+ The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread.
+
+ The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results.
+
+ If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs.
+
+ A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails.
+
+ The default is platform specific.
stages:
- floorplan
- place
@@ -393,6 +412,7 @@ PLACE_DENSITY_LB_ADDON:
- floorplan
- place
tunable: 1
+ type: float
REPAIR_PDN_VIA_LAYER:
description: |
Remove power grid vias which generate DRC violations after detailed routing.
@@ -400,7 +420,6 @@ GLOBAL_PLACEMENT_ARGS:
description: >
Use additional tuning parameters during global placement other than default
args defined in global_place.tcl.
- default: ""
ENABLE_DPO:
description: |
Enable detail placement with improve_placement feature.
@@ -596,7 +615,6 @@ VERILOG_DEFINES:
description: >
Preprocessor defines passed to the language frontend.
Example: `-D HPDCACHE_ASSERT_OFF`
- default: ""
stages:
- synth
SDC_FILE:
@@ -676,20 +694,24 @@ SYNTH_KEEP_MODULES:
SYNTH_ARGS:
description: |
Optional synthesis variables for yosys.
- default: -flatten
+SYNTH_HIER_SEPARATOR:
+ description: |
+ Separator used for the synthesis flatten stage.
+ default: .
VERILOG_TOP_PARAMS:
description: |
Apply toplevel params (if exist).
stages:
- synth
- default: ""
CORE_ASPECT_RATIO:
description: >
The core aspect ratio (height / width). This value is ignored if
`CORE_UTILIZATION` is undefined.
stages:
- floorplan
+ default: 1.0
tunable: 1
+ type: float
CORE_MARGIN:
description: >
The margin between the core area and die area, specified in microns.
@@ -699,7 +721,9 @@ CORE_MARGIN:
is undefined.
stages:
- floorplan
+ default: 1.0
tunable: 1
+ type: float
DIE_AREA:
description: >
The die area specified as a list of lower-left and upper-right corners in
@@ -708,18 +732,6 @@ DIE_AREA:
stages:
- floorplan
tunable: 1
-RESYNTH_AREA_RECOVER:
- description: |
- Enable re-synthesis for area reclaim.
- stages:
- - floorplan
- default: 0
-RESYNTH_TIMING_RECOVER:
- description: |
- Enable re-synthesis for timing optimization.
- stages:
- - floorplan
- default: 0
MACRO_ROWS_HALO_X:
description: >
Horizontal distance between the edge of the macro and the beginning of the
@@ -756,6 +768,7 @@ CTS_CLUSTER_DIAMETER:
stages:
- cts
tunable: 1
+ type: float
CTS_CLUSTER_SIZE:
description: >
Maximum number of sinks per cluster.
@@ -763,6 +776,7 @@ CTS_CLUSTER_SIZE:
stages:
- cts
tunable: 1
+ type: int
CTS_LIB_NAME:
description: |
Name of the Liberty library to use in selecting the clock buffers.
diff --git a/flow/scripts/view_cells.tcl b/flow/scripts/view_cells.tcl
index d6bf433d9a..c7a4ca087c 100644
--- a/flow/scripts/view_cells.tcl
+++ b/flow/scripts/view_cells.tcl
@@ -2,7 +2,7 @@
read_lef $::env(TECH_LEF)
read_lef $::env(SC_LEF)
-if {[info exist ::env(ADDITIONAL_LEFS)]} {
+if { [info exist ::env(ADDITIONAL_LEFS)] } {
foreach lef $::env(ADDITIONAL_LEFS) {
read_lef $lef
}
@@ -16,9 +16,9 @@ set block [odb::dbBlock_create $chip all_cells]
# Get all the masters
set masters {}
foreach lib [$db getLibs] {
- foreach master [$lib getMasters] {
- lappend masters $master
- }
+ foreach master [$lib getMasters] {
+ lappend masters $master
+ }
}
# Find the number of masters & the max width and height of any master
@@ -26,9 +26,9 @@ set max_width 0
set max_height 0
set num_masters 0
foreach master $masters {
- set max_width [expr max($max_width, [$master getWidth])]
- set max_height [expr max($max_height, [$master getHeight])]
- incr num_masters
+ set max_width [expr max($max_width, [$master getWidth])]
+ set max_height [expr max($max_height, [$master getHeight])]
+ incr num_masters
}
# The steps for laying out the cells
@@ -42,15 +42,15 @@ set x_width [expr ceil(sqrt($num_masters * $y_step / $x_step))]
set x 0
set y 0
foreach master $masters {
- set inst [odb::dbInst_create $block $master [$master getName]]
- $inst setPlacementStatus PLACED
- $inst setLocation [expr $x * $x_step] [expr $y * $y_step]
-
- incr x
- if {$x == $x_width} {
- set x 0
- incr y
- }
+ set inst [odb::dbInst_create $block $master [$master getName]]
+ $inst setPlacementStatus PLACED
+ $inst setLocation [expr $x * $x_step] [expr $y * $y_step]
+
+ incr x
+ if { $x == $x_width } {
+ set x 0
+ incr y
+ }
}
gui::design_created
gui::fit
diff --git a/flow/scripts/write_ref_sdc.tcl b/flow/scripts/write_ref_sdc.tcl
index 5de57dc045..60c6bb7658 100644
--- a/flow/scripts/write_ref_sdc.tcl
+++ b/flow/scripts/write_ref_sdc.tcl
@@ -19,7 +19,7 @@ if { [llength $clks] == 0 } {
set ref_period [expr ($period - $slack) * (1.0 - $margin/100.0)]
utl::info "FLW" 8 "Clock $clk_name period [format %.3f $ref_period]"
utl::info "FLW" 9 "Clock $clk_name slack [format %.3f $slack]"
-
+
set sources [$clk sources]
# Redefine clock with updated period.
create_clock -name $clk_name -period $ref_period $sources
diff --git a/flow/tutorials/scripts/drt/drc_fix.tcl b/flow/tutorials/scripts/drt/drc_fix.tcl
index e62042582a..b54c0fe41d 100644
--- a/flow/tutorials/scripts/drt/drc_fix.tcl
+++ b/flow/tutorials/scripts/drt/drc_fix.tcl
@@ -9,8 +9,8 @@ read_sdc ./gcd/gcd.sdc
set_global_routing_layer_adjustment met1-met5 0.5
set_routing_layers -signal met1-met5
global_route -guide_file [make_result_file route.guide] \
- -congestion_iterations 100 \
- -verbose
+ -congestion_iterations 100 \
+ -verbose
source ../../../platforms/sky130hd/setRC.tcl
set_propagated_clock [all_clocks]
@@ -22,10 +22,10 @@ set_thread_count 2
set drc_rpt [make_result_file 5_route_drc.rpt]
set maze_log [make_result_file maze.log]
detailed_route -output_drc $drc_rpt \
- -output_maze $maze_log \
- -bottom_routing_layer met1 \
- -top_routing_layer met5 \
- -verbose 1
+ -output_maze $maze_log \
+ -bottom_routing_layer met1 \
+ -top_routing_layer met5 \
+ -verbose 1
set route_def [make_result_file 5_route.def]
write_def $route_def
puts "Number of DRC Violations = [detailed_route_num_drvs]"
diff --git a/flow/tutorials/scripts/drt/drc_issue.tcl b/flow/tutorials/scripts/drt/drc_issue.tcl
index 0ea32dce63..8ddc41817e 100644
--- a/flow/tutorials/scripts/drt/drc_issue.tcl
+++ b/flow/tutorials/scripts/drt/drc_issue.tcl
@@ -9,8 +9,8 @@ read_sdc ./gcd/gcd.sdc
set_global_routing_layer_adjustment met1-met5 0.5
set_routing_layers -signal met1-met5
global_route -guide_file [make_result_file route.guide] \
- -congestion_iterations 100 \
- -verbose
+ -congestion_iterations 100 \
+ -verbose
source ../../../platforms/sky130hd/setRC.tcl
set_propagated_clock [all_clocks]
@@ -22,10 +22,10 @@ set_thread_count 2
set drc_rpt [make_result_file 5_route_drc.rpt]
set maze_log [make_result_file maze.log]
detailed_route -output_drc $drc_rpt \
- -output_maze $maze_log \
- -bottom_routing_layer met1 \
- -top_routing_layer met5 \
- -verbose 1
+ -output_maze $maze_log \
+ -bottom_routing_layer met1 \
+ -top_routing_layer met5 \
+ -verbose 1
set route_def [make_result_file 5_route.def]
write_def $route_def
puts "Number of DRC Violations = [detailed_route_num_drvs]"
diff --git a/flow/tutorials/scripts/drt/helpers.tcl b/flow/tutorials/scripts/drt/helpers.tcl
index be1af8e7c2..bfb1fe8386 100644
--- a/flow/tutorials/scripts/drt/helpers.tcl
+++ b/flow/tutorials/scripts/drt/helpers.tcl
@@ -14,7 +14,7 @@ proc make_result_file { filename } {
# puts [exec cat $file] without forking.
proc report_file { file } {
set stream [open $file r]
-
+
while { [gets $stream line] >= 0 } {
puts $line
}
@@ -24,9 +24,9 @@ proc report_file { file } {
proc diff_files { file1 file2 } {
set stream1 [open $file1 r]
set stream2 [open $file2 r]
-
+
set line 1
- set diff_line 0;
+ set diff_line 0
while { [gets $stream1 line1] >= 0 && [gets $stream2 line2] >= 0 } {
if { $line1 != $line2 } {
set diff_line $line
diff --git a/flow/tutorials/scripts/gui/load_lef.tcl b/flow/tutorials/scripts/gui/load_lef.tcl
index 259bdb4c03..34d5760cb8 100644
--- a/flow/tutorials/scripts/gui/load_lef.tcl
+++ b/flow/tutorials/scripts/gui/load_lef.tcl
@@ -1,6 +1,6 @@
-proc load_lef_sky130 {} {
- set FLOW_PATH [exec pwd]
- read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
- read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
+proc load_lef_sky130 { } {
+ set FLOW_PATH [exec pwd]
+ read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
+ read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
}
create_toolbar_button -name "Load_LEF" -text "Load_LEF" -script {load_lef_sky130} -echo
diff --git a/flow/util/BUILD.bazel b/flow/util/BUILD.bazel
index 92641ed57b..b8892cbab6 100644
--- a/flow/util/BUILD.bazel
+++ b/flow/util/BUILD.bazel
@@ -25,7 +25,6 @@ MAKEFILE_SHARED = [
filegroup(
name = "makefile",
srcs = glob(MAKEFILE_SHARED + [
- "*.pl",
"*.py",
"*.sh",
]),
@@ -36,7 +35,7 @@ filegroup(
filegroup(
name = "makefile_yosys",
srcs = glob(MAKEFILE_SHARED) + [
- "mergeLib.pl",
+ "merge_lib.py",
"preprocessLib.py",
],
visibility = ["//visibility:public"],
diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl
index 2507dd5fb9..76e02aa17e 100644
--- a/flow/util/cell-veneer/lefdef.tcl
+++ b/flow/util/cell-veneer/lefdef.tcl
@@ -1,18 +1,16 @@
-proc absolute_rectangle {rect offset} {
- return [list \
- [expr [lindex $rect 0] + [lindex $offset 0]] \
- [expr [lindex $rect 1] + [lindex $offset 1]] \
- [expr [lindex $rect 2] + [lindex $offset 0]] \
- [expr [lindex $rect 3] + [lindex $offset 1]] \
- ]
-}
-proc relative_rectangle {rect offset} {
- return [list \
- [expr [lindex $rect 0] - [lindex $offset 0]] \
- [expr [lindex $rect 1] - [lindex $offset 1]] \
- [expr [lindex $rect 2] - [lindex $offset 0]] \
- [expr [lindex $rect 3] - [lindex $offset 1]] \
- ]
+proc absolute_rectangle { rect offset } {
+ return [list \
+ [expr [lindex $rect 0] + [lindex $offset 0]] \
+ [expr [lindex $rect 1] + [lindex $offset 1]] \
+ [expr [lindex $rect 2] + [lindex $offset 0]] \
+ [expr [lindex $rect 3] + [lindex $offset 1]]]
+}
+proc relative_rectangle { rect offset } {
+ return [list \
+ [expr [lindex $rect 0] - [lindex $offset 0]] \
+ [expr [lindex $rect 1] - [lindex $offset 1]] \
+ [expr [lindex $rect 2] - [lindex $offset 0]] \
+ [expr [lindex $rect 3] - [lindex $offset 1]]]
}
if [package vcompare 8.6 $tcl_version] {
@@ -25,919 +23,921 @@ if [package vcompare 8.6 $tcl_version] {
}
namespace eval lef {
- variable lefOut stdout
- variable def_units 2000
-
- proc open {file_name} {
- variable lefOut
- set lefOut [::open $file_name w]
- }
-
- proc close {} {
- variable lefOut
- if {$lefOut != "stdout"} {
- ::close $lefOut
- }
- set lefOut stdout
- }
-
- proc out {args} {
- variable lefOut
-
- if {[llength $args] == 2} {
- puts [lindex $args 0] $lefOut [lindex $args 1]
- } else {
- puts $lefOut [lindex $args 0]
- }
- }
+variable lefOut stdout
+variable def_units 2000
- variable cells
-
- proc get_cells {} {
- variable cells
- return $cells
- }
-
- proc get_cell {cell_name} {
- variable cells
- return [dict get $cells $cell_name]
- }
-
- proc get_width {cell} {
- return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]]
- }
-
- proc get_height {cell} {
- return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]]
- }
-
- proc read_macros {file_name} {
- variable cells
- variable def_units
-
- set ch [::open $file_name]
-
- set cells {}
+proc open { file_name } {
+ variable lefOut
+ set lefOut [::open $file_name w]
+}
- while {![eof $ch]} {
- set line [gets $ch]
+proc close { } {
+ variable lefOut
+ if { $lefOut != "stdout" } {
+ ::close $lefOut
+ }
+ set lefOut stdout
+}
- if {[regexp {MACRO\s*([^\s]*)} $line - cell_name]} {
- dict set cells $cell_name units $def_units
- dict set cells $cell_name name $cell_name
- while {![eof $ch]} {
- set line [gets $ch]
- if {[regexp {^\s*$} $line]} {
- continue
- } elseif {[regexp {CLASS\s+([^\s]*)} $line - cell_class]} {
- dict set cells $cell_name cell_class $cell_class
- } elseif {[regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y]} {
- dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] {expr round($x * $def_units)}]
- } elseif {[regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y]} {
- dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] {expr round($x * $def_units)}]]
- } elseif {[regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height]} {
- dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]]
- } elseif {[regexp {SYMMETRY\s+(.*)\s;} $line - symmetry]} {
- dict set cells $cell_name symmetry $symmetry
- } elseif {[regexp {SITE\s+([^\s]*)} $line - site]} {
- dict set cells $cell_name site $site
- } elseif {[regexp {PIN\s*([^\s]*)} $line - pin_name]} {
- set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}]
- if {[info vars antennamodel] != ""} {
- unset antennamodel
- }
- while {![eof $ch]} {
- set line [gets $ch]
- if {[regexp {^\s*$} $line]} {
- continue
- } elseif {[regexp {DIRECTION\s+([^\s]*)} $line - direction]} {
- dict set cells $cell_name pins $pin_name direction $direction
- } elseif {[regexp {USE\s+([^\s]*)} $line - use]} {
- dict set cells $cell_name pins $pin_name use $use
- } elseif {[regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel]} {
- continue
- } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer]} {
- if {[info vars antennamodel] == ""} {
- set antennamodel "default"
- }
- if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} {
- set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel]
- } else {
- set model {}
- }
- lappend model [list gate_area $gate_area layer $layer]
- dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model
- } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area]} {
- if {[info vars antennamodel] == ""} {
- set antennamodel "default"
- }
- if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} {
- set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel]
- } else {
- set model {}
- }
- lappend model [list gate_area $gate_area]
- dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model
- } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer]} {
- dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea
- dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea
- } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea]} {
- dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea
- } elseif {[regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape]} {
- dict set cells $cell_name pins $pin_name shape $shape
- } elseif {[regexp {PORT} $line]} {
- set port {}
- dict set port orientation N
- while {![eof $ch]} {
- set line [gets $ch]
- if {[regexp {^\s*$} $line]} {
- continue
- } elseif {[regexp {LAYER\s+([^\s]*)} $line - layer]} {
- continue
- } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} {
- if {[dict exists $port layers $layer shapes]} {
- set layer_shapes [dict get $port layers $layer shapes]
- } else {
- set layer_shapes {}
- }
- if {[dict exists $port fixed]} {
- set offset [dict get $port fixed]
- } else {
- set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}]
- dict set port fixed $offset
- }
- set new_shape [list \
- rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \
- mask $mask \
- ]
- lappend layer_shapes $new_shape
- dict set port layers $layer shapes $layer_shapes
- } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} {
- if {[dict exists $port layers $layer shapes]} {
- set layer_shapes [dict get $port layers $layer shapes]
- } else {
- set layer_shapes {}
- }
- if {[dict exists $port fixed]} {
- set offset [dict get $port fixed]
- } else {
- set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}]
- dict set port fixed $offset
- }
- set new_shape [list \
- rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \
- ]
- lappend layer_shapes $new_shape
- dict set port layers $layer shapes $layer_shapes
- } elseif {[regexp {END} $line]} {
- if {[dict exists $cells $cell_name pins $pin_name ports]} {
- set ports [dict get $cells $cell_name pins $pin_name ports]
- } else {
- set ports {}
- }
- lappend ports $port
- dict set cells $cell_name pins $pin_name ports $ports
- break
- } else {
- error "Parsing failure PORT:\n$line"
- }
- }
- } elseif {[regexp "END\\s$pin_pattern" $line]} {
- break
- } else {
- error "Parsing failure PIN:\n$line"
- }
- }
- } elseif {[regexp {OBS} $line]} {
- while {![eof $ch]} {
- set line [gets $ch]
- if {[regexp {^\s*$} $line]} {
- continue
- } elseif {[regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw]} {
- if {$drw != ""} {
- dict set cells $cell_name layers $layer drw $drw
- }
- continue
- } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} {
- if {[dict exists $cells $cell_name obstructions $layer]} {
- set obstructions [dict get $cells $cell_name obstructions $layer]
- } else {
- set obstructions {}
- }
- lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] mask $mask]
- dict set cells $cell_name obstructions $layer $obstructions
- } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} {
- if {[dict exists $cells $cell_name obstructions $layer]} {
- set obstructions [dict get $cells $cell_name obstructions $layer]
- } else {
- set obstructions {}
- }
- lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}]]
- dict set cells $cell_name obstructions $layer $obstructions
- } elseif {[regexp {END} $line]} {
- break
- } else {
- error "Parsing failure OBS:\n$line"
- }
- }
- } elseif {[regexp "END\\s*$cell_name" $line]} {
- break
- } else {
- error "Parsing failure MACRO\n$line"
- }
- }
- }
- }
+proc out { args } {
+ variable lefOut
- ::close $ch
- }
+ if { [llength $args] == 2 } {
+ puts [lindex $args 0] $lefOut [lindex $args 1]
+ } else {
+ puts $lefOut [lindex $args 0]
+ }
+}
- proc get_blockage_layers {design} {
- if {[dict exists $design blockage_layers]} {
- return [dict get $design blockage_layers]
- }
+variable cells
- set blocked_layers {}
+proc get_cells { } {
+ variable cells
+ return $cells
+}
- dict for {layer_name obstructions} [dict get $design obstructions] {
- lappend blocked_layers $layer_name
- }
- return $blocked_layers
- }
+proc get_cell { cell_name } {
+ variable cells
+ return [dict get $cells $cell_name]
+}
- proc write_header {} {
- }
- proc write_footer {} {
- }
- # Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries
- # - cell_class
- # - origin
- # - foreign
- # - ref
- # - origin
- # - die_area
- # - symmetry
- # - site
- # - pins: dict with the name of the pin as the key
- # - antenna_model
- # - gate_area
- # - layer
- # - antennadiffarea
- # - layer
- # - area
- # - direction
- # - use
- # - shape
- # - ports: a list of lists of shapes that make up a physical connection
- # - layer
- # - rect
- # - mask?
- # - obstructions
- # - layer: a dictionaries with layer_name as the key
- # - rect
- # - mask?
- #
- proc write {design} {
- set def_units [dict get $design units]
-
- out "MACRO [dict get $design name]"
- out " CLASS [dict get $design cell_class] ;"
- if {[dict exists $design origin]} {
- out " ORIGIN [dict get $design origin] ;"
- } else {
- out " ORIGIN 0.0 0.0 ;"
- }
- out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;"
- out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;"
- out " SYMMETRY [dict get $design symmetry] ;"
- if {[dict exists $design site]} {
- out " SITE [dict get $design site] ;"
- }
+proc get_width { cell } {
+ return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]]
+}
- if {[dict exists $design pins]} {
- dict for {pin_name pin} [dict get $design pins] {
- out " PIN $pin_name"
- out " DIRECTION [dict get $pin direction] ;"
- if {[dict exists $pin use]} {
- out " USE [dict get $pin use] ;"
- }
- foreach port [dict get $pin ports] {
- out " PORT "
- foreach layer_name [dict keys [dict get $port layers]] {
- set shapes [dict get $port layers $layer_name shapes]
-
- out " LAYER $layer_name ;"
- foreach shape $shapes {
- if {[dict exists $port fixed]} {
- set offset [dict get $port fixed]
- } elseif {[dict exists $port placed]} {
- set offset [dict get $port placed]
- } else {
- set offset [list 0 0]
- }
- set rect [absolute_rectangle [dict get $shape rect] $offset]
-
- if {[dict exists $shape mask]} {
- out " RECT MASK [dict get $shape mask] [lmap x $rect {expr 1.0 * $x / $def_units}] ;"
- } else {
- out " RECT [lmap x $rect {expr 1.0 * $x / $def_units}] ;"
- }
- }
- }
- out " END "
- }
- out " END $pin_name"
- }
- }
+proc get_height { cell } {
+ return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]]
+}
- if {[dict exists $design obstructions]} {
- out " OBS"
- if {[dict get $design use_sheet_obstructions]} {
- dict for {layer_name obstructions} [dict get $design obstructions] {
- lappend blocked_layers $layer_name
+proc read_macros { file_name } {
+ variable cells
+ variable def_units
+
+ set ch [::open $file_name]
+
+ set cells {}
+
+ while { ![eof $ch] } {
+ set line [gets $ch]
+
+ if { [regexp {MACRO\s*([^\s]*)} $line - cell_name] } {
+ dict set cells $cell_name units $def_units
+ dict set cells $cell_name name $cell_name
+ while { ![eof $ch] } {
+ set line [gets $ch]
+ if { [regexp {^\s*$} $line] } {
+ continue
+ } elseif { [regexp {CLASS\s+([^\s]*)} $line - cell_class] } {
+ dict set cells $cell_name cell_class $cell_class
+ } elseif { [regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y] } {
+ dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }]
+ } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } {
+ dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] { expr round($x * $def_units) }]]
+ } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } {
+ dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]]
+ } elseif { [regexp {SYMMETRY\s+(.*)\s;} $line - symmetry] } {
+ dict set cells $cell_name symmetry $symmetry
+ } elseif { [regexp {SITE\s+([^\s]*)} $line - site] } {
+ dict set cells $cell_name site $site
+ } elseif { [regexp {PIN\s*([^\s]*)} $line - pin_name] } {
+ set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}]
+ if { [info vars antennamodel] != "" } {
+ unset antennamodel
+ }
+ while { ![eof $ch] } {
+ set line [gets $ch]
+ if { [regexp {^\s*$} $line] } {
+ continue
+ } elseif { [regexp {DIRECTION\s+([^\s]*)} $line - direction] } {
+ dict set cells $cell_name pins $pin_name direction $direction
+ } elseif { [regexp {USE\s+([^\s]*)} $line - use] } {
+ dict set cells $cell_name pins $pin_name use $use
+ } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } {
+ continue
+ } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer] } {
+ if { [info vars antennamodel] == "" } {
+ set antennamodel "default"
+ }
+ if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } {
+ set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel]
+ } else {
+ set model {}
+ }
+ lappend model [list gate_area $gate_area layer $layer]
+ dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model
+ } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area] } {
+ if { [info vars antennamodel] == "" } {
+ set antennamodel "default"
}
- set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]"
- foreach layer_name [get_blockage_layers $design] {
- if {[dict exists $design layers $layer_name drw]} {
- set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] "
+ if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } {
+ set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel]
+ } else {
+ set model {}
+ }
+ lappend model [list gate_area $gate_area]
+ dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model
+ } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer] } {
+ dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea
+ dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea
+ } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } {
+ dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea
+ } elseif { [regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape] } {
+ dict set cells $cell_name pins $pin_name shape $shape
+ } elseif { [regexp {PORT} $line] } {
+ set port {}
+ dict set port orientation N
+ while { ![eof $ch] } {
+ set line [gets $ch]
+ if { [regexp {^\s*$} $line] } {
+ continue
+ } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } {
+ continue
+ } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } {
+ if { [dict exists $port layers $layer shapes] } {
+ set layer_shapes [dict get $port layers $layer shapes]
+ } else {
+ set layer_shapes {}
+ }
+ if { [dict exists $port fixed] } {
+ set offset [dict get $port fixed]
+ } else {
+ set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }]
+ dict set port fixed $offset
+ }
+ set new_shape [list \
+ rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset] \
+ mask $mask]
+ lappend layer_shapes $new_shape
+ dict set port layers $layer shapes $layer_shapes
+ } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } {
+ if { [dict exists $port layers $layer shapes] } {
+ set layer_shapes [dict get $port layers $layer shapes]
+ } else {
+ set layer_shapes {}
+ }
+ if { [dict exists $port fixed] } {
+ set offset [dict get $port fixed]
+ } else {
+ set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }]
+ dict set port fixed $offset
+ }
+ set new_shape [list \
+ rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset]]
+ lappend layer_shapes $new_shape
+ dict set port layers $layer shapes $layer_shapes
+ } elseif { [regexp {END} $line] } {
+ if { [dict exists $cells $cell_name pins $pin_name ports] } {
+ set ports [dict get $cells $cell_name pins $pin_name ports]
+ } else {
+ set ports {}
+ }
+ lappend ports $port
+ dict set cells $cell_name pins $pin_name ports $ports
+ break
} else {
- set drw ""
+ error "Parsing failure PORT:\n$line"
}
- out " LAYER $layer_name $drw;"
- out " RECT $sheet ;"
}
+ } elseif { [regexp "END\\s$pin_pattern" $line] } {
+ break
} else {
- dict for {layer_name obstructions} [dict get $design obstructions] {
- out " LAYER $layer_name ;"
- foreach obs $obstructions {
- if {[dict exists $obs mask]} {
- out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;"
- } else {
- out " RECT [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;"
- }
- }
+ error "Parsing failure PIN:\n$line"
+ }
+ }
+ } elseif { [regexp {OBS} $line] } {
+ while { ![eof $ch] } {
+ set line [gets $ch]
+ if { [regexp {^\s*$} $line] } {
+ continue
+ } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw] } {
+ if { $drw != "" } {
+ dict set cells $cell_name layers $layer drw $drw
+ }
+ continue
+ } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } {
+ if { [dict exists $cells $cell_name obstructions $layer] } {
+ set obstructions [dict get $cells $cell_name obstructions $layer]
+ } else {
+ set obstructions {}
+ }
+ lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] mask $mask]
+ dict set cells $cell_name obstructions $layer $obstructions
+ } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } {
+ if { [dict exists $cells $cell_name obstructions $layer] } {
+ set obstructions [dict get $cells $cell_name obstructions $layer]
+ } else {
+ set obstructions {}
}
+ lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]]
+ dict set cells $cell_name obstructions $layer $obstructions
+ } elseif { [regexp {END} $line] } {
+ break
+ } else {
+ error "Parsing failure OBS:\n$line"
}
- out " END"
+ }
+ } elseif { [regexp "END\\s*$cell_name" $line] } {
+ break
+ } else {
+ error "Parsing failure MACRO\n$line"
}
- out "END [dict get $design name]"
- out ""
+ }
}
-
- proc write_cells {file_name cells} {
- lef open $file_name
-
- out "###############################################################"
- out "# Created by cell-veneer"
- out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]"
- out "###############################################################"
- out ""
- out "VERSION 5.8 ;"
- out "BUSBITCHARS \"\[\]\" ;"
- out "DIVIDERCHAR \"/\" ;"
- out ""
- out "SITE sc10p5mcpp84_14lpp"
- out " CLASS CORE ;"
- out " SIZE 0.084 BY 0.672 ;"
- out " SYMMETRY Y ;"
- out "END sc10p5mcpp84_14lpp"
- out ""
- out "SITE sc10p5mcpp84_14lpp_pg"
- out " CLASS CORE ;"
- out " SIZE 0.084 BY 1.344 ;"
- out " SYMMETRY Y ;"
- out "END sc10p5mcpp84_14lpp_pg"
- out ""
+ }
- dict for {cell_name cell} $cells {
- lef write $cell
- }
+ ::close $ch
+}
- out "END LIBRARY"
- out ""
- lef close
- }
+proc get_blockage_layers { design } {
+ if { [dict exists $design blockage_layers] } {
+ return [dict get $design blockage_layers]
+ }
- proc write_macros {file_name cells} {
- lef open $file_name
+ set blocked_layers {}
- out "###############################################################"
- out "# Created by cell-veneer"
- out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]"
- out "###############################################################"
- out ""
- out "VERSION 5.8 ;"
- out "BUSBITCHARS \"\[\]\" ;"
- out "DIVIDERCHAR \"/\" ;"
- out ""
+ dict for {layer_name obstructions} [dict get $design obstructions] {
+ lappend blocked_layers $layer_name
+ }
+ return $blocked_layers
+}
- dict for {cell_name cell} $cells {
- lef write $cell
- }
+proc write_header { } {
- out "END LIBRARY"
- out ""
- lef close
- }
+}
+proc write_footer { } {
- namespace export read_macros get_width get_height
- namespace export get_cell get_cells write write_cells write_macros
- namespace export open close out
- namespace ensemble create
}
+# Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries
+# - cell_class
+# - origin
+# - foreign
+# - ref
+# - origin
+# - die_area
+# - symmetry
+# - site
+# - pins: dict with the name of the pin as the key
+# - antenna_model
+# - gate_area
+# - layer
+# - antennadiffarea
+# - layer
+# - area
+# - direction
+# - use
+# - shape
+# - ports: a list of lists of shapes that make up a physical connection
+# - layer
+# - rect
+# - mask?
+# - obstructions
+# - layer: a dictionaries with layer_name as the key
+# - rect
+# - mask?
+#
+proc write { design } {
+ set def_units [dict get $design units]
+
+ out "MACRO [dict get $design name]"
+ out " CLASS [dict get $design cell_class] ;"
+ if { [dict exists $design origin] } {
+ out " ORIGIN [dict get $design origin] ;"
+ } else {
+ out " ORIGIN 0.0 0.0 ;"
+ }
+ out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;"
+ out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;"
+ out " SYMMETRY [dict get $design symmetry] ;"
+ if { [dict exists $design site] } {
+ out " SITE [dict get $design site] ;"
+ }
+
+ if { [dict exists $design pins] } {
+ dict for {pin_name pin} [dict get $design pins] {
+ out " PIN $pin_name"
+ out " DIRECTION [dict get $pin direction] ;"
+ if { [dict exists $pin use] } {
+ out " USE [dict get $pin use] ;"
+ }
+ foreach port [dict get $pin ports] {
+ out " PORT "
+ foreach layer_name [dict keys [dict get $port layers]] {
+ set shapes [dict get $port layers $layer_name shapes]
+
+ out " LAYER $layer_name ;"
+ foreach shape $shapes {
+ if { [dict exists $port fixed] } {
+ set offset [dict get $port fixed]
+ } elseif { [dict exists $port placed] } {
+ set offset [dict get $port placed]
+ } else {
+ set offset [list 0 0]
+ }
+ set rect [absolute_rectangle [dict get $shape rect] $offset]
-namespace eval def {
- variable def_units
- variable defOut stdout
- variable designs {}
-
- proc open {file_name} {
- variable defOut
- set defOut [::open $file_name w]
- }
-
- proc close {} {
- variable defOut
- if {$defOut != "stdout"} {
- ::close $defOut
+ if { [dict exists $shape mask] } {
+ out " RECT MASK [dict get $shape mask] [lmap x $rect { expr 1.0 * $x / $def_units }] ;"
+ } else {
+ out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;"
+ }
+ }
}
- set defOut stdout
+ out " END "
+ }
+ out " END $pin_name"
}
-
- proc out {args} {
- variable defOut
-
- if {[llength $args] == 2} {
- puts [lindex $args 0] $defOut [lindex $args 1]
+ }
+
+ if { [dict exists $design obstructions] } {
+ out " OBS"
+ if { [dict get $design use_sheet_obstructions] } {
+ dict for {layer_name obstructions} [dict get $design obstructions] {
+ lappend blocked_layers $layer_name
+ }
+ set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]"
+ foreach layer_name [get_blockage_layers $design] {
+ if { [dict exists $design layers $layer_name drw] } {
+ set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] "
} else {
- puts $defOut [lindex $args 0]
+ set drw ""
}
+ out " LAYER $layer_name $drw;"
+ out " RECT $sheet ;"
+ }
+ } else {
+ dict for {layer_name obstructions} [dict get $design obstructions] {
+ out " LAYER $layer_name ;"
+ foreach obs $obstructions {
+ if { [dict exists $obs mask] } {
+ out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;"
+ } else {
+ out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;"
+ }
+ }
+ }
}
+ out " END"
+ }
+ out "END [dict get $design name]"
+ out ""
+}
- # Write out DEF from a design structure which is a dictionary with the following keys
- # - name
- # - tool
- # - units
- # - die_area
- # - core_area
- # - rows: dict with the index of the row as the key
- # - site
- # - start
- # - height
- # - orientation
- # - num_sites
- # - site_width
- # - pins: dict with the name of the pin as the key
- # - net_name
- # - direction
- # - use
- # - special
- # - ports : a list of dictionaries, one per port
- # - orientation
- # - (placed|fixed)
- # - layers
- # - spacing
- # - designrulewidth
- # - shapes : list of rectangles (or polygons)
- # - (rect|polygon)
- # - physical_viarules: dict with the name of the viarule as the key
- # - rule
- # - cutsize
- # - layers
- # - cutspacing
- # - enclosure
- # - rowcol
- # - components: dict with the instance name of the component as the key
- # - inst_name
- # - cell_name
- # - (fixed|placed)?
- # - orientation
- # - nets: dict with the name of the net as the key
- # - use: SIGNAL | POWER | GROUND
- # - connections: list of instance pin pairs
- # - routes: list of dictionaries
- # - layer
- # - points: list of points, where a point can be an XY location or the name of a VIA
- # - special_nets: dict with the name of the net as the key
- # - use: SIGNAL | POWER | GROUND
- # - connections: list of instance pin pairs
- # - routes: list of dictioaries
- # - layer
- # - width
- # - shape
- # - points: list of points, where a point can be an XY location or the name of a VIA
- #
-
- proc shift_point {point x y} {
- return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]]
- }
-
- proc shift_rect {rect x y} {
- return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]]
- }
+proc write_cells { file_name cells } {
+ lef open $file_name
+
+ out "###############################################################"
+ out "# Created by cell-veneer"
+ out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]"
+ out "###############################################################"
+ out ""
+ out "VERSION 5.8 ;"
+ out "BUSBITCHARS \"\[\]\" ;"
+ out "DIVIDERCHAR \"/\" ;"
+ out ""
+ out "SITE sc10p5mcpp84_14lpp"
+ out " CLASS CORE ;"
+ out " SIZE 0.084 BY 0.672 ;"
+ out " SYMMETRY Y ;"
+ out "END sc10p5mcpp84_14lpp"
+ out ""
+ out "SITE sc10p5mcpp84_14lpp_pg"
+ out " CLASS CORE ;"
+ out " SIZE 0.084 BY 1.344 ;"
+ out " SYMMETRY Y ;"
+ out "END sc10p5mcpp84_14lpp_pg"
+ out ""
+
+ dict for {cell_name cell} $cells {
+ lef write $cell
+ }
+
+ out "END LIBRARY"
+ out ""
+ lef close
+}
- proc shift_origin {design x y} {
- if {[dict exists $design die_area]} {
- dict set design die_area [shift_rect [dict get $design die_area] $x $y]
- }
- if {[dict exists $design core_area]} {
- dict set design core_area [shift_rect [dict get $design core_area] $x $y]
- }
- if {[dict exists $design rows]} {
- }
- if {[dict exists $design pins]} {
- dict for {pin_name pin} [dict get $design pins] {
- set ports {}
- foreach port [dict get $pin ports] {
- if {[dict exists $port fixed]} {
- dict set port fixed [shift_point [dict get $port fixed] $x $y]
- } elseif {[dict exists $port placed]} {
- dict set port placed [shift_point [dict get $port placed] $x $y]
- }
- lappend ports $port
- }
- dict set design pins $pin_name ports $ports
- }
- }
- if {[dict exists $design components]} {
- dict for {inst_name inst} [dict get $design components] {
- if {[dict exists $inst fixed]} {
- dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y]
- } elseif {[dict exists $inst placed]} {
- dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y]
- }
- }
- }
- if {[dict exists $design nets]} {
- dict for {net_name net} [dict get $design nets] {
- if {[dict exists $net routes]} {
- set routes {}
- foreach route [dict get $net routes] {
- set points {}
- foreach point $points {
- if {[llength $point] == 2} {
- lappend points [shift_point $point $x $y]
- } else {
- lappend points $point
- }
- }
- lappend routes $route
- }
- dict set design nets $net_name routes $routes
- }
- }
- }
- if {[dict exists $design special_nets]} {
- dict for {net_name net} [dict get $design special_nets] {
- set routes {}
- if {[dict exists $net routes]} {
- foreach route [dict get $net routes] {
- set points {}
- foreach point $points {
- if {[llength $point] == 2} {
- lappend points [shift_point $point $x $y]
- } else {
- lappend points $point
- }
- }
- lappend routes $route
- }
- dict set design special_nets $net_name routes $routes
- }
- }
- }
- if {[dict exists $design obstructions]} {
- dict for {layer_name obstructions} [dict get $design obstructions] {
- set new_obs {}
- foreach obs $obstructions {
- dict set obs rect [def::shift_rect [dict get $obs rect] $x $y]
- lappend new_obs $obs
- }
- dict set design obstructions $layer_name $new_obs
- }
- }
+proc write_macros { file_name cells } {
+ lef open $file_name
+
+ out "###############################################################"
+ out "# Created by cell-veneer"
+ out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]"
+ out "###############################################################"
+ out ""
+ out "VERSION 5.8 ;"
+ out "BUSBITCHARS \"\[\]\" ;"
+ out "DIVIDERCHAR \"/\" ;"
+ out ""
+
+ dict for {cell_name cell} $cells {
+ lef write $cell
+ }
+
+ out "END LIBRARY"
+ out ""
+ lef close
+}
- return $design
- }
+namespace export read_macros get_width get_height
+namespace export get_cell get_cells write write_cells write_macros
+namespace export open close out
+namespace ensemble create
+}
- variable layer_info {}
- proc set_layer_info {layer_name key value} {
- variable layer_info
+namespace eval def {
+variable def_units
+variable defOut stdout
+variable designs {}
- dict set layer_info layers $layer_name $key $value
- }
+proc open { file_name } {
+ variable defOut
+ set defOut [::open $file_name w]
+}
- proc get_layer_width {layer_name} {
- variable layer_info
- return [dict get $layer_info layers $layer_name width]
- }
+proc close { } {
+ variable defOut
+ if { $defOut != "stdout" } {
+ ::close $defOut
+ }
+ set defOut stdout
+}
- proc get_layer_non_preferred_width {layer_name} {
- variable layer_info
- if {[dict exists $layer_info layers $layer_name non_preferred_width]} {
- return [dict get $layer_info layers $layer_name non_preferred_width]
- }
- return [dict get $layer_info layers $layer_name width]
- }
+proc out { args } {
+ variable defOut
- proc get_layer_direction {layer_name} {
- variable layer_info
- return [dict get $layer_info layers $layer_name direction]
- }
+ if { [llength $args] == 2 } {
+ puts [lindex $args 0] $defOut [lindex $args 1]
+ } else {
+ puts $defOut [lindex $args 0]
+ }
+}
- proc get_line_direction {points} {
- if {[lindex $points 0 0] == [lindex $points 1 0]} {
- set direction "VERTICAL"
- } elseif {[lindex $points 0 1] == [lindex $points 1 1]} {
- set direction "HORIZONTAL"
- } else {
- error "Non orthogonal line $points"
+# Write out DEF from a design structure which is a dictionary with the following keys
+# - name
+# - tool
+# - units
+# - die_area
+# - core_area
+# - rows: dict with the index of the row as the key
+# - site
+# - start
+# - height
+# - orientation
+# - num_sites
+# - site_width
+# - pins: dict with the name of the pin as the key
+# - net_name
+# - direction
+# - use
+# - special
+# - ports : a list of dictionaries, one per port
+# - orientation
+# - (placed|fixed)
+# - layers
+# - spacing
+# - designrulewidth
+# - shapes : list of rectangles (or polygons)
+# - (rect|polygon)
+# - physical_viarules: dict with the name of the viarule as the key
+# - rule
+# - cutsize
+# - layers
+# - cutspacing
+# - enclosure
+# - rowcol
+# - components: dict with the instance name of the component as the key
+# - inst_name
+# - cell_name
+# - (fixed|placed)?
+# - orientation
+# - nets: dict with the name of the net as the key
+# - use: SIGNAL | POWER | GROUND
+# - connections: list of instance pin pairs
+# - routes: list of dictionaries
+# - layer
+# - points: list of points, where a point can be an XY location or the name of a VIA
+# - special_nets: dict with the name of the net as the key
+# - use: SIGNAL | POWER | GROUND
+# - connections: list of instance pin pairs
+# - routes: list of dictioaries
+# - layer
+# - width
+# - shape
+# - points: list of points, where a point can be an XY location or the name of a VIA
+#
+
+proc shift_point { point x y } {
+ return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]]
+}
+
+proc shift_rect { rect x y } {
+ return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]]
+}
+
+proc shift_origin { design x y } {
+ if { [dict exists $design die_area] } {
+ dict set design die_area [shift_rect [dict get $design die_area] $x $y]
+ }
+ if { [dict exists $design core_area] } {
+ dict set design core_area [shift_rect [dict get $design core_area] $x $y]
+ }
+ if { [dict exists $design rows] } {
+
+ }
+ if { [dict exists $design pins] } {
+ dict for {pin_name pin} [dict get $design pins] {
+ set ports {}
+ foreach port [dict get $pin ports] {
+ if { [dict exists $port fixed] } {
+ dict set port fixed [shift_point [dict get $port fixed] $x $y]
+ } elseif { [dict exists $port placed] } {
+ dict set port placed [shift_point [dict get $port placed] $x $y]
+ }
+ lappend ports $port
+ }
+ dict set design pins $pin_name ports $ports
+ }
+ }
+ if { [dict exists $design components] } {
+ dict for {inst_name inst} [dict get $design components] {
+ if { [dict exists $inst fixed] } {
+ dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y]
+ } elseif { [dict exists $inst placed] } {
+ dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y]
+ }
+ }
+ }
+ if { [dict exists $design nets] } {
+ dict for {net_name net} [dict get $design nets] {
+ if { [dict exists $net routes] } {
+ set routes {}
+ foreach route [dict get $net routes] {
+ set points {}
+ foreach point $points {
+ if { [llength $point] == 2 } {
+ lappend points [shift_point $point $x $y]
+ } else {
+ lappend points $point
+ }
+ }
+ lappend routes $route
}
- return $direction
+ dict set design nets $net_name routes $routes
+ }
}
- proc get_line_width {layer_name points} {
- set direction [get_line_direction $points]
-
- if {[get_layer_direction $layer_name] == $direction} {
- return [get_layer_width $layer_name]
- } else {
- return [get_layer_non_preferred_width $layer_name]
+ }
+ if { [dict exists $design special_nets] } {
+ dict for {net_name net} [dict get $design special_nets] {
+ set routes {}
+ if { [dict exists $net routes] } {
+ foreach route [dict get $net routes] {
+ set points {}
+ foreach point $points {
+ if { [llength $point] == 2 } {
+ lappend points [shift_point $point $x $y]
+ } else {
+ lappend points $point
+ }
+ }
+ lappend routes $route
}
+ dict set design special_nets $net_name routes $routes
+ }
+ }
+ }
+ if { [dict exists $design obstructions] } {
+ dict for {layer_name obstructions} [dict get $design obstructions] {
+ set new_obs {}
+ foreach obs $obstructions {
+ dict set obs rect [def::shift_rect [dict get $obs rect] $x $y]
+ lappend new_obs $obs
+ }
+ dict set design obstructions $layer_name $new_obs
}
+ }
- proc get_extended_line {layer_name points} {
- if {[llength [lindex $points 1]] == 1} {
- return "( [lindex $points 0] ) [lindex $points 1]"
- }
+ return $design
+}
- set direction [get_line_direction $points]
+variable layer_info {}
+proc set_layer_info { layer_name key value } {
+ variable layer_info
- if {$direction == [get_layer_direction $layer_name]} {
- set extension [expr [get_layer_non_preferred_width $layer_name] / 2]
- } else {
- set extension [expr [get_layer_width $layer_name] / 2]
- }
+ dict set layer_info layers $layer_name $key $value
+}
- if {$direction == "VERTICAL"} {
- set x_min [lindex $points 0 0]
- set x_max [lindex $points 0 0]
- set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension]
- set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension]
- } else {
- set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])]
- set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])]
- set y_min [lindex $points 0 1]
- set y_max [lindex $points 0 1]
- }
+proc get_layer_width { layer_name } {
+ variable layer_info
+ return [dict get $layer_info layers $layer_name width]
+}
- return "( $x_min $y_min ) ( $x_max $y_max )"
- }
+proc get_layer_non_preferred_width { layer_name } {
+ variable layer_info
+ if { [dict exists $layer_info layers $layer_name non_preferred_width] } {
+ return [dict get $layer_info layers $layer_name non_preferred_width]
+ }
+ return [dict get $layer_info layers $layer_name width]
+}
- proc write {design} {
- out "###############################################################"
- if {[dict exists $design tool]} {
- out "# Created by [dict get $design tool]"
- }
- out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]"
- out "###############################################################"
-
- out "VERSION 5.8 ;"
- out "DIVIDERCHAR \"/\" ;"
- out "BUSBITCHARS \"\[\]\" ;"
- out "DESIGN [dict get $design name] ;"
- out "UNITS DISTANCE MICRONS [dict get $design units] ;"
- out ""
+proc get_layer_direction { layer_name } {
+ variable layer_info
+ return [dict get $layer_info layers $layer_name direction]
+}
- if {[dict exists $design properties]} {
- out "PROPERTYDEFINITIONS "
- if {[dict exists $design properties core_area]} {
- out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;"
- out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;"
- out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;"
- out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;"
- }
- out "END PROPERTYDEFINITIONS"
- }
+proc get_line_direction { points } {
+ if { [lindex $points 0 0] == [lindex $points 1 0] } {
+ set direction "VERTICAL"
+ } elseif { [lindex $points 0 1] == [lindex $points 1 1] } {
+ set direction "HORIZONTAL"
+ } else {
+ error "Non orthogonal line $points"
+ }
+ return $direction
+}
+proc get_line_width { layer_name points } {
+ set direction [get_line_direction $points]
+
+ if { [get_layer_direction $layer_name] == $direction } {
+ return [get_layer_width $layer_name]
+ } else {
+ return [get_layer_non_preferred_width $layer_name]
+ }
+}
- out ""
- out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;"
+proc get_extended_line { layer_name points } {
+ if { [llength [lindex $points 1]] == 1 } {
+ return "( [lindex $points 0] ) [lindex $points 1]"
+ }
+
+ set direction [get_line_direction $points]
+
+ if { $direction == [get_layer_direction $layer_name] } {
+ set extension [expr [get_layer_non_preferred_width $layer_name] / 2]
+ } else {
+ set extension [expr [get_layer_width $layer_name] / 2]
+ }
+
+ if { $direction == "VERTICAL" } {
+ set x_min [lindex $points 0 0]
+ set x_max [lindex $points 0 0]
+ set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension]
+ set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension]
+ } else {
+ set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])]
+ set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])]
+ set y_min [lindex $points 0 1]
+ set y_max [lindex $points 0 1]
+ }
+
+ return "( $x_min $y_min ) ( $x_max $y_max )"
+}
- if {[dict exists $design tracks]} {
- }
-
- if {[dict exists $design rows]} {
- foreach idx [lsort -integer [dict keys $design rows]] {
- out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]"
- out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;"
+proc write { design } {
+ out "###############################################################"
+ if { [dict exists $design tool] } {
+ out "# Created by [dict get $design tool]"
+ }
+ out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]"
+ out "###############################################################"
+
+ out "VERSION 5.8 ;"
+ out "DIVIDERCHAR \"/\" ;"
+ out "BUSBITCHARS \"\[\]\" ;"
+ out "DESIGN [dict get $design name] ;"
+ out "UNITS DISTANCE MICRONS [dict get $design units] ;"
+ out ""
+
+ if { [dict exists $design properties] } {
+ out "PROPERTYDEFINITIONS "
+ if { [dict exists $design properties core_area] } {
+ out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;"
+ out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;"
+ out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;"
+ out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;"
+ }
+ out "END PROPERTYDEFINITIONS"
+ }
+
+ out ""
+ out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;"
+
+ if { [dict exists $design tracks] } {
+
+ }
+
+ if { [dict exists $design rows] } {
+ foreach idx [lsort -integer [dict keys $design rows]] {
+ out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]"
+ out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;"
+ }
+ }
+
+ if { [dict exists $design pins] } {
+ out ""
+ out "PINS [dict size [dict get $design pins]] ;"
+ dict for {pin_name pin} [dict get $design pins] {
+ out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] "
+ if { [dict exists $pin use] } {
+ out -nonewline "+ USE [dict get $pin use] "
+ }
+ if { [dict exists $pin special] } {
+ out -nonewline "+ SPECIAL "
+ }
+ out ""
+ if { [dict exists $pin ports] } {
+ foreach port [dict get $pin ports] {
+ if { [llength [dict get $design pins $pin_name ports]] > 1 } {
+ out " + PORT "
+ }
+ dict for {layer_name layer_info} [dict get $port layers] {
+ foreach shape [dict get $port layers $layer_name shapes] {
+ out -nonewline " + LAYER $layer_name "
+ if { [dict exists $port layers $layer_name spacing] } {
+ out "SPACING [dict get $port layers $layer_name spacing] "
+ } elseif { [dict exists $port layers $layer_name designrulewidth] } {
+ out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] "
+ }
+ out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) "
}
- }
-
- if {[dict exists $design pins]} {
- out ""
- out "PINS [dict size [dict get $design pins]] ;"
- dict for {pin_name pin} [dict get $design pins] {
- out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] "
- if {[dict exists $pin use]} {
- out -nonewline "+ USE [dict get $pin use] "
- }
- if {[dict exists $pin special]} {
- out -nonewline "+ SPECIAL "
- }
- out ""
- if {[dict exists $pin ports]} {
- foreach port [dict get $pin ports] {
- if {[llength [dict get $design pins $pin_name ports]] > 1} {
- out " + PORT "
- }
- dict for {layer_name layer_info} [dict get $port layers] {
- foreach shape [dict get $port layers $layer_name shapes] {
- out -nonewline " + LAYER $layer_name "
- if {[dict exists $port layers $layer_name spacing]} {
- out "SPACING [dict get $port layers $layer_name spacing] "
- } elseif {[dict exists $port layers $layer_name designrulewidth]} {
- out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] "
- }
- out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) "
- }
- }
- if {[dict exists $port fixed]} {
- out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] "
- } elseif {[dict exists $shape placed]} {
- out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] "
- }
- }
- out " ;"
- }
+ }
+ if { [dict exists $port fixed] } {
+ out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] "
+ } elseif { [dict exists $shape placed] } {
+ out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] "
+ }
+ }
+ out " ;"
+ }
+ }
+ out "END PINS"
+ }
+
+ ##### Generating via rules
+
+ if { [dict exists $design physical_viarules] } {
+ out ""
+ out "VIAS [dict size [dict get $design physical_viarules]] ;"
+ dict for {name rule} [dict get $design physical_viarules] {
+ out "- $name"
+ out " + VIARULE [dict get $rule rule]"
+ out " + CUTSIZE [dict get $rule cutsize]"
+ out " + LAYERS [dict get $rule layers]"
+ out " + CUTSPACING [dict get $rule cutspacing]"
+ out " + ENCLOSURE [dict get $rule enclosure]"
+ out " + ROWCOL [dict get $rule rowcol]"
+ out " ;"
+ }
+ out "END VIAS"
+ }
+
+ if { [dict exists $design components] } {
+ out ""
+ out "COMPONENTS [dict size [dict get $design components]] ;"
+ dict for {inst_name inst} [dict get $design components] {
+ out -nonewline "- $inst_name [dict get $inst cell_name] "
+ if { [dict exists $inst fixed] } {
+ out -nonewline "+ FIXED ( [dict get $inst fixed] ) "
+ } elseif { [dict exists $inst placed] } {
+ out -nonewline "+ PLACED ( [dict get $inst placed] ) "
+ }
+ if { [dict exists $inst orientation] } {
+ out -nonewline "[dict get $inst orientation] "
+ }
+ out ";"
+ }
+ out "END COMPONENTS"
+ }
+
+ if { [dict exists $design nets] } {
+ out ""
+ out "SPECIALNETS [dict size [dict get $design nets]] ;"
+ dict for {net_name net} [dict get $design nets] {
+ out -nonewline "- $net_name "
+ foreach connection [dict get $net connections] {
+ out " ( $connection )"
+ }
+ if { [dict exists $net routes] } {
+ set type "ROUTED"
+ foreach route [dict get $net routes] {
+ set first_point [lindex [dict get $route points] 0]
+
+ foreach point [lrange [dict get $route points] 1 end] {
+ set points [get_extended_line [dict get $route layer] [list $first_point $point]]
+ if { [dict exists $route shape] } {
+ set shape " + SHAPE [dict get $route shape] "
+ } else {
+ set shape ""
}
- out "END PINS"
- }
-
- ##### Generating via rules
-
- if {[dict exists $design physical_viarules]} {
- out ""
- out "VIAS [dict size [dict get $design physical_viarules]] ;"
- dict for {name rule} [dict get $design physical_viarules] {
- out "- $name"
- out " + VIARULE [dict get $rule rule]"
- out " + CUTSIZE [dict get $rule cutsize]"
- out " + LAYERS [dict get $rule layers]"
- out " + CUTSPACING [dict get $rule cutspacing]"
- out " + ENCLOSURE [dict get $rule enclosure]"
- out " + ROWCOL [dict get $rule rowcol]"
- out " ;"
+ if { [dict exists $route mask] } {
+ set mask "MASK [dict get $route mask] "
+ } else {
+ set mask ""
}
- out "END VIAS"
- }
-
- if {[dict exists $design components]} {
- out ""
- out "COMPONENTS [dict size [dict get $design components]] ;"
- dict for {inst_name inst} [dict get $design components] {
- out -nonewline "- $inst_name [dict get $inst cell_name] "
- if {[dict exists $inst fixed]} {
- out -nonewline "+ FIXED ( [dict get $inst fixed] ) "
- } elseif {[dict exists $inst placed]} {
- out -nonewline "+ PLACED ( [dict get $inst placed] ) "
- }
- if {[dict exists $inst orientation]} {
- out -nonewline "[dict get $inst orientation] "
- }
- out ";"
+ if { [llength $point] == 2 } {
+ out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] "
+ out -nonewline $shape
+ out -nonewline $points
+ out -nonewline $mask
+ } else {
+ out -nonewline " + $type [dict get $route layer] 0 "
+ out -nonewline $shape
+ out -nonewline $points
+ out -nonewline $mask
}
- out "END COMPONENTS"
- }
-
- if {[dict exists $design nets]} {
out ""
- out "SPECIALNETS [dict size [dict get $design nets]] ;"
- dict for {net_name net} [dict get $design nets] {
- out -nonewline "- $net_name "
- foreach connection [dict get $net connections] {
- out " ( $connection )"
- }
- if {[dict exists $net routes]} {
- set type "ROUTED"
- foreach route [dict get $net routes] {
- set first_point [lindex [dict get $route points] 0]
-
- foreach point [lrange [dict get $route points] 1 end] {
- set points [get_extended_line [dict get $route layer] [list $first_point $point]]
- if {[dict exists $route shape]} {
- set shape " + SHAPE [dict get $route shape] "
- } else {
- set shape ""
- }
- if {[dict exists $route mask]} {
- set mask "MASK [dict get $route mask] "
- } else {
- set mask ""
- }
- if {[llength $point] == 2} {
- out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] "
- out -nonewline $shape
- out -nonewline $points
- out -nonewline $mask
- } else {
- out -nonewline " + $type [dict get $route layer] 0 "
- out -nonewline $shape
- out -nonewline $points
- out -nonewline $mask
- }
- out ""
- set first_point $point
- set type "ROUTED"
- }
- }
- }
- out " + USE [dict get $net use]\n ;"
- }
- out "END SPECIALNETS"
+ set first_point $point
+ set type "ROUTED"
+ }
}
-
- if {[dict exists $design special_nets]} {
- out ""
- out "SPECIALNETS [dict size [dict get $design special_nets]] ;"
- dict for {net_name net} [dict get $design special_nets] {
- out -nonewline "- $net_name "
- foreach connection [dict get $net connections] {
- out " ( $connection )"
- }
- if {[dict exists $net routes]} {
- set route [lindex [dict get $net routes] 0]
- out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] "
- foreach point [dict get $route points] {
- out -nonewline " $point"
- }
- out ""
-
- foreach route [lrange [dict get $net routes] 1 end] {
- out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] "
- foreach point [dict get $route points] {
- out -nonewline " $point"
- }
- out ""
- }
- }
- out " + USE [dict get $net use]\n ;"
- }
- out "\nEND SPECIALNETS"
+ }
+ out " + USE [dict get $net use]\n ;"
+ }
+ out "END SPECIALNETS"
+ }
+
+ if { [dict exists $design special_nets] } {
+ out ""
+ out "SPECIALNETS [dict size [dict get $design special_nets]] ;"
+ dict for {net_name net} [dict get $design special_nets] {
+ out -nonewline "- $net_name "
+ foreach connection [dict get $net connections] {
+ out " ( $connection )"
+ }
+ if { [dict exists $net routes] } {
+ set route [lindex [dict get $net routes] 0]
+ out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] "
+ foreach point [dict get $route points] {
+ out -nonewline " $point"
}
-
out ""
- out "END DESIGN"
+
+ foreach route [lrange [dict get $net routes] 1 end] {
+ out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] "
+ foreach point [dict get $route points] {
+ out -nonewline " $point"
+ }
+ out ""
+ }
+ }
+ out " + USE [dict get $net use]\n ;"
}
+ out "\nEND SPECIALNETS"
+ }
- proc new_design {design_name units {die_area {0 0 0 0}}} {
- variable designs
- variable current_design
- set current_design $design_name
+ out ""
+ out "END DESIGN"
+}
- dict set designs $current_design [list name $design_name units $units die_area $die_area]
- }
+proc new_design { design_name units { die_area {0 0 0 0} } } {
+ variable designs
+ variable current_design
+ set current_design $design_name
- proc add_component {inst_name cell_name x y orientation status} {
- variable designs
- variable current_design
+ dict set designs $current_design [list name $design_name units $units die_area $die_area]
+}
- dict set designs $current_design components $inst_name inst_name $inst_name
- dict set designs $current_design components $inst_name cell_name $cell_name
- dict set designs $current_design components $inst_name $status [list $x $y]
- dict set designs $current_design components $inst_name orientation $orientation
- }
-
- proc get_current_design {} {
- variable designs
- variable current_design
+proc add_component { inst_name cell_name x y orientation status } {
+ variable designs
+ variable current_design
- return [dict get $designs $current_design]
- }
-
- proc write_cells {cells} {
- dict for {cell_name cell} $cells {
- def open ${cell_name}.def
- def write $cell
- def close
- }
- }
-
- proc set_def_units {units} {
- variable def_units
-
- set def_units $units
- }
-
- proc get_def_units {} {
- variable def_units
-
- return $def_units
- }
-
- namespace export new_design add_component get_current_design
- namespace export set_def_units get_def_units shift_origin shift_rect
- namespace export open close out write write_cells
- namespace export set_layer_info
- namespace ensemble create
+ dict set designs $current_design components $inst_name inst_name $inst_name
+ dict set designs $current_design components $inst_name cell_name $cell_name
+ dict set designs $current_design components $inst_name $status [list $x $y]
+ dict set designs $current_design components $inst_name orientation $orientation
+}
+
+proc get_current_design { } {
+ variable designs
+ variable current_design
+
+ return [dict get $designs $current_design]
+}
+
+proc write_cells { cells } {
+ dict for {cell_name cell} $cells {
+ def open ${cell_name}.def
+ def write $cell
+ def close
+ }
+}
+
+proc set_def_units { units } {
+ variable def_units
+
+ set def_units $units
+}
+
+proc get_def_units { } {
+ variable def_units
+
+ return $def_units
+}
+
+namespace export new_design add_component get_current_design
+namespace export set_def_units get_def_units shift_origin shift_rect
+namespace export open close out write write_cells
+namespace export set_layer_info
+namespace ensemble create
}
package provide lefdef 1.0.0
diff --git a/flow/util/cell-veneer/pkgIndex.tcl b/flow/util/cell-veneer/pkgIndex.tcl
index 806a34f75f..b739cc635c 100644
--- a/flow/util/cell-veneer/pkgIndex.tcl
+++ b/flow/util/cell-veneer/pkgIndex.tcl
@@ -1,3 +1,2 @@
-package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]]
+package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]]
package ifneeded wrapper 1.0.0 [list source [file join $dir wrap_stdcells.tcl]]
-
diff --git a/flow/util/cell-veneer/wrap.tcl b/flow/util/cell-veneer/wrap.tcl
index 3ca893b8fd..8fa52113ab 100755
--- a/flow/util/cell-veneer/wrap.tcl
+++ b/flow/util/cell-veneer/wrap.tcl
@@ -5,7 +5,7 @@ exec tclsh "$0" ${1+"$@"}
package require wrapper
package require lefdef
-if {[set idx [lsearch -exact $argv {-cfg}]] > -1} {
+if { [set idx [lsearch -exact $argv {-cfg}]] > -1 } {
set cfg_file [lindex $argv [expr $idx + 1]]
set argv [lreplace $argv $idx [expr $idx + 1]]
@@ -15,7 +15,7 @@ if {[set idx [lsearch -exact $argv {-cfg}]] > -1} {
wrapper critical 2 "no configuration data loaded"
}
-if {[lindex $argv 0] == "-macro"} {
+if { [lindex $argv 0] == "-macro" } {
set lef_files [lrange $argv 1 end]
set cells {}
foreach file_name $lef_files {
diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl
index f6abb4a674..96b2612cfa 100644
--- a/flow/util/cell-veneer/wrap_stdcells.tcl
+++ b/flow/util/cell-veneer/wrap_stdcells.tcl
@@ -1,701 +1,683 @@
namespace eval wrapper {
- variable wrapper_cfg
-
- proc set_message {level message} {
- return "\[$level\] $message"
- }
+variable wrapper_cfg
- proc debug {message} {
- set state [info frame -1]
- set str ""
- if {[dict exists $state file]} {
- set str "$str[dict get $state file]:"
- }
- if {[dict exists $state proc]} {
- set str "$str[dict get $state proc]:"
- }
- if {[dict exists $state line]} {
- set str "$str[dict get $state line]"
- }
- puts [set_message DEBUG "$str: $message"]
- }
+proc set_message { level message } {
+ return "\[$level\] $message"
+}
- proc information {id message} {
- puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]]
+proc debug { message } {
+ set state [info frame -1]
+ set str ""
+ if { [dict exists $state file] } {
+ set str "$str[dict get $state file]:"
}
-
- proc warning {id message} {
- puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]]
+ if { [dict exists $state proc] } {
+ set str "$str[dict get $state proc]:"
}
-
- proc err {id message} {
- puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]]
+ if { [dict exists $state line] } {
+ set str "$str[dict get $state line]"
}
+ puts [set_message DEBUG "$str: $message"]
+}
- proc critical {id message} {
- error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]]
- }
+proc information { id message } {
+ puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]]
+}
+
+proc warning { id message } {
+ puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]]
+}
+
+proc err { id message } {
+ puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]]
+}
+
+proc critical { id message } {
+ error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]]
+}
+
+proc find_cells_with_m2_pins { } {
+ set cells [lef get_cells]
+ set data {}
+
+ dict for {cell_name cell} $cells {
+ dict for {pin_name pin} [dict get $cell pins] {
+ foreach port [dict get $pin ports] {
+ set offset [wrapper::get_port_offset $port]
+ set layer_name "M2"
+ if { [dict exists $port layers $layer_name] } {
+ foreach shape [dict get $port layers $layer_name shapes] {
+ set rect [absolute_rectangle [dict get $shape rect] $offset]
+ set x1 [lindex $rect 0]
+ set y1 [lindex $rect 1]
+ set x2 [lindex $rect 2]
+ set y2 [lindex $rect 3]
- proc find_cells_with_m2_pins {} {
- set cells [lef get_cells]
- set data {}
-
- dict for {cell_name cell} $cells {
- dict for {pin_name pin} [dict get $cell pins] {
- foreach port [dict get $pin ports] {
- set offset [wrapper::get_port_offset $port]
- set layer_name "M2"
- if {[dict exists $port layers $layer_name]} {
- foreach shape [dict get $port layers $layer_name shapes] {
-
- set rect [absolute_rectangle [dict get $shape rect] $offset]
- set x1 [lindex $rect 0]
- set y1 [lindex $rect 1]
- set x2 [lindex $rect 2]
- set y2 [lindex $rect 3]
-
- if {[dict exists $data $cell_name pins $pin_name]} {
- set pins [dict get $data $cell_name pins $pin_name]
- } else {
- set pins {}
- }
- if {round($y2 - $y1) > 64} {
- error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1"
- }
- lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2]
- dict set data $cell_name pins $pin_name $pins
+ if { [dict exists $data $cell_name pins $pin_name] } {
+ set pins [dict get $data $cell_name pins $pin_name]
+ } else {
+ set pins {}
+ }
+ if { round($y2 - $y1) > 64 } {
+ error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1"
}
+ lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2]
+ dict set data $cell_name pins $pin_name $pins
}
}
}
+ }
- if {[dict exists $data $cell_name]} {
- dict for {layer_name obstructions} [dict get $cell obstructions] {
- if {$layer_name == "M2"} {
- foreach obs $obstructions {
- set rect [dict get $obs rect]
- set x1 [lindex $rect 0]
- set y1 [lindex $rect 1]
- set x2 [lindex $rect 2]
- set y2 [lindex $rect 3]
-
- if {round(($y2 - $y1)) > 64} {
- error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1"
- }
- if {[dict exists $data $cell_name blockages]} {
- set blockages [dict get $data $cell_name blockages]
- } else {
- set blockages {}
- }
-
- lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2]
- dict set data $cell_name blockages $blockages
+ if { [dict exists $data $cell_name] } {
+ dict for {layer_name obstructions} [dict get $cell obstructions] {
+ if { $layer_name == "M2" } {
+ foreach obs $obstructions {
+ set rect [dict get $obs rect]
+ set x1 [lindex $rect 0]
+ set y1 [lindex $rect 1]
+ set x2 [lindex $rect 2]
+ set y2 [lindex $rect 3]
+
+ if { round(($y2 - $y1)) > 64 } {
+ error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1"
+ }
+ if { [dict exists $data $cell_name blockages] } {
+ set blockages [dict get $data $cell_name blockages]
+ } else {
+ set blockages {}
}
+
+ lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2]
+ dict set data $cell_name blockages $blockages
}
}
}
}
-
- return $data
}
- proc clear_left {physical_pin blockages} {
- set track [dict get $physical_pin track]
+ return $data
+}
- foreach blockage $blockages {
- if {[dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from]} {
- return 0
- }
+proc clear_left { physical_pin blockages } {
+ set track [dict get $physical_pin track]
+
+ foreach blockage $blockages {
+ if { [dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from] } {
+ return 0
}
- return 1
}
+ return 1
+}
- proc clear_right {physical_pin blockages} {
- set track [dict get $physical_pin track]
+proc clear_right { physical_pin blockages } {
+ set track [dict get $physical_pin track]
- foreach blockage $blockages {
- if {[dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to]} {
- return 0
- }
+ foreach blockage $blockages {
+ if { [dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to] } {
+ return 0
}
- return 1
}
+ return 1
+}
- proc create_def_wrapper {cell_name new_cell_name} {
- variable tech
- set orig_cell [lef get_cell $cell_name]
-
- set design $orig_cell
-
- dict set design name $new_cell_name
- dict set design tool "cell-veneer"
- dict set design units 2000
- dict set design use_sheet_obstructions 0
- if {[dict exists $tech use_sheet_obstructions]} {
- dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions]
- }
- if {[dict exists $tech blockage_layers]} {
- dict set design blockage_layers [dict get $tech blockage_layers]
- }
- dict set design die_area [dict get $orig_cell die_area]
-
- dict set design components u0 cell_name $cell_name
- dict set design components u0 placed "0 0"
- dict set design components u0 orientation "N"
-
- dict for {pin_name pin} [dict get $orig_cell pins] {
-
- dict set design pins $pin_name net_name $pin_name
- if {[dict exists $pin use]} {
- if {[dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND"} {
- dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"]
- dict set design special_nets $pin_name use [dict get $pin use]
- } else {
- dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"]
- dict set design nets $pin_name use [dict get $pin use]
- }
+proc create_def_wrapper { cell_name new_cell_name } {
+ variable tech
+ set orig_cell [lef get_cell $cell_name]
+
+ set design $orig_cell
+
+ dict set design name $new_cell_name
+ dict set design tool "cell-veneer"
+ dict set design units 2000
+ dict set design use_sheet_obstructions 0
+ if { [dict exists $tech use_sheet_obstructions] } {
+ dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions]
+ }
+ if { [dict exists $tech blockage_layers] } {
+ dict set design blockage_layers [dict get $tech blockage_layers]
+ }
+ dict set design die_area [dict get $orig_cell die_area]
+
+ dict set design components u0 cell_name $cell_name
+ dict set design components u0 placed "0 0"
+ dict set design components u0 orientation "N"
+
+ dict for {pin_name pin} [dict get $orig_cell pins] {
+ dict set design pins $pin_name net_name $pin_name
+ if { [dict exists $pin use] } {
+ if { [dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND" } {
+ dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"]
+ dict set design special_nets $pin_name use [dict get $pin use]
} else {
dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"]
+ dict set design nets $pin_name use [dict get $pin use]
}
+ } else {
+ dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"]
}
-
- return $design
}
-
- proc get_port_offset {port} {
- if {[dict exists $port fixed]} {
- return [dict get $port fixed]
- } elseif {[dict exists $port placed]} {
- return [dict get $port fixed]
- }
- return [list 0 0]
+ return $design
+}
+
+proc get_port_offset { port } {
+ if { [dict exists $port fixed] } {
+ return [dict get $port fixed]
+ } elseif { [dict exists $port placed] } {
+ return [dict get $port fixed]
}
- proc move_m2_pins_to_edge {cell_name cell_data} {
- variable wrapper_cfg
-
- set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]]
- set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2]
- set def_units [dict get $wrapper_cfg def_units]
- set layer_name [dict get $wrapper_cfg remove_pins layer]
- set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)]
- set new_pin_layer_name [dict get $wrapper_cfg new_pins layer]
- set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)]
- set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2]
- set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod]
- set lower_y [expr 2 * 128]
- set upper_y [expr 8 * 128]
- set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)]
-
- set right_padding 0
- set left_padding 0
-
- # Determine which sides to route the M2 pins to and create a wire
- dict for {pin_name pin} [dict get $cell_data pins] {
- set wires {}
- foreach physical_pin $pin {
- if {[dict get $physical_pin to] >= [expr $cell_width / 2.0]} {
- if {[dict exists $cell_data blockages]} {
- if {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} {
- set direction right
- } elseif {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} {
- set direction left
- } else {
- set direction blocked
- }
- } else {
+ return [list 0 0]
+}
+
+proc move_m2_pins_to_edge { cell_name cell_data } {
+ variable wrapper_cfg
+
+ set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]]
+ set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2]
+ set def_units [dict get $wrapper_cfg def_units]
+ set layer_name [dict get $wrapper_cfg remove_pins layer]
+ set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)]
+ set new_pin_layer_name [dict get $wrapper_cfg new_pins layer]
+ set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)]
+ set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2]
+ set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod]
+ set lower_y [expr 2 * 128]
+ set upper_y [expr 8 * 128]
+ set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)]
+
+ set right_padding 0
+ set left_padding 0
+
+ # Determine which sides to route the M2 pins to and create a wire
+ dict for {pin_name pin} [dict get $cell_data pins] {
+ set wires {}
+ foreach physical_pin $pin {
+ if { [dict get $physical_pin to] >= [expr $cell_width / 2.0] } {
+ if { [dict exists $cell_data blockages] } {
+ if { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } {
set direction right
+ } elseif { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } {
+ set direction left
+ } else {
+ set direction blocked
}
} else {
- if {[dict exists $cell_data blockages]} {
- if {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} {
- set direction left
- } elseif {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} {
- set direction right
- } else {
- set direction blocked
- }
- } else {
+ set direction right
+ }
+ } else {
+ if { [dict exists $cell_data blockages] } {
+ if { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } {
set direction left
+ } elseif { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } {
+ set direction right
+ } else {
+ set direction blocked
}
- }
-
- if {$direction == "blocked"} {
- break
- }
-
- set y [expr [dict get $physical_pin track] * 128]
- if {$direction == "right"} {
- set x1 [dict get $physical_pin to]
- set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))]
- set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap]
- incr right_padding
- } elseif {$direction == "left"} {
- set x1 [dict get $physical_pin from]
- set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))]
- set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap]
- incr left_padding
- }
-
- # Route M2 out to the side of the block
- lappend wires [list \
- layer $layer_name \
- points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]]
- ]
- set new_wire [list \
- layer "M1" \
- points [list [list $x2 $lower_y] [list $x2 $upper_y]] \
- ]
- if {[dict exists $wrapper_cfg new_pins mask]} {
- dict set new_wire mask [dict get $wrapper_cfg new_pins mask]
- }
- lappend wires $new_wire
- # Add the new M2 wire as an obstruction when writing the LEF of the cell
- if {[dict exists $design obstructions $layer_name]} {
- set obstructions [dict get $design obstructions $layer_name]
} else {
- set obstructions {}
+ set direction left
}
- lappend obstructions [list \
- rect [list \
- [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \
- [expr max($x1, $x3)] [expr $y + round($layer_width / 2)] \
- ]
- ]
- dict set design obstructions $layer_name $obstructions
+ }
+ if { $direction == "blocked" } {
break
}
- if {$direction == "blocked"} {
- break
+ set y [expr [dict get $physical_pin track] * 128]
+ if { $direction == "right" } {
+ set x1 [dict get $physical_pin to]
+ set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))]
+ set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap]
+ incr right_padding
+ } elseif { $direction == "left" } {
+ set x1 [dict get $physical_pin from]
+ set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))]
+ set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap]
+ incr left_padding
}
- set ports {}
- foreach port [dict get $design pins $pin_name ports] {
- if {[dict exists $port layers "M2"]} {
- set offset [get_port_offset $port]
- # Copy all M2 pins on instance to M2 obstructions
- foreach shape [dict get $port layers "M2" shapes] {
- set pin_rect [absolute_rectangle [dict get $shape rect] $offset]
-
- set m2_obstructions [dict get $design obstructions M2]
- lappend m2_obstructions [list \
- rect $pin_rect \
- ]
- dict set design obstructions M2 $m2_obstructions
- }
- # Replace the M2 port with an M1 port which is now at the side of the cells
- set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y]
- if {[dict exists $port layers "M1" shapes]} {
- set shapes [dict get $port layers "M1" shapes]
- } else {
- set shapes {}
- }
- set new_shape [list \
- rect [relative_rectangle $new_pin_rect $offset] \
- ]
- if {[dict exists $wrapper_cfg new_pins mask]} {
- dict set new_shape mask [dict get $wrapper_cfg new_pins mask]
- }
- lappend shapes $new_shape
- dict set port layers M1 shapes $shapes
- }
- dict set port layers [dict remove [dict get $port layers] "M2"]
- lappend ports $port
+ # Route M2 out to the side of the block
+ lappend wires [list \
+ layer $layer_name \
+ points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]]]
+ set new_wire [list \
+ layer "M1" \
+ points [list [list $x2 $lower_y] [list $x2 $upper_y]]]
+ if { [dict exists $wrapper_cfg new_pins mask] } {
+ dict set new_wire mask [dict get $wrapper_cfg new_pins mask]
+ }
+ lappend wires $new_wire
+ # Add the new M2 wire as an obstruction when writing the LEF of the cell
+ if { [dict exists $design obstructions $layer_name] } {
+ set obstructions [dict get $design obstructions $layer_name]
+ } else {
+ set obstructions {}
}
- dict set design pins $pin_name ports $ports
- dict set design nets $pin_name routes $wires
+ lappend obstructions [list \
+ rect [list \
+ [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \
+ [expr max($x1, $x3)] [expr $y + round($layer_width / 2)]]]
+ dict set design obstructions $layer_name $obstructions
+
+ break
}
- # Adjust the placement of the component if we have padding on the left
- if {$left_padding > 0} {
- dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0]
+ if { $direction == "blocked" } {
+ break
}
- # Add in the cell padding
- set pad_idx 0
- if {$left_padding > 0} {
- for {set i 0} {$i <= $left_padding} {incr i} {
- set x [expr $padding_cell_width * ($i + 1) * -1]
- set y 0
- dict set design components p$pad_idx inst_name p$pad_idx
- dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell]
- dict set design components p$pad_idx placed [list $x $y]
- dict set design components p$pad_idx orientation N
-
- # Add all obstructions of padding cell to obstructions of wrapper
- dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] {
- if {[dict exists $design obstructions $layer_name]} {
- set current_obstructions [dict get $design obstructions $layer_name]
- } else {
- set current_obstructions {}
- }
- foreach obs $obstructions {
- dict set obs rect [def shift_rect [dict get $obs rect] $x $y]
- lappend current_obstructions $obs
- }
- dict set design obstructions $layer_name $current_obstructions
+ set ports {}
+ foreach port [dict get $design pins $pin_name ports] {
+ if { [dict exists $port layers "M2"] } {
+ set offset [get_port_offset $port]
+ # Copy all M2 pins on instance to M2 obstructions
+ foreach shape [dict get $port layers "M2" shapes] {
+ set pin_rect [absolute_rectangle [dict get $shape rect] $offset]
+
+ set m2_obstructions [dict get $design obstructions M2]
+ lappend m2_obstructions [list \
+ rect $pin_rect]
+ dict set design obstructions M2 $m2_obstructions
}
- incr pad_idx
+ # Replace the M2 port with an M1 port which is now at the side of the cells
+ set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y]
+ if { [dict exists $port layers "M1" shapes] } {
+ set shapes [dict get $port layers "M1" shapes]
+ } else {
+ set shapes {}
+ }
+ set new_shape [list \
+ rect [relative_rectangle $new_pin_rect $offset]]
+ if { [dict exists $wrapper_cfg new_pins mask] } {
+ dict set new_shape mask [dict get $wrapper_cfg new_pins mask]
+ }
+ lappend shapes $new_shape
+ dict set port layers M1 shapes $shapes
}
- } else {
- set left_padding -1
+ dict set port layers [dict remove [dict get $port layers] "M2"]
+ lappend ports $port
}
- if {$right_padding > 0} {
- for {set i 0} {$i <= $right_padding} {incr i} {
- set x [expr $padding_cell_width * $i + $cell_width]
- set y 0
- dict set design components p$pad_idx inst_name p$pad_idx
- dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell]
- dict set design components p$pad_idx placed [list $x $y]
- dict set design components p$pad_idx orientation N
-
- # Add all obstructions of padding cell to obstructions of wrapper
- dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] {
- if {[dict exists $design obstructions $layer_name]} {
- set current_obstructions [dict get $design obstructions $layer_name]
- } else {
- set current_obstructions {}
- }
- foreach obs $obstructions {
- dict set obs rect [def shift_rect [dict get $obs rect] $x $y]
- lappend current_obstructions $obs
- }
- dict set design obstructions $layer_name $current_obstructions
+ dict set design pins $pin_name ports $ports
+ dict set design nets $pin_name routes $wires
+ }
+
+ # Adjust the placement of the component if we have padding on the left
+ if { $left_padding > 0 } {
+ dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0]
+ }
+
+ # Add in the cell padding
+ set pad_idx 0
+ if { $left_padding > 0 } {
+ for { set i 0 } { $i <= $left_padding } { incr i } {
+ set x [expr $padding_cell_width * ($i + 1) * -1]
+ set y 0
+ dict set design components p$pad_idx inst_name p$pad_idx
+ dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell]
+ dict set design components p$pad_idx placed [list $x $y]
+ dict set design components p$pad_idx orientation N
+
+ # Add all obstructions of padding cell to obstructions of wrapper
+ dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] {
+ if { [dict exists $design obstructions $layer_name] } {
+ set current_obstructions [dict get $design obstructions $layer_name]
+ } else {
+ set current_obstructions {}
+ }
+ foreach obs $obstructions {
+ dict set obs rect [def shift_rect [dict get $obs rect] $x $y]
+ lappend current_obstructions $obs
}
- incr pad_idx
+ dict set design obstructions $layer_name $current_obstructions
}
+ incr pad_idx
}
+ } else {
+ set left_padding -1
+ }
+ if { $right_padding > 0 } {
+ for { set i 0 } { $i <= $right_padding } { incr i } {
+ set x [expr $padding_cell_width * $i + $cell_width]
+ set y 0
+ dict set design components p$pad_idx inst_name p$pad_idx
+ dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell]
+ dict set design components p$pad_idx placed [list $x $y]
+ dict set design components p$pad_idx orientation N
+
+ # Add all obstructions of padding cell to obstructions of wrapper
+ dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] {
+ if { [dict exists $design obstructions $layer_name] } {
+ set current_obstructions [dict get $design obstructions $layer_name]
+ } else {
+ set current_obstructions {}
+ }
+ foreach obs $obstructions {
+ dict set obs rect [def shift_rect [dict get $obs rect] $x $y]
+ lappend current_obstructions $obs
+ }
+ dict set design obstructions $layer_name $current_obstructions
+ }
+ incr pad_idx
+ }
+ }
- # Adjust origin so that 0,0 is the lowr left corner of the cell
- set adjustment [expr $padding_cell_width * ($left_padding + 1)]
- set design [def shift_origin $design $adjustment 0]
-
- dict set design die_area [list \
- 0 \
- 0 \
- [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \
- [lindex [dict get $design die_area] 3] \
- ]
-
- # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper
- # VDD overlaps by 0.009 on each side
- # VSS overlaps by 0.009 on each side
- # VNW overlaps the edges of the cell by 0.1 on both sides
- set extend_ports {
+ # Adjust origin so that 0,0 is the lowr left corner of the cell
+ set adjustment [expr $padding_cell_width * ($left_padding + 1)]
+ set design [def shift_origin $design $adjustment 0]
+
+ dict set design die_area [list \
+ 0 \
+ 0 \
+ [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \
+ [lindex [dict get $design die_area] 3]]
+
+ # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper
+ # VDD overlaps by 0.009 on each side
+ # VSS overlaps by 0.009 on each side
+ # VNW overlaps the edges of the cell by 0.1 on both sides
+ set extend_ports {
VDD {layer M1 overlap 0.009}
VSS {layer M1 overlap 0.009}
VNW {layer NW overlap 0.1}
VPW {layer SXCUT overlap 0}
}
- dict for {pin_name info} $extend_ports {
- set layer [dict get $info layer]
- set overlap [dict get $info overlap]
-
- set ports {}
- foreach port [dict get $design pins $pin_name ports] {
- if {[dict exists $port layers $layer]} {
- set shapes {}
- set offset [get_port_offset $port]
-
- foreach shape [dict get $port layers $layer shapes] {
- set rect [absolute_rectangle [dict get $shape rect] $offset]
- dict set shape rect [relative_rectangle \
- [list \
- [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \
- [lindex $rect 1] \
- [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \
- [lindex $rect 3] \
- ] \
- $offset \
- ]
- lappend shapes $shape
- }
- dict set port layers $layer shapes $shapes
+ dict for {pin_name info} $extend_ports {
+ set layer [dict get $info layer]
+ set overlap [dict get $info overlap]
+
+ set ports {}
+ foreach port [dict get $design pins $pin_name ports] {
+ if { [dict exists $port layers $layer] } {
+ set shapes {}
+ set offset [get_port_offset $port]
+
+ foreach shape [dict get $port layers $layer shapes] {
+ set rect [absolute_rectangle [dict get $shape rect] $offset]
+ dict set shape rect [relative_rectangle \
+ [list \
+ [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \
+ [lindex $rect 1] \
+ [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \
+ [lindex $rect 3]] \
+ $offset]
+ lappend shapes $shape
}
- lappend ports $port
+ dict set port layers $layer shapes $shapes
}
- dict set design pins $pin_name ports $ports
+ lappend ports $port
}
-
- return $design
+ dict set design pins $pin_name ports $ports
}
- proc build_wrappers {data} {
- variable wrapper_cfg
-
- set designs {}
+ return $design
+}
- dict for {cell_name cell_data} $data {
- set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg]
- dict set designs [dict get $data name] $data
- }
+proc build_wrappers { data } {
+ variable wrapper_cfg
- return $designs
- }
+ set designs {}
- proc get_pin_rect {port layer} {
- if {[dict exists $port fixed]} {
- set offset [dict get $port fixed]
- } elseif {[dict exists $port placed]} {
- set offset [dict get $port placed]
- } else {
- set offset [list 0 0]
- }
-
- return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset]
+ dict for {cell_name cell_data} $data {
+ set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg]
+ dict set designs [dict get $data name] $data
}
-
- proc wrap_macro {cell_name} {
- variable tech
- set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod]
- debug "$tech"
- debug "[dict get $wrapper use_sheet_obstructions]"
-
- set cell [lef get_cell $cell_name]
- # debug "$cell_name"
-
- # Order the signal pins based on the y location of the pin
- set pin_info {}
- set net_info {}
- set grid_pins {}
- dict for {pin_name pin} [dict get $cell pins] {
- if {[dict get $pin use] != "SIGNAL"} {continue}
-
- # CHEAT: Assume that there is only one port for each pin and one rectangle per layer
- set port [lindex [dict get $pin ports] 0]
- if {[dict exists $port layers C4]} {
- set pin_rect [get_pin_rect $port C4]
- dict set net_info $pin_name pin_layer "C4"
- } elseif {[dict exists $port layers M3]} {
- set pin_rect [get_pin_rect $port M3]
- dict set net_info $pin_name pin_layer "M3"
- }
+ return $designs
+}
- set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2]
- set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))]
+proc get_pin_rect { port layer } {
+ if { [dict exists $port fixed] } {
+ set offset [dict get $port fixed]
+ } elseif { [dict exists $port placed] } {
+ set offset [dict get $port placed]
+ } else {
+ set offset [list 0 0]
+ }
- # Need to check that the grid point we're trying to use is going to be accessible.
- # If it is not, then try the point 2 grid points higher
- if {[dict exists $grid_pins $grid_y]} {
- if {[dict exists [expr $grid_y + 2]]} {
- puts "Cell $cell_name"
- puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]"
- exit -1
- }
- set grid_y [expr $grid_y + 2]
- }
- dict set grid_pins $grid_y $pin_name
+ return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset]
+}
- dict set net_info $pin_name grid_y $grid_y
- dict set net_info $pin_name macro_pin_y $macro_pin_y
+proc wrap_macro { cell_name } {
+ variable tech
+ set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod]
+ debug "$tech"
+ debug "[dict get $wrapper use_sheet_obstructions]"
+
+ set cell [lef get_cell $cell_name]
+ # debug "$cell_name"
+
+ # Order the signal pins based on the y location of the pin
+ set pin_info {}
+ set net_info {}
+ set grid_pins {}
+
+ dict for {pin_name pin} [dict get $cell pins] {
+ if { [dict get $pin use] != "SIGNAL" } { continue }
+
+ # CHEAT: Assume that there is only one port for each pin and one rectangle per layer
+ set port [lindex [dict get $pin ports] 0]
+ if { [dict exists $port layers C4] } {
+ set pin_rect [get_pin_rect $port C4]
+ dict set net_info $pin_name pin_layer "C4"
+ } elseif { [dict exists $port layers M3] } {
+ set pin_rect [get_pin_rect $port M3]
+ dict set net_info $pin_name pin_layer "M3"
}
- set order [lsort -integer [dict keys $grid_pins]]
- set prev_pos [lindex $order 0]
+ set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2]
+ set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))]
- # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro
- # If there is another pin close by, the we will need to have the jog 3 grids further in
- dict set net_info [dict get $grid_pins $prev_pos] h_offset 3
- foreach pin_pos [lrange $order 1 end] {
- if {$pin_pos - $prev_pos > 3} {
- dict set net_info [dict get $grid_pins $pin_pos] h_offset 3
- } else {
- dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3]
+ # Need to check that the grid point we're trying to use is going to be accessible.
+ # If it is not, then try the point 2 grid points higher
+ if { [dict exists $grid_pins $grid_y] } {
+ if { [dict exists [expr $grid_y + 2]] } {
+ puts "Cell $cell_name"
+ puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]"
+ exit -1
}
- set prev_pos $pin_pos
+ set grid_y [expr $grid_y + 2]
}
+ dict set grid_pins $grid_y $pin_name
- # Work out where to place the instance based on the size of amount of jogging space needed
- set wrapper_depth 0
- dict for {net_name net} [dict get $net_info] {
- if {$wrapper_depth < [dict get $net h_offset]} {
- set wrapper_depth [dict get $net h_offset]
- }
+ dict set net_info $pin_name grid_y $grid_y
+ dict set net_info $pin_name macro_pin_y $macro_pin_y
+ }
+
+ set order [lsort -integer [dict keys $grid_pins]]
+ set prev_pos [lindex $order 0]
+
+ # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro
+ # If there is another pin close by, the we will need to have the jog 3 grids further in
+ dict set net_info [dict get $grid_pins $prev_pos] h_offset 3
+ foreach pin_pos [lrange $order 1 end] {
+ if { $pin_pos - $prev_pos > 3 } {
+ dict set net_info [dict get $grid_pins $pin_pos] h_offset 3
+ } else {
+ dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3]
}
- set wrapper_depth [expr $wrapper_depth + 3]
- set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]]
- set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )]
- set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])]
-
- # Now we know where the macro is placed, we know the size of the wrapper
- dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height]
- # debug "Set die area [dict get $wrapper die_area]"
- # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM
-
- # Shift the wrapper so the lower left corner is at (0, 0)
- set wrapper [def shift_origin $wrapper $macro_x 0]
- # debug "Shifted die area [dict get $wrapper die_area]"
-
- # Add obstructions
- foreach obs_layer {M3 J3 C4} {
- set obstructions {}
- if {[dict exists $wrapper obstructions $obs_layer]} {
- set obstructions [dict get $wrapper obstructions $obs_layer]
- }
- # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]"
- lappend obstructions [list rect [list 0 0 $macro_x $height]]
- # debug "[lindex $obstructions 0]"
- dict set wrapper obstructions $obs_layer $obstructions
- # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]"
+ set prev_pos $pin_pos
+ }
+
+ # Work out where to place the instance based on the size of amount of jogging space needed
+ set wrapper_depth 0
+ dict for {net_name net} [dict get $net_info] {
+ if { $wrapper_depth < [dict get $net h_offset] } {
+ set wrapper_depth [dict get $net h_offset]
}
-
-
- # Add wrapper pins and nets
- dict for {net_name net} [dict get $net_info] {
- set grid_y [dict get $net grid_y]
- set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]]
-
- set new_port [lindex [dict get $wrapper pins $net_name ports] 0]
- dict set new_port layers {}
- dict set new_port fixed [list 0 $y_position]
- dict set new_port layers "C4" shapes [list \
- [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]] \
- ]
- # debug "Replacing pin $net_name with $new_port"
- dict set wrapper pins $net_name ports [list $new_port]
-
- set segments {}
-
- # First segment from RAM to jog location, to the y grid of the pin
- set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]]
- set width [dict get $tech layer [dict get $net pin_layer] width]
+ }
+ set wrapper_depth [expr $wrapper_depth + 3]
+ set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]]
+ set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )]
+ set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])]
+
+ # Now we know where the macro is placed, we know the size of the wrapper
+ dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height]
+ # debug "Set die area [dict get $wrapper die_area]"
+ # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM
+
+ # Shift the wrapper so the lower left corner is at (0, 0)
+ set wrapper [def shift_origin $wrapper $macro_x 0]
+ # debug "Shifted die area [dict get $wrapper die_area]"
+
+ # Add obstructions
+ foreach obs_layer {M3 J3 C4} {
+ set obstructions {}
+ if { [dict exists $wrapper obstructions $obs_layer] } {
+ set obstructions [dict get $wrapper obstructions $obs_layer]
+ }
+ # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]"
+ lappend obstructions [list rect [list 0 0 $macro_x $height]]
+ # debug "[lindex $obstructions 0]"
+ dict set wrapper obstructions $obs_layer $obstructions
+ # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]"
+ }
+
+
+ # Add wrapper pins and nets
+ dict for {net_name net} [dict get $net_info] {
+ set grid_y [dict get $net grid_y]
+ set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]]
+
+ set new_port [lindex [dict get $wrapper pins $net_name ports] 0]
+ dict set new_port layers {}
+ dict set new_port fixed [list 0 $y_position]
+ dict set new_port layers "C4" shapes [list \
+ [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]]]
+ # debug "Replacing pin $net_name with $new_port"
+ dict set wrapper pins $net_name ports [list $new_port]
+
+ set segments {}
+
+ # First segment from RAM to jog location, to the y grid of the pin
+ set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]]
+ set width [dict get $tech layer [dict get $net pin_layer] width]
+ lappend segments [list \
+ layer [dict get $net pin_layer] \
+ points [list \
+ "$macro_x [dict get $net macro_pin_y]" \
+ "$target_grid_point [dict get $net macro_pin_y]" \
+ "$target_grid_point $y_position"]]
+ if { [dict get $net pin_layer] != "C4" } {
lappend segments [list \
layer [dict get $net pin_layer] \
- points [list \
- "$macro_x [dict get $net macro_pin_y]" \
- "$target_grid_point [dict get $net macro_pin_y]" \
- "$target_grid_point $y_position" \
- ]
- ]
- if {[dict get $net pin_layer] != "C4"} {
- lappend segments [list \
- layer [dict get $net pin_layer] \
- points [list \
- "$target_grid_point $y_position" \
- [dict get $tech via] \
- ] \
- ]
- }
- lappend segments [list \
- layer C4 \
points [list \
"$target_grid_point $y_position" \
- "0 $y_position" \
- ] \
- ]
-
- dict set wrapper nets $net_name routes $segments
+ [dict get $tech via]]]
}
+ lappend segments [list \
+ layer C4 \
+ points [list \
+ "$target_grid_point $y_position" \
+ "0 $y_position"]]
- return $wrapper
+ dict set wrapper nets $net_name routes $segments
}
- proc test_harness {wrappers} {
- variable wrapper_cfg
-
- set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]]
- set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]]
- set idx 0
- set num_cells [dict size $wrappers]
- set num_grids [expr round(sqrt($num_cells)) + 1]
- set max_cell_width 0
- dict for {cell_name cell} $wrappers {
- set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])]
- }
- set grid_x_size [expr $max_cell_width + (2 * $site_width)]
- set grid_y_size [expr 4 * $site_height]
+ return $wrapper
+}
- def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]]
+proc test_harness { wrappers } {
+ variable wrapper_cfg
- foreach cell [dict keys $wrappers] {
- set x [expr round(($idx % $num_grids) * $grid_x_size)]
- set y [expr round(round($idx / $num_grids) * $grid_y_size)]
+ set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]]
+ set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]]
+ set idx 0
+ set num_cells [dict size $wrappers]
+ set num_grids [expr round(sqrt($num_cells)) + 1]
+ set max_cell_width 0
+ dict for {cell_name cell} $wrappers {
+ set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])]
+ }
+ set grid_x_size [expr $max_cell_width + (2 * $site_width)]
+ set grid_y_size [expr 4 * $site_height]
- set orig_cell [regsub {_mod} $cell {}]
- def add_component "w_$idx" $cell $x $y N placed
- def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed
+ def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]]
- incr idx
- }
+ foreach cell [dict keys $wrappers] {
+ set x [expr round(($idx % $num_grids) * $grid_x_size)]
+ set y [expr round(round($idx / $num_grids) * $grid_y_size)]
- def open test_harness.def
- def write [set design [def get_current_design]]
- def close
+ set orig_cell [regsub {_mod} $cell {}]
+ def add_component "w_$idx" $cell $x $y N placed
+ def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed
- return $design
+ incr idx
}
- proc set_stdcell_config {config} {
- variable wrapper_cfg
- set wrapper_cfg $config
- }
+ def open test_harness.def
+ def write [set design [def get_current_design]]
+ def close
- proc run {} {
- set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef
+ return $design
+}
- lef read_macros $file_name
- set data [wrapper find_cells_with_m2_pins]
+proc set_stdcell_config { config } {
+ variable wrapper_cfg
+ set wrapper_cfg $config
+}
- set wrappers [wrapper build_wrappers $data]
+proc run { } {
+ set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef
- lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers
- def write_cells $wrappers
- }
+ lef read_macros $file_name
+ set data [wrapper find_cells_with_m2_pins]
- proc convert_tech_to_def_units {tech} {
- set def_units [dict get $tech units]
- dict for {layer_name layer} [dict get $tech layer] {
- foreach property {depth width non_preferred_width} {
- if {[dict exists $layer $property]} {
- dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)]
- }
+ set wrappers [wrapper build_wrappers $data]
+
+ lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers
+ def write_cells $wrappers
+}
+
+proc convert_tech_to_def_units { tech } {
+ set def_units [dict get $tech units]
+ dict for {layer_name layer} [dict get $tech layer] {
+ foreach property {depth width non_preferred_width} {
+ if { [dict exists $layer $property] } {
+ dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)]
}
}
-
- foreach layer_name [dict keys [dict get $tech layer]] {
- foreach property {direction width non_preferred_width} {
- if {[dict exists $tech layer $layer_name $property]} {
- def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property]
- }
+ }
+
+ foreach layer_name [dict keys [dict get $tech layer]] {
+ foreach property {direction width non_preferred_width} {
+ if { [dict exists $tech layer $layer_name $property] } {
+ def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property]
}
}
+ }
- dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)]
- dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)]
+ dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)]
+ dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)]
- return $tech
- }
+ return $tech
+}
- proc set_macro_config {lef_tech} {
- variable tech
-
- set tech [convert_tech_to_def_units $lef_tech]
- }
-
- proc macro {lef_file} {
- lef read_macros $lef_file
- set cells {}
-
- foreach cell_name [dict keys [lef get_cells]] {
+proc set_macro_config { lef_tech } {
+ variable tech
+
+ set tech [convert_tech_to_def_units $lef_tech]
+}
+
+proc macro { lef_file } {
+ lef read_macros $lef_file
+ set cells {}
+
+ foreach cell_name [dict keys [lef get_cells]] {
# debug "$cell_name"
- set designs [list ${cell_name}_mod [wrap_macro $cell_name]]
- lef write_macros ${cell_name}_mod.lef $designs
- def write_cells $designs
- lappend cells $cell_name
- }
-
- return $cells
+ set designs [list ${cell_name}_mod [wrap_macro $cell_name]]
+ lef write_macros ${cell_name}_mod.lef $designs
+ def write_cells $designs
+ lappend cells $cell_name
}
- namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config
- namespace export information warning err critical
- namespace export build_wrappers
- namespace export test_harness
- namespace ensemble create
+ return $cells
+}
+
+namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config
+namespace export information warning err critical
+namespace export build_wrappers
+namespace export test_harness
+namespace ensemble create
}
package provide wrapper 1.0.0
diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py
index fab6256e2a..0b5ebee993 100755
--- a/flow/util/genMetrics.py
+++ b/flow/util/genMetrics.py
@@ -13,7 +13,6 @@
import argparse
import json
-import pandas as pd
import re
from glob import glob
@@ -346,10 +345,6 @@ def extract_metrics(
else:
metrics_dict["total_time"] = str(total)
- metrics_df = pd.DataFrame(list(metrics_dict.items()))
- col_index = metrics_df.iloc[0][1] + "__" + metrics_df.iloc[1][1]
- metrics_df.columns = ["Metrics", col_index]
-
if hier_json:
# Convert the Metrics dictionary to hierarchical format by stripping
# the stage as a 'key'
@@ -363,13 +358,11 @@ def extract_metrics(
with open(output, "w") as resultSpecfile:
json.dump(metrics_dict, resultSpecfile, indent=2, sort_keys=True)
- return metrics_dict, metrics_df
-
args = parse_args()
now = datetime.now()
-metrics_dict, metrics_df = extract_metrics(
+extract_metrics(
os.path.join(os.path.dirname(os.path.realpath(__file__)), "../"),
args.platform,
args.design,
diff --git a/flow/util/mergeLib.pl b/flow/util/mergeLib.pl
deleted file mode 100755
index 146a75febf..0000000000
--- a/flow/util/mergeLib.pl
+++ /dev/null
@@ -1,61 +0,0 @@
-#!/usr/bin/env perl
-
-# This script is sourced from Brown (with slight modifications). It merges
-# several timing libraries into one.
-# ------------------------------------------------------------------------------
-
-use strict;
-use warnings;
-
-my $sclname = $ARGV[0];
-shift @ARGV;
-my $cnt = @ARGV;
-
-if($cnt>0){
- process_header($ARGV[0]);
- my $file;
- foreach my $file (@ARGV) {
- process_cells($file)
- }
- print "\n}\n";
-} else {
- print "use: mergeLib.pl new_library_name lib1 lib2 lib3 ....";
-}
-
-
-sub process_header {
- my $filename = shift;
- open(my $fh, '<', $filename) or die "Could not open file $filename $!";
- while (<$fh>) {
- if(/library\s*\(/) {
- print "library ($sclname) {\n";
- next;
- }
- last if(/^[\t\s]*cell\s*\(/);
- print $_;
- }
- close($fh)
-}
-
-sub process_cells {
- my $filename = shift;
-
- open(my $fh, '<', $filename) or die "Could not open file $filename $!";
-
- my $flag = 0;
- # cut the cells
- while (<$fh>) {
- #chomp $_;
- if(/^[\t\s]*cell\s*\(/) {#&& $flag==0){
- die "Error! new cell before finishing the previous one!\n" if($flag!=0);
- print "\n$_";
- $flag=1;
- } elsif($flag > 0){
- $flag++ if(/\{/);
- $flag-- if(/\}/);
- #print "...}\n" if($flag==0);
- print "$_";
- }
- }
- close($fh)
-}
diff --git a/flow/util/merge_lib.py b/flow/util/merge_lib.py
new file mode 100755
index 0000000000..961b5e2330
--- /dev/null
+++ b/flow/util/merge_lib.py
@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+
+import re
+import sys
+
+
+def process_header(filename, sclname):
+ with open(filename, "r") as fh:
+ for line in fh:
+ if re.search(r"library\s*\(", line):
+ print(f"library ({sclname}) {{")
+ continue
+ if re.match(r"^[\t ]*cell\s*\(", line):
+ break
+ print(line, end="")
+
+
+def process_cells(filename):
+ with open(filename, "r") as fh:
+ flag = 0 # brace depth
+ for line in fh:
+ # Match 'cell ( ... )' with optional whitespace
+ if re.match(r"^[\t ]*cell\s*\(", line):
+ if flag != 0:
+ raise RuntimeError(
+ "Error! new cell before finishing the previous one!"
+ )
+ print() # print blank line like Perl
+ print(line, end="")
+ flag = 1 # entering a cell block
+ elif flag > 0:
+ # Increase/decrease brace depth
+ flag += line.count("{")
+ flag -= line.count("}")
+ print(line, end="")
+
+ # Optionally: reset flag to 0 here if it's finished
+ # But not necessary unless you're adding post-processing
+
+
+def main():
+ if len(sys.argv) < 3:
+ print("use: mergeLib.py new_library_name lib1 lib2 lib3 ....")
+ sys.exit(1)
+
+ sclname = sys.argv[1]
+ files = sys.argv[2:]
+
+ process_header(files[0], sclname)
+ for file in files:
+ process_cells(file)
+ print("\n}")
+
+
+if __name__ == "__main__":
+ main()
diff --git a/flow/util/requirements_lock.txt b/flow/util/requirements_lock.txt
index 17d4824261..e6aa58ad02 100644
--- a/flow/util/requirements_lock.txt
+++ b/flow/util/requirements_lock.txt
@@ -1,5 +1,5 @@
#
-# This file is autogenerated by pip-compile with Python 3.12
+# This file is autogenerated by pip-compile with Python 3.13
# by the following command:
#
# bazel run //flow/util:requirements.update
diff --git a/flow/util/utils.mk b/flow/util/utils.mk
index c7a5a79621..84f10aa11a 100644
--- a/flow/util/utils.mk
+++ b/flow/util/utils.mk
@@ -5,9 +5,9 @@ metadata: finish metadata-generate metadata-check
.PHONY: metadata-generate
metadata-generate:
- @mkdir -p $(REPORTS_DIR)
- @echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt
- $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \
+ mkdir -p $(REPORTS_DIR)
+ echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt
+ $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \
-p $(PLATFORM) \
-v $(FLOW_VARIANT) \
--logs $(LOG_DIR) \
@@ -20,7 +20,7 @@ export RULES_JSON ?= $(DESIGN_DIR)/rules-$(FLOW_VARIANT).json
.PHONY: metadata-check
metadata-check:
- @$(UTILS_DIR)/checkMetadata.py \
+ $(PYTHON_EXE) $(UTILS_DIR)/checkMetadata.py \
-m $(REPORTS_DIR)/metadata.json \
-r $(RULES_JSON) 2>&1 \
| tee $(abspath $(REPORTS_DIR)/metadata-check.log)
@@ -40,8 +40,8 @@ update_metadata:
.PHONY: do-update_rules
do-update_rules:
- @mkdir -p $(REPORTS_DIR)
- $(UTILS_DIR)/genRuleFile.py \
+ mkdir -p $(REPORTS_DIR)
+ $(PYTHON_EXE) $(UTILS_DIR)/genRuleFile.py \
--rules $(RULES_JSON) \
--new-rules $(REPORTS_DIR)/rules.json \
--reference $(REPORTS_DIR)/metadata.json \
@@ -59,7 +59,7 @@ update_rules: do-update_rules do-copy_update_rules
.PHONY: do-update_rules_force
do-update_rules_force:
- @mkdir -p $(REPORTS_DIR)
+ mkdir -p $(REPORTS_DIR)
$(UTILS_DIR)/genRuleFile.py \
--rules $(RULES_JSON) \
--new-rules $(REPORTS_DIR)/rules.json \
@@ -74,7 +74,7 @@ update_rules_force: do-update_rules_force
.PHONY: update_metadata_autotuner
update_metadata_autotuner:
- @$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \
+ $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \
-p $(PLATFORM) \
-v $(FLOW_VARIANT) \
--logs $(LOG_DIR) \
@@ -93,7 +93,7 @@ $(RESULTS_DIR)/6_net_rc.csv:
.PHONY: correlate_rc
correlate_rc: $(RESULTS_DIR)/6_net_rc.csv
- $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv
+ $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv
# TODO Make always wants to redo designs with this rule, regardless of which variations are tried.
# $(MAKE) DESIGN_CONFIG=$$config write_net_rc; \
@@ -104,7 +104,7 @@ correlate_platform_rc:
design=$$(basename $$(dirname $$config)); \
make DESIGN_CONFIG=./$$config results/$(PLATFORM)/$$design/base/6_net_rc.csv; \
done
- $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv)
+ $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv)
# Run test using gnu parallel
#-------------------------------------------------------------------------------
diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl
index 9e5dd99b58..68aa931832 100644
--- a/flow/util/write_net_rc.tcl
+++ b/flow/util/write_net_rc.tcl
@@ -56,20 +56,22 @@ proc write_rc_csv { filename } {
}
}
}
- puts $stream ""
+ puts $stream ""
set use_drt_data [env_var_exists_and_non_empty CORRELATE_DRT_WIRELENGTH]
foreach net [get_nets *] {
set db_net [sta::sta_to_db_net $net]
set type [$db_net getSigType]
- if {([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) &&
- (!$use_drt_data || [$db_net getWire] ne "NULL")} {
+ if {
+ ([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) &&
+ (!$use_drt_data || [$db_net getWire] ne "NULL")
+ } {
set net_name [get_full_name $net]
lassign $rc_var1($net_name) wire_res1 wire_cap1
lassign $rc_var2($net_name) wire_res2 wire_cap2
lassign $rc_var3($net_name) wire_res3 wire_cap3
- puts -nonewline $stream "[get_full_name $net],[expr {[string equal $type "CLOCK"] ? "clock" : "signal"}],"
+ puts -nonewline $stream "[get_full_name $net],[expr { [string equal $type "CLOCK"] ? "clock" : "signal" }],"
puts -nonewline $stream "[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]"
set db_net [sta::sta_to_db_net $net]
@@ -79,13 +81,13 @@ proc write_rc_csv { filename } {
set layer_lengths [grt::route_layer_lengths $db_net]
}
- for {set layer 0} {$layer < [$tech getLayerCount]} {incr layer} {
+ for { set layer 0 } { $layer < [$tech getLayerCount] } { incr layer } {
set length [lindex $layer_lengths $layer]
if $is_routing($layer) {
puts -nonewline $stream ",[ord::dbu_to_microns $length]"
} else {
puts -nonewline $stream ",$length"
- }
+ }
}
puts $stream ""
@@ -197,7 +199,7 @@ proc compare_wire_rc1 { net var_name ref_var_name } {
} else {
set cap_delta 0.0
}
-
+
set total_cap [expr $pin_cap + $wire_cap]
set total_cap_ref [expr $pin_cap + $wire_cap_ref]
if { $total_cap_ref != 0.0 } {
@@ -205,7 +207,7 @@ proc compare_wire_rc1 { net var_name ref_var_name } {
} else {
set total_delta 0.0
}
-
+
set fanout [llength [get_pins -of $net -filter "direction == input"]]
puts -nonewline "[format %-20s $net_name] [format %5d $fanout] [format %8s [sta::format_capacitance $wire_cap 3]] [format %8s [sta::format_capacitance $wire_cap_ref 3]] [format %4.0f $cap_delta]% [format %4.0f $total_delta]%"
diff --git a/tclint.toml b/tclint.toml
new file mode 100644
index 0000000000..314f9c3e0b
--- /dev/null
+++ b/tclint.toml
@@ -0,0 +1,23 @@
+# hardcoded list of paths to exclude while we incrementally lint codebase
+# See issue #3268 for tracking
+exclude = [
+ "flow/results",
+ "flow/logs",
+ "flow/designs",
+ "flow/platforms",
+ "flow/util",
+ "flow/scripts/*.tcl",
+ "tools/OpenROAD",
+ "tools/yosys",
+]
+
+ignore = [
+ "unbraced-expr",
+]
+
+[style]
+indent = 2
+line-length = 100
+allow-aligned-sets = true
+indent-namespace-eval = false
+spaces-in-braces = true
\ No newline at end of file
diff --git a/tools/AutoTuner/requirements.txt b/tools/AutoTuner/requirements.txt
index 42a0c73e91..d4a4dbe5ff 100644
--- a/tools/AutoTuner/requirements.txt
+++ b/tools/AutoTuner/requirements.txt
@@ -5,7 +5,7 @@ optuna==3.6.0
pandas>=2.0,<=2.2.1
bayesian-optimization==1.4.0
colorama==0.4.6
-tensorboard>=2.14.0,<=2.16.2
+tensorboard>=2.17.0
protobuf>=5.26.1
SQLAlchemy==1.4.17
urllib3>=1.26.17
diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py
index 5d3e3e75d1..2d87b710ac 100644
--- a/tools/AutoTuner/src/autotuner/distributed.py
+++ b/tools/AutoTuner/src/autotuner/distributed.py
@@ -154,8 +154,8 @@ def step(self):
install_path=INSTALL_PATH,
)
self.step_ += 1
- (score, effective_clk_period, num_drc) = self.evaluate(
- read_metrics(metrics_file)
+ (score, effective_clk_period, num_drc, die_area) = self.evaluate(
+ read_metrics(metrics_file, args.stop_stage)
)
# Feed the score back to Tune.
# return must match 'metric' used in tune.run()
@@ -163,6 +163,7 @@ def step(self):
METRIC: score,
"effective_clk_period": effective_clk_period,
"num_drc": num_drc,
+ "die_area": die_area,
}
def evaluate(self, metrics):
@@ -174,13 +175,13 @@ def evaluate(self, metrics):
error = "ERR" in metrics.values()
not_found = "N/A" in metrics.values()
if error or not_found:
- return (ERROR_METRIC, "-", "-")
+ return (ERROR_METRIC, "-", "-", "-")
effective_clk_period = metrics["clk_period"] - metrics["worst_slack"]
num_drc = metrics["num_drc"]
gamma = effective_clk_period / 10
score = effective_clk_period
score = score * (100 / self.step_) + gamma * num_drc
- return (score, effective_clk_period, num_drc)
+ return (score, effective_clk_period, num_drc, metrics["die_area"])
def _is_valid_config(self, config):
"""
@@ -247,13 +248,13 @@ def evaluate(self, metrics):
error = "ERR" in metrics.values() or "ERR" in reference.values()
not_found = "N/A" in metrics.values() or "N/A" in reference.values()
if error or not_found:
- return (ERROR_METRIC, "-", "-")
+ return (ERROR_METRIC, "-", "-", "-")
ppa = self.get_ppa(metrics)
gamma = ppa / 10
score = ppa * (self.step_ / 100) ** (-1) + (gamma * metrics["num_drc"])
effective_clk_period = metrics["clk_period"] - metrics["worst_slack"]
num_drc = metrics["num_drc"]
- return (score, effective_clk_period, num_drc)
+ return (score, effective_clk_period, num_drc, metrics["die_area"])
def parse_arguments():
@@ -307,6 +308,14 @@ def parse_arguments():
default=None,
help="Time limit (in hours) for each trial run. Default is no limit.",
)
+ parser.add_argument(
+ "--stop_stage",
+ type=str,
+ metavar="",
+ choices=["floorplan", "place", "cts", "globalroute", "route", "finish"],
+ default="finish",
+ help="Name of the stage to stop after. Default is finish.",
+ )
tune_parser.add_argument(
"--resume",
action="store_true",
@@ -598,7 +607,7 @@ def main():
TrainClass = set_training_class(args.eval)
# PPAImprov requires a reference file to compute training scores.
if args.eval == "ppa-improv":
- reference = read_metrics(args.reference)
+ reference = read_metrics(args.reference, args.stop_stage)
tune_args = dict(
name=args.experiment,
diff --git a/tools/AutoTuner/src/autotuner/utils.py b/tools/AutoTuner/src/autotuner/utils.py
index b503f1fec9..61aebb3390 100644
--- a/tools/AutoTuner/src/autotuner/utils.py
+++ b/tools/AutoTuner/src/autotuner/utils.py
@@ -330,6 +330,8 @@ def openroad(
make_command += f" FLOW_VARIANT={flow_variant} {parameters}"
make_command += " EQUIVALENCE_CHECK=0"
make_command += f" NUM_CORES={args.openroad_threads} SHELL=bash"
+ if args.stop_stage != "finish":
+ make_command += f" {args.stop_stage}"
run_command(
args,
make_command,
@@ -358,22 +360,29 @@ def openroad(
return metrics_file
-def read_metrics(file_name):
+def read_metrics(file_name, stop_stage):
"""
Collects metrics to evaluate the user-defined objective function.
+
+ stop_stage indicates the last stage executed, so get most of the metrics
+ from that stage. The default stop stage is "finish". But if the run stops
+ before "finish", then no need to extract the metrics from the route stage,
+ so set them to 0
"""
with open(file_name) as file:
data = json.load(file)
clk_period = 9999999
worst_slack = "ERR"
- wirelength = "ERR"
- num_drc = "ERR"
total_power = "ERR"
core_util = "ERR"
final_util = "ERR"
design_area = "ERR"
die_area = "ERR"
core_area = "ERR"
+ if stop_stage != "finish":
+ num_drc = wirelength = 0
+ else:
+ num_drc = wirelength = "ERR"
for stage_name, value in data.items():
if stage_name == "constraints" and len(value["clocks__details"]) > 0:
clk_period = float(value["clocks__details"][0].split()[1])
@@ -383,17 +392,17 @@ def read_metrics(file_name):
num_drc = value["route__drc_errors"]
if stage_name == "detailedroute" and "route__wirelength" in value:
wirelength = value["route__wirelength"]
- if stage_name == "finish" and "timing__setup__ws" in value:
+ if stage_name == stop_stage and "timing__setup__ws" in value:
worst_slack = value["timing__setup__ws"]
- if stage_name == "finish" and "power__total" in value:
+ if stage_name == stop_stage and "power__total" in value:
total_power = value["power__total"]
- if stage_name == "finish" and "design__instance__utilization" in value:
+ if stage_name == stop_stage and "design__instance__utilization" in value:
final_util = value["design__instance__utilization"]
- if stage_name == "finish" and "design__instance__area" in value:
+ if stage_name == stop_stage and "design__instance__area" in value:
design_area = value["design__instance__area"]
- if stage_name == "finish" and "design__core__area" in value:
+ if stage_name == stop_stage and "design__core__area" in value:
core_area = value["design__core__area"]
- if stage_name == "finish" and "design__die__area" in value:
+ if stage_name == stop_stage and "design__die__area" in value:
die_area = value["design__die__area"]
ret = {
"clk_period": clk_period,
diff --git a/tools/OpenROAD b/tools/OpenROAD
index 663c42b140..c79c8317e0 160000
--- a/tools/OpenROAD
+++ b/tools/OpenROAD
@@ -1 +1 @@
-Subproject commit 663c42b140b136003c556c8dc386d3e982e0b586
+Subproject commit c79c8317e05ecbf45eba5096a74cb421ab97b7ae
diff --git a/tools/yosys b/tools/yosys
index db72ec3bde..9ed031ddd5 160000
--- a/tools/yosys
+++ b/tools/yosys
@@ -1 +1 @@
-Subproject commit db72ec3bde296a9512b2d1e6fabf81cfb07c2c1b
+Subproject commit 9ed031ddd588442f22be13ce608547a5809b62f0