diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 0ae8c0824e7cf7..2b2de2068e4c2b 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -905,6 +905,7 @@ properties:
               - xiaomi,jasmine
               - xiaomi,lavender
               - xiaomi,lavender-boe
+              - xiaomi,lavender-shenchao
               - xiaomi,lavender-tianma
               - xiaomi,platina
           - const: qcom,sdm660
diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
index 800a2f0a4dad98..bc5ea793db661e 100644
--- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
@@ -23,6 +23,12 @@ properties:
     items:
       - enum:
           - tianma,fhd-video
+          - novatek,nt36672a-shenchao-lavender
+          - novatek,nt36672a-tianma-beryllium
+          - novatek,nt36672a-tianma-lavender
+          - novatek,nt36672a-tianma-jasmine
+          - novatek,nt36672a-tianma-tulip
+          - novatek,nt36672-txd-x00td
       - const: novatek,nt36672a
     description: This indicates the panel manufacturer of the panel that is
       in turn using the NT36672A panel driver. This compatible string
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index fb8605219d6a0f..19c8d7b5d0eb4f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -223,6 +223,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm636-xiaomi-tulip.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm636-xiaomi-whyred.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-clover-plus.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-jasmine.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-lavender-shenchao.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-lavender-tianma.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-lavender-boe.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-platina.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts b/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts
index 2e2488c899929e..5b837388a23c76 100644
--- a/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts
+++ b/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts
@@ -211,16 +211,15 @@
 
 	status = "okay";
 
-	touchscreen@62 {
-		compatible = "novatek,nt36525";
-		reg = <0x62>;
-		vdd-supply = <&vreg_l11a_1p8>;
-		interrupt-parent = <&tlmm>;
-		interrupts = <67 IRQ_TYPE_EDGE_RISING>;
+	touchscreen@1 {
+		compatible = "novatek,nt36672a-ts";
+		reg = <0x1>;
+		iovcc-supply = <&vreg_l11a_1p8>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_RISING>;
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&ts_pins_active>;
 		pinctrl-1 = <&ts_int_sleep &ts_rst_sleep>;
-		reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
 		touchscreen-size-x = <1080>;
 		touchscreen-size-y = <2160>;
 	};
@@ -251,8 +250,9 @@
 
 	panel: panel@0 {
 		reg = <0>;
-		compatible = "mdss,novatek-nt36672-txd";
+		compatible = "novatek,nt36672-txd-x00td", "novatek,nt36672a";
 
+		vddio-supply = <&vreg_l11a_1p8>;
 		backlight = <&pm660l_wled>;
 
 		reset-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts b/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts
index 94ad772ac95fe5..a5824566b4fd1a 100644
--- a/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts
+++ b/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts
@@ -119,18 +119,15 @@
 &blsp_i2c1 {
 	status = "okay";
 
-	/* Novatek NT36672A touchscreen */
-	touchscreen@62 {
-		compatible = "novatek,nt36525";
-		reg = <0x62>;
-		interrupt-parent = <&tlmm>;
-		vdd-supply = <&vreg_l11a_1p8>;
-		vio-supply = <&vreg_l11a_1p8>;
-		interrupts = <67 IRQ_TYPE_EDGE_RISING>;
+	touchscreen@1 {
+		compatible = "novatek,nt36672a-ts";
+		reg = <0x1>;
+		iovcc-supply = <&vreg_l11a_1p8>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_RISING>;
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&ts_pins_active>;
 		pinctrl-1 = <&ts_int_sleep &ts_rst_sleep>;
-		reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
 		touchscreen-size-x = <1080>;
 		touchscreen-size-y = <2280>;
 	};
@@ -179,11 +176,11 @@
 	vdda-supply = <&vreg_l1a_1p225>;
 
 	panel: panel@0 {
-		compatible = "tianma,nt36672a-xiaomi-tulip-simple";
+		compatible = "novatek,nt36672a-tianma-tulip", "novatek,nt36672a";
 		reg = <0>;
 
 		reset-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
-
+		vddio-supply = <&vreg_l11a_1p8>;
 		backlight = <&pm660l_wled>;
 
 		pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-jasmine.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-jasmine.dts
index 9f9bc91a8d10cb..7cb02f0234a91a 100644
--- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-jasmine.dts
+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-jasmine.dts
@@ -148,17 +148,16 @@
 &blsp_i2c1 {
 	status = "okay";
 
-	/* Novatek NT36672A touchscreen */
-	touchscreen@62 {
-		compatible = "novatek,nt36525";
-		reg = <0x62>;
-		vdd-supply = <&vreg_l11a_1p8>;
-		interrupt-parent = <&tlmm>;
-		interrupts = <67 IRQ_TYPE_EDGE_RISING>;
+	touchscreen@1 {
+		compatible = "novatek,nt36672a-ts";
+		reg = <0x1>;
+		iovcc-supply = <&vreg_l11a_1p8>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_RISING>;
+		panel = <&panel>;
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&ts_pins_active>;
 		pinctrl-1 = <&ts_int_sleep &ts_rst_sleep>;
-		reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
 		touchscreen-size-x = <1080>;
 		touchscreen-size-y = <2160>;
 	};
@@ -177,13 +176,12 @@
 	vdd-supply = <&vreg_l1b_0p925>;
 	vdda-supply = <&vreg_l1a_1p225>;
 
-	panel@0 {
-		compatible = "mdss,nt36672-tianma";
+	panel: panel@0 {
+		compatible = "novatek,nt36672a-tianma-jasmine", "novatek,nt36672a";
 		reg = <0>;
 
 		reset-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
-		disp-te-gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
+		vddio-supply = <&vreg_l11a_1p8>;
 		backlight = <&pm660l_wled>;
 
 		pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-shenchao.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-shenchao.dts
new file mode 100644
index 00000000000000..7fbd82e206cb83
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-shenchao.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024, Barnabas Czeman <trabarni@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sdm660-xiaomi-lavender-common.dtsi"
+
+/ {
+	model = "Xiaomi Redmi Note 7 (Shenchao)";
+	compatible = "xiaomi,lavender-shenchao", "qcom,sdm660";
+};
+
+&blsp_i2c1 {
+	status = "okay";
+
+	touchscreen@1 {
+		compatible = "novatek,nt36672a-ts";
+		reg = <0x1>;
+
+		iovcc-supply = <&vreg_l11a_1p8>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_RISING>;
+
+		panel = <&panel>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&ts_pins_active>;
+		pinctrl-1 = <&ts_int_sleep &ts_rst_sleep>;
+
+		reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
+
+		touchscreen-size-x = <1080>;
+		touchscreen-size-y = <2340>;
+	};
+};
+
+&panel {
+	compatible = "novatek,nt36672a-shenchao-lavender", "novatek,nt36672a";
+	vddio-supply = <&vreg_l11a_1p8>;
+};
+
+&tlmm {
+	ts_pins_active: ts-pins-active-state {
+		pins = "gpio66", "gpio67";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-pull-up;
+	};
+
+	ts_rst_sleep: ts-rst-sleep-state {
+		pins = "gpio66";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	ts_int_sleep: ts-int-sleep-state {
+		pins = "gpio67";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-tianma.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-tianma.dts
index f14e214921b46b..6f50901f9c891a 100644
--- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-tianma.dts
+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender-tianma.dts
@@ -15,24 +15,29 @@
 &blsp_i2c1 {
 	status = "okay";
 
-	/* Novatek NT36672A touchscreen */
-	touchscreen@62 {
-		compatible = "novatek,nt36525";
-		reg = <0x62>;
-		vdd-supply = <&vreg_l11a_1p8>;
-		interrupt-parent = <&tlmm>;
-		interrupts = <67 IRQ_TYPE_EDGE_RISING>;
+	touchscreen@1 {
+		compatible = "novatek,nt36672a-ts";
+		reg = <0x1>;
+
+		iovcc-supply = <&vreg_l11a_1p8>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_RISING>;
+
+		panel = <&panel>;
+
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&ts_pins_active>;
 		pinctrl-1 = <&ts_int_sleep &ts_rst_sleep>;
-		reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+
+		reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
+
 		touchscreen-size-x = <1080>;
 		touchscreen-size-y = <2340>;
 	};
 };
 
 &panel {
-	compatible = "tianma,nt36672a-xiaomi-lavender-simple";
+	compatible = "novatek,nt36672a-tianma-lavender", "novatek,nt36672a";
+	vddio-supply = <&vreg_l11a_1p8>;
 };
 
 &tlmm {
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c
index c2abd20e0734bd..483595f05a55a6 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c
@@ -28,10 +28,6 @@
 
 #include <video/mipi_display.h>
 
-struct nt36672a_panel_cmd {
-	const char data[2];
-};
-
 static const char * const nt36672a_regulator_names[] = {
 	"vddio",
 	"vddpos",
@@ -54,14 +50,10 @@ struct nt36672a_panel_desc {
 	unsigned long mode_flags;
 	enum mipi_dsi_pixel_format format;
 	unsigned int lanes;
+	enum gpiod_flags reset_gpio_flags;
 
-	unsigned int num_on_cmds_1;
-	const struct nt36672a_panel_cmd *on_cmds_1;
-	unsigned int num_on_cmds_2;
-	const struct nt36672a_panel_cmd *on_cmds_2;
-
-	unsigned int num_off_cmds;
-	const struct nt36672a_panel_cmd *off_cmds;
+	int (*init_cmds)(struct drm_panel *panel);
+	int (*off_cmds)(struct drm_panel *panel);
 };
 
 struct nt36672a_panel {
@@ -79,23 +71,740 @@ static inline struct nt36672a_panel *to_nt36672a_panel(struct drm_panel *panel)
 	return container_of(panel, struct nt36672a_panel, base);
 }
 
-static int nt36672a_send_cmds(struct drm_panel *panel, const struct nt36672a_panel_cmd *cmds,
-			      int num)
+static int shenchao_lavender_init_cmds(struct drm_panel *panel)
 {
 	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
-	unsigned int i;
-	int err;
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	pinfo->link->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x96);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x27);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd9, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x31);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8a, 0x31);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8e, 0xe4);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8f, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9d, 0xb0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x26);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_CONTINUE,
+				     0x12);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xaa, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xae, 0x8a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0xfa);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x01);
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 70);
+	mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00b8);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x03, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY,
+				     0x2c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+	return dsi_ctx.accum_err;
+}
+
+static int tianma_beryllium_init_cmds(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	/* send first part of init cmds (.on_cmds_1) */
+	/* skin enhancement mode */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x22);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0xC0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x60);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x70);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x58);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x78);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x77);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x39);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x2D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x2E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x32);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x37);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x3A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0xFE);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x77);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0xCD);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0xD0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0xD0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x07);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x0C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x03);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x09);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x88);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x83, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x85, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x86, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x89, 0x91);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8A, 0x98);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8B, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8C, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8D, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8E, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8F, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x93, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x95, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x96, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x97, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x98, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x99, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9A, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9B, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9C, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9D, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9E, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA0, 0x8A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA2, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA6, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA7, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA9, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAA, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAB, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAC, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAD, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAE, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAF, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x76);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x76);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB9, 0x05);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBA, 0x0D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBB, 0x14);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBC, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBD, 0x18);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBE, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBF, 0x05);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC0, 0x0D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC1, 0x14);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC2, 0x03);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC3, 0x07);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC4, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC5, 0xA0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC6, 0x55);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC7, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC8, 0x39);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC9, 0x44);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCA, 0x12);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCD, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDB, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDC, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDD, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE4, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE5, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE8, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE9, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xEA, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xEB, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xEC, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xED, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xEE, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xEF, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF0, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF1, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF2, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF3, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF4, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF5, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xF6, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x23);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	/* dimming enable */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x84);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x2D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x00);
+	 /* resolution 1080*2246 */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x7B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x6F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x0B);
+	 /* UI mode */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0xFC);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0xF8);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0xF4);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0xF1);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xEE);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xEB);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0xE8);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xE5);
+	 /* STILL mode */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0xED);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0xD5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0xBF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0xA6);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x96);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x86);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x76);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x66);
+	 /* MOVING mode */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x0E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0xF6);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0xEA);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0xE1);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0xD8);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xCE);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0xC3);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0xBA);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xB3);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x26);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0xAF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x00);
+
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+
+	/* 0x46 = 70 ms delay */
+	mipi_dsi_msleep(&dsi_ctx, 70);
+
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
 
-	for (i = 0; i < num; i++) {
-		const struct nt36672a_panel_cmd *cmd = &cmds[i];
+	/* Send rest of the init cmds (.on_cmds_2) */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC3, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC4, 0x54);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x10);
 
-		err = mipi_dsi_dcs_write(pinfo->link, cmd->data[0], cmd->data + 1, 1);
+	mipi_dsi_msleep(&dsi_ctx, 120);
 
-		if (err < 0)
-			return err;
+	return dsi_ctx.accum_err;
+}
+
+/* Tianma-beryllium specific handler with specific delays */
+static int tianma_beryllium_off_cmds(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	/* send off cmds */
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC3, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x10);
+
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+
+	/* 120ms delay required here as per DCS spec */
+	mipi_dsi_msleep(&dsi_ctx, 120);
+
+	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+
+	/* 0x3C = 60ms delay */
+	mipi_dsi_msleep(&dsi_ctx, 60);
+
+	return dsi_ctx.accum_err;
+}
+
+static int tianma_lavender_init_cmds(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	pinfo->link->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x96);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x31);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8a, 0x31);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8e, 0xe4);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8f, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x26);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_CONTINUE, 0x12);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xaa, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xae, 0x8a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x10);
+
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 80);
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x01);
+	mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+
+	if (of_device_is_compatible(dev_of_node(&pinfo->link->dev),
+				    "novatek,nt36672a-tianma-lavender")) {
+		/* lavender specific part */
+		mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x03, 0x04);
+		mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00b8);
+	} else {
+		/* tulip specific part */
+		mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ff);
 	}
 
-	return 0;
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
+
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+	return dsi_ctx.accum_err;
+}
+
+static int tianma_lavender_off_cmds(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	pinfo->link->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 20);
+	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 120);
+
+	return dsi_ctx.accum_err;
+}
+
+static int txd_x00td_init_cmds(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x9e);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x94);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x35);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x66);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x99);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x95, 0xf5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x96, 0xf5);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x23);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x6c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0xe6);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x24);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0xa9);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x0f);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x17);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x15);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xa9);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x05);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x03);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x0f);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x17);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x15);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x13);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x08);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x08);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x72);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x72);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x72);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x83);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x08);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x9c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x45);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8e, 0xf0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x76);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x93, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x99, 0x33);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9b, 0xff);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdc, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdd, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdf, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x75);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe9, 0x08);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xed, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0,
+				     0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00,
+				     0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98,
+				     0x00, 0xac);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1,
+				     0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01,
+				     0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22,
+				     0x02, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2,
+				     0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02,
+				     0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a,
+				     0x03, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3,
+				     0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03,
+				     0xbd, 0x03, 0xd6, 0x03, 0xda);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4,
+				     0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00,
+				     0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98,
+				     0x00, 0xac);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5,
+				     0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01,
+				     0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22,
+				     0x02, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6,
+				     0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02,
+				     0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a,
+				     0x03, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb7,
+				     0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03,
+				     0xbd, 0x03, 0xd6, 0x03, 0xda);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8,
+				     0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00,
+				     0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98,
+				     0x00, 0xac);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9,
+				     0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01,
+				     0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22,
+				     0x02, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+				     0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02,
+				     0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a,
+				     0x03, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb,
+				     0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03,
+				     0xbd, 0x03, 0xd6, 0x03, 0xda);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x21);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0,
+				     0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00,
+				     0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98,
+				     0x00, 0xac);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1,
+				     0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01,
+				     0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22,
+				     0x02, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2,
+				     0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02,
+				     0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a,
+				     0x03, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3,
+				     0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03,
+				     0xbd, 0x03, 0xd6, 0x03, 0xda);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4,
+				     0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00,
+				     0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98,
+				     0x00, 0xac);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5,
+				     0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01,
+				     0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22,
+				     0x02, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6,
+				     0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02,
+				     0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a,
+				     0x03, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb7,
+				     0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03,
+				     0xbd, 0x03, 0xd6, 0x03, 0xda);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8,
+				     0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00,
+				     0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98,
+				     0x00, 0xac);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9,
+				     0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01,
+				     0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22,
+				     0x02, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+				     0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02,
+				     0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a,
+				     0x03, 0x68);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb,
+				     0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03,
+				     0xbd, 0x03, 0xd6, 0x03, 0xda);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x0c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x81);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0xd7);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x82);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x76);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x76);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x25);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x80);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x22);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x60);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x2d);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8d, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd8, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd9, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xda, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdb, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdc, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x26);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0xc8);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x97);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1e);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x99, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x27);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x0e);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0xb0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0xd0);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 70);
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+	mipi_dsi_usleep_range(&dsi_ctx, 10000, 11000);
+
+	return dsi_ctx.accum_err;
+}
+
+static int txd_x00td_off(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 50);
+	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 120);
+
+	return dsi_ctx.accum_err;
+}
+
+static int tianma_jasmine_init_cmds(struct drm_panel *panel)
+{
+	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->link };
+
+	pinfo->link->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x20);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_PARTIAL_ROWS, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x2f);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x10);
+
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+	mipi_dsi_msleep(&dsi_ctx, 70);
+
+	mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ff);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x03, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
+
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+	usleep_range(5000, 6000);
+
+	return dsi_ctx.accum_err;
 }
 
 static int nt36672a_panel_power_off(struct drm_panel *panel)
@@ -112,31 +821,24 @@ static int nt36672a_panel_power_off(struct drm_panel *panel)
 	return ret;
 }
 
-static int nt36672a_panel_unprepare(struct drm_panel *panel)
+static int nt36672a_panel_disable(struct drm_panel *panel)
 {
 	struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
-	int ret;
+	int ret = 0;
 
 	/* send off cmds */
-	ret = nt36672a_send_cmds(panel, pinfo->desc->off_cmds,
-				 pinfo->desc->num_off_cmds);
-
-	if (ret < 0)
-		dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret);
-
-	ret = mipi_dsi_dcs_set_display_off(pinfo->link);
-	if (ret < 0)
-		dev_err(panel->dev, "set_display_off cmd failed ret = %d\n", ret);
-
-	/* 120ms delay required here as per DCS spec */
-	msleep(120);
+	if (pinfo->desc->off_cmds) {
+		ret = pinfo->desc->off_cmds(panel);
+		if (ret < 0)
+			dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret);
+	}
 
-	ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->link);
-	if (ret < 0)
-		dev_err(panel->dev, "enter_sleep cmd failed ret = %d\n", ret);
+	return ret;
+}
 
-	/* 0x3C = 60ms delay */
-	msleep(60);
+static int nt36672a_panel_unprepare(struct drm_panel *panel)
+{
+	int ret;
 
 	ret = nt36672a_panel_power_off(panel);
 	if (ret < 0)
@@ -176,41 +878,12 @@ static int nt36672a_panel_prepare(struct drm_panel *panel)
 	if (err < 0)
 		goto poweroff;
 
-	/* send first part of init cmds */
-	err = nt36672a_send_cmds(panel, pinfo->desc->on_cmds_1,
-				 pinfo->desc->num_on_cmds_1);
-
-	if (err < 0) {
-		dev_err(panel->dev, "failed to send DCS Init 1st Code: %d\n", err);
-		goto poweroff;
-	}
-
-	err = mipi_dsi_dcs_exit_sleep_mode(pinfo->link);
-	if (err < 0) {
-		dev_err(panel->dev, "failed to exit sleep mode: %d\n", err);
-		goto poweroff;
-	}
-
-	/* 0x46 = 70 ms delay */
-	msleep(70);
-
-	err = mipi_dsi_dcs_set_display_on(pinfo->link);
+	err = pinfo->desc->init_cmds(panel);
 	if (err < 0) {
-		dev_err(panel->dev, "failed to Set Display ON: %d\n", err);
+		dev_err(panel->dev, "Failed to init panel!\n");
 		goto poweroff;
 	}
 
-	/* Send rest of the init cmds */
-	err = nt36672a_send_cmds(panel, pinfo->desc->on_cmds_2,
-				 pinfo->desc->num_on_cmds_2);
-
-	if (err < 0) {
-		dev_err(panel->dev, "failed to send DCS Init 2nd Code: %d\n", err);
-		goto poweroff;
-	}
-
-	msleep(120);
-
 	return 0;
 
 poweroff:
@@ -242,316 +915,12 @@ static int nt36672a_panel_get_modes(struct drm_panel *panel,
 }
 
 static const struct drm_panel_funcs panel_funcs = {
+	.disable = nt36672a_panel_disable,
 	.unprepare = nt36672a_panel_unprepare,
 	.prepare = nt36672a_panel_prepare,
 	.get_modes = nt36672a_panel_get_modes,
 };
 
-static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_1[] = {
-	/* skin enhancement mode */
-	{ .data = {0xFF, 0x22} },
-	{ .data = {0x00, 0x40} },
-	{ .data = {0x01, 0xC0} },
-	{ .data = {0x02, 0x40} },
-	{ .data = {0x03, 0x40} },
-	{ .data = {0x04, 0x40} },
-	{ .data = {0x05, 0x40} },
-	{ .data = {0x06, 0x40} },
-	{ .data = {0x07, 0x40} },
-	{ .data = {0x08, 0x40} },
-	{ .data = {0x09, 0x40} },
-	{ .data = {0x0A, 0x40} },
-	{ .data = {0x0B, 0x40} },
-	{ .data = {0x0C, 0x40} },
-	{ .data = {0x0D, 0x40} },
-	{ .data = {0x0E, 0x40} },
-	{ .data = {0x0F, 0x40} },
-	{ .data = {0x10, 0x40} },
-	{ .data = {0x11, 0x50} },
-	{ .data = {0x12, 0x60} },
-	{ .data = {0x13, 0x70} },
-	{ .data = {0x14, 0x58} },
-	{ .data = {0x15, 0x68} },
-	{ .data = {0x16, 0x78} },
-	{ .data = {0x17, 0x77} },
-	{ .data = {0x18, 0x39} },
-	{ .data = {0x19, 0x2D} },
-	{ .data = {0x1A, 0x2E} },
-	{ .data = {0x1B, 0x32} },
-	{ .data = {0x1C, 0x37} },
-	{ .data = {0x1D, 0x3A} },
-	{ .data = {0x1E, 0x40} },
-	{ .data = {0x1F, 0x40} },
-	{ .data = {0x20, 0x40} },
-	{ .data = {0x21, 0x40} },
-	{ .data = {0x22, 0x40} },
-	{ .data = {0x23, 0x40} },
-	{ .data = {0x24, 0x40} },
-	{ .data = {0x25, 0x40} },
-	{ .data = {0x26, 0x40} },
-	{ .data = {0x27, 0x40} },
-	{ .data = {0x28, 0x40} },
-	{ .data = {0x2D, 0x00} },
-	{ .data = {0x2F, 0x40} },
-	{ .data = {0x30, 0x40} },
-	{ .data = {0x31, 0x40} },
-	{ .data = {0x32, 0x40} },
-	{ .data = {0x33, 0x40} },
-	{ .data = {0x34, 0x40} },
-	{ .data = {0x35, 0x40} },
-	{ .data = {0x36, 0x40} },
-	{ .data = {0x37, 0x40} },
-	{ .data = {0x38, 0x40} },
-	{ .data = {0x39, 0x40} },
-	{ .data = {0x3A, 0x40} },
-	{ .data = {0x3B, 0x40} },
-	{ .data = {0x3D, 0x40} },
-	{ .data = {0x3F, 0x40} },
-	{ .data = {0x40, 0x40} },
-	{ .data = {0x41, 0x40} },
-	{ .data = {0x42, 0x40} },
-	{ .data = {0x43, 0x40} },
-	{ .data = {0x44, 0x40} },
-	{ .data = {0x45, 0x40} },
-	{ .data = {0x46, 0x40} },
-	{ .data = {0x47, 0x40} },
-	{ .data = {0x48, 0x40} },
-	{ .data = {0x49, 0x40} },
-	{ .data = {0x4A, 0x40} },
-	{ .data = {0x4B, 0x40} },
-	{ .data = {0x4C, 0x40} },
-	{ .data = {0x4D, 0x40} },
-	{ .data = {0x4E, 0x40} },
-	{ .data = {0x4F, 0x40} },
-	{ .data = {0x50, 0x40} },
-	{ .data = {0x51, 0x40} },
-	{ .data = {0x52, 0x40} },
-	{ .data = {0x53, 0x01} },
-	{ .data = {0x54, 0x01} },
-	{ .data = {0x55, 0xFE} },
-	{ .data = {0x56, 0x77} },
-	{ .data = {0x58, 0xCD} },
-	{ .data = {0x59, 0xD0} },
-	{ .data = {0x5A, 0xD0} },
-	{ .data = {0x5B, 0x50} },
-	{ .data = {0x5C, 0x50} },
-	{ .data = {0x5D, 0x50} },
-	{ .data = {0x5E, 0x50} },
-	{ .data = {0x5F, 0x50} },
-	{ .data = {0x60, 0x50} },
-	{ .data = {0x61, 0x50} },
-	{ .data = {0x62, 0x50} },
-	{ .data = {0x63, 0x50} },
-	{ .data = {0x64, 0x50} },
-	{ .data = {0x65, 0x50} },
-	{ .data = {0x66, 0x50} },
-	{ .data = {0x67, 0x50} },
-	{ .data = {0x68, 0x50} },
-	{ .data = {0x69, 0x50} },
-	{ .data = {0x6A, 0x50} },
-	{ .data = {0x6B, 0x50} },
-	{ .data = {0x6C, 0x50} },
-	{ .data = {0x6D, 0x50} },
-	{ .data = {0x6E, 0x50} },
-	{ .data = {0x6F, 0x50} },
-	{ .data = {0x70, 0x07} },
-	{ .data = {0x71, 0x00} },
-	{ .data = {0x72, 0x00} },
-	{ .data = {0x73, 0x00} },
-	{ .data = {0x74, 0x06} },
-	{ .data = {0x75, 0x0C} },
-	{ .data = {0x76, 0x03} },
-	{ .data = {0x77, 0x09} },
-	{ .data = {0x78, 0x0F} },
-	{ .data = {0x79, 0x68} },
-	{ .data = {0x7A, 0x88} },
-	{ .data = {0x7C, 0x80} },
-	{ .data = {0x7D, 0x80} },
-	{ .data = {0x7E, 0x80} },
-	{ .data = {0x7F, 0x00} },
-	{ .data = {0x80, 0x00} },
-	{ .data = {0x81, 0x00} },
-	{ .data = {0x83, 0x01} },
-	{ .data = {0x84, 0x00} },
-	{ .data = {0x85, 0x80} },
-	{ .data = {0x86, 0x80} },
-	{ .data = {0x87, 0x80} },
-	{ .data = {0x88, 0x40} },
-	{ .data = {0x89, 0x91} },
-	{ .data = {0x8A, 0x98} },
-	{ .data = {0x8B, 0x80} },
-	{ .data = {0x8C, 0x80} },
-	{ .data = {0x8D, 0x80} },
-	{ .data = {0x8E, 0x80} },
-	{ .data = {0x8F, 0x80} },
-	{ .data = {0x90, 0x80} },
-	{ .data = {0x91, 0x80} },
-	{ .data = {0x92, 0x80} },
-	{ .data = {0x93, 0x80} },
-	{ .data = {0x94, 0x80} },
-	{ .data = {0x95, 0x80} },
-	{ .data = {0x96, 0x80} },
-	{ .data = {0x97, 0x80} },
-	{ .data = {0x98, 0x80} },
-	{ .data = {0x99, 0x80} },
-	{ .data = {0x9A, 0x80} },
-	{ .data = {0x9B, 0x80} },
-	{ .data = {0x9C, 0x80} },
-	{ .data = {0x9D, 0x80} },
-	{ .data = {0x9E, 0x80} },
-	{ .data = {0x9F, 0x80} },
-	{ .data = {0xA0, 0x8A} },
-	{ .data = {0xA2, 0x80} },
-	{ .data = {0xA6, 0x80} },
-	{ .data = {0xA7, 0x80} },
-	{ .data = {0xA9, 0x80} },
-	{ .data = {0xAA, 0x80} },
-	{ .data = {0xAB, 0x80} },
-	{ .data = {0xAC, 0x80} },
-	{ .data = {0xAD, 0x80} },
-	{ .data = {0xAE, 0x80} },
-	{ .data = {0xAF, 0x80} },
-	{ .data = {0xB7, 0x76} },
-	{ .data = {0xB8, 0x76} },
-	{ .data = {0xB9, 0x05} },
-	{ .data = {0xBA, 0x0D} },
-	{ .data = {0xBB, 0x14} },
-	{ .data = {0xBC, 0x0F} },
-	{ .data = {0xBD, 0x18} },
-	{ .data = {0xBE, 0x1F} },
-	{ .data = {0xBF, 0x05} },
-	{ .data = {0xC0, 0x0D} },
-	{ .data = {0xC1, 0x14} },
-	{ .data = {0xC2, 0x03} },
-	{ .data = {0xC3, 0x07} },
-	{ .data = {0xC4, 0x0A} },
-	{ .data = {0xC5, 0xA0} },
-	{ .data = {0xC6, 0x55} },
-	{ .data = {0xC7, 0xFF} },
-	{ .data = {0xC8, 0x39} },
-	{ .data = {0xC9, 0x44} },
-	{ .data = {0xCA, 0x12} },
-	{ .data = {0xCD, 0x80} },
-	{ .data = {0xDB, 0x80} },
-	{ .data = {0xDC, 0x80} },
-	{ .data = {0xDD, 0x80} },
-	{ .data = {0xE0, 0x80} },
-	{ .data = {0xE1, 0x80} },
-	{ .data = {0xE2, 0x80} },
-	{ .data = {0xE3, 0x80} },
-	{ .data = {0xE4, 0x80} },
-	{ .data = {0xE5, 0x40} },
-	{ .data = {0xE6, 0x40} },
-	{ .data = {0xE7, 0x40} },
-	{ .data = {0xE8, 0x40} },
-	{ .data = {0xE9, 0x40} },
-	{ .data = {0xEA, 0x40} },
-	{ .data = {0xEB, 0x40} },
-	{ .data = {0xEC, 0x40} },
-	{ .data = {0xED, 0x40} },
-	{ .data = {0xEE, 0x40} },
-	{ .data = {0xEF, 0x40} },
-	{ .data = {0xF0, 0x40} },
-	{ .data = {0xF1, 0x40} },
-	{ .data = {0xF2, 0x40} },
-	{ .data = {0xF3, 0x40} },
-	{ .data = {0xF4, 0x40} },
-	{ .data = {0xF5, 0x40} },
-	{ .data = {0xF6, 0x40} },
-	{ .data = {0xFB, 0x1} },
-	{ .data = {0xFF, 0x23} },
-	{ .data = {0xFB, 0x01} },
-	/* dimming enable */
-	{ .data = {0x01, 0x84} },
-	{ .data = {0x05, 0x2D} },
-	{ .data = {0x06, 0x00} },
-	 /* resolution 1080*2246 */
-	{ .data = {0x11, 0x01} },
-	{ .data = {0x12, 0x7B} },
-	{ .data = {0x15, 0x6F} },
-	{ .data = {0x16, 0x0B} },
-	 /* UI mode */
-	{ .data = {0x29, 0x0A} },
-	{ .data = {0x30, 0xFF} },
-	{ .data = {0x31, 0xFF} },
-	{ .data = {0x32, 0xFF} },
-	{ .data = {0x33, 0xFF} },
-	{ .data = {0x34, 0xFF} },
-	{ .data = {0x35, 0xFF} },
-	{ .data = {0x36, 0xFF} },
-	{ .data = {0x37, 0xFF} },
-	{ .data = {0x38, 0xFC} },
-	{ .data = {0x39, 0xF8} },
-	{ .data = {0x3A, 0xF4} },
-	{ .data = {0x3B, 0xF1} },
-	{ .data = {0x3D, 0xEE} },
-	{ .data = {0x3F, 0xEB} },
-	{ .data = {0x40, 0xE8} },
-	{ .data = {0x41, 0xE5} },
-	 /* STILL mode */
-	{ .data = {0x2A, 0x13} },
-	{ .data = {0x45, 0xFF} },
-	{ .data = {0x46, 0xFF} },
-	{ .data = {0x47, 0xFF} },
-	{ .data = {0x48, 0xFF} },
-	{ .data = {0x49, 0xFF} },
-	{ .data = {0x4A, 0xFF} },
-	{ .data = {0x4B, 0xFF} },
-	{ .data = {0x4C, 0xFF} },
-	{ .data = {0x4D, 0xED} },
-	{ .data = {0x4E, 0xD5} },
-	{ .data = {0x4F, 0xBF} },
-	{ .data = {0x50, 0xA6} },
-	{ .data = {0x51, 0x96} },
-	{ .data = {0x52, 0x86} },
-	{ .data = {0x53, 0x76} },
-	{ .data = {0x54, 0x66} },
-	 /* MOVING mode */
-	{ .data = {0x2B, 0x0E} },
-	{ .data = {0x58, 0xFF} },
-	{ .data = {0x59, 0xFF} },
-	{ .data = {0x5A, 0xFF} },
-	{ .data = {0x5B, 0xFF} },
-	{ .data = {0x5C, 0xFF} },
-	{ .data = {0x5D, 0xFF} },
-	{ .data = {0x5E, 0xFF} },
-	{ .data = {0x5F, 0xFF} },
-	{ .data = {0x60, 0xF6} },
-	{ .data = {0x61, 0xEA} },
-	{ .data = {0x62, 0xE1} },
-	{ .data = {0x63, 0xD8} },
-	{ .data = {0x64, 0xCE} },
-	{ .data = {0x65, 0xC3} },
-	{ .data = {0x66, 0xBA} },
-	{ .data = {0x67, 0xB3} },
-	{ .data = {0xFF, 0x25} },
-	{ .data = {0xFB, 0x01} },
-	{ .data = {0x05, 0x04} },
-	{ .data = {0xFF, 0x26} },
-	{ .data = {0xFB, 0x01} },
-	{ .data = {0x1C, 0xAF} },
-	{ .data = {0xFF, 0x10} },
-	{ .data = {0xFB, 0x01} },
-	{ .data = {0x51, 0xFF} },
-	{ .data = {0x53, 0x24} },
-	{ .data = {0x55, 0x00} },
-};
-
-static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_2[] = {
-	{ .data = {0xFF, 0x24} },
-	{ .data = {0xFB, 0x01} },
-	{ .data = {0xC3, 0x01} },
-	{ .data = {0xC4, 0x54} },
-	{ .data = {0xFF, 0x10} },
-};
-
-static const struct nt36672a_panel_cmd tianma_fhd_video_off_cmds[] = {
-	{ .data = {0xFF, 0x24} },
-	{ .data = {0xFB, 0x01} },
-	{ .data = {0xC3, 0x01} },
-	{ .data = {0xFF, 0x10} },
-};
-
 static const struct drm_display_mode tianma_fhd_video_panel_default_mode = {
 	.clock		= 161331,
 
@@ -580,12 +949,178 @@ static const struct nt36672a_panel_desc tianma_fhd_video_panel_desc = {
 			| MIPI_DSI_MODE_VIDEO_BURST,
 	.format = MIPI_DSI_FMT_RGB888,
 	.lanes = 4,
-	.on_cmds_1 = tianma_fhd_video_on_cmds_1,
-	.num_on_cmds_1 = ARRAY_SIZE(tianma_fhd_video_on_cmds_1),
-	.on_cmds_2 = tianma_fhd_video_on_cmds_2,
-	.num_on_cmds_2 = ARRAY_SIZE(tianma_fhd_video_on_cmds_2),
-	.off_cmds = tianma_fhd_video_off_cmds,
-	.num_off_cmds = ARRAY_SIZE(tianma_fhd_video_off_cmds),
+	.reset_gpio_flags = GPIOD_OUT_LOW,
+
+	.init_cmds = tianma_beryllium_init_cmds,
+	.off_cmds = tianma_beryllium_off_cmds,
+};
+
+static const struct drm_display_mode shenchao_lavender_panel_default_mode = {
+	.clock = (1080 + 90 + 2 + 120) * (2340 + 10 + 3 + 8) * 60 / 1000,
+
+	.hdisplay = 1080,
+	.hsync_start = 1080 + 90,
+	.hsync_end = 1080 + 90 + 2,
+	.htotal = 1080 + 90 + 2 + 120,
+
+	.vdisplay = 2340,
+	.vsync_start = 2340 + 10,
+	.vsync_end = 2340 + 10 + 3,
+	.vtotal = 2340 + 10 + 3 + 8,
+
+	.type = DRM_MODE_TYPE_DRIVER,
+};
+
+static const struct nt36672a_panel_desc shenchao_lavender_panel_desc = {
+	.display_mode = &shenchao_lavender_panel_default_mode,
+
+	.width_mm = 67,
+	.height_mm = 145,
+
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+	.reset_gpio_flags = GPIOD_OUT_HIGH,
+
+	.init_cmds = shenchao_lavender_init_cmds,
+	/* lavender shenchao panel uses the same off sequence as tianma one */
+	.off_cmds = tianma_lavender_off_cmds,
+};
+
+static const struct drm_display_mode tianma_lavender_panel_default_mode = {
+	.clock		= (1080 + 90 + 2 + 120) * (2340 + 10 + 3 + 8) * 60 / 1000,
+
+	.hdisplay	= 1080,
+	.hsync_start	= 1080 + 90,
+	.hsync_end	= 1080 + 90 + 2,
+	.htotal		= 1080 + 90 + 2 + 120,
+
+	.vdisplay	= 2340,
+	.vsync_start	= 2340 + 10,
+	.vsync_end	= 2340 + 10 + 3,
+	.vtotal		= 2340 + 10 + 3 + 8,
+
+	.width_mm = 67,
+	.height_mm = 145,
+	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct nt36672a_panel_desc tianma_lavender_panel_desc = {
+	.display_mode = &tianma_lavender_panel_default_mode,
+
+	.width_mm = 67,
+	.height_mm = 145,
+
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+	.reset_gpio_flags = GPIOD_OUT_HIGH,
+
+	.init_cmds = tianma_lavender_init_cmds,
+	.off_cmds = tianma_lavender_off_cmds,
+};
+
+static const struct drm_display_mode tianma_jasmine_panel_default_mode = {
+	.clock		= (1080 + 96 + 4 + 56) * (2160 + 4 + 2 + 33) * 60 / 1000,
+
+	.hdisplay	= 1080,
+	.hsync_start 	= 1080 + 96,
+	.hsync_end	= 1080 + 96 + 4,
+	.htotal		= 1080 + 96 + 4 + 56,
+
+	.vdisplay	= 2160,
+	.vsync_start	= 2160 + 4,
+	.vsync_end	= 2160 + 4 + 2,
+	.vtotal		= 2160 + 4 + 2 + 33,
+
+	.width_mm = 68,
+	.height_mm = 136,
+	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct nt36672a_panel_desc tianma_jasmine_panel_desc = {
+	.display_mode = &tianma_jasmine_panel_default_mode,
+
+	.width_mm = 68,
+	.height_mm = 136,
+
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+	.reset_gpio_flags = GPIOD_OUT_HIGH,
+
+	.init_cmds = tianma_jasmine_init_cmds,
+	/* jasmine panel uses the same off sequence as lavender */
+	.off_cmds = tianma_lavender_off_cmds,
+};
+
+static const struct drm_display_mode tianmaplus_e7t_tulip_mode = {
+	.clock		= (1080 + 100 + 28 + 120) * (2280 + 10 + 3 + 8) * 60 / 1000,
+	.hdisplay	= 1080,
+	.hsync_start	= 1080 + 100,
+	.hsync_end	= 1080 + 100 + 28,
+	.htotal		= 1080 + 100 + 28 + 120,
+
+	.vdisplay	= 2280,
+	.vsync_start	= 2280 + 10,
+	.vsync_end	= 2280 + 10 + 3,
+	.vtotal		= 2280 + 10 + 3 + 8,
+
+	.width_mm = 68,
+	.height_mm = 143,
+	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct nt36672a_panel_desc tianmaplus_e7t_tulip_panel_desc = {
+	.display_mode = &tianmaplus_e7t_tulip_mode,
+
+	.width_mm = 68,
+	.height_mm = 143,
+
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+	.reset_gpio_flags = GPIOD_OUT_HIGH,
+
+	/* tulip panel uses almost the same init/off sequences as lavender */
+	.init_cmds = tianma_lavender_init_cmds,
+	.off_cmds = tianma_lavender_off_cmds,
+};
+
+static const struct drm_display_mode txd_x00td_mode = {
+	.clock = (1080 + 122 + 8 + 76) * (2160 + 20 + 4 + 28) * 60 / 1000,
+	.hdisplay = 1080,
+	.hsync_start = 1080 + 122,
+	.hsync_end = 1080 + 122 + 8,
+	.htotal = 1080 + 122 + 8 + 76,
+	.vdisplay = 2160,
+	.vsync_start = 2160 + 20,
+	.vsync_end = 2160 + 20 + 4,
+	.vtotal = 2160 + 20 + 4 + 28,
+	.width_mm = 68,
+	.height_mm = 136,
+	.type = DRM_MODE_TYPE_DRIVER,
+};
+
+static const struct nt36672a_panel_desc txd_x00td_panel_desc = {
+	.display_mode = &txd_x00td_mode,
+
+	.width_mm = 68,
+	.height_mm = 136,
+
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			  MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_NO_EOT_PACKET |
+			  MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+	.reset_gpio_flags = GPIOD_OUT_HIGH,
+
+	.init_cmds = txd_x00td_init_cmds,
+	.off_cmds = txd_x00td_off,
 };
 
 static int nt36672a_panel_add(struct nt36672a_panel *pinfo)
@@ -603,12 +1138,12 @@ static int nt36672a_panel_add(struct nt36672a_panel *pinfo)
 	if (ret < 0)
 		return dev_err_probe(dev, ret, "failed to get regulators\n");
 
-	pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+	pinfo->reset_gpio = devm_gpiod_get(dev, "reset", pinfo->desc->reset_gpio_flags);
 	if (IS_ERR(pinfo->reset_gpio))
 		return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio),
 				     "failed to get reset gpio from DT\n");
 
-	drm_panel_init(&pinfo->base, dev, &panel_funcs, DRM_MODE_CONNECTOR_DSI);
+	pinfo->base.prepare_prev_first = true;
 
 	ret = drm_panel_of_backlight(&pinfo->base);
 	if (ret)
@@ -625,9 +1160,10 @@ static int nt36672a_panel_probe(struct mipi_dsi_device *dsi)
 	const struct nt36672a_panel_desc *desc;
 	int err;
 
-	pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), GFP_KERNEL);
-	if (!pinfo)
-		return -ENOMEM;
+	pinfo = devm_drm_panel_alloc(&dsi->dev, struct nt36672a_panel, base,
+				     &panel_funcs, DRM_MODE_CONNECTOR_DSI);
+	if (IS_ERR(pinfo))
+		return PTR_ERR(pinfo);
 
 	desc = of_device_get_match_data(&dsi->dev);
 	dsi->mode_flags = desc->mode_flags;
@@ -663,16 +1199,21 @@ static void nt36672a_panel_remove(struct mipi_dsi_device *dsi)
 	drm_panel_remove(&pinfo->base);
 }
 
-static const struct of_device_id tianma_fhd_video_of_match[] = {
+static const struct of_device_id panel_nt36672a_match[] = {
 	{ .compatible = "tianma,fhd-video", .data = &tianma_fhd_video_panel_desc },
+	{ .compatible = "novatek,nt36672a-shenchao-lavender", .data = &shenchao_lavender_panel_desc },
+	{ .compatible = "novatek,nt36672a-tianma-lavender", .data = &tianma_lavender_panel_desc },
+	{ .compatible = "novatek,nt36672a-tianma-jasmine", .data = &tianma_jasmine_panel_desc },
+	{ .compatible = "novatek,nt36672a-tianma-tulip", .data = &tianmaplus_e7t_tulip_panel_desc },
+	{ .compatible = "novatek,nt36672-txd-x00td", .data = &txd_x00td_panel_desc },
 	{ },
 };
-MODULE_DEVICE_TABLE(of, tianma_fhd_video_of_match);
+MODULE_DEVICE_TABLE(of, panel_nt36672a_match);
 
 static struct mipi_dsi_driver nt36672a_panel_driver = {
 	.driver = {
-		.name = "panel-tianma-nt36672a",
-		.of_match_table = tianma_fhd_video_of_match,
+		.name = "panel-novatek-nt36672a",
+		.of_match_table = panel_nt36672a_match,
 	},
 	.probe = nt36672a_panel_probe,
 	.remove = nt36672a_panel_remove,
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 87644d209d82d5..401247fc1a21df 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -660,7 +660,7 @@ config TOUCHSCREEN_MTOUCH
 
 config TOUCHSCREEN_NOVATEK_NVT_TS
 	tristate "Novatek NT11205 touchscreen support"
-	depends on I2C
+	depends on I2C && (DRM || !DRM)
 	help
 	  Say Y here if you have a Novatek NT11205 touchscreen.
 	  If unsure, say N.
diff --git a/drivers/input/touchscreen/novatek-nvt-ts.c b/drivers/input/touchscreen/novatek-nvt-ts.c
index 44b58e0dc1ada1..6a756e06e6ee1a 100644
--- a/drivers/input/touchscreen/novatek-nvt-ts.c
+++ b/drivers/input/touchscreen/novatek-nvt-ts.c
@@ -6,6 +6,7 @@
  * Copyright (c) 2023 Hans de Goede <hdegoede@redhat.com>
  */
 
+#include <drm/drm_panel.h>
 #include <linux/delay.h>
 #include <linux/gpio/consumer.h>
 #include <linux/interrupt.h>
@@ -14,7 +15,6 @@
 #include <linux/input/mt.h>
 #include <linux/input/touchscreen.h>
 #include <linux/module.h>
-
 #include <linux/unaligned.h>
 
 #define NVT_TS_TOUCH_START		0x00
@@ -61,6 +61,12 @@ struct nvt_ts_data {
 	struct touchscreen_properties prop;
 	int max_touches;
 	u8 buf[NVT_TS_TOUCH_SIZE * NVT_TS_MAX_TOUCHES];
+	/*
+	 * Sometimes Novatek touchscreen is paired together with Novatek panel,
+	 * and they need to be powered together in sync.
+	 */
+	struct drm_panel_follower panel_follower;
+	bool is_panel_follower;
 };
 
 static int nvt_ts_read_data(struct i2c_client *client, u8 reg, u8 *data, int count)
@@ -97,6 +103,9 @@ static irqreturn_t nvt_ts_irq(int irq, void *dev_id)
 	bool active;
 	u8 *touch;
 
+	if (!data->input)
+		return IRQ_HANDLED;
+
 	error = nvt_ts_read_data(data->client, NVT_TS_TOUCH_START, data->buf,
 				 data->max_touches * NVT_TS_TOUCH_SIZE);
 	if (error)
@@ -155,6 +164,7 @@ static int nvt_ts_start(struct input_dev *dev)
 
 	enable_irq(data->client->irq);
 	gpiod_set_value_cansleep(data->reset_gpio, 0);
+	msleep(100); // TODO: is it really needed? probably
 
 	return 0;
 }
@@ -172,6 +182,9 @@ static int nvt_ts_suspend(struct device *dev)
 {
 	struct nvt_ts_data *data = i2c_get_clientdata(to_i2c_client(dev));
 
+	if (data->is_panel_follower)
+		return 0;
+
 	mutex_lock(&data->input->mutex);
 	if (input_device_enabled(data->input))
 		nvt_ts_stop(data->input);
@@ -184,6 +197,9 @@ static int nvt_ts_resume(struct device *dev)
 {
 	struct nvt_ts_data *data = i2c_get_clientdata(to_i2c_client(dev));
 
+	if (data->is_panel_follower)
+		return 0;
+
 	mutex_lock(&data->input->mutex);
 	if (input_device_enabled(data->input))
 		nvt_ts_start(data->input);
@@ -192,32 +208,17 @@ static int nvt_ts_resume(struct device *dev)
 	return 0;
 }
 
-static DEFINE_SIMPLE_DEV_PM_OPS(nvt_ts_pm_ops, nvt_ts_suspend, nvt_ts_resume);
-
-static int nvt_ts_probe(struct i2c_client *client)
+static int nvt_ts_initial_power_on_and_register_inputdev(struct nvt_ts_data *data)
 {
-	struct device *dev = &client->dev;
+	struct device *dev = &data->client->dev;
 	int error, width, height, irq_type;
-	struct nvt_ts_data *data;
 	const struct nvt_ts_i2c_chip_data *chip;
 	struct input_dev *input;
 
-	if (!client->irq) {
-		dev_err(dev, "Error no irq specified\n");
-		return -EINVAL;
-	}
-
-	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-	if (!data)
-		return -ENOMEM;
-
-	chip = device_get_match_data(&client->dev);
+	chip = device_get_match_data(dev);
 	if (!chip)
 		return -EINVAL;
 
-	data->client = client;
-	i2c_set_clientdata(client, data);
-
 	/*
 	 * VCC is the analog voltage supply
 	 * IOVCC is the digital voltage supply
@@ -278,7 +279,7 @@ static int nvt_ts_probe(struct i2c_client *client)
 	if (!input)
 		return -ENOMEM;
 
-	input->name = client->name;
+	input->name = data->client->name;
 	input->id.bustype = BUS_I2C;
 	input->open = nvt_ts_start;
 	input->close = nvt_ts_stop;
@@ -295,10 +296,11 @@ static int nvt_ts_probe(struct i2c_client *client)
 	data->input = input;
 	input_set_drvdata(input, data);
 
-	error = devm_request_threaded_irq(dev, client->irq, NULL, nvt_ts_irq,
+	error = devm_request_threaded_irq(dev, data->client->irq, NULL,
+					  nvt_ts_irq,
 					  IRQF_ONESHOT | IRQF_NO_AUTOEN |
 						nvt_ts_irq_type[irq_type],
-					  client->name, data);
+					  data->client->name, data);
 	if (error) {
 		dev_err(dev, "failed to request irq: %d\n", error);
 		return error;
@@ -313,6 +315,91 @@ static int nvt_ts_probe(struct i2c_client *client)
 	return 0;
 }
 
+static int on_novatek_panel_prepared(struct drm_panel_follower *follower)
+{
+	struct nvt_ts_data *data = container_of(follower, struct nvt_ts_data, panel_follower);
+	int ret;
+	dev_info(&data->client->dev, "%s\n", __func__); // REMOVEME
+
+	/* Is this the first power on? */
+	if (!data->input) {
+		dev_info(&data->client->dev, "doing initial power on\n"); // REMOVEME
+		ret = nvt_ts_initial_power_on_and_register_inputdev(data);
+		if (ret)
+			return ret;
+	}
+
+	mutex_lock(&data->input->mutex);
+	if (input_device_enabled(data->input))
+		nvt_ts_start(data->input);
+	mutex_unlock(&data->input->mutex);
+
+	return 0;
+}
+
+static int on_novatek_panel_unpreparing(struct drm_panel_follower *follower)
+{
+	struct nvt_ts_data *data = container_of(follower, struct nvt_ts_data, panel_follower);
+	dev_info(&data->client->dev, "%s\n", __func__); // REMOVEME
+
+	mutex_lock(&data->input->mutex);
+	if (input_device_enabled(data->input))
+		nvt_ts_stop(data->input);
+	mutex_unlock(&data->input->mutex);
+
+	return 0;
+}
+
+static const struct drm_panel_follower_funcs nvt_ts_follower_funcs = {
+	.panel_prepared = on_novatek_panel_prepared,
+	.panel_unpreparing = on_novatek_panel_unpreparing,
+};
+
+static DEFINE_SIMPLE_DEV_PM_OPS(nvt_ts_pm_ops, nvt_ts_suspend, nvt_ts_resume);
+
+static int nvt_ts_probe(struct i2c_client *client)
+{
+	struct device *dev = &client->dev;
+	struct nvt_ts_data *data;
+
+	if (!client->irq) {
+		dev_err(dev, "Error no irq specified\n");
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->client = client;
+	i2c_set_clientdata(client, data);
+
+	/* check if "panel = <&...>" is set in DT */
+	if (drm_is_panel_follower(dev)) {
+		/* register self as follower */
+		dev_info(dev, "probing in follower mode\n"); // REMOVEME
+		data->is_panel_follower = true;
+		data->panel_follower.funcs = &nvt_ts_follower_funcs;
+		drm_panel_add_follower(dev, &data->panel_follower);
+		/*
+		 * In this mode, we can't do anything more at this moment.
+		 * Need to wait for callbacks from panel.
+		 */
+		return 0;
+	}
+
+	dev_info(dev, "probing in normal mode\n"); // REMOVEME
+	return nvt_ts_initial_power_on_and_register_inputdev(data);
+}
+
+static void nvt_ts_remove(struct i2c_client *client)
+{
+	struct nvt_ts_data *data = i2c_get_clientdata(client);
+
+	if (data->is_panel_follower)
+		drm_panel_remove_follower(&data->panel_follower);
+}
+
 static const struct nvt_ts_i2c_chip_data nvt_nt11205_ts_data = {
 	.wake_type = 0x05,
 	.chip_id = 0x05,
@@ -344,6 +431,7 @@ static struct i2c_driver nvt_ts_driver = {
 		.of_match_table = nvt_ts_of_match,
 	},
 	.probe = nvt_ts_probe,
+	.remove = nvt_ts_remove,
 	.id_table = nvt_ts_i2c_id,
 };