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VuTuLan opened this issue Apr 16, 2025 · 0 comments
Open

srsUE can't attach to srsGNB #1167

VuTuLan opened this issue Apr 16, 2025 · 0 comments

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@VuTuLan
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VuTuLan commented Apr 16, 2025

In my project I used srsGNB with srsUE over-the-air and it worked but for some reason the UE could not connect to the network. Here is the image I ran in the project:
--== srsRAN gNB (commit 2be82d8) ==--

Lower PHY in quad executor mode.
Available radio types: uhd.
[INFO] [UHD] linux; GNU C++ version 13.3.0; Boost_108300; UHD_4.7.0.0-0-ga5ed1872
[INFO] [LOGGING] Fastpath logging disabled at runtime.
Making USRP object with args 'type=n3xx,addr=192.168.180.93,master_clock_rate=245.76e6,send_frame_size=8000,recv_frame_size=8000'
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[INFO] [MPMD] Initializing 1 device(s) in parallel with args: mgmt_addr=192.168.180.93,type=n3xx,product=n320,serial=32550F9,name=ni-n3xx-32550F9,fpga=HG,claimed=False,addr=192.168.180.93,master_clock_rate=245.76e6,send_frame_size=8000,recv_frame_size=8000
[DEBUG] [MPMD] Claiming mboard 0
[DEBUG] [MPMD] Device args: mgmt_addr=[192.168.180.93](http://192.168.180.93/),type=n3xx,product=n320,serial=32550F9,name=ni-n3xx-32550F9,fpga=HG,claimed=False,addr=[192.168.180.93](http://192.168.180.93/),master_clock_rate=245.76e6,send_frame_size=8000,recv_frame_size=8000'. RPC address: [192.168.180.93](http://192.168.180.93/) [DEBUG] [MPMD] MPM reports device info: addr=[192.168.180.93](http://192.168.180.93/),claimed=True,connection=remote,dboard_0_pid=338,dboard_0_serial=3252A13,dboard_1_pid=338,dboard_1_serial=3252A16,description=N300-Series Device,eeprom_version=3,fpga=HG,fpga_version=8.2,fpga_version_hash=c37b318.clean,fs_version=20240628134248,mender_artifact=v4.7.0.0_n3xx,mpm_sw_version=4.7.0.0-ga5ed1872,mpm_version=5.3,name=ni-n3xx-32550F9,pid=16962,product=n320,rev=10,rpc_connection=remote,serial=32550F9,type=n3xx [DEBUG] [MPMD] Found 8 motherboard sensors. [DEBUG] [MPMD] Initializing mboard 0 [DEBUG] [MPMD::MB_IFACE] Adding clock iface radio_clk, frequency: 245.76 MHz, mutable: Yes [DEBUG] [MPMD::MB_IFACE] Adding clock iface bus_clk, frequency: 200 MHz, mutable: No [DEBUG] [MPMD] Path MTU for address [192.168.180.93](http://192.168.180.93/): 1500 [DEBUG] [MPMD] Found 8 motherboard sensors. [DEBUG] [MPMD] Found 2 updateable motherboard components. [DEBUG] [RFNOC::MGMT] Starting topology discovery from device[local]:2/sep:1 [DEBUG] [RFNOC::MGMT] Discovered node device:1/xport:0 [DEBUG] [RFNOC::MGMT] Initialized node device:1/xport:0 [DEBUG] [RFNOC::MGMT] Discovered node device:1/xbar:0 [DEBUG] [RFNOC::MGMT] Initialized node device:1/xbar:0 [INFO] [MPM.PeriphManager] init() called with device args fpga=HG,master_clock_rate=245.76e6,mgmt_addr=192.168.180.93,name=ni-n3xx-32550F9,product=n320,recv_frame_size=8000,send_frame_size=8000,clock_source=internal,time_source=internal'.
[INFO] [MPM.Rhodium-0] init() called with args fpga=HG,master_clock_rate=245.76e6,mgmt_addr=192.168.180.93,name=ni-n3xx-32550F9,product=n320,recv_frame_size=8000,send_frame_size=8000,clock_source=internal,time_source=internal' [INFO] [MPM.Rhodium-1] init() called with args fpga=HG,master_clock_rate=245.76e6,mgmt_addr=192.168.180.93,name=ni-n3xx-32550F9,product=n320,recv_frame_size=8000,send_frame_size=8000,clock_source=internal,time_source=internal'
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:3
[DEBUG] [RFNOC::MGMT] The following endpoints are reachable from device[local]:2/sep:1
[DEBUG] [RFNOC::MGMT] * 1:0
[DEBUG] [RFNOC::MGMT] * 1:1
[DEBUG] [RFNOC::MGMT] * 1:2
[DEBUG] [RFNOC::MGMT] * 1:3
[DEBUG] [RFNOC::GRAPH] Connecting the Host to Endpoint 1:0 through Adapter 0 (0 = no preference)...
[DEBUG] [RFNOC::MGMT] Throttling stream endpoint to 100% (0x0)
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,0) to EPID=2
[DEBUG] [RFNOC] Started thread uhd_ctrl_ep0001 to process messages control messages on EPID 1
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC] Created ctrlport endpoint for port 0 on EPID 1
[DEBUG] [RFNOC::GRAPH] Connection to Endpoint 1:0 completed through Device 2. Using EPIDs 1 -> 2.
[DEBUG] [RFNOC] Created ctrlport endpoint for port 2 on EPID 1
[DEBUG] [0/DUC#0] Checking compat number for FPGA component 0/DUC#0': Expecting 0.1, actual: 0.1. [DEBUG] [0/DUC#0] Loading DUC with 3 halfbands and max CIC interpolation 255 [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#0 (NOC ID=d0c00000) [DEBUG] [RFNOC] Created ctrlport endpoint for port 3 on EPID 1 [DEBUG] [0/DDC#0] Checking compat number for FPGA component 0/DDC#0': Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#0] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#0 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 4 on EPID 1
[DEBUG] [0/Radio#0] Checking compat number for FPGA component 0/Radio#0': Expecting 0.1, actual: 0.1. [DEBUG] [0/Radio#0] Master Clock Rate is: 245.76 MHz. [DEBUG] [LMX2592] Storing register cache completely to LMX via SPI... [DEBUG] [LMX2592] Writing registers complete: Updated 43 registers. [DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI... [DEBUG] [LMX2592] Writing registers complete: Updated 1 registers. [DEBUG] [LMX2592] Storing register cache completely to LMX via SPI... [DEBUG] [LMX2592] Writing registers complete: Updated 43 registers. [DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI... [DEBUG] [LMX2592] Writing registers complete: Updated 1 registers. [DEBUG] [0/Radio#0] LO distribution board is present [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#0 (NOC ID=12ad1000) [DEBUG] [RFNOC] Created ctrlport endpoint for port 5 on EPID 1 [DEBUG] [0/DUC#1] Checking compat number for FPGA component 0/DUC#1': Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#1] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#1 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 6 on EPID 1
[DEBUG] [0/DDC#1] Checking compat number for FPGA component 0/DDC#1': Expecting 0.1, actual: 0.1. [DEBUG] [0/DDC#1] Loading DDC with 3 halfbands and max CIC decimation 255 [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#1 (NOC ID=ddc00000) [DEBUG] [RFNOC] Created ctrlport endpoint for port 7 on EPID 1 [DEBUG] [0/Radio#1] Checking compat number for FPGA component 0/Radio#1': Expecting 0.1, actual: 0.1.
[DEBUG] [0/Radio#1] Master Clock Rate is: 245.76 MHz.
[DEBUG] [LMX2592] Storing register cache completely to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 43 registers.
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 1 registers.
[DEBUG] [LMX2592] Storing register cache completely to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 43 registers.
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 1 registers.
[DEBUG] [0/Radio#1] LO distribution board is NOT present
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#1 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 8 on EPID 1
[DEBUG] [0/Replay#0] Checking compat number for FPGA component `0/Replay#0': Expecting 1.2, actual: 1.2.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Replay#0 (NOC ID=4e91a000)
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#0] Not setting frequency until sampling rate is set.
[DEBUG] [MB_CTRL] Synchronizing 1 timekeepers
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 15 registers.
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 1 registers.
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 1 registers.
[DEBUG] [0/Radio#0] Loading any available frontend corrections for TX at 1.8425e+09
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 15 registers.
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 1 registers.
[DEBUG] [LMX2592] Storing register cache selectively to LMX via SPI...
[DEBUG] [LMX2592] Writing registers complete: Updated 1 registers.
[DEBUG] [0/Radio#0] Loading any available frontend corrections for RX at 1.7475e+09
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: fc32
Num inputs: 1
Output format: sc16_chdr
Num outputs: 1
Using best available prio: 3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=3 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Established a route from EPID=3 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Finished TX stream setup for EPID=2
[DEBUG] [MULTI_USRP] Inconsistent TX rates when creating streamer! Harmonizing to 7.68e+06
[WARNING] [0/Radio#0] Attempting to set tick rate to 0. Skipping.
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: sc16_chdr
Num inputs: 1
Output format: fc32
Num outputs: 1
Using best available prio: 3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=4 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Throttling stream endpoint to 100% (0x0)
[DEBUG] [RFNOC::MGMT] Initiated RX stream setup for EPID=2
[DEBUG] [RFNOC::MGMT] Finished RX stream setup for EPID=2
[DEBUG] [0/Radio#0] spp value 2032 exceeds MTU of 1500! Coercing to 371
Cell pci=1, bw=5 MHz, 1T1R, dl_arfcn=368500 (n3), dl_freq=1842.5 MHz, dl_ssb_arfcn=368410, ul_freq=1747.5 MHz

N2: Connection to AMF on 127.0.0.2:38412 completed

and run srsUE:
Active RF plugins: libsrsran_rf_uhd.so libsrsran_rf_zmq.so
Inactive RF plugins:
Reading configuration file ue.cf...

Built in Release mode using commit ec29b0c1f on branch master.

Opening 1 channels in RF device=uhd with args=type=n3xx,addr=192.168.180.94,master_clock_rate=245.76e6,clock_source=internal,send_frame_size=8000,recv_frame_size=8000
Supported RF device list: UHD zmq file
[INFO] [UHD] linux; GNU C++ version 11.4.0; Boost_107400; UHD_4.7.0.0-0-ga5ed1872
Opening USRP channels=1, args: type=n3xx,addr=192.168.180.94,master_clock_rate=245.76e6,clock_source=internal,send_frame_size=8000,recv_frame_size=8000
[INFO] [LOGGING] Fastpath logging disabled at runtime.
[INFO] [UHD RF] RF UHD Generic instance constructed
[INFO] [MPMD] Initializing 1 device(s) in parallel with args: mgmt_addr=192.168.180.94,type=n3xx,product=n320,serial=32550F7,name=ni-n3xx-32550F7,fpga=HG,claimed=False,addr=192.168.180.94,master_clock_rate=245.76e6,clock_source=internal,send_frame_size=8000,recv_frame_size=8000
[INFO] [MPM.PeriphManager] init() called with device args clock_source=internal,fpga=HG,master_clock_rate=245.76e6,mgmt_addr=192.168.180.94,name=ni-n3xx-32550F7,product=n320,recv_frame_size=8000,send_frame_size=8000,time_source=internal'. [INFO] [MPM.Rhodium-0] init() called with args clock_source=internal,fpga=HG,master_clock_rate=245.76e6,mgmt_addr=192.168.180.94,name=ni-n3xx-32550F7,product=n320,recv_frame_size=8000,send_frame_size=8000,time_source=internal'
[INFO] [MPM.Rhodium-1] init() called with args `clock_source=internal,fpga=HG,master_clock_rate=245.76e6,mgmt_addr=192.168.180.94,name=ni-n3xx-32550F7,product=n320,recv_frame_size=8000,send_frame_size=8000,time_source=internal'
Setting manual TX/RX offset to 300 samples
Waiting PHY to initialize ... done!
Attaching UE...
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=7374
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=7534
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=7694
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=7854
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=8014
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=8174
Random Access Transmission: prach_occasion=0, preamble_index=0, ra-rnti=0x39, tti=8334
someone help me !

ue.config file:
rf]
freq_offset = 0
tx_gain = 60
rx_gain = 60
srate = 7.68e6
nof_antennas = 1

device_args = type=n3xx,addr=192.168.180.94,master_clock_rate=245.76e6,clock_source=internal,send_frame_size=8000,recv_frame_size=8000
device_name = uhd
time_adv_nsamples = 300
continuous_tx = auto

[expert]
lte_sample_rates = true

[rat.eutra]
dl_earfcn = 3400
nof_carriers = 0

[rat.nr]
bands = 3
nof_carriers = 1
max_nof_prb = 25
nof_prb = 25

[pcap]
enable = none
mac_filename = /tmp/ue_mac.pcap
mac_nr_filename = /tmp/ue_mac_nr.pcap
nas_filename = /tmp/ue_nas.pcap

[log]
all_level = debug
phy_lib_level = debug
all_hex_limit = 32
filename =/tmp/ue.log
file_max_size = -1

[usim]
mode = soft
algo = milenage
opc = 63BFA50EE6523365FF14C1F45F88737D
k = 00112233445566778899aabbccddeeff
imsi = 001010123456780
imei = 353490069873319

[rrc]
ue_category = 4
release = 15

[nas]
apn = srsapn
apn_protocol = ipv4

[gui]
enable = true

gnb config file:
cu_cp:
amf:
addr: 127.0.0.2
port: 38412
bind_addr: 127.0.1.1
supported_tracking_areas:
- tac: 7
plmn_list:
- plmn: "00101"
tai_slice_support_list:
- sst: 1

ru_sdr:
device_driver: uhd
device_args: type=n3xx,addr=192.168.180.93,master_clock_rate=245.76e6,send_frame_size=8000,recv_frame_size=8000
time_alignment_calibration: 0 # This will set an offset of -170 samples
srate: 7.68
tx_gain: 60
rx_gain: 60

cell_cfg:
dl_arfcn: 368500
band: 3
channel_bandwidth_MHz: 5
common_scs: 15
plmn: "00101"
tac: 7
pdcch:
dedicated:
ss2_type: common
dci_format_0_1_and_1_1: false
common:
ss0_index: 0
coreset0_index: 0
prach:
prach_config_index: 1
ra_resp_window: 8
pdsch:
mcs_table: qam64
pucch:
f0_or_f1_nof_cell_res_sr: 2
f2_or_f3_or_f4_nof_cell_res_csi: 2
ssb:
ssb_period: 10 # Optional UINT (10). Sets the period of SSB scheduling in milliseconds. Supported: [5, 10, 20].
ssb_block_power_dbm: -16 # Optional INT (-16). Sets the SS PBCH block power in dBm. Supported: [-60 - +50].
pss_to_sss_epre_db: 0 # Optional UINT (0). Sets the Synchronization Signal Block Primary Synchronization Signal to Secondary Synchronization Signal Energy Per Re>

log:
filename: /tmp/gnb.log
all_level: debug

pcap:
mac_enable: enable
mac_filename: /tmp/gnb_mac.pcap
ngap_enable: enable
ngap_filename: /tmp/gnb_ngap.pcap

UE.log

gnb.log
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