How to configure asynchronous reset #2098
Comments
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The reset pin into the ChipTop is asynchronous w.r.t. any other clock inputs. A reset synchronizer sync's that reset to the clock for the digital logic. |
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Thank you for your reply, but if I wish to remove the synchronization tool for chiptop. Because I hope to ultimately obtain a digital top system with asynchronous reset. |
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This isn't well supported anymore. To support the complexity of the clocking and reset network for a multi-clock-domain SoC, it was necessary to move to global synchronous reset. Reverting that would be a very invasive change. Could you describe why you need asynchronous reset for all the digital logic? |
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Because our project requires this project as a sub IP, but we only use the Digital level |
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Also, may I ask if I can generate a system with Digital as the top-level separately |
Users can now use the `WithAsyncClockGroups` config fragment to coerce certain clock groups to use an asynchronous reset. Note that users will likely also want to use the new `WithAsyncResetRocketSubsystem` config fragment, which ensures the Rocket Chip Debug Module also uses an async reset. Omitting this will lead to signals being driven by both sync and async resets, which will cause `firtool` compilation errors. The new `AsyncResetRocketConfig` config demonstrates this. Note that it doesn't use async reset for the Rocket Tile itself (just the uncore), as the Rocket Tile doesn't support async resets (it's hard-coded to use synchronous resets). Resolves ucb-bar#2098.
Users can now use the `WithAsyncClockGroups` config fragment to coerce certain clock groups to use an asynchronous reset. Note that users will likely also want to use the new `WithAsyncResetRocketSubsystem` config fragment, which ensures the Rocket Chip Debug Module also uses an async reset. Omitting this will lead to signals being driven by both sync and async resets, which will cause `firtool` compilation errors. The new `AsyncResetRocketConfig` config demonstrates this. Note that it doesn't use async reset for the Rocket Tile itself (just the uncore), as the Rocket Tile doesn't support async resets (it's hard-coded to use synchronous resets). Resolves ucb-bar#2098.
Background Work
Feature Description
Hello, I have encountered some questions and would like to seek advice. At present, the RTL I generate under chipyard is synchronously reset. I hope to generate an asynchronous reset system. Are there any configuration options that can be modified？
Motivating Example
Hello, I have encountered some questions and would like to seek advice. At present, the RTL I generate under chipyard is synchronously reset. I hope to generate an asynchronous reset system. Are there any configuration options that can be modified？
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