diff --git a/CMSIS/AmbiqMicro/Include/apollo2.h b/CMSIS/AmbiqMicro/Include/apollo2.h new file mode 100644 index 0000000..aa81337 --- /dev/null +++ b/CMSIS/AmbiqMicro/Include/apollo2.h @@ -0,0 +1,14326 @@ +/* + * Copyright (c) 2020, Ambiq Micro, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file apollo2.h + * @brief CMSIS HeaderFile + * @version 1.0 + * @date 05. March 2020 + * @note Generated by SVDConv V3.3.27 on Thursday, 05.03.2020 15:24:57 + * from File './apollo2.svd', + * last modified on Thursday, 05.03.2020 21:24:57 + */ + + + +/** @addtogroup Ambiq Micro + * @{ + */ + + +/** @addtogroup apollo2 + * @{ + */ + + +#ifndef APOLLO2_H +#define APOLLO2_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== apollo2 Specific Interrupt Numbers =========================================== */ + BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT */ + WDT_IRQn = 1, /*!< 1 WDT */ + CLKGEN_RTC_IRQn = 2, /*!< 2 CLKGEN_RTC */ + VCOMP_IRQn = 3, /*!< 3 VCOMP */ + IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE */ + IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC */ + IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 */ + IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 */ + IOMSTR2_IRQn = 8, /*!< 8 IOMSTR2 */ + IOMSTR3_IRQn = 9, /*!< 9 IOMSTR3 */ + IOMSTR4_IRQn = 10, /*!< 10 IOMSTR4 */ + IOMSTR5_IRQn = 11, /*!< 11 IOMSTR5 */ + GPIO_IRQn = 12, /*!< 12 GPIO */ + CTIMER_IRQn = 13, /*!< 13 CTIMER */ + UART0_IRQn = 14, /*!< 14 UART0 */ + UART1_IRQn = 15, /*!< 15 UART1 */ + ADC_IRQn = 16, /*!< 16 ADC */ + PDM_IRQn = 17, /*!< 17 PDM */ + STIMER_IRQn = 18, /*!< 18 STIMER */ + STIMER_CMPR0_IRQn = 19, /*!< 19 STIMER_CMPR0 */ + STIMER_CMPR1_IRQn = 20, /*!< 20 STIMER_CMPR1 */ + STIMER_CMPR2_IRQn = 21, /*!< 21 STIMER_CMPR2 */ + STIMER_CMPR3_IRQn = 22, /*!< 22 STIMER_CMPR3 */ + STIMER_CMPR4_IRQn = 23, /*!< 23 STIMER_CMPR4 */ + STIMER_CMPR5_IRQn = 24, /*!< 24 STIMER_CMPR5 */ + STIMER_CMPR6_IRQn = 25, /*!< 25 STIMER_CMPR6 */ + STIMER_CMPR7_IRQn = 26 /*!< 26 STIMER_CMPR7 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0100U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_apollo2.h" /*!< apollo2 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog Digital Converter Control (ADC) + */ + +typedef struct { /*!< (@ 0x50010000) ADC Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t ADCEN : 1; /*!< [0..0] This bit enables the ADC module. While the ADC is enabled, + the ADCCFG and SLOT Configuration regsiter settings must + remain stable and unchanged. All configuration register + settings, slot configuration settings and window comparison + settings should be written prior to setting the ADCEN bit + to '1'. */ + __IM uint32_t : 1; + __IOM uint32_t RPTEN : 1; /*!< [2..2] This bit enables Repeating Scan Mode. */ + __IOM uint32_t LPMODE : 1; /*!< [3..3] Select power mode to enter between active scans. */ + __IOM uint32_t CKMODE : 1; /*!< [4..4] Clock mode register */ + __IM uint32_t : 3; + __IOM uint32_t REFSEL : 2; /*!< [9..8] Select the ADC reference voltage. */ + __IM uint32_t : 6; + __IOM uint32_t TRIGSEL : 3; /*!< [18..16] Select the ADC trigger source. */ + __IOM uint32_t TRIGPOL : 1; /*!< [19..19] This bit selects the ADC trigger polarity for external + off chip triggers. */ + __IM uint32_t : 4; + __IOM uint32_t CLKSEL : 2; /*!< [25..24] Select the source and frequency for the ADC clock. + All values not enumerated below are undefined. */ + } CFG_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) ADC Power Status */ + + struct { + __IOM uint32_t PWDSTAT : 1; /*!< [0..0] Indicates the power-status of the ADC. */ + } STAT_b; + } ; + + union { + __IOM uint32_t SWT; /*!< (@ 0x00000008) Software trigger */ + + struct { + __IOM uint32_t SWT : 8; /*!< [7..0] Writing 0x37 to this register generates a software trigger. */ + } SWT_b; + } ; + + union { + __IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */ + + struct { + __IOM uint32_t SLEN0 : 1; /*!< [0..0] This bit enables slot 0 for ADC conversions. */ + __IOM uint32_t WCEN0 : 1; /*!< [1..1] This bit enables the window compare function for slot + 0. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL0 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE0 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL0 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL0CFG_b; + } ; + + union { + __IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */ + + struct { + __IOM uint32_t SLEN1 : 1; /*!< [0..0] This bit enables slot 1 for ADC conversions. */ + __IOM uint32_t WCEN1 : 1; /*!< [1..1] This bit enables the window compare function for slot + 1. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL1 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE1 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL1 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL1CFG_b; + } ; + + union { + __IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */ + + struct { + __IOM uint32_t SLEN2 : 1; /*!< [0..0] This bit enables slot 2 for ADC conversions. */ + __IOM uint32_t WCEN2 : 1; /*!< [1..1] This bit enables the window compare function for slot + 2. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL2 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE2 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL2 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL2CFG_b; + } ; + + union { + __IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */ + + struct { + __IOM uint32_t SLEN3 : 1; /*!< [0..0] This bit enables slot 3 for ADC conversions. */ + __IOM uint32_t WCEN3 : 1; /*!< [1..1] This bit enables the window compare function for slot + 3. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL3 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE3 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL3 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL3CFG_b; + } ; + + union { + __IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */ + + struct { + __IOM uint32_t SLEN4 : 1; /*!< [0..0] This bit enables slot 4 for ADC conversions. */ + __IOM uint32_t WCEN4 : 1; /*!< [1..1] This bit enables the window compare function for slot + 4. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL4 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE4 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL4 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL4CFG_b; + } ; + + union { + __IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */ + + struct { + __IOM uint32_t SLEN5 : 1; /*!< [0..0] This bit enables slot 5 for ADC conversions. */ + __IOM uint32_t WCEN5 : 1; /*!< [1..1] This bit enables the window compare function for slot + 5. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL5 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE5 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL5 : 3; /*!< [26..24] Select number of measurements to average in the accumulate + divide module for this slot. */ + } SL5CFG_b; + } ; + + union { + __IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */ + + struct { + __IOM uint32_t SLEN6 : 1; /*!< [0..0] This bit enables slot 6 for ADC conversions. */ + __IOM uint32_t WCEN6 : 1; /*!< [1..1] This bit enables the window compare function for slot + 6. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL6 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE6 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL6 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL6CFG_b; + } ; + + union { + __IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */ + + struct { + __IOM uint32_t SLEN7 : 1; /*!< [0..0] This bit enables slot 7 for ADC conversions. */ + __IOM uint32_t WCEN7 : 1; /*!< [1..1] This bit enables the window compare function for slot + 7. */ + __IM uint32_t : 6; + __IOM uint32_t CHSEL7 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + __IM uint32_t : 4; + __IOM uint32_t PRMODE7 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + __IM uint32_t : 6; + __IOM uint32_t ADSEL7 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL7CFG_b; + } ; + + union { + __IOM uint32_t WULIM; /*!< (@ 0x0000002C) Window Comparator Upper Limits Register */ + + struct { + __IOM uint32_t ULIM : 20; /*!< [19..0] Sets the upper limit for the wondow comparator. */ + } WULIM_b; + } ; + + union { + __IOM uint32_t WLLIM; /*!< (@ 0x00000030) Window Comparator Lower Limits Register */ + + struct { + __IOM uint32_t LLIM : 20; /*!< [19..0] Sets the lower limit for the wondow comparator. */ + } WLLIM_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000038) FIFO Data and Valid Count Register */ + + struct { + __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ + __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ + __IOM uint32_t SLOTNUM : 3; /*!< [30..28] Slot number associated with this FIFO data. */ + __IOM uint32_t RSVD : 1; /*!< [31..31] RESERVED. */ + } FIFO_b; + } ; + __IM uint32_t RESERVED1[113]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) ADC Interrupt registers: Enable */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) ADC Interrupt registers: Status */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) ADC Interrupt registers: Clear */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) ADC Interrupt registers: Set */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + } INTSET_b; + } ; +} ADC_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Flash Cache Controller (CACHECTRL) + */ + +typedef struct { /*!< (@ 0x40018000) CACHECTRL Structure */ + + union { + __IOM uint32_t CACHECFG; /*!< (@ 0x00000000) Flash Cache Control Register */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the main flash cache controller logic and enables + power to the cache RAMs. Instruction and Data caching need + to be enabled independently using the ICACHE_ENABLE and + DCACHE_ENABLE bits. */ + __IOM uint32_t LRU : 1; /*!< [1..1] Sets the cache replacement policy. 0=LRR (least recently + replaced), 1=LRU (least recently used). LRR minimizes writes + to the TAG SRAM and is recommended. */ + __IOM uint32_t ENABLE_NC0 : 1; /*!< [2..2] Enable Non-cacheable region 0. See the NCR0 registers + to set the region boundaries and size. */ + __IOM uint32_t ENABLE_NC1 : 1; /*!< [3..3] Enable Non-cacheable region 1. See the NCR1 registers + to set the region boundaries and size. */ + __IOM uint32_t CONFIG : 3; /*!< [6..4] Sets the cache configuration. Only a single configuration + of 0x5 is valid. */ + __IOM uint32_t SERIAL : 1; /*!< [7..7] Bitfield should always be programmed to 0. */ + __IOM uint32_t ICACHE_ENABLE : 1; /*!< [8..8] Enable Flash Instruction Caching. When set to 1, all + instruction accesses to flash will be cached. */ + __IOM uint32_t DCACHE_ENABLE : 1; /*!< [9..9] Enable Flash Data Caching. When set to 1, all instruction + accesses to flash will be cached. */ + __IOM uint32_t CACHE_CLKGATE : 1; /*!< [10..10] Enable clock gating of individual cache RAMs. This + bit should be enabled for normal operation for lowest power + consumption. */ + __IOM uint32_t CACHE_LS : 1; /*!< [11..11] Enable LS (light sleep) of cache RAMs. This should + not be enabled for normal operation. When this bit is set, + the cache's RAMS will be put into light sleep mode while + inactive. NOTE: if the cache is actively used, this may + have an adverse affect on power since entering/exiting + LS mode may consume more power than would be saved. */ + __IOM uint32_t DLY : 4; /*!< [15..12] Unused. Should be left at default value. */ + __IOM uint32_t SMDLY : 4; /*!< [19..16] Unused. Should be left at default value. */ + __IOM uint32_t DATA_CLKGATE : 1; /*!< [20..20] Enable clock gating of entire cache data array subsystem. + This should be enabled for normal operation. */ + __IM uint32_t : 3; + __IOM uint32_t ENABLE_MONITOR : 1; /*!< [24..24] Enable Cache Monitoring Stats. Only enable this for + debug/performance analysis since it will consume additional + power. See IMON/DMON registers for data. */ + } CACHECFG_b; + } ; + + union { + __IOM uint32_t FLASHCFG; /*!< (@ 0x00000004) Flash Control Register */ + + struct { + __IOM uint32_t RD_WAIT : 3; /*!< [2..0] Sets read waitstates for flash accesses (in clock cycles). + This should be left at the default value for normal flash + operation. */ + } FLASHCFG_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Cache Control */ + + struct { + __IOM uint32_t INVALIDATE : 1; /*!< [0..0] Writing a 1 to this bitfield invalidates the flash cache + contents. */ + __IOM uint32_t RESET_STAT : 1; /*!< [1..1] Writing a 1 to this bitfield will reset the cache monitor + statistics (DMON0-3, IMON0-3). Statistic gathering can + be paused/stopped by disabling the MONITOR_ENABLE bit in + CACHECFG, which will maintain the count values until the + stats are reset by writing this bitfield. */ + __IOM uint32_t CACHE_READY : 1; /*!< [2..2] Cache Ready Status. A value of 1 indicates the cache + is enabled and not processing an invalidate operation. */ + __IM uint32_t : 1; + __IOM uint32_t FLASH0_SLM_STATUS : 1; /*!< [4..4] Flash Sleep Mode Status. When 1, flash instance 0 is + asleep. */ + __IOM uint32_t FLASH0_SLM_DISABLE : 1; /*!< [5..5] Disable Flash Sleep Mode. Allows CPU to manually disable + SLM mode. Performing a flash read will also wake the array. */ + __IOM uint32_t FLASH0_SLM_ENABLE : 1; /*!< [6..6] Enable Flash Sleep Mode. After writing this bit, the + flash instance 0 will enter a low-power mode until the + CPU writes the SLM_DISABLE bit or a flash access occurs. + Wake from SLM requires ~5us, so this should only be set + if the flash will not be accessed for reasonably long time. */ + __IM uint32_t : 1; + __IOM uint32_t FLASH1_SLM_STATUS : 1; /*!< [8..8] Flash Sleep Mode Status. When 1, flash instance 1 is + asleep. */ + __IOM uint32_t FLASH1_SLM_DISABLE : 1; /*!< [9..9] Disable Flash Sleep Mode. Allows CPU to manually disable + SLM mode. Performing a flash read will also wake the array. */ + __IOM uint32_t FLASH1_SLM_ENABLE : 1; /*!< [10..10] Enable Flash Sleep Mode. After writing this bit, the + flash instance 1 will enter a low-power mode until the + CPU writes the SLM_DISABLE bit or a flash access occurs. + Wake from SLM requires ~5us, so this should only be set + if the flash will not be accessed for reasonably long time. */ + } CTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t NCR0START; /*!< (@ 0x00000010) Flash Cache Noncachable Region 0 Start Address. */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t ADDR : 16; /*!< [19..4] Start address for non-cacheable region 0. The physical + address of the start of this region should be programmed + to this register and must be aligned to a 16-byte boundary + (thus the lower 4 address bits are unused). */ + } NCR0START_b; + } ; + + union { + __IOM uint32_t NCR0END; /*!< (@ 0x00000014) Flash Cache Noncachable Region 0 End */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t ADDR : 16; /*!< [19..4] End address for non-cacheable region 0. The physical + address of the end of this region should be programmed + to this register and must be aligned to a 16-byte boundary + (thus the lower 4 address bits are unused). */ + } NCR0END_b; + } ; + + union { + __IOM uint32_t NCR1START; /*!< (@ 0x00000018) Flash Cache Noncachable Region 1 Start */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t ADDR : 16; /*!< [19..4] Start address for non-cacheable region 1. The physical + address of the start of this region should be programmed + to this register and must be aligned to a 16-byte boundary + (thus the lower 4 address bits are unused). */ + } NCR1START_b; + } ; + + union { + __IOM uint32_t NCR1END; /*!< (@ 0x0000001C) Flash Cache Noncachable Region 1 End */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t ADDR : 16; /*!< [19..4] End address for non-cacheable region 1. The physical + address of the end of this region should be programmed + to this register and must be aligned to a 16-byte boundary + (thus the lower 4 address bits are unused). */ + } NCR1END_b; + } ; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t CACHEMODE; /*!< (@ 0x00000030) Flash Cache Mode Register. Used to trim performance/power. */ + + struct { + __IOM uint32_t THROTTLE1 : 1; /*!< [0..0] Disallow cache data RAM writes on tag RAM fill cycles. + Value should be left at zero for optimal performance. */ + __IOM uint32_t THROTTLE2 : 1; /*!< [1..1] Disallow cache data RAM writes on tag RAM read cycles. + Value should be left at zero for optimal performance. */ + __IOM uint32_t THROTTLE3 : 1; /*!< [2..2] Disallow cache data RAM writes on data RAM read cycles. + Value should be left at zero for optimal performance. */ + __IOM uint32_t THROTTLE4 : 1; /*!< [3..3] Disallow Data RAM reads (from line hits) on tag RAM fill + cycles. Value should be left at zero for optimal performance. */ + __IOM uint32_t THROTTLE5 : 1; /*!< [4..4] Disallow Data RAM reads (from line hits) during lookup + read ops. Value should be left at zero for optimal performance. */ + __IOM uint32_t THROTTLE6 : 1; /*!< [5..5] Disallow Simultaneous Data RAM reads (from 2 line hits + on each bus). Value should be left at zero for optimal + performance. */ + } CACHEMODE_b; + } ; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t DMON0; /*!< (@ 0x00000040) Data Cache Total Accesses */ + + struct { + __IOM uint32_t DACCESS_COUNT : 32; /*!< [31..0] Total accesses to data cache */ + } DMON0_b; + } ; + + union { + __IOM uint32_t DMON1; /*!< (@ 0x00000044) Data Cache Tag Lookups */ + + struct { + __IOM uint32_t DLOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from data cache */ + } DMON1_b; + } ; + + union { + __IOM uint32_t DMON2; /*!< (@ 0x00000048) Data Cache Hits */ + + struct { + __IOM uint32_t DHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations */ + } DMON2_b; + } ; + + union { + __IOM uint32_t DMON3; /*!< (@ 0x0000004C) Data Cache Line Hits */ + + struct { + __IOM uint32_t DLINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ + } DMON3_b; + } ; + + union { + __IOM uint32_t IMON0; /*!< (@ 0x00000050) Instruction Cache Total Accesses */ + + struct { + __IOM uint32_t IACCESS_COUNT : 32; /*!< [31..0] Total accesses to Instruction cache */ + } IMON0_b; + } ; + + union { + __IOM uint32_t IMON1; /*!< (@ 0x00000054) Instruction Cache Tag Lookups */ + + struct { + __IOM uint32_t ILOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from Instruction cache */ + } IMON1_b; + } ; + + union { + __IOM uint32_t IMON2; /*!< (@ 0x00000058) Instruction Cache Hits */ + + struct { + __IOM uint32_t IHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations */ + } IMON2_b; + } ; + + union { + __IOM uint32_t IMON3; /*!< (@ 0x0000005C) Instruction Cache Line Hits */ + + struct { + __IOM uint32_t ILINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ + } IMON3_b; + } ; +} CACHECTRL_Type; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock Generator (CLKGEN) + */ + +typedef struct { /*!< (@ 0x40004000) CLKGEN Structure */ + + union { + __IOM uint32_t CALXT; /*!< (@ 0x00000000) XT Oscillator Control */ + + struct { + __IOM uint32_t CALXT : 11; /*!< [10..0] XT Oscillator calibration value */ + } CALXT_b; + } ; + + union { + __IOM uint32_t CALRC; /*!< (@ 0x00000004) RC Oscillator Control */ + + struct { + __IOM uint32_t CALRC : 18; /*!< [17..0] LFRC Oscillator calibration value */ + } CALRC_b; + } ; + + union { + __IOM uint32_t ACALCTR; /*!< (@ 0x00000008) Autocalibration Counter */ + + struct { + __IOM uint32_t ACALCTR : 24; /*!< [23..0] Autocalibration Counter result. */ + } ACALCTR_b; + } ; + + union { + __IOM uint32_t OCTRL; /*!< (@ 0x0000000C) Oscillator Control */ + + struct { + __IOM uint32_t STOPXT : 1; /*!< [0..0] Stop the XT Oscillator to the RTC */ + __IOM uint32_t STOPRC : 1; /*!< [1..1] Stop the LFRC Oscillator to the RTC */ + __IM uint32_t : 4; + __IOM uint32_t FOS : 1; /*!< [6..6] Oscillator switch on failure function */ + __IOM uint32_t OSEL : 1; /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT) */ + __IOM uint32_t ACAL : 3; /*!< [10..8] Autocalibration control */ + } OCTRL_b; + } ; + + union { + __IOM uint32_t CLKOUT; /*!< (@ 0x00000010) CLKOUT Frequency Select */ + + struct { + __IOM uint32_t CKSEL : 6; /*!< [5..0] CLKOUT signal select. Note that HIGH_DRIVE should be + selected if any high frequencies (such as from HFRC) are + selected for CLKOUT. */ + __IM uint32_t : 1; + __IOM uint32_t CKEN : 1; /*!< [7..7] Enable the CLKOUT signal */ + } CLKOUT_b; + } ; + + union { + __IOM uint32_t CLKKEY; /*!< (@ 0x00000014) Key Register for Clock Control Register */ + + struct { + __IOM uint32_t CLKKEY : 32; /*!< [31..0] Key register value. */ + } CLKKEY_b; + } ; + + union { + __IOM uint32_t CCTRL; /*!< (@ 0x00000018) HFRC Clock Control */ + + struct { + __IOM uint32_t CORESEL : 1; /*!< [0..0] Core Clock divisor */ + } CCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x0000001C) Clock Generator Status */ + + struct { + __IOM uint32_t OMODE : 1; /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT) */ + __IOM uint32_t OSCF : 1; /*!< [1..1] XT Oscillator is enabled but not oscillating */ + } STATUS_b; + } ; + + union { + __IOM uint32_t HFADJ; /*!< (@ 0x00000020) HFRC Adjustment */ + + struct { + __IOM uint32_t HFADJEN : 1; /*!< [0..0] HFRC adjustment control */ + __IOM uint32_t HFADJCK : 3; /*!< [3..1] Repeat period for HFRC adjustment */ + __IM uint32_t : 4; + __IOM uint32_t HFXTADJ : 12; /*!< [19..8] Target HFRC adjustment value. */ + __IOM uint32_t HFWARMUP : 1; /*!< [20..20] XT warmup period for HFRC adjustment */ + __IOM uint32_t HFADJ_GAIN : 3; /*!< [23..21] Gain control for HFRC adjustment */ + } HFADJ_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CLOCKEN; /*!< (@ 0x00000028) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN : 32; /*!< [31..0] Clock enable status */ + } CLOCKEN_b; + } ; + + union { + __IOM uint32_t CLOCKEN2; /*!< (@ 0x0000002C) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN2 : 32; /*!< [31..0] Clock enable status 2 */ + } CLOCKEN2_b; + } ; + + union { + __IOM uint32_t CLOCKEN3; /*!< (@ 0x00000030) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN3 : 32; /*!< [31..0] Clock enable status 3 */ + } CLOCKEN3_b; + } ; + + union { + __IOM uint32_t UARTEN; /*!< (@ 0x00000034) UART Enable */ + + struct { + __IOM uint32_t UART0EN : 2; /*!< [1..0] UART0 system clock control */ + __IM uint32_t : 6; + __IOM uint32_t UART1EN : 2; /*!< [9..8] UART1 system clock control */ + } UARTEN_b; + } ; + __IM uint32_t RESERVED1[50]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000100) CLKGEN Interrupt Register: Enable */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000104) CLKGEN Interrupt Register: Status */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000108) CLKGEN Interrupt Register: Clear */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000010C) CLKGEN Interrupt Register: Set */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTSET_b; + } ; +} CLKGEN_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Counter/Timer (CTIMER) + */ + +typedef struct { /*!< (@ 0x40008000) CTIMER Structure */ + + union { + __IOM uint32_t TMR0; /*!< (@ 0x00000000) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA0 : 16; /*!< [15..0] Counter/Timer A0. */ + __IOM uint32_t CTTMRB0 : 16; /*!< [31..16] Counter/Timer B0. */ + } TMR0_b; + } ; + + union { + __IOM uint32_t CMPRA0; /*!< (@ 0x00000004) Counter/Timer A0 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR1A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper + limit for timer half A. */ + } CMPRA0_b; + } ; + + union { + __IOM uint32_t CMPRB0; /*!< (@ 0x00000008) Counter/Timer B0 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR1B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper + limit for timer half B. */ + } CMPRB0_b; + } ; + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x0000000C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA0EN : 1; /*!< [0..0] Counter/Timer A0 Enable bit. */ + __IOM uint32_t TMRA0CLK : 5; /*!< [5..1] Counter/Timer A0 Clock Select. */ + __IOM uint32_t TMRA0FN : 3; /*!< [8..6] Counter/Timer A0 Function Select. */ + __IOM uint32_t TMRA0IE0 : 1; /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA0IE1 : 1; /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA0CLR : 1; /*!< [11..11] Counter/Timer A0 Clear bit. */ + __IOM uint32_t TMRA0POL : 1; /*!< [12..12] Counter/Timer A0 output polarity. */ + __IOM uint32_t TMRA0PE : 1; /*!< [13..13] Counter/Timer A0 Output Enable bit. */ + __IM uint32_t : 2; + __IOM uint32_t TMRB0EN : 1; /*!< [16..16] Counter/Timer B0 Enable bit. */ + __IOM uint32_t TMRB0CLK : 5; /*!< [21..17] Counter/Timer B0 Clock Select. */ + __IOM uint32_t TMRB0FN : 3; /*!< [24..22] Counter/Timer B0 Function Select. */ + __IOM uint32_t TMRB0IE0 : 1; /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB0IE1 : 1; /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB0CLR : 1; /*!< [27..27] Counter/Timer B0 Clear bit. */ + __IOM uint32_t TMRB0POL : 1; /*!< [28..28] Counter/Timer B0 output polarity. */ + __IOM uint32_t TMRB0PE : 1; /*!< [29..29] Counter/Timer B0 Output Enable bit. */ + __IM uint32_t : 1; + __IOM uint32_t CTLINK0 : 1; /*!< [31..31] Counter/Timer A0/B0 Link bit. */ + } CTRL0_b; + } ; + + union { + __IOM uint32_t TMR1; /*!< (@ 0x00000010) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA1 : 16; /*!< [15..0] Counter/Timer A1. */ + __IOM uint32_t CTTMRB1 : 16; /*!< [31..16] Counter/Timer B1. */ + } TMR1_b; + } ; + + union { + __IOM uint32_t CMPRA1; /*!< (@ 0x00000014) Counter/Timer A1 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 0. */ + __IOM uint32_t CMPR1A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 1. */ + } CMPRA1_b; + } ; + + union { + __IOM uint32_t CMPRB1; /*!< (@ 0x00000018) Counter/Timer B1 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 0. */ + __IOM uint32_t CMPR1B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 1. */ + } CMPRB1_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x0000001C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA1EN : 1; /*!< [0..0] Counter/Timer A1 Enable bit. */ + __IOM uint32_t TMRA1CLK : 5; /*!< [5..1] Counter/Timer A1 Clock Select. */ + __IOM uint32_t TMRA1FN : 3; /*!< [8..6] Counter/Timer A1 Function Select. */ + __IOM uint32_t TMRA1IE0 : 1; /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA1IE1 : 1; /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA1CLR : 1; /*!< [11..11] Counter/Timer A1 Clear bit. */ + __IOM uint32_t TMRA1POL : 1; /*!< [12..12] Counter/Timer A1 output polarity. */ + __IOM uint32_t TMRA1PE : 1; /*!< [13..13] Counter/Timer A1 Output Enable bit. */ + __IM uint32_t : 2; + __IOM uint32_t TMRB1EN : 1; /*!< [16..16] Counter/Timer B1 Enable bit. */ + __IOM uint32_t TMRB1CLK : 5; /*!< [21..17] Counter/Timer B1 Clock Select. */ + __IOM uint32_t TMRB1FN : 3; /*!< [24..22] Counter/Timer B1 Function Select. */ + __IOM uint32_t TMRB1IE0 : 1; /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB1IE1 : 1; /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB1CLR : 1; /*!< [27..27] Counter/Timer B1 Clear bit. */ + __IOM uint32_t TMRB1POL : 1; /*!< [28..28] Counter/Timer B1 output polarity. */ + __IOM uint32_t TMRB1PE : 1; /*!< [29..29] Counter/Timer B1 Output Enable bit. */ + __IM uint32_t : 1; + __IOM uint32_t CTLINK1 : 1; /*!< [31..31] Counter/Timer A1/B1 Link bit. */ + } CTRL1_b; + } ; + + union { + __IOM uint32_t TMR2; /*!< (@ 0x00000020) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA2 : 16; /*!< [15..0] Counter/Timer A2. */ + __IOM uint32_t CTTMRB2 : 16; /*!< [31..16] Counter/Timer B2. */ + } TMR2_b; + } ; + + union { + __IOM uint32_t CMPRA2; /*!< (@ 0x00000024) Counter/Timer A2 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 0. */ + __IOM uint32_t CMPR1A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 1. */ + } CMPRA2_b; + } ; + + union { + __IOM uint32_t CMPRB2; /*!< (@ 0x00000028) Counter/Timer B2 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 0. */ + __IOM uint32_t CMPR1B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 1. */ + } CMPRB2_b; + } ; + + union { + __IOM uint32_t CTRL2; /*!< (@ 0x0000002C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA2EN : 1; /*!< [0..0] Counter/Timer A2 Enable bit. */ + __IOM uint32_t TMRA2CLK : 5; /*!< [5..1] Counter/Timer A2 Clock Select. */ + __IOM uint32_t TMRA2FN : 3; /*!< [8..6] Counter/Timer A2 Function Select. */ + __IOM uint32_t TMRA2IE0 : 1; /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA2IE1 : 1; /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA2CLR : 1; /*!< [11..11] Counter/Timer A2 Clear bit. */ + __IOM uint32_t TMRA2POL : 1; /*!< [12..12] Counter/Timer A2 output polarity. */ + __IOM uint32_t TMRA2PE : 1; /*!< [13..13] Counter/Timer A2 Output Enable bit. */ + __IM uint32_t : 2; + __IOM uint32_t TMRB2EN : 1; /*!< [16..16] Counter/Timer B2 Enable bit. */ + __IOM uint32_t TMRB2CLK : 5; /*!< [21..17] Counter/Timer B2 Clock Select. */ + __IOM uint32_t TMRB2FN : 3; /*!< [24..22] Counter/Timer B2 Function Select. */ + __IOM uint32_t TMRB2IE0 : 1; /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB2IE1 : 1; /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB2CLR : 1; /*!< [27..27] Counter/Timer B2 Clear bit. */ + __IOM uint32_t TMRB2POL : 1; /*!< [28..28] Counter/Timer B2 output polarity. */ + __IOM uint32_t TMRB2PE : 1; /*!< [29..29] Counter/Timer B2 Output Enable bit. */ + __IM uint32_t : 1; + __IOM uint32_t CTLINK2 : 1; /*!< [31..31] Counter/Timer A2/B2 Link bit. */ + } CTRL2_b; + } ; + + union { + __IOM uint32_t TMR3; /*!< (@ 0x00000030) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA3 : 16; /*!< [15..0] Counter/Timer A3. */ + __IOM uint32_t CTTMRB3 : 16; /*!< [31..16] Counter/Timer B3. */ + } TMR3_b; + } ; + + union { + __IOM uint32_t CMPRA3; /*!< (@ 0x00000034) Counter/Timer A3 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 0. */ + __IOM uint32_t CMPR1A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 1. */ + } CMPRA3_b; + } ; + + union { + __IOM uint32_t CMPRB3; /*!< (@ 0x00000038) Counter/Timer B3 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ + __IOM uint32_t CMPR1B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ + } CMPRB3_b; + } ; + + union { + __IOM uint32_t CTRL3; /*!< (@ 0x0000003C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA3EN : 1; /*!< [0..0] Counter/Timer A3 Enable bit. */ + __IOM uint32_t TMRA3CLK : 5; /*!< [5..1] Counter/Timer A3 Clock Select. */ + __IOM uint32_t TMRA3FN : 3; /*!< [8..6] Counter/Timer A3 Function Select. */ + __IOM uint32_t TMRA3IE0 : 1; /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA3IE1 : 1; /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA3CLR : 1; /*!< [11..11] Counter/Timer A3 Clear bit. */ + __IOM uint32_t TMRA3POL : 1; /*!< [12..12] Counter/Timer A3 output polarity. */ + __IOM uint32_t TMRA3PE : 1; /*!< [13..13] Counter/Timer A3 Output Enable bit. */ + __IM uint32_t : 1; + __IOM uint32_t ADCEN : 1; /*!< [15..15] Special Timer A3 enable for ADC function. */ + __IOM uint32_t TMRB3EN : 1; /*!< [16..16] Counter/Timer B3 Enable bit. */ + __IOM uint32_t TMRB3CLK : 5; /*!< [21..17] Counter/Timer B3 Clock Select. */ + __IOM uint32_t TMRB3FN : 3; /*!< [24..22] Counter/Timer B3 Function Select. */ + __IOM uint32_t TMRB3IE0 : 1; /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB3IE1 : 1; /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB3CLR : 1; /*!< [27..27] Counter/Timer B3 Clear bit. */ + __IOM uint32_t TMRB3POL : 1; /*!< [28..28] Counter/Timer B3 output polarity. */ + __IOM uint32_t TMRB3PE : 1; /*!< [29..29] Counter/Timer B3 Output Enable bit. */ + __IM uint32_t : 1; + __IOM uint32_t CTLINK3 : 1; /*!< [31..31] Counter/Timer A3/B3 Link bit. */ + } CTRL3_b; + } ; + __IM uint32_t RESERVED[48]; + + union { + __IOM uint32_t STCFG; /*!< (@ 0x00000100) Configuration Register */ + + struct { + __IOM uint32_t CLKSEL : 4; /*!< [3..0] Selects an appropriate clock source and divider to use + for the System Timer clock. */ + __IM uint32_t : 4; + __IOM uint32_t COMPARE_A_EN : 1; /*!< [8..8] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_B_EN : 1; /*!< [9..9] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_C_EN : 1; /*!< [10..10] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_D_EN : 1; /*!< [11..11] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_E_EN : 1; /*!< [12..12] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_F_EN : 1; /*!< [13..13] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_G_EN : 1; /*!< [14..14] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_H_EN : 1; /*!< [15..15] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IM uint32_t : 14; + __IOM uint32_t CLEAR : 1; /*!< [30..30] Set this bit to one to clear the System Timer register. + If this bit is set to '1', the system timer register will + stay cleared. It needs to be set to '0' for the system + timer to start running. */ + __IOM uint32_t FREEZE : 1; /*!< [31..31] Set this bit to one to freeze the clock input to the + COUNTER register. Once frozen, the value can be safely + written from the MCU. Unfreeze to resume. */ + } STCFG_b; + } ; + + union { + __IOM uint32_t STTMR; /*!< (@ 0x00000104) System Timer Count Register (Real Time Counter) */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } STTMR_b; + } ; + + union { + __IOM uint32_t CAPTURE_CONTROL; /*!< (@ 0x00000108) Capture Control Register */ + + struct { + __IOM uint32_t CAPTURE_A : 1; /*!< [0..0] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE_B : 1; /*!< [1..1] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE_C : 1; /*!< [2..2] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE_D : 1; /*!< [3..3] Selects whether capture is enabled for the specified + capture register. */ + } CAPTURE_CONTROL_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SCMPR0; /*!< (@ 0x00000110) Compare Register A */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_A_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR0_b; + } ; + + union { + __IOM uint32_t SCMPR1; /*!< (@ 0x00000114) Compare Register B */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_B_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR1_b; + } ; + + union { + __IOM uint32_t SCMPR2; /*!< (@ 0x00000118) Compare Register C */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_C_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR2_b; + } ; + + union { + __IOM uint32_t SCMPR3; /*!< (@ 0x0000011C) Compare Register D */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_D_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR3_b; + } ; + + union { + __IOM uint32_t SCMPR4; /*!< (@ 0x00000120) Compare Register E */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_E_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR4_b; + } ; + + union { + __IOM uint32_t SCMPR5; /*!< (@ 0x00000124) Compare Register F */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_F_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR5_b; + } ; + + union { + __IOM uint32_t SCMPR6; /*!< (@ 0x00000128) Compare Register G */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_G_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR6_b; + } ; + + union { + __IOM uint32_t SCMPR7; /*!< (@ 0x0000012C) Compare Register H */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_H_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR7_b; + } ; + __IM uint32_t RESERVED2[44]; + + union { + __IOM uint32_t SCAPT0; /*!< (@ 0x000001E0) Capture Register A */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT0_b; + } ; + + union { + __IOM uint32_t SCAPT1; /*!< (@ 0x000001E4) Capture Register B */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT1_b; + } ; + + union { + __IOM uint32_t SCAPT2; /*!< (@ 0x000001E8) Capture Register C */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT2_b; + } ; + + union { + __IOM uint32_t SCAPT3; /*!< (@ 0x000001EC) Capture Register D */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT3_b; + } ; + + union { + __IOM uint32_t SNVR0; /*!< (@ 0x000001F0) System Timer NVRAM_A Register */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR0_b; + } ; + + union { + __IOM uint32_t SNVR1; /*!< (@ 0x000001F4) System Timer NVRAM_B Register */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR1_b; + } ; + + union { + __IOM uint32_t SNVR2; /*!< (@ 0x000001F8) System Timer NVRAM_C Register */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR2_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Counter/Timer Interrupts: Enable */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [8..8] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [9..9] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [10..10] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [11..11] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [12..12] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [13..13] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [14..14] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [15..15] Counter/Timer B3 interrupt based on COMPR1. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Counter/Timer Interrupts: Status */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [8..8] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [9..9] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [10..10] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [11..11] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [12..12] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [13..13] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [14..14] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [15..15] Counter/Timer B3 interrupt based on COMPR1. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Counter/Timer Interrupts: Clear */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [8..8] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [9..9] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [10..10] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [11..11] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [12..12] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [13..13] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [14..14] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [15..15] Counter/Timer B3 interrupt based on COMPR1. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Counter/Timer Interrupts: Set */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [8..8] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [9..9] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [10..10] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [11..11] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [12..12] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [13..13] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [14..14] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [15..15] Counter/Timer B3 interrupt based on COMPR1. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED4[60]; + + union { + __IOM uint32_t STMINTEN; /*!< (@ 0x00000300) STIMER Interrupt registers: Enable */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTEN_b; + } ; + + union { + __IOM uint32_t STMINTSTAT; /*!< (@ 0x00000304) STIMER Interrupt registers: Status */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTSTAT_b; + } ; + + union { + __IOM uint32_t STMINTCLR; /*!< (@ 0x00000308) STIMER Interrupt registers: Clear */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTCLR_b; + } ; + + union { + __IOM uint32_t STMINTSET; /*!< (@ 0x0000030C) STIMER Interrupt registers: Set */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTSET_b; + } ; +} CTIMER_Type; /*!< Size = 784 (0x310) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose IO (GPIO) + */ + +typedef struct { /*!< (@ 0x40010000) GPIO Structure */ + + union { + __IOM uint32_t PADREGA; /*!< (@ 0x00000000) Pad Configuration Register A */ + + struct { + __IOM uint32_t PAD0PULL : 1; /*!< [0..0] Pad 0 pullup enable */ + __IOM uint32_t PAD0INPEN : 1; /*!< [1..1] Pad 0 input enable */ + __IOM uint32_t PAD0STRNG : 1; /*!< [2..2] Pad 0 drive strength */ + __IOM uint32_t PAD0FNCSEL : 3; /*!< [5..3] Pad 0 function select */ + __IOM uint32_t PAD0RSEL : 2; /*!< [7..6] Pad 0 pullup resistor selection. */ + __IOM uint32_t PAD1PULL : 1; /*!< [8..8] Pad 1 pullup enable */ + __IOM uint32_t PAD1INPEN : 1; /*!< [9..9] Pad 1 input enable */ + __IOM uint32_t PAD1STRNG : 1; /*!< [10..10] Pad 1 drive strength */ + __IOM uint32_t PAD1FNCSEL : 3; /*!< [13..11] Pad 1 function select */ + __IOM uint32_t PAD1RSEL : 2; /*!< [15..14] Pad 1 pullup resistor selection. */ + __IOM uint32_t PAD2PULL : 1; /*!< [16..16] Pad 2 pullup enable */ + __IOM uint32_t PAD2INPEN : 1; /*!< [17..17] Pad 2 input enable */ + __IOM uint32_t PAD2STRNG : 1; /*!< [18..18] Pad 2 drive strength */ + __IOM uint32_t PAD2FNCSEL : 3; /*!< [21..19] Pad 2 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD3PULL : 1; /*!< [24..24] Pad 3 pullup enable */ + __IOM uint32_t PAD3INPEN : 1; /*!< [25..25] Pad 3 input enable. */ + __IOM uint32_t PAD3STRNG : 1; /*!< [26..26] Pad 3 drive strength. */ + __IOM uint32_t PAD3FNCSEL : 3; /*!< [29..27] Pad 3 function select */ + } PADREGA_b; + } ; + + union { + __IOM uint32_t PADREGB; /*!< (@ 0x00000004) Pad Configuration Register B */ + + struct { + __IOM uint32_t PAD4PULL : 1; /*!< [0..0] Pad 4 pullup enable */ + __IOM uint32_t PAD4INPEN : 1; /*!< [1..1] Pad 4 input enable */ + __IOM uint32_t PAD4STRNG : 1; /*!< [2..2] Pad 4 drive strength */ + __IOM uint32_t PAD4FNCSEL : 3; /*!< [5..3] Pad 4 function select */ + __IM uint32_t : 1; + __IOM uint32_t PAD4PWRDN : 1; /*!< [7..7] Pad 4 VSS power switch enable */ + __IOM uint32_t PAD5PULL : 1; /*!< [8..8] Pad 5 pullup enable */ + __IOM uint32_t PAD5INPEN : 1; /*!< [9..9] Pad 5 input enable */ + __IOM uint32_t PAD5STRNG : 1; /*!< [10..10] Pad 5 drive strength */ + __IOM uint32_t PAD5FNCSEL : 3; /*!< [13..11] Pad 5 function select */ + __IOM uint32_t PAD5RSEL : 2; /*!< [15..14] Pad 5 pullup resistor selection. */ + __IOM uint32_t PAD6PULL : 1; /*!< [16..16] Pad 6 pullup enable */ + __IOM uint32_t PAD6INPEN : 1; /*!< [17..17] Pad 6 input enable */ + __IOM uint32_t PAD6STRNG : 1; /*!< [18..18] Pad 6 drive strength */ + __IOM uint32_t PAD6FNCSEL : 3; /*!< [21..19] Pad 6 function select */ + __IOM uint32_t PAD6RSEL : 2; /*!< [23..22] Pad 6 pullup resistor selection. */ + __IOM uint32_t PAD7PULL : 1; /*!< [24..24] Pad 7 pullup enable */ + __IOM uint32_t PAD7INPEN : 1; /*!< [25..25] Pad 7 input enable */ + __IOM uint32_t PAD7STRNG : 1; /*!< [26..26] Pad 7 drive strength */ + __IOM uint32_t PAD7FNCSEL : 3; /*!< [29..27] Pad 7 function select */ + } PADREGB_b; + } ; + + union { + __IOM uint32_t PADREGC; /*!< (@ 0x00000008) Pad Configuration Register C */ + + struct { + __IOM uint32_t PAD8PULL : 1; /*!< [0..0] Pad 8 pullup enable */ + __IOM uint32_t PAD8INPEN : 1; /*!< [1..1] Pad 8 input enable */ + __IOM uint32_t PAD8STRNG : 1; /*!< [2..2] Pad 8 drive strength */ + __IOM uint32_t PAD8FNCSEL : 3; /*!< [5..3] Pad 8 function select */ + __IOM uint32_t PAD8RSEL : 2; /*!< [7..6] Pad 8 pullup resistor selection. */ + __IOM uint32_t PAD9PULL : 1; /*!< [8..8] Pad 9 pullup enable */ + __IOM uint32_t PAD9INPEN : 1; /*!< [9..9] Pad 9 input enable */ + __IOM uint32_t PAD9STRNG : 1; /*!< [10..10] Pad 9 drive strength */ + __IOM uint32_t PAD9FNCSEL : 3; /*!< [13..11] Pad 9 function select */ + __IOM uint32_t PAD9RSEL : 2; /*!< [15..14] Pad 9 pullup resistor selection */ + __IOM uint32_t PAD10PULL : 1; /*!< [16..16] Pad 10 pullup enable */ + __IOM uint32_t PAD10INPEN : 1; /*!< [17..17] Pad 10 input enable */ + __IOM uint32_t PAD10STRNG : 1; /*!< [18..18] Pad 10 drive strength */ + __IOM uint32_t PAD10FNCSEL : 3; /*!< [21..19] Pad 10 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD11PULL : 1; /*!< [24..24] Pad 11 pullup enable */ + __IOM uint32_t PAD11INPEN : 1; /*!< [25..25] Pad 11 input enable */ + __IOM uint32_t PAD11STRNG : 1; /*!< [26..26] Pad 11 drive strength */ + __IOM uint32_t PAD11FNCSEL : 3; /*!< [29..27] Pad 11 function select */ + } PADREGC_b; + } ; + + union { + __IOM uint32_t PADREGD; /*!< (@ 0x0000000C) Pad Configuration Register D */ + + struct { + __IOM uint32_t PAD12PULL : 1; /*!< [0..0] Pad 12 pullup enable */ + __IOM uint32_t PAD12INPEN : 1; /*!< [1..1] Pad 12 input enable */ + __IOM uint32_t PAD12STRNG : 1; /*!< [2..2] Pad 12 drive strength */ + __IOM uint32_t PAD12FNCSEL : 3; /*!< [5..3] Pad 12 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD13PULL : 1; /*!< [8..8] Pad 13 pullup enable */ + __IOM uint32_t PAD13INPEN : 1; /*!< [9..9] Pad 13 input enable */ + __IOM uint32_t PAD13STRNG : 1; /*!< [10..10] Pad 13 drive strength */ + __IOM uint32_t PAD13FNCSEL : 3; /*!< [13..11] Pad 13 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD14PULL : 1; /*!< [16..16] Pad 14 pullup enable */ + __IOM uint32_t PAD14INPEN : 1; /*!< [17..17] Pad 14 input enable */ + __IOM uint32_t PAD14STRNG : 1; /*!< [18..18] Pad 14 drive strength */ + __IOM uint32_t PAD14FNCSEL : 3; /*!< [21..19] Pad 14 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD15PULL : 1; /*!< [24..24] Pad 15 pullup enable */ + __IOM uint32_t PAD15INPEN : 1; /*!< [25..25] Pad 15 input enable */ + __IOM uint32_t PAD15STRNG : 1; /*!< [26..26] Pad 15 drive strength */ + __IOM uint32_t PAD15FNCSEL : 3; /*!< [29..27] Pad 15 function select */ + } PADREGD_b; + } ; + + union { + __IOM uint32_t PADREGE; /*!< (@ 0x00000010) Pad Configuration Register E */ + + struct { + __IOM uint32_t PAD16PULL : 1; /*!< [0..0] Pad 16 pullup enable */ + __IOM uint32_t PAD16INPEN : 1; /*!< [1..1] Pad 16 input enable */ + __IOM uint32_t PAD16STRNG : 1; /*!< [2..2] Pad 16 drive strength */ + __IOM uint32_t PAD16FNCSEL : 3; /*!< [5..3] Pad 16 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD17PULL : 1; /*!< [8..8] Pad 17 pullup enable */ + __IOM uint32_t PAD17INPEN : 1; /*!< [9..9] Pad 17 input enable */ + __IOM uint32_t PAD17STRNG : 1; /*!< [10..10] Pad 17 drive strength */ + __IOM uint32_t PAD17FNCSEL : 3; /*!< [13..11] Pad 17 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD18PULL : 1; /*!< [16..16] Pad 18 pullup enable */ + __IOM uint32_t PAD18INPEN : 1; /*!< [17..17] Pad 18 input enable */ + __IOM uint32_t PAD18STRNG : 1; /*!< [18..18] Pad 18 drive strength */ + __IOM uint32_t PAD18FNCSEL : 3; /*!< [21..19] Pad 18 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD19PULL : 1; /*!< [24..24] Pad 19 pullup enable */ + __IOM uint32_t PAD19INPEN : 1; /*!< [25..25] Pad 19 input enable */ + __IOM uint32_t PAD19STRNG : 1; /*!< [26..26] Pad 19 drive strength */ + __IOM uint32_t PAD19FNCSEL : 3; /*!< [29..27] Pad 19 function select */ + } PADREGE_b; + } ; + + union { + __IOM uint32_t PADREGF; /*!< (@ 0x00000014) Pad Configuration Register F */ + + struct { + __IOM uint32_t PAD20PULL : 1; /*!< [0..0] Pad 20 pulldown enable */ + __IOM uint32_t PAD20INPEN : 1; /*!< [1..1] Pad 20 input enable */ + __IOM uint32_t PAD20STRNG : 1; /*!< [2..2] Pad 20 drive strength */ + __IOM uint32_t PAD20FNCSEL : 3; /*!< [5..3] Pad 20 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD21PULL : 1; /*!< [8..8] Pad 21 pullup enable */ + __IOM uint32_t PAD21INPEN : 1; /*!< [9..9] Pad 21 input enable */ + __IOM uint32_t PAD21STRNG : 1; /*!< [10..10] Pad 21 drive strength */ + __IOM uint32_t PAD21FNCSEL : 3; /*!< [13..11] Pad 21 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD22PULL : 1; /*!< [16..16] Pad 22 pullup enable */ + __IOM uint32_t PAD22INPEN : 1; /*!< [17..17] Pad 22 input enable */ + __IOM uint32_t PAD22STRNG : 1; /*!< [18..18] Pad 22 drive strength */ + __IOM uint32_t PAD22FNCSEL : 3; /*!< [21..19] Pad 22 function select */ + __IM uint32_t : 1; + __IOM uint32_t PAD22PWRUP : 1; /*!< [23..23] Pad 22 upper power switch enable */ + __IOM uint32_t PAD23PULL : 1; /*!< [24..24] Pad 23 pullup enable */ + __IOM uint32_t PAD23INPEN : 1; /*!< [25..25] Pad 23 input enable */ + __IOM uint32_t PAD23STRNG : 1; /*!< [26..26] Pad 23 drive strength */ + __IOM uint32_t PAD23FNCSEL : 3; /*!< [29..27] Pad 23 function select */ + } PADREGF_b; + } ; + + union { + __IOM uint32_t PADREGG; /*!< (@ 0x00000018) Pad Configuration Register G */ + + struct { + __IOM uint32_t PAD24PULL : 1; /*!< [0..0] Pad 24 pullup enable */ + __IOM uint32_t PAD24INPEN : 1; /*!< [1..1] Pad 24 input enable */ + __IOM uint32_t PAD24STRNG : 1; /*!< [2..2] Pad 24 drive strength */ + __IOM uint32_t PAD24FNCSEL : 3; /*!< [5..3] Pad 24 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD25PULL : 1; /*!< [8..8] Pad 25 pullup enable */ + __IOM uint32_t PAD25INPEN : 1; /*!< [9..9] Pad 25 input enable */ + __IOM uint32_t PAD25STRNG : 1; /*!< [10..10] Pad 25 drive strength */ + __IOM uint32_t PAD25FNCSEL : 3; /*!< [13..11] Pad 25 function select */ + __IOM uint32_t PAD25RSEL : 2; /*!< [15..14] Pad 25 pullup resistor selection. */ + __IOM uint32_t PAD26PULL : 1; /*!< [16..16] Pad 26 pullup enable */ + __IOM uint32_t PAD26INPEN : 1; /*!< [17..17] Pad 26 input enable */ + __IOM uint32_t PAD26STRNG : 1; /*!< [18..18] Pad 26 drive strength */ + __IOM uint32_t PAD26FNCSEL : 3; /*!< [21..19] Pad 26 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD27PULL : 1; /*!< [24..24] Pad 27 pullup enable */ + __IOM uint32_t PAD27INPEN : 1; /*!< [25..25] Pad 27 input enable */ + __IOM uint32_t PAD27STRNG : 1; /*!< [26..26] Pad 27 drive strength */ + __IOM uint32_t PAD27FNCSEL : 3; /*!< [29..27] Pad 27 function select */ + __IOM uint32_t PAD27RSEL : 2; /*!< [31..30] Pad 27 pullup resistor selection. */ + } PADREGG_b; + } ; + + union { + __IOM uint32_t PADREGH; /*!< (@ 0x0000001C) Pad Configuration Register H */ + + struct { + __IOM uint32_t PAD28PULL : 1; /*!< [0..0] Pad 28 pullup enable */ + __IOM uint32_t PAD28INPEN : 1; /*!< [1..1] Pad 28 input enable */ + __IOM uint32_t PAD28STRNG : 1; /*!< [2..2] Pad 28 drive strength */ + __IOM uint32_t PAD28FNCSEL : 3; /*!< [5..3] Pad 28 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD29PULL : 1; /*!< [8..8] Pad 29 pullup enable */ + __IOM uint32_t PAD29INPEN : 1; /*!< [9..9] Pad 29 input enable */ + __IOM uint32_t PAD29STRNG : 1; /*!< [10..10] Pad 29 drive strength */ + __IOM uint32_t PAD29FNCSEL : 3; /*!< [13..11] Pad 29 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD30PULL : 1; /*!< [16..16] Pad 30 pullup enable */ + __IOM uint32_t PAD30INPEN : 1; /*!< [17..17] Pad 30 input enable */ + __IOM uint32_t PAD30STRNG : 1; /*!< [18..18] Pad 30 drive strength */ + __IOM uint32_t PAD30FNCSEL : 3; /*!< [21..19] Pad 30 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD31PULL : 1; /*!< [24..24] Pad 31 pullup enable */ + __IOM uint32_t PAD31INPEN : 1; /*!< [25..25] Pad 31 input enable */ + __IOM uint32_t PAD31STRNG : 1; /*!< [26..26] Pad 31 drive strength */ + __IOM uint32_t PAD31FNCSEL : 3; /*!< [29..27] Pad 31 function select */ + } PADREGH_b; + } ; + + union { + __IOM uint32_t PADREGI; /*!< (@ 0x00000020) Pad Configuration Register I */ + + struct { + __IOM uint32_t PAD32PULL : 1; /*!< [0..0] Pad 32 pullup enable */ + __IOM uint32_t PAD32INPEN : 1; /*!< [1..1] Pad 32 input enable */ + __IOM uint32_t PAD32STRNG : 1; /*!< [2..2] Pad 32 drive strength */ + __IOM uint32_t PAD32FNCSEL : 3; /*!< [5..3] Pad 32 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD33PULL : 1; /*!< [8..8] Pad 33 pullup enable */ + __IOM uint32_t PAD33INPEN : 1; /*!< [9..9] Pad 33 input enable */ + __IOM uint32_t PAD33STRNG : 1; /*!< [10..10] Pad 33 drive strength */ + __IOM uint32_t PAD33FNCSEL : 3; /*!< [13..11] Pad 33 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD34PULL : 1; /*!< [16..16] Pad 34 pullup enable */ + __IOM uint32_t PAD34INPEN : 1; /*!< [17..17] Pad 34 input enable */ + __IOM uint32_t PAD34STRNG : 1; /*!< [18..18] Pad 34 drive strength */ + __IOM uint32_t PAD34FNCSEL : 3; /*!< [21..19] Pad 34 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD35PULL : 1; /*!< [24..24] Pad 35 pullup enable */ + __IOM uint32_t PAD35INPEN : 1; /*!< [25..25] Pad 35 input enable */ + __IOM uint32_t PAD35STRNG : 1; /*!< [26..26] Pad 35 drive strength */ + __IOM uint32_t PAD35FNCSEL : 3; /*!< [29..27] Pad 35 function select */ + } PADREGI_b; + } ; + + union { + __IOM uint32_t PADREGJ; /*!< (@ 0x00000024) Pad Configuration Register J */ + + struct { + __IOM uint32_t PAD36PULL : 1; /*!< [0..0] Pad 36 pullup enable */ + __IOM uint32_t PAD36INPEN : 1; /*!< [1..1] Pad 36 input enable */ + __IOM uint32_t PAD36STRNG : 1; /*!< [2..2] Pad 36 drive strength */ + __IOM uint32_t PAD36FNCSEL : 3; /*!< [5..3] Pad 36 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD37PULL : 1; /*!< [8..8] Pad 37 pullup enable */ + __IOM uint32_t PAD37INPEN : 1; /*!< [9..9] Pad 37 input enable */ + __IOM uint32_t PAD37STRNG : 1; /*!< [10..10] Pad 37 drive strength */ + __IOM uint32_t PAD37FNCSEL : 3; /*!< [13..11] Pad 37 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD38PULL : 1; /*!< [16..16] Pad 38 pullup enable */ + __IOM uint32_t PAD38INPEN : 1; /*!< [17..17] Pad 38 input enable */ + __IOM uint32_t PAD38STRNG : 1; /*!< [18..18] Pad 38 drive strength */ + __IOM uint32_t PAD38FNCSEL : 3; /*!< [21..19] Pad 38 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD39PULL : 1; /*!< [24..24] Pad 39 pullup enable */ + __IOM uint32_t PAD39INPEN : 1; /*!< [25..25] Pad 39 input enable */ + __IOM uint32_t PAD39STRNG : 1; /*!< [26..26] Pad 39 drive strength */ + __IOM uint32_t PAD39FNCSEL : 3; /*!< [29..27] Pad 39 function select */ + __IOM uint32_t PAD39RSEL : 2; /*!< [31..30] Pad 39 pullup resistor selection. */ + } PADREGJ_b; + } ; + + union { + __IOM uint32_t PADREGK; /*!< (@ 0x00000028) Pad Configuration Register K */ + + struct { + __IOM uint32_t PAD40PULL : 1; /*!< [0..0] Pad 40 pullup enable */ + __IOM uint32_t PAD40INPEN : 1; /*!< [1..1] Pad 40 input enable */ + __IOM uint32_t PAD40STRNG : 1; /*!< [2..2] Pad 40 drive strength */ + __IOM uint32_t PAD40FNCSEL : 3; /*!< [5..3] Pad 40 function select */ + __IOM uint32_t PAD40RSEL : 2; /*!< [7..6] Pad 40 pullup resistor selection. */ + __IOM uint32_t PAD41PULL : 1; /*!< [8..8] Pad 41 pullup enable */ + __IOM uint32_t PAD41INPEN : 1; /*!< [9..9] Pad 41 input enable */ + __IOM uint32_t PAD41STRNG : 1; /*!< [10..10] Pad 41 drive strength */ + __IOM uint32_t PAD41FNCSEL : 3; /*!< [13..11] Pad 41 function select */ + __IM uint32_t : 1; + __IOM uint32_t PAD41PWRUP : 1; /*!< [15..15] Pad 41 upper power switch enable */ + __IOM uint32_t PAD42PULL : 1; /*!< [16..16] Pad 42 pullup enable */ + __IOM uint32_t PAD42INPEN : 1; /*!< [17..17] Pad 42 input enable */ + __IOM uint32_t PAD42STRNG : 1; /*!< [18..18] Pad 42 drive strength */ + __IOM uint32_t PAD42FNCSEL : 3; /*!< [21..19] Pad 42 function select */ + __IOM uint32_t PAD42RSEL : 2; /*!< [23..22] Pad 42 pullup resistor selection. */ + __IOM uint32_t PAD43PULL : 1; /*!< [24..24] Pad 43 pullup enable */ + __IOM uint32_t PAD43INPEN : 1; /*!< [25..25] Pad 43 input enable */ + __IOM uint32_t PAD43STRNG : 1; /*!< [26..26] Pad 43 drive strength */ + __IOM uint32_t PAD43FNCSEL : 3; /*!< [29..27] Pad 43 function select */ + __IOM uint32_t PAD43RSEL : 2; /*!< [31..30] Pad 43 pullup resistor selection. */ + } PADREGK_b; + } ; + + union { + __IOM uint32_t PADREGL; /*!< (@ 0x0000002C) Pad Configuration Register L */ + + struct { + __IOM uint32_t PAD44PULL : 1; /*!< [0..0] Pad 44 pullup enable */ + __IOM uint32_t PAD44INPEN : 1; /*!< [1..1] Pad 44 input enable */ + __IOM uint32_t PAD44STRNG : 1; /*!< [2..2] Pad 44 drive strength */ + __IOM uint32_t PAD44FNCSEL : 3; /*!< [5..3] Pad 44 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD45PULL : 1; /*!< [8..8] Pad 45 pullup enable */ + __IOM uint32_t PAD45INPEN : 1; /*!< [9..9] Pad 45 input enable */ + __IOM uint32_t PAD45STRNG : 1; /*!< [10..10] Pad 45 drive strength */ + __IOM uint32_t PAD45FNCSEL : 3; /*!< [13..11] Pad 45 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD46PULL : 1; /*!< [16..16] Pad 46 pullup enable */ + __IOM uint32_t PAD46INPEN : 1; /*!< [17..17] Pad 46 input enable */ + __IOM uint32_t PAD46STRNG : 1; /*!< [18..18] Pad 46 drive strength */ + __IOM uint32_t PAD46FNCSEL : 3; /*!< [21..19] Pad 46 function select */ + __IM uint32_t : 2; + __IOM uint32_t PAD47PULL : 1; /*!< [24..24] Pad 47 pullup enable */ + __IOM uint32_t PAD47INPEN : 1; /*!< [25..25] Pad 47 input enable */ + __IOM uint32_t PAD47STRNG : 1; /*!< [26..26] Pad 47 drive strength */ + __IOM uint32_t PAD47FNCSEL : 3; /*!< [29..27] Pad 47 function select */ + } PADREGL_b; + } ; + + union { + __IOM uint32_t PADREGM; /*!< (@ 0x00000030) Pad Configuration Register M */ + + struct { + __IOM uint32_t PAD48PULL : 1; /*!< [0..0] Pad 48 pullup enable */ + __IOM uint32_t PAD48INPEN : 1; /*!< [1..1] Pad 48 input enable */ + __IOM uint32_t PAD48STRNG : 1; /*!< [2..2] Pad 48 drive strength */ + __IOM uint32_t PAD48FNCSEL : 3; /*!< [5..3] Pad 48 function select */ + __IOM uint32_t PAD48RSEL : 2; /*!< [7..6] Pad 48 pullup resistor selection. */ + __IOM uint32_t PAD49PULL : 1; /*!< [8..8] Pad 49 pullup enable */ + __IOM uint32_t PAD49INPEN : 1; /*!< [9..9] Pad 49 input enable */ + __IOM uint32_t PAD49STRNG : 1; /*!< [10..10] Pad 49 drive strength */ + __IOM uint32_t PAD49FNCSEL : 3; /*!< [13..11] Pad 49 function select */ + __IOM uint32_t PAD49RSEL : 2; /*!< [15..14] Pad 49 pullup resistor selection. */ + } PADREGM_b; + } ; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t CFGA; /*!< (@ 0x00000040) GPIO Configuration Register A */ + + struct { + __IOM uint32_t GPIO0INCFG : 1; /*!< [0..0] GPIO0 input enable. */ + __IOM uint32_t GPIO0OUTCFG : 2; /*!< [2..1] GPIO0 output configuration. */ + __IOM uint32_t GPIO0INTD : 1; /*!< [3..3] GPIO0 interrupt direction. */ + __IOM uint32_t GPIO1INCFG : 1; /*!< [4..4] GPIO1 input enable. */ + __IOM uint32_t GPIO1OUTCFG : 2; /*!< [6..5] GPIO1 output configuration. */ + __IOM uint32_t GPIO1INTD : 1; /*!< [7..7] GPIO1 interrupt direction. */ + __IOM uint32_t GPIO2INCFG : 1; /*!< [8..8] GPIO2 input enable. */ + __IOM uint32_t GPIO2OUTCFG : 2; /*!< [10..9] GPIO2 output configuration. */ + __IOM uint32_t GPIO2INTD : 1; /*!< [11..11] GPIO2 interrupt direction. */ + __IOM uint32_t GPIO3INCFG : 1; /*!< [12..12] GPIO3 input enable. */ + __IOM uint32_t GPIO3OUTCFG : 2; /*!< [14..13] GPIO3 output configuration. */ + __IOM uint32_t GPIO3INTD : 1; /*!< [15..15] GPIO3 interrupt direction. */ + __IOM uint32_t GPIO4INCFG : 1; /*!< [16..16] GPIO4 input enable. */ + __IOM uint32_t GPIO4OUTCFG : 2; /*!< [18..17] GPIO4 output configuration. */ + __IOM uint32_t GPIO4INTD : 1; /*!< [19..19] GPIO4 interrupt direction. */ + __IOM uint32_t GPIO5INCFG : 1; /*!< [20..20] GPIO5 input enable. */ + __IOM uint32_t GPIO5OUTCFG : 2; /*!< [22..21] GPIO5 output configuration. */ + __IOM uint32_t GPIO5INTD : 1; /*!< [23..23] GPIO5 interrupt direction. */ + __IOM uint32_t GPIO6INCFG : 1; /*!< [24..24] GPIO6 input enable. */ + __IOM uint32_t GPIO6OUTCFG : 2; /*!< [26..25] GPIO6 output configuration. */ + __IOM uint32_t GPIO6INTD : 1; /*!< [27..27] GPIO6 interrupt direction. */ + __IOM uint32_t GPIO7INCFG : 1; /*!< [28..28] GPIO7 input enable. */ + __IOM uint32_t GPIO7OUTCFG : 2; /*!< [30..29] GPIO7 output configuration. */ + __IOM uint32_t GPIO7INTD : 1; /*!< [31..31] GPIO7 interrupt direction. */ + } CFGA_b; + } ; + + union { + __IOM uint32_t CFGB; /*!< (@ 0x00000044) GPIO Configuration Register B */ + + struct { + __IOM uint32_t GPIO8INCFG : 1; /*!< [0..0] GPIO8 input enable. */ + __IOM uint32_t GPIO8OUTCFG : 2; /*!< [2..1] GPIO8 output configuration. */ + __IOM uint32_t GPIO8INTD : 1; /*!< [3..3] GPIO8 interrupt direction. */ + __IOM uint32_t GPIO9INCFG : 1; /*!< [4..4] GPIO9 input enable. */ + __IOM uint32_t GPIO9OUTCFG : 2; /*!< [6..5] GPIO9 output configuration. */ + __IOM uint32_t GPIO9INTD : 1; /*!< [7..7] GPIO9 interrupt direction. */ + __IOM uint32_t GPIO10INCFG : 1; /*!< [8..8] GPIO10 input enable. */ + __IOM uint32_t GPIO10OUTCFG : 2; /*!< [10..9] GPIO10 output configuration. */ + __IOM uint32_t GPIO10INTD : 1; /*!< [11..11] GPIO10 interrupt direction. */ + __IOM uint32_t GPIO11INCFG : 1; /*!< [12..12] GPIO11 input enable. */ + __IOM uint32_t GPIO11OUTCFG : 2; /*!< [14..13] GPIO11 output configuration. */ + __IOM uint32_t GPIO11INTD : 1; /*!< [15..15] GPIO11 interrupt direction. */ + __IOM uint32_t GPIO12INCFG : 1; /*!< [16..16] GPIO12 input enable. */ + __IOM uint32_t GPIO12OUTCFG : 2; /*!< [18..17] GPIO12 output configuration. */ + __IOM uint32_t GPIO12INTD : 1; /*!< [19..19] GPIO12 interrupt direction. */ + __IOM uint32_t GPIO13INCFG : 1; /*!< [20..20] GPIO13 input enable. */ + __IOM uint32_t GPIO13OUTCFG : 2; /*!< [22..21] GPIO13 output configuration. */ + __IOM uint32_t GPIO13INTD : 1; /*!< [23..23] GPIO13 interrupt direction. */ + __IOM uint32_t GPIO14INCFG : 1; /*!< [24..24] GPIO14 input enable. */ + __IOM uint32_t GPIO14OUTCFG : 2; /*!< [26..25] GPIO14 output configuration. */ + __IOM uint32_t GPIO14INTD : 1; /*!< [27..27] GPIO14 interrupt direction. */ + __IOM uint32_t GPIO15INCFG : 1; /*!< [28..28] GPIO15 input enable. */ + __IOM uint32_t GPIO15OUTCFG : 2; /*!< [30..29] GPIO15 output configuration. */ + __IOM uint32_t GPIO15INTD : 1; /*!< [31..31] GPIO15 interrupt direction. */ + } CFGB_b; + } ; + + union { + __IOM uint32_t CFGC; /*!< (@ 0x00000048) GPIO Configuration Register C */ + + struct { + __IOM uint32_t GPIO16INCFG : 1; /*!< [0..0] GPIO16 input enable. */ + __IOM uint32_t GPIO16OUTCFG : 2; /*!< [2..1] GPIO16 output configuration. */ + __IOM uint32_t GPIO16INTD : 1; /*!< [3..3] GPIO16 interrupt direction. */ + __IOM uint32_t GPIO17INCFG : 1; /*!< [4..4] GPIO17 input enable. */ + __IOM uint32_t GPIO17OUTCFG : 2; /*!< [6..5] GPIO17 output configuration. */ + __IOM uint32_t GPIO17INTD : 1; /*!< [7..7] GPIO17 interrupt direction. */ + __IOM uint32_t GPIO18INCFG : 1; /*!< [8..8] GPIO18 input enable. */ + __IOM uint32_t GPIO18OUTCFG : 2; /*!< [10..9] GPIO18 output configuration. */ + __IOM uint32_t GPIO18INTD : 1; /*!< [11..11] GPIO18 interrupt direction. */ + __IOM uint32_t GPIO19INCFG : 1; /*!< [12..12] GPIO19 input enable. */ + __IOM uint32_t GPIO19OUTCFG : 2; /*!< [14..13] GPIO19 output configuration. */ + __IOM uint32_t GPIO19INTD : 1; /*!< [15..15] GPIO19 interrupt direction. */ + __IOM uint32_t GPIO20INCFG : 1; /*!< [16..16] GPIO20 input enable. */ + __IOM uint32_t GPIO20OUTCFG : 2; /*!< [18..17] GPIO20 output configuration. */ + __IOM uint32_t GPIO20INTD : 1; /*!< [19..19] GPIO20 interrupt direction. */ + __IOM uint32_t GPIO21INCFG : 1; /*!< [20..20] GPIO21 input enable. */ + __IOM uint32_t GPIO21OUTCFG : 2; /*!< [22..21] GPIO21 output configuration. */ + __IOM uint32_t GPIO21INTD : 1; /*!< [23..23] GPIO21 interrupt direction. */ + __IOM uint32_t GPIO22INCFG : 1; /*!< [24..24] GPIO22 input enable. */ + __IOM uint32_t GPIO22OUTCFG : 2; /*!< [26..25] GPIO22 output configuration. */ + __IOM uint32_t GPIO22INTD : 1; /*!< [27..27] GPIO22 interrupt direction. */ + __IOM uint32_t GPIO23INCFG : 1; /*!< [28..28] GPIO23 input enable. */ + __IOM uint32_t GPIO23OUTCFG : 2; /*!< [30..29] GPIO23 output configuration. */ + __IOM uint32_t GPIO23INTD : 1; /*!< [31..31] GPIO23 interrupt direction. */ + } CFGC_b; + } ; + + union { + __IOM uint32_t CFGD; /*!< (@ 0x0000004C) GPIO Configuration Register D */ + + struct { + __IOM uint32_t GPIO24INCFG : 1; /*!< [0..0] GPIO24 input enable. */ + __IOM uint32_t GPIO24OUTCFG : 2; /*!< [2..1] GPIO24 output configuration. */ + __IOM uint32_t GPIO24INTD : 1; /*!< [3..3] GPIO24 interrupt direction. */ + __IOM uint32_t GPIO25INCFG : 1; /*!< [4..4] GPIO25 input enable. */ + __IOM uint32_t GPIO25OUTCFG : 2; /*!< [6..5] GPIO25 output configuration. */ + __IOM uint32_t GPIO25INTD : 1; /*!< [7..7] GPIO25 interrupt direction. */ + __IOM uint32_t GPIO26INCFG : 1; /*!< [8..8] GPIO26 input enable. */ + __IOM uint32_t GPIO26OUTCFG : 2; /*!< [10..9] GPIO26 output configuration. */ + __IOM uint32_t GPIO26INTD : 1; /*!< [11..11] GPIO26 interrupt direction. */ + __IOM uint32_t GPIO27INCFG : 1; /*!< [12..12] GPIO27 input enable. */ + __IOM uint32_t GPIO27OUTCFG : 2; /*!< [14..13] GPIO27 output configuration. */ + __IOM uint32_t GPIO27INTD : 1; /*!< [15..15] GPIO27 interrupt direction. */ + __IOM uint32_t GPIO28INCFG : 1; /*!< [16..16] GPIO28 input enable. */ + __IOM uint32_t GPIO28OUTCFG : 2; /*!< [18..17] GPIO28 output configuration. */ + __IOM uint32_t GPIO28INTD : 1; /*!< [19..19] GPIO28 interrupt direction. */ + __IOM uint32_t GPIO29INCFG : 1; /*!< [20..20] GPIO29 input enable. */ + __IOM uint32_t GPIO29OUTCFG : 2; /*!< [22..21] GPIO29 output configuration. */ + __IOM uint32_t GPIO29INTD : 1; /*!< [23..23] GPIO29 interrupt direction. */ + __IOM uint32_t GPIO30INCFG : 1; /*!< [24..24] GPIO30 input enable. */ + __IOM uint32_t GPIO30OUTCFG : 2; /*!< [26..25] GPIO30 output configuration. */ + __IOM uint32_t GPIO30INTD : 1; /*!< [27..27] GPIO30 interrupt direction. */ + __IOM uint32_t GPIO31INCFG : 1; /*!< [28..28] GPIO31 input enable. */ + __IOM uint32_t GPIO31OUTCFG : 2; /*!< [30..29] GPIO31 output configuration. */ + __IOM uint32_t GPIO31INTD : 1; /*!< [31..31] GPIO31 interrupt direction. */ + } CFGD_b; + } ; + + union { + __IOM uint32_t CFGE; /*!< (@ 0x00000050) GPIO Configuration Register E */ + + struct { + __IOM uint32_t GPIO32INCFG : 1; /*!< [0..0] GPIO32 input enable. */ + __IOM uint32_t GPIO32OUTCFG : 2; /*!< [2..1] GPIO32 output configuration. */ + __IOM uint32_t GPIO32INTD : 1; /*!< [3..3] GPIO32 interrupt direction. */ + __IOM uint32_t GPIO33INCFG : 1; /*!< [4..4] GPIO33 input enable. */ + __IOM uint32_t GPIO33OUTCFG : 2; /*!< [6..5] GPIO33 output configuration. */ + __IOM uint32_t GPIO33INTD : 1; /*!< [7..7] GPIO33 interrupt direction. */ + __IOM uint32_t GPIO34INCFG : 1; /*!< [8..8] GPIO34 input enable. */ + __IOM uint32_t GPIO34OUTCFG : 2; /*!< [10..9] GPIO34 output configuration. */ + __IOM uint32_t GPIO34INTD : 1; /*!< [11..11] GPIO34 interrupt direction. */ + __IOM uint32_t GPIO35INCFG : 1; /*!< [12..12] GPIO35 input enable. */ + __IOM uint32_t GPIO35OUTCFG : 2; /*!< [14..13] GPIO35 output configuration. */ + __IOM uint32_t GPIO35INTD : 1; /*!< [15..15] GPIO35 interrupt direction. */ + __IOM uint32_t GPIO36INCFG : 1; /*!< [16..16] GPIO36 input enable. */ + __IOM uint32_t GPIO36OUTCFG : 2; /*!< [18..17] GPIO36 output configuration. */ + __IOM uint32_t GPIO36INTD : 1; /*!< [19..19] GPIO36 interrupt direction. */ + __IOM uint32_t GPIO37INCFG : 1; /*!< [20..20] GPIO37 input enable. */ + __IOM uint32_t GPIO37OUTCFG : 2; /*!< [22..21] GPIO37 output configuration. */ + __IOM uint32_t GPIO37INTD : 1; /*!< [23..23] GPIO37 interrupt direction. */ + __IOM uint32_t GPIO38INCFG : 1; /*!< [24..24] GPIO38 input enable. */ + __IOM uint32_t GPIO38OUTCFG : 2; /*!< [26..25] GPIO38 output configuration. */ + __IOM uint32_t GPIO38INTD : 1; /*!< [27..27] GPIO38 interrupt direction. */ + __IOM uint32_t GPIO39INCFG : 1; /*!< [28..28] GPIO39 input enable. */ + __IOM uint32_t GPIO39OUTCFG : 2; /*!< [30..29] GPIO39 output configuration. */ + __IOM uint32_t GPIO39INTD : 1; /*!< [31..31] GPIO39 interrupt direction. */ + } CFGE_b; + } ; + + union { + __IOM uint32_t CFGF; /*!< (@ 0x00000054) GPIO Configuration Register F */ + + struct { + __IOM uint32_t GPIO40INCFG : 1; /*!< [0..0] GPIO40 input enable. */ + __IOM uint32_t GPIO40OUTCFG : 2; /*!< [2..1] GPIO40 output configuration. */ + __IOM uint32_t GPIO40INTD : 1; /*!< [3..3] GPIO40 interrupt direction. */ + __IOM uint32_t GPIO41INCFG : 1; /*!< [4..4] GPIO41 input enable. */ + __IOM uint32_t GPIO41OUTCFG : 2; /*!< [6..5] GPIO41 output configuration. */ + __IOM uint32_t GPIO41INTD : 1; /*!< [7..7] GPIO41 interrupt direction. */ + __IOM uint32_t GPIO42INCFG : 1; /*!< [8..8] GPIO42 input enable. */ + __IOM uint32_t GPIO42OUTCFG : 2; /*!< [10..9] GPIO42 output configuration. */ + __IOM uint32_t GPIO42INTD : 1; /*!< [11..11] GPIO42 interrupt direction. */ + __IOM uint32_t GPIO43INCFG : 1; /*!< [12..12] GPIO43 input enable. */ + __IOM uint32_t GPIO43OUTCFG : 2; /*!< [14..13] GPIO43 output configuration. */ + __IOM uint32_t GPIO43INTD : 1; /*!< [15..15] GPIO43 interrupt direction. */ + __IOM uint32_t GPIO44INCFG : 1; /*!< [16..16] GPIO44 input enable. */ + __IOM uint32_t GPIO44OUTCFG : 2; /*!< [18..17] GPIO44 output configuration. */ + __IOM uint32_t GPIO44INTD : 1; /*!< [19..19] GPIO44 interrupt direction. */ + __IOM uint32_t GPIO45INCFG : 1; /*!< [20..20] GPIO45 input enable. */ + __IOM uint32_t GPIO45OUTCFG : 2; /*!< [22..21] GPIO45 output configuration. */ + __IOM uint32_t GPIO45INTD : 1; /*!< [23..23] GPIO45 interrupt direction. */ + __IOM uint32_t GPIO46INCFG : 1; /*!< [24..24] GPIO46 input enable. */ + __IOM uint32_t GPIO46OUTCFG : 2; /*!< [26..25] GPIO46 output configuration. */ + __IOM uint32_t GPIO46INTD : 1; /*!< [27..27] GPIO46 interrupt direction. */ + __IOM uint32_t GPIO47INCFG : 1; /*!< [28..28] GPIO47 input enable. */ + __IOM uint32_t GPIO47OUTCFG : 2; /*!< [30..29] GPIO47 output configuration. */ + __IOM uint32_t GPIO47INTD : 1; /*!< [31..31] GPIO47 interrupt direction. */ + } CFGF_b; + } ; + + union { + __IOM uint32_t CFGG; /*!< (@ 0x00000058) GPIO Configuration Register G */ + + struct { + __IOM uint32_t GPIO48INCFG : 1; /*!< [0..0] GPIO48 input enable. */ + __IOM uint32_t GPIO48OUTCFG : 2; /*!< [2..1] GPIO48 output configuration. */ + __IOM uint32_t GPIO48INTD : 1; /*!< [3..3] GPIO48 interrupt direction. */ + __IOM uint32_t GPIO49INCFG : 1; /*!< [4..4] GPIO49 input enable. */ + __IOM uint32_t GPIO49OUTCFG : 2; /*!< [6..5] GPIO49 output configuration. */ + __IOM uint32_t GPIO49INTD : 1; /*!< [7..7] GPIO49 interrupt direction. */ + } CFGG_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t PADKEY; /*!< (@ 0x00000060) Key Register for all pad configuration registers */ + + struct { + __IOM uint32_t PADKEY : 32; /*!< [31..0] Key register value. */ + } PADKEY_b; + } ; + __IM uint32_t RESERVED2[7]; + + union { + __IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A */ + + struct { + __IOM uint32_t RDA : 32; /*!< [31..0] GPIO31-0 read data. */ + } RDA_b; + } ; + + union { + __IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B */ + + struct { + __IOM uint32_t RDB : 18; /*!< [17..0] GPIO49-32 read data. */ + } RDB_b; + } ; + + union { + __IOM uint32_t WTA; /*!< (@ 0x00000088) GPIO Output Register A */ + + struct { + __IOM uint32_t WTA : 32; /*!< [31..0] GPIO31-0 write data. */ + } WTA_b; + } ; + + union { + __IOM uint32_t WTB; /*!< (@ 0x0000008C) GPIO Output Register B */ + + struct { + __IOM uint32_t WTB : 18; /*!< [17..0] GPIO49-32 write data. */ + } WTB_b; + } ; + + union { + __IOM uint32_t WTSA; /*!< (@ 0x00000090) GPIO Output Register A Set */ + + struct { + __IOM uint32_t WTSA : 32; /*!< [31..0] Set the GPIO31-0 write data. */ + } WTSA_b; + } ; + + union { + __IOM uint32_t WTSB; /*!< (@ 0x00000094) GPIO Output Register B Set */ + + struct { + __IOM uint32_t WTSB : 18; /*!< [17..0] Set the GPIO49-32 write data. */ + } WTSB_b; + } ; + + union { + __IOM uint32_t WTCA; /*!< (@ 0x00000098) GPIO Output Register A Clear */ + + struct { + __IOM uint32_t WTCA : 32; /*!< [31..0] Clear the GPIO31-0 write data. */ + } WTCA_b; + } ; + + union { + __IOM uint32_t WTCB; /*!< (@ 0x0000009C) GPIO Output Register B Clear */ + + struct { + __IOM uint32_t WTCB : 18; /*!< [17..0] Clear the GPIO49-32 write data. */ + } WTCB_b; + } ; + + union { + __IOM uint32_t ENA; /*!< (@ 0x000000A0) GPIO Enable Register A */ + + struct { + __IOM uint32_t ENA : 32; /*!< [31..0] GPIO31-0 output enables */ + } ENA_b; + } ; + + union { + __IOM uint32_t ENB; /*!< (@ 0x000000A4) GPIO Enable Register B */ + + struct { + __IOM uint32_t ENB : 18; /*!< [17..0] GPIO49-32 output enables */ + } ENB_b; + } ; + + union { + __IOM uint32_t ENSA; /*!< (@ 0x000000A8) GPIO Enable Register A Set */ + + struct { + __IOM uint32_t ENSA : 32; /*!< [31..0] Set the GPIO31-0 output enables */ + } ENSA_b; + } ; + + union { + __IOM uint32_t ENSB; /*!< (@ 0x000000AC) GPIO Enable Register B Set */ + + struct { + __IOM uint32_t ENSB : 18; /*!< [17..0] Set the GPIO49-32 output enables */ + } ENSB_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t ENCA; /*!< (@ 0x000000B4) GPIO Enable Register A Clear */ + + struct { + __IOM uint32_t ENCA : 32; /*!< [31..0] Clear the GPIO31-0 output enables */ + } ENCA_b; + } ; + + union { + __IOM uint32_t ENCB; /*!< (@ 0x000000B8) GPIO Enable Register B Clear */ + + struct { + __IOM uint32_t ENCB : 18; /*!< [17..0] Clear the GPIO49-32 output enables */ + } ENCB_b; + } ; + + union { + __IOM uint32_t STMRCAP; /*!< (@ 0x000000BC) STIMER Capture Control */ + + struct { + __IOM uint32_t STSEL0 : 6; /*!< [5..0] STIMER Capture 0 Select. */ + __IOM uint32_t STPOL0 : 1; /*!< [6..6] STIMER Capture 0 Polarity. */ + __IM uint32_t : 1; + __IOM uint32_t STSEL1 : 6; /*!< [13..8] STIMER Capture 1 Select. */ + __IOM uint32_t STPOL1 : 1; /*!< [14..14] STIMER Capture 1 Polarity. */ + __IM uint32_t : 1; + __IOM uint32_t STSEL2 : 6; /*!< [21..16] STIMER Capture 2 Select. */ + __IOM uint32_t STPOL2 : 1; /*!< [22..22] STIMER Capture 2 Polarity. */ + __IM uint32_t : 1; + __IOM uint32_t STSEL3 : 6; /*!< [29..24] STIMER Capture 3 Select. */ + __IOM uint32_t STPOL3 : 1; /*!< [30..30] STIMER Capture 3 Polarity. */ + } STMRCAP_b; + } ; + + union { + __IOM uint32_t IOM0IRQ; /*!< (@ 0x000000C0) IOM0 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM0IRQ : 6; /*!< [5..0] IOMSTR0 IRQ pad select. */ + } IOM0IRQ_b; + } ; + + union { + __IOM uint32_t IOM1IRQ; /*!< (@ 0x000000C4) IOM1 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM1IRQ : 6; /*!< [5..0] IOMSTR1 IRQ pad select. */ + } IOM1IRQ_b; + } ; + + union { + __IOM uint32_t IOM2IRQ; /*!< (@ 0x000000C8) IOM2 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM2IRQ : 6; /*!< [5..0] IOMSTR2 IRQ pad select. */ + } IOM2IRQ_b; + } ; + + union { + __IOM uint32_t IOM3IRQ; /*!< (@ 0x000000CC) IOM3 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM3IRQ : 6; /*!< [5..0] IOMSTR3 IRQ pad select. */ + } IOM3IRQ_b; + } ; + + union { + __IOM uint32_t IOM4IRQ; /*!< (@ 0x000000D0) IOM4 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM4IRQ : 6; /*!< [5..0] IOMSTR4 IRQ pad select. */ + } IOM4IRQ_b; + } ; + + union { + __IOM uint32_t IOM5IRQ; /*!< (@ 0x000000D4) IOM5 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM5IRQ : 6; /*!< [5..0] IOMSTR5 IRQ pad select. */ + } IOM5IRQ_b; + } ; + + union { + __IOM uint32_t LOOPBACK; /*!< (@ 0x000000D8) IOM to IOS Loopback Control */ + + struct { + __IOM uint32_t LOOPBACK : 3; /*!< [2..0] IOM to IOS loopback control. */ + } LOOPBACK_b; + } ; + + union { + __IOM uint32_t GPIOOBS; /*!< (@ 0x000000DC) GPIO Observation Mode Sample register */ + + struct { + __IOM uint32_t OBS_DATA : 16; /*!< [15..0] Sample of the data output on the GPIO observation port. + May have async sampling issues, as the data is not synronized + to the read operation. Intended for debug purposes only */ + } GPIOOBS_b; + } ; + + union { + __IOM uint32_t ALTPADCFGA; /*!< (@ 0x000000E0) Alternate Pad Configuration reg0 (Pads 3,2,1,0) */ + + struct { + __IOM uint32_t PAD0_DS1 : 1; /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction + with PAD0STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD0_SR : 1; /*!< [4..4] Pad 0 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD1_DS1 : 1; /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction + with PAD1STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD1_SR : 1; /*!< [12..12] Pad 1 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD2_DS1 : 1; /*!< [16..16] Pad 2 high order drive strength selection. Used in + conjunction with PAD2STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD2_SR : 1; /*!< [20..20] Pad 2 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD3_DS1 : 1; /*!< [24..24] Pad 3 high order drive strength selection. Used in + conjunction with PAD3STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD3_SR : 1; /*!< [28..28] Pad 3 slew rate selection. */ + } ALTPADCFGA_b; + } ; + + union { + __IOM uint32_t ALTPADCFGB; /*!< (@ 0x000000E4) Alternate Pad Configuration reg1 (Pads 7,6,5,4) */ + + struct { + __IOM uint32_t PAD4_DS1 : 1; /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction + with PAD4STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD4_SR : 1; /*!< [4..4] Pad 4 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD5_DS1 : 1; /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction + with PAD5STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD5_SR : 1; /*!< [12..12] Pad 5 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD6_DS1 : 1; /*!< [16..16] Pad 6 high order drive strength selection. Used in + conjunction with PAD6STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD6_SR : 1; /*!< [20..20] Pad 6 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD7_DS1 : 1; /*!< [24..24] Pad 7 high order drive strength selection. Used in + conjunction with PAD7STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD7_SR : 1; /*!< [28..28] Pad 7 slew rate selection. */ + } ALTPADCFGB_b; + } ; + + union { + __IOM uint32_t ALTPADCFGC; /*!< (@ 0x000000E8) Alternate Pad Configuration reg2 (Pads 11,10,9,8) */ + + struct { + __IOM uint32_t PAD8_DS1 : 1; /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction + with PAD8STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD8_SR : 1; /*!< [4..4] Pad 8 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD9_DS1 : 1; /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction + with PAD9STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD9_SR : 1; /*!< [12..12] Pad 9 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD10_DS1 : 1; /*!< [16..16] Pad 10 high order drive strength selection. Used in + conjunction with PAD10STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD10_SR : 1; /*!< [20..20] Pad 10 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD11_DS1 : 1; /*!< [24..24] Pad 11 high order drive strength selection. Used in + conjunction with PAD11STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD11_SR : 1; /*!< [28..28] Pad 11 slew rate selection. */ + } ALTPADCFGC_b; + } ; + + union { + __IOM uint32_t ALTPADCFGD; /*!< (@ 0x000000EC) Alternate Pad Configuration reg3 (Pads 15,14,13,12) */ + + struct { + __IOM uint32_t PAD12_DS1 : 1; /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction + with PAD12STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD12_SR : 1; /*!< [4..4] Pad 12 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD13_DS1 : 1; /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction + with PAD13STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD13_SR : 1; /*!< [12..12] Pad 13 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD14_DS1 : 1; /*!< [16..16] Pad 14 high order drive strength selection. Used in + conjunction with PAD14STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD14_SR : 1; /*!< [20..20] Pad 14 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD15_DS1 : 1; /*!< [24..24] Pad 15 high order drive strength selection. Used in + conjunction with PAD15STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD15_SR : 1; /*!< [28..28] Pad 15 slew rate selection. */ + } ALTPADCFGD_b; + } ; + + union { + __IOM uint32_t ALTPADCFGE; /*!< (@ 0x000000F0) Alternate Pad Configuration reg4 (Pads 19,18,17,16) */ + + struct { + __IOM uint32_t PAD16_DS1 : 1; /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction + with PAD16STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD16_SR : 1; /*!< [4..4] Pad 16 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD17_DS1 : 1; /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction + with PAD17STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD17_SR : 1; /*!< [12..12] Pad 17 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD18_DS1 : 1; /*!< [16..16] Pad 18 high order drive strength selection. Used in + conjunction with PAD18STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD18_SR : 1; /*!< [20..20] Pad 18 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD19_DS1 : 1; /*!< [24..24] Pad 19 high order drive strength selection. Used in + conjunction with PAD19STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD19_SR : 1; /*!< [28..28] Pad 19 slew rate selection. */ + } ALTPADCFGE_b; + } ; + + union { + __IOM uint32_t ALTPADCFGF; /*!< (@ 0x000000F4) Alternate Pad Configuration reg5 (Pads 23,22,21,20) */ + + struct { + __IOM uint32_t PAD20_DS1 : 1; /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction + with PAD20STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD20_SR : 1; /*!< [4..4] Pad 20 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD21_DS1 : 1; /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction + with PAD21STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD21_SR : 1; /*!< [12..12] Pad 21 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD22_DS1 : 1; /*!< [16..16] Pad 22 high order drive strength selection. Used in + conjunction with PAD22STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD22_SR : 1; /*!< [20..20] Pad 22 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD23_DS1 : 1; /*!< [24..24] Pad 23 high order drive strength selection. Used in + conjunction with PAD23STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD23_SR : 1; /*!< [28..28] Pad 23 slew rate selection. */ + } ALTPADCFGF_b; + } ; + + union { + __IOM uint32_t ALTPADCFGG; /*!< (@ 0x000000F8) Alternate Pad Configuration reg6 (Pads 27,26,25,24) */ + + struct { + __IOM uint32_t PAD24_DS1 : 1; /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction + with PAD24STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD24_SR : 1; /*!< [4..4] Pad 24 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD25_DS1 : 1; /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction + with PAD25STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD25_SR : 1; /*!< [12..12] Pad 25 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD26_DS1 : 1; /*!< [16..16] Pad 26 high order drive strength selection. Used in + conjunction with PAD26STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD26_SR : 1; /*!< [20..20] Pad 26 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD27_DS1 : 1; /*!< [24..24] Pad 27 high order drive strength selection. Used in + conjunction with PAD27STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD27_SR : 1; /*!< [28..28] Pad 27 slew rate selection. */ + } ALTPADCFGG_b; + } ; + + union { + __IOM uint32_t ALTPADCFGH; /*!< (@ 0x000000FC) Alternate Pad Configuration reg7 (Pads 31,30,29,28) */ + + struct { + __IOM uint32_t PAD28_DS1 : 1; /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction + with PAD28STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD28_SR : 1; /*!< [4..4] Pad 28 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD29_DS1 : 1; /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction + with PAD29STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD29_SR : 1; /*!< [12..12] Pad 29 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD30_DS1 : 1; /*!< [16..16] Pad 30 high order drive strength selection. Used in + conjunction with PAD30STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD30_SR : 1; /*!< [20..20] Pad 30 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD31_DS1 : 1; /*!< [24..24] Pad 31 high order drive strength selection. Used in + conjunction with PAD31STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD31_SR : 1; /*!< [28..28] Pad 31 slew rate selection. */ + } ALTPADCFGH_b; + } ; + + union { + __IOM uint32_t ALTPADCFGI; /*!< (@ 0x00000100) Alternate Pad Configuration reg8 (Pads 35,34,33,32) */ + + struct { + __IOM uint32_t PAD32_DS1 : 1; /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction + with PAD32STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD32_SR : 1; /*!< [4..4] Pad 32 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD33_DS1 : 1; /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction + with PAD33STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD33_SR : 1; /*!< [12..12] Pad 33 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD34_DS1 : 1; /*!< [16..16] Pad 34 high order drive strength selection. Used in + conjunction with PAD34STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD34_SR : 1; /*!< [20..20] Pad 34 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD35_DS1 : 1; /*!< [24..24] Pad 35 high order drive strength selection. Used in + conjunction with PAD35STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD35_SR : 1; /*!< [28..28] Pad 35 slew rate selection. */ + } ALTPADCFGI_b; + } ; + + union { + __IOM uint32_t ALTPADCFGJ; /*!< (@ 0x00000104) Alternate Pad Configuration reg9 (Pads 39,38,37,36) */ + + struct { + __IOM uint32_t PAD36_DS1 : 1; /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction + with PAD36STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD36_SR : 1; /*!< [4..4] Pad 36 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD37_DS1 : 1; /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction + with PAD37STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD37_SR : 1; /*!< [12..12] Pad 37 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD38_DS1 : 1; /*!< [16..16] Pad 38 high order drive strength selection. Used in + conjunction with PAD38STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD38_SR : 1; /*!< [20..20] Pad 38 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD39_DS1 : 1; /*!< [24..24] Pad 39 high order drive strength selection. Used in + conjunction with PAD39STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD39_SR : 1; /*!< [28..28] Pad 39 slew rate selection. */ + } ALTPADCFGJ_b; + } ; + + union { + __IOM uint32_t ALTPADCFGK; /*!< (@ 0x00000108) Alternate Pad Configuration reg10 (Pads 43,42,41,40) */ + + struct { + __IOM uint32_t PAD40_DS1 : 1; /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction + with PAD40STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD40_SR : 1; /*!< [4..4] Pad 40 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD41_DS1 : 1; /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction + with PAD41STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD41_SR : 1; /*!< [12..12] Pad 41 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD42_DS1 : 1; /*!< [16..16] Pad 42 high order drive strength selection. Used in + conjunction with PAD42STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD42_SR : 1; /*!< [20..20] Pad 42 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD43_DS1 : 1; /*!< [24..24] Pad 43 high order drive strength selection. Used in + conjunction with PAD43STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD43_SR : 1; /*!< [28..28] Pad 43 slew rate selection. */ + } ALTPADCFGK_b; + } ; + + union { + __IOM uint32_t ALTPADCFGL; /*!< (@ 0x0000010C) Alternate Pad Configuration reg11 (Pads 47,46,45,44) */ + + struct { + __IOM uint32_t PAD44_DS1 : 1; /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction + with PAD44STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD44_SR : 1; /*!< [4..4] Pad 44 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD45_DS1 : 1; /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction + with PAD45STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD45_SR : 1; /*!< [12..12] Pad 45 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD46_DS1 : 1; /*!< [16..16] Pad 46 high order drive strength selection. Used in + conjunction with PAD46STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD46_SR : 1; /*!< [20..20] Pad 46 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD47_DS1 : 1; /*!< [24..24] Pad 47 high order drive strength selection. Used in + conjunction with PAD47STRNG field to set the pad drive + strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD47_SR : 1; /*!< [28..28] Pad 47 slew rate selection. */ + } ALTPADCFGL_b; + } ; + + union { + __IOM uint32_t ALTPADCFGM; /*!< (@ 0x00000110) Alternate Pad Configuration reg12 (Pads 49,48) */ + + struct { + __IOM uint32_t PAD48_DS1 : 1; /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction + with PAD48STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD48_SR : 1; /*!< [4..4] Pad 48 slew rate selection. */ + __IM uint32_t : 3; + __IOM uint32_t PAD49_DS1 : 1; /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction + with PAD49STRNG field to set the pad drive strength. */ + __IM uint32_t : 3; + __IOM uint32_t PAD49_SR : 1; /*!< [12..12] Pad 49 slew rate selection. */ + } ALTPADCFGM_b; + } ; + __IM uint32_t RESERVED4[59]; + + union { + __IOM uint32_t INT0EN; /*!< (@ 0x00000200) GPIO Interrupt Registers 31-0: Enable */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0EN_b; + } ; + + union { + __IOM uint32_t INT0STAT; /*!< (@ 0x00000204) GPIO Interrupt Registers 31-0: Status */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0STAT_b; + } ; + + union { + __IOM uint32_t INT0CLR; /*!< (@ 0x00000208) GPIO Interrupt Registers 31-0: Clear */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0CLR_b; + } ; + + union { + __IOM uint32_t INT0SET; /*!< (@ 0x0000020C) GPIO Interrupt Registers 31-0: Set */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0SET_b; + } ; + + union { + __IOM uint32_t INT1EN; /*!< (@ 0x00000210) GPIO Interrupt Registers 49-32: Enable */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1EN_b; + } ; + + union { + __IOM uint32_t INT1STAT; /*!< (@ 0x00000214) GPIO Interrupt Registers 49-32: Status */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1STAT_b; + } ; + + union { + __IOM uint32_t INT1CLR; /*!< (@ 0x00000218) GPIO Interrupt Registers 49-32: Clear */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1CLR_b; + } ; + + union { + __IOM uint32_t INT1SET; /*!< (@ 0x0000021C) GPIO Interrupt Registers 49-32: Set */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1SET_b; + } ; +} GPIO_Type; /*!< Size = 544 (0x220) */ + + + +/* =========================================================================================================================== */ +/* ================ IOMSTR0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C/SPI Master (IOMSTR0) + */ + +typedef struct { /*!< (@ 0x50004000) IOMSTR0 Structure */ + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ + + struct { + __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO access port. */ + } FIFO_b; + } ; + __IM uint32_t RESERVED[63]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointers */ + + struct { + __IOM uint32_t FIFOSIZ : 8; /*!< [7..0] The number of bytes currently in the FIFO. */ + __IM uint32_t : 8; + __IOM uint32_t FIFOREM : 8; /*!< [23..16] The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ + if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t TLNGTH; /*!< (@ 0x00000104) Transfer Length */ + + struct { + __IOM uint32_t TLNGTH : 12; /*!< [11..0] Remaining transfer length. */ + } TLNGTH_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFORTHR : 7; /*!< [6..0] FIFO read threshold. */ + __IM uint32_t : 1; + __IOM uint32_t FIFOWTHR : 7; /*!< [14..8] FIFO write threshold. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000010C) I/O Clock Configuration */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ + __IOM uint32_t DIV3 : 1; /*!< [11..11] Enable divide by 3. */ + __IOM uint32_t DIVEN : 1; /*!< [12..12] Enable clock division by TOTPER. */ + __IM uint32_t : 3; + __IOM uint32_t LOWPER : 8; /*!< [23..16] Clock low count minus 1. */ + __IOM uint32_t TOTPER : 8; /*!< [31..24] Clock total count minus 1. */ + } CLKCFG_b; + } ; + + union { + __IOM uint32_t CMD; /*!< (@ 0x00000110) Command Register */ + + struct { + __IOM uint32_t CMD : 32; /*!< [31..0] This register holds the I/O Command */ + } CMD_b; + } ; + + union { + __IOM uint32_t CMDRPT; /*!< (@ 0x00000114) Command Repeat Register */ + + struct { + __IOM uint32_t CMDRPT : 5; /*!< [4..0] These bits hold the Command repeat count. */ + } CMDRPT_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000118) Status Register */ + + struct { + __IOM uint32_t ERR : 1; /*!< [0..0] This bit indicates if an error interrupt has occurred. */ + __IOM uint32_t CMDACT : 1; /*!< [1..1] This bit indicates if the I/O Command is active. */ + __IOM uint32_t IDLEST : 1; /*!< [2..2] This bit indicates if the I/O state machine is IDLE. */ + } STATUS_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x0000011C) I/O Master Configuration */ + + struct { + __IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */ + __IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */ + __IOM uint32_t SPHA : 1; /*!< [2..2] This bit selects SPI phase. */ + __IOM uint32_t FULLDUP : 1; /*!< [3..3] This bit selects full duplex mode. */ + __IOM uint32_t STARTRD : 2; /*!< [5..4] This bit selects the preread timing. */ + __IM uint32_t : 2; + __IOM uint32_t WTFC : 1; /*!< [8..8] This bit enables write mode flow control. */ + __IOM uint32_t RDFC : 1; /*!< [9..9] This bit enables read mode flow control. */ + __IOM uint32_t MOSIINV : 1; /*!< [10..10] This bit invewrts MOSI when flow control is enabled. */ + __IOM uint32_t FCDEL : 1; /*!< [11..11] This bit must be left at the default value of 0. */ + __IOM uint32_t WTFCIRQ : 1; /*!< [12..12] This bit selects the write mode flow control signal. */ + __IOM uint32_t WTFCPOL : 1; /*!< [13..13] This bit selects the write flow control signal polarity. */ + __IOM uint32_t RDFCPOL : 1; /*!< [14..14] This bit selects the read flow control signal polarity. */ + __IM uint32_t : 16; + __IOM uint32_t IFCEN : 1; /*!< [31..31] This bit enables the IO Master. */ + } CFG_b; + } ; + __IM uint32_t RESERVED1[56]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */ + __IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Read FIFO Underflow interrupt. An attempt + was made to read FIFO when empty (i.e. while FIFOSIZ less + than 4). */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Write FIFO Overflow interrupt. An attempt + was made to write the FIFO while it was full (i.e. while + FIFOSIZ > 124). */ + __IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. The expected ACK from + the slave was not received by the IOM. */ + __IOM uint32_t WTLEN : 1; /*!< [5..5] This is the WTLEN interrupt. */ + __IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. An attempt + was made to read the FIFO during a write CMD. Or an attempt + was made to write the FIFO on a read CMD. */ + __IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. Software attempted + to issue a CMD while another CMD was already in progress. + Or an attempt was made to issue a non-zero-length write + CMD with an empty FIFO. */ + __IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. A START from another + master was detected. Software must wait for a STOP before + proceeding. */ + __IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. A STOP bit was detected + by the IOM. */ + __IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. This error + occurs if another master collides with an IO Master transfer. + Generally, the IOM started an operation but found SDA already + low. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */ + __IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Read FIFO Underflow interrupt. An attempt + was made to read FIFO when empty (i.e. while FIFOSIZ less + than 4). */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Write FIFO Overflow interrupt. An attempt + was made to write the FIFO while it was full (i.e. while + FIFOSIZ > 124). */ + __IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. The expected ACK from + the slave was not received by the IOM. */ + __IOM uint32_t WTLEN : 1; /*!< [5..5] This is the WTLEN interrupt. */ + __IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. An attempt + was made to read the FIFO during a write CMD. Or an attempt + was made to write the FIFO on a read CMD. */ + __IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. Software attempted + to issue a CMD while another CMD was already in progress. + Or an attempt was made to issue a non-zero-length write + CMD with an empty FIFO. */ + __IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. A START from another + master was detected. Software must wait for a STOP before + proceeding. */ + __IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. A STOP bit was detected + by the IOM. */ + __IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. This error + occurs if another master collides with an IO Master transfer. + Generally, the IOM started an operation but found SDA already + low. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */ + __IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Read FIFO Underflow interrupt. An attempt + was made to read FIFO when empty (i.e. while FIFOSIZ less + than 4). */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Write FIFO Overflow interrupt. An attempt + was made to write the FIFO while it was full (i.e. while + FIFOSIZ > 124). */ + __IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. The expected ACK from + the slave was not received by the IOM. */ + __IOM uint32_t WTLEN : 1; /*!< [5..5] This is the WTLEN interrupt. */ + __IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. An attempt + was made to read the FIFO during a write CMD. Or an attempt + was made to write the FIFO on a read CMD. */ + __IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. Software attempted + to issue a CMD while another CMD was already in progress. + Or an attempt was made to issue a non-zero-length write + CMD with an empty FIFO. */ + __IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. A START from another + master was detected. Software must wait for a STOP before + proceeding. */ + __IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. A STOP bit was detected + by the IOM. */ + __IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. This error + occurs if another master collides with an IO Master transfer. + Generally, the IOM started an operation but found SDA already + low. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */ + __IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Read FIFO Underflow interrupt. An attempt + was made to read FIFO when empty (i.e. while FIFOSIZ less + than 4). */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Write FIFO Overflow interrupt. An attempt + was made to write the FIFO while it was full (i.e. while + FIFOSIZ > 124). */ + __IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. The expected ACK from + the slave was not received by the IOM. */ + __IOM uint32_t WTLEN : 1; /*!< [5..5] This is the WTLEN interrupt. */ + __IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. An attempt + was made to read the FIFO during a write CMD. Or an attempt + was made to write the FIFO on a read CMD. */ + __IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. Software attempted + to issue a CMD while another CMD was already in progress. + Or an attempt was made to issue a non-zero-length write + CMD with an empty FIFO. */ + __IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. A START from another + master was detected. Software must wait for a STOP before + proceeding. */ + __IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. A STOP bit was detected + by the IOM. */ + __IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. This error + occurs if another master collides with an IO Master transfer. + Generally, the IOM started an operation but found SDA already + low. */ + } INTSET_b; + } ; +} IOMSTR0_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C/SPI Slave (IOSLAVE) + */ + +typedef struct { /*!< (@ 0x50000000) IOSLAVE Structure */ + __IM uint32_t RESERVED[64]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointer */ + + struct { + __IOM uint32_t FIFOPTR : 8; /*!< [7..0] Current FIFO pointer. */ + __IOM uint32_t FIFOSIZ : 8; /*!< [15..8] The number of bytes currently in the hardware FIFO. */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOCFG; /*!< (@ 0x00000104) FIFO Configuration */ + + struct { + __IOM uint32_t FIFOBASE : 5; /*!< [4..0] These bits hold the base address of the I/O FIFO in 8 + byte segments. The IO Slave FIFO is situated in LRAM at + (FIFOBASE*8) to (FIFOMAX*8-1). */ + __IM uint32_t : 3; + __IOM uint32_t FIFOMAX : 6; /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments. + It is also the beginning of the RAM area of the LRAM. Note + that no RAM area is configured if FIFOMAX is set to 0x1F. */ + __IM uint32_t : 10; + __IOM uint32_t ROBASE : 6; /*!< [29..24] Defines the read-only area. The IO Slave read-only + area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1) */ + } FIFOCFG_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO size interrupt threshold. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FUPD; /*!< (@ 0x0000010C) FIFO Update Status */ + + struct { + __IOM uint32_t FIFOUPD : 1; /*!< [0..0] This bit indicates that a FIFO update is underway. */ + __IOM uint32_t IOREAD : 1; /*!< [1..1] This bitfield indicates an IO read is active. */ + } FUPD_b; + } ; + + union { + __IOM uint32_t FIFOCTR; /*!< (@ 0x00000110) Overall FIFO Counter */ + + struct { + __IOM uint32_t FIFOCTR : 10; /*!< [9..0] Virtual FIFO byte count */ + } FIFOCTR_b; + } ; + + union { + __IOM uint32_t FIFOINC; /*!< (@ 0x00000114) Overall FIFO Counter Increment */ + + struct { + __IOM uint32_t FIFOINC : 10; /*!< [9..0] Increment the Overall FIFO Counter by this value on a + write */ + } FIFOINC_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000118) I/O Slave Configuration */ + + struct { + __IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */ + __IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */ + __IOM uint32_t LSB : 1; /*!< [2..2] This bit selects the transfer bit ordering. */ + __IM uint32_t : 1; + __IOM uint32_t STARTRD : 1; /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read. */ + __IM uint32_t : 3; + __IOM uint32_t I2CADDR : 12; /*!< [19..8] 7-bit or 10-bit I2C device address. */ + __IM uint32_t : 11; + __IOM uint32_t IFCEN : 1; /*!< [31..31] IOSLAVE interface enable. */ + } CFG_b; + } ; + + union { + __IOM uint32_t PRENC; /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode */ + + struct { + __IOM uint32_t PRENC : 5; /*!< [4..0] These bits hold the priority encode of the REGACC interrupts. */ + } PRENC_b; + } ; + + union { + __IOM uint32_t IOINTCTL; /*!< (@ 0x00000120) I/O Interrupt Control */ + + struct { + __IOM uint32_t IOINTEN : 8; /*!< [7..0] These read-only bits indicate whether the IOINT interrupts + are enabled. */ + __IOM uint32_t IOINT : 8; /*!< [15..8] These bits read the IOINT interrupts. */ + __IOM uint32_t IOINTCLR : 1; /*!< [16..16] This bit clears all of the IOINT interrupts when written + with a 1. */ + __IM uint32_t : 7; + __IOM uint32_t IOINTSET : 8; /*!< [31..24] These bits set the IOINT interrupts when written with + a 1. */ + } IOINTCTL_b; + } ; + + union { + __IOM uint32_t GENADD; /*!< (@ 0x00000124) General Address Data */ + + struct { + __IOM uint32_t GADATA : 8; /*!< [7..0] The data supplied on the last General Address reference. */ + } GENADD_b; + } ; + __IM uint32_t RESERVED1[54]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Slave Interrupts: Enable */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Slave Interrupts: Status */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Slave Interrupts: Clear */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Slave Interrupts: Set */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTSET_b; + } ; + + union { + __IOM uint32_t REGACCINTEN; /*!< (@ 0x00000210) Register Access Interrupts: Enable */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTEN_b; + } ; + + union { + __IOM uint32_t REGACCINTSTAT; /*!< (@ 0x00000214) Register Access Interrupts: Status */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTSTAT_b; + } ; + + union { + __IOM uint32_t REGACCINTCLR; /*!< (@ 0x00000218) Register Access Interrupts: Clear */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTCLR_b; + } ; + + union { + __IOM uint32_t REGACCINTSET; /*!< (@ 0x0000021C) Register Access Interrupts: Set */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTSET_b; + } ; +} IOSLAVE_Type; /*!< Size = 544 (0x220) */ + + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU Miscellaneous Control Logic (MCUCTRL) + */ + +typedef struct { /*!< (@ 0x40020000) MCUCTRL Structure */ + + union { + __IOM uint32_t CHIP_INFO; /*!< (@ 0x00000000) Chip Information Register */ + + struct { + __IOM uint32_t PARTNUM : 32; /*!< [31..0] BCD part number. */ + } CHIP_INFO_b; + } ; + + union { + __IOM uint32_t CHIPID0; /*!< (@ 0x00000004) Unique Chip ID 0 */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Unique chip ID 0. */ + } CHIPID0_b; + } ; + + union { + __IOM uint32_t CHIPID1; /*!< (@ 0x00000008) Unique Chip ID 1 */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Unique chip ID 1. */ + } CHIPID1_b; + } ; + + union { + __IOM uint32_t CHIPREV; /*!< (@ 0x0000000C) Chip Revision */ + + struct { + __IOM uint32_t REVMIN : 4; /*!< [3..0] Minor Revision ID. */ + __IOM uint32_t REVMAJ : 4; /*!< [7..4] Major Revision ID. */ + } CHIPREV_b; + } ; + + union { + __IOM uint32_t VENDORID; /*!< (@ 0x00000010) Unique Vendor ID */ + + struct { + __IOM uint32_t VALUE : 32; /*!< [31..0] Unique Vendor ID */ + } VENDORID_b; + } ; + + union { + __IOM uint32_t DEBUGGER; /*!< (@ 0x00000014) Debugger Access Control */ + + struct { + __IOM uint32_t LOCKOUT : 1; /*!< [0..0] Lockout of debugger (SWD). */ + } DEBUGGER_b; + } ; + __IM uint32_t RESERVED[18]; + + union { + __IOM uint32_t BUCK; /*!< (@ 0x00000060) Analog Buck Control */ + + struct { + __IOM uint32_t BUCKSWE : 1; /*!< [0..0] Buck Register Software Override Enable. This will enable + the override values for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, + MEMBUCKRST, all to be propagated to the control logic, + instead of the normal power control module signal. Note + - Must take care to have correct value for ALL the register + bits when this SWE is enabled. */ + __IOM uint32_t BYPBUCKCORE : 1; /*!< [1..1] Not used. Additional control of buck is available in + the power control module */ + __IOM uint32_t COREBUCKPWD : 1; /*!< [2..2] Core buck power down override. 1=Powered Down; 0=Enabled; + Value is propagated only when the BUCKSWE bit is active, + otherwise control is from the power control module. */ + __IOM uint32_t SLEEPBUCKANA : 1; /*!< [3..3] HFRC clkgen bit 0 override. When set, this will override + to 0 bit 0 of the hfrc_freq_clkgen internal bus (see internal + Shelby-1473) */ + __IOM uint32_t MEMBUCKPWD : 1; /*!< [4..4] Memory buck power down override. 1=Powered Down; 0=Enabled; + Value is propagated only when the BUCKSWE bit is active, + otherwise control is from the power control module. */ + __IOM uint32_t BYPBUCKMEM : 1; /*!< [5..5] Not used. Additional control of buck is available in + the power control module */ + __IOM uint32_t COREBUCKRST : 1; /*!< [6..6] Reset control override for Core Buck; 0=enabled, 1=reset; + Value is propagated only when the BUCKSWE bit is active, + otherwise control is from the power control module. */ + __IOM uint32_t MEMBUCKRST : 1; /*!< [7..7] Reset control override for Mem Buck; 0=enabled, 1=reset; + Value is propagated only when the BUCKSWE bit is active, + otherwise contrl is from the power control module. */ + } BUCK_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t BUCK3; /*!< (@ 0x00000068) Buck control reg 3 */ + + struct { + __IOM uint32_t COREBUCKHYSTTRIM : 2; /*!< [1..0] Hysterisis trim for core buck */ + __IOM uint32_t COREBUCKZXTRIM : 4; /*!< [5..2] Core buck zero crossing trim value */ + __IOM uint32_t COREBUCKBURSTEN : 1; /*!< [6..6] Core Buck burst enable. 0=disabled, 1=enabled */ + __IOM uint32_t COREBUCKLOTON : 4; /*!< [10..7] Core Buck low TON trim value */ + __IOM uint32_t MEMBUCKHYSTTRIM : 2; /*!< [12..11] Hysterisis trim for mem buck */ + __IOM uint32_t MEMBUCKZXTRIM : 4; /*!< [16..13] Memory buck zero crossing trim value */ + __IOM uint32_t MEMBUCKBURSTEN : 1; /*!< [17..17] MEM Buck burst enable 0=disable, 0=disabled, 1=enable. */ + __IOM uint32_t MEMBUCKLOTON : 4; /*!< [21..18] MEM Buck low TON trim value */ + } BUCK3_b; + } ; + __IM uint32_t RESERVED2[5]; + + union { + __IOM uint32_t LDOREG1; /*!< (@ 0x00000080) Analog LDO Reg 1 */ + + struct { + __IOM uint32_t TRIMCORELDOR1 : 10; /*!< [9..0] CORE LDO Active mode ouput trim (R1). */ + __IOM uint32_t TRIMCORELDOR3 : 4; /*!< [13..10] CORE LDO tempco trim (R3). */ + __IOM uint32_t CORELDOLPTRIM : 6; /*!< [19..14] CORE LDO Low Power Trim */ + __IOM uint32_t CORELDOIBSTRM : 1; /*!< [20..20] CORE LDO IBIAS Trim */ + } LDOREG1_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t LDOREG3; /*!< (@ 0x00000088) LDO Control Register 3 */ + + struct { + __IOM uint32_t MEMLDOLPTRIM : 6; /*!< [5..0] MEM LDO TRIM for low power mode with ADC inactive */ + __IOM uint32_t MEMLDOLPALTTRIM : 6; /*!< [11..6] MEM LDO TRIM for low power mode with ADC active */ + __IOM uint32_t TRIMMEMLDOR1 : 6; /*!< [17..12] MEM LDO active mode trim (R1). */ + } LDOREG3_b; + } ; + __IM uint32_t RESERVED4[29]; + + union { + __IOM uint32_t BODPORCTRL; /*!< (@ 0x00000100) BOD and PDR control Register */ + + struct { + __IOM uint32_t PWDPDR : 1; /*!< [0..0] PDR Power Down. */ + __IOM uint32_t PWDBOD : 1; /*!< [1..1] BOD Power Down. */ + __IOM uint32_t PDREXTREFSEL : 1; /*!< [2..2] PDR External Reference Select. */ + __IOM uint32_t BODEXTREFSEL : 1; /*!< [3..3] BOD External Reference Select. */ + } BODPORCTRL_b; + } ; + + union { + __IOM uint32_t ADCPWRDLY; /*!< (@ 0x00000104) ADC Power Up Delay Control */ + + struct { + __IOM uint32_t ADCPWR0 : 8; /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK + increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments + for ADC_CLKSEL = 0x2. */ + __IOM uint32_t ADCPWR1 : 8; /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments + for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL + = 0x2. */ + } ADCPWRDLY_b; + } ; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t ADCCAL; /*!< (@ 0x0000010C) ADC Calibration Control */ + + struct { + __IOM uint32_t CALONPWRUP : 1; /*!< [0..0] Run ADC Calibration on initial power up sequence */ + __IOM uint32_t ADCCALIBRATED : 1; /*!< [1..1] Status for ADC Calibration */ + } ADCCAL_b; + } ; + + union { + __IOM uint32_t ADCBATTLOAD; /*!< (@ 0x00000110) ADC Battery Load Enable */ + + struct { + __IOM uint32_t BATTLOAD : 1; /*!< [0..0] Enable the ADC battery load resistor */ + } ADCBATTLOAD_b; + } ; + + union { + __IOM uint32_t BUCKTRIM; /*!< (@ 0x00000114) Trim settings for Core and Mem buck modules */ + + struct { + __IOM uint32_t MEMBUCKR1 : 6; /*!< [5..0] Trim values for BUCK regulator. */ + __IM uint32_t : 2; + __IOM uint32_t COREBUCKR1_LO : 6; /*!< [13..8] Core Buck voltage output trim bits[5:0], Concatenate + with field COREBUCKR1_HI for the full trim value. */ + __IM uint32_t : 2; + __IOM uint32_t COREBUCKR1_HI : 4; /*!< [19..16] Core Buck voltage output trim bits[9:6]. Concatenate + with field COREBUCKR1_LO for the full trim value. */ + __IM uint32_t : 4; + __IOM uint32_t RSVD2 : 6; /*!< [29..24] RESERVED. */ + } BUCKTRIM_b; + } ; + __IM uint32_t RESERVED6[3]; + + union { + __IOM uint32_t XTALGENCTRL; /*!< (@ 0x00000124) XTAL Oscillator General Control */ + + struct { + __IOM uint32_t ACWARMUP : 2; /*!< [1..0] Auto-calibration delay control */ + __IOM uint32_t XTALBIASTRIM : 6; /*!< [7..2] XTAL IBIAS trim */ + __IOM uint32_t XTALKSBIASTRIM : 6; /*!< [13..8] XTAL IBIAS Kick start trim . This trim value is used + during the startup process to enable a faster lock and + is applied when the kickstart signal is active. */ + } XTALGENCTRL_b; + } ; + __IM uint32_t RESERVED7[30]; + + union { + __IOM uint32_t BOOTLOADERLOW; /*!< (@ 0x000001A0) Determines whether the bootloader code is visible + at address 0x00000000 */ + + struct { + __IOM uint32_t VALUE : 1; /*!< [0..0] Determines whether the bootloader code is visible at + address 0x00000000 or not. */ + } BOOTLOADERLOW_b; + } ; + + union { + __IOM uint32_t SHADOWVALID; /*!< (@ 0x000001A4) Register to indicate whether the shadow registers + have been successfully loaded from the Flash + Information Space. */ + + struct { + __IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the shadow registers contain valid + data from the Flash Information Space. */ + __IOM uint32_t BL_DSLEEP : 1; /*!< [1..1] Indicates whether the bootloader should sleep or deep + sleep if no image loaded. */ + } SHADOWVALID_b; + } ; + __IM uint32_t RESERVED8[6]; + + union { + __IOM uint32_t ICODEFAULTADDR; /*!< (@ 0x000001C0) ICODE bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } ICODEFAULTADDR_b; + } ; + + union { + __IOM uint32_t DCODEFAULTADDR; /*!< (@ 0x000001C4) DCODE bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } DCODEFAULTADDR_b; + } ; + + union { + __IOM uint32_t SYSFAULTADDR; /*!< (@ 0x000001C8) System bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] SYS bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } SYSFAULTADDR_b; + } ; + + union { + __IOM uint32_t FAULTSTATUS; /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault + detection. Any write to this register will + clear all of the status bits within the + register. */ + + struct { + __IOM uint32_t ICODE : 1; /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a + fault has been detected, and the ICODEFAULTADDR register + will contain the bus address which generated the fault. */ + __IOM uint32_t DCODE : 1; /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault + has been detected, and the DCODEFAULTADDR register will + contain the bus address which generated the fault. */ + __IOM uint32_t SYS : 1; /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault + has been detected, and the SYSFAULTADDR register will contain + the bus address which generated the fault. */ + } FAULTSTATUS_b; + } ; + + union { + __IOM uint32_t FAULTCAPTUREEN; /*!< (@ 0x000001D0) Enable the fault capture registers */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture + monitors are enabled and addresses which generate a hard + fault are captured into the FAULTADDR registers. */ + } FAULTCAPTUREEN_b; + } ; + __IM uint32_t RESERVED9[11]; + + union { + __IOM uint32_t DBGR1; /*!< (@ 0x00000200) Read-only debug register 1 */ + + struct { + __IOM uint32_t ONETO8 : 32; /*!< [31..0] Read-only register for communication validation */ + } DBGR1_b; + } ; + + union { + __IOM uint32_t DBGR2; /*!< (@ 0x00000204) Read-only debug register 2 */ + + struct { + __IOM uint32_t COOLCODE : 32; /*!< [31..0] Read-only register for communication validation */ + } DBGR2_b; + } ; + __IM uint32_t RESERVED10[6]; + + union { + __IOM uint32_t PMUENABLE; /*!< (@ 0x00000220) Control bit to enable/disable the PMU */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will + place the MCU into the lowest power consuming Deep Sleep + mode upon execution of a WFI instruction (dependent on + the setting of the SLEEPDEEP bit in the ARM SCR register). + When cleared, regardless of the requested sleep mode, the + PMU will not enter the lowest power Deep Sleep mode, instead + entering the Sleep mode. */ + } PMUENABLE_b; + } ; + __IM uint32_t RESERVED11[11]; + + union { + __IOM uint32_t TPIUCTRL; /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable + and frequency for the M4's TPIU interface. */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled + and data can be streamed out of the MCU's SWO port using + the ARM ITM and TPIU modules. */ + __IM uint32_t : 7; + __IOM uint32_t CLKSEL : 3; /*!< [10..8] This field selects the frequency of the ARM M4 TPIU + port. */ + } TPIUCTRL_b; + } ; +} MCUCTRL_Type; /*!< Size = 596 (0x254) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PDM Audio (PDM) + */ + +typedef struct { /*!< (@ 0x50011000) PDM Structure */ + + union { + __IOM uint32_t PCFG; /*!< (@ 0x00000000) PDM Configuration Register */ + + struct { + __IOM uint32_t PDMCORE : 1; /*!< [0..0] Data Streaming Control. */ + __IOM uint32_t SOFTMUTE : 1; /*!< [1..1] Soft mute control. */ + __IOM uint32_t CYCLES : 3; /*!< [4..2] Number of clocks during gain-setting changes. */ + __IOM uint32_t HPCUTOFF : 4; /*!< [8..5] High pass filter coefficients. */ + __IOM uint32_t ADCHPD : 1; /*!< [9..9] High pass filter disable. */ + __IOM uint32_t SINCRATE : 7; /*!< [16..10] SINC decimation rate. */ + __IOM uint32_t MCLKDIV : 2; /*!< [18..17] PDM_CLK frequency divisor. */ + __IM uint32_t : 4; + __IOM uint32_t PGALEFT : 4; /*!< [26..23] Left channel PGA gain. */ + __IOM uint32_t PGARIGHT : 4; /*!< [30..27] Right channel PGA gain. */ + __IOM uint32_t LRSWAP : 1; /*!< [31..31] Left/right channel swap. */ + } PCFG_b; + } ; + + union { + __IOM uint32_t VCFG; /*!< (@ 0x00000004) Voice Configuration Register */ + + struct { + __IM uint32_t : 3; + __IOM uint32_t CHSET : 2; /*!< [4..3] Set PCM channels. */ + __IM uint32_t : 3; + __IOM uint32_t PCMPACK : 1; /*!< [8..8] PCM data packing enable. */ + __IM uint32_t : 7; + __IOM uint32_t SELAP : 1; /*!< [16..16] Select PDM input clock source. */ + __IOM uint32_t DMICKDEL : 1; /*!< [17..17] PDM clock sampling delay. */ + __IM uint32_t : 1; + __IOM uint32_t BCLKINV : 1; /*!< [19..19] I2S BCLK input inversion. */ + __IOM uint32_t I2SMODE : 1; /*!< [20..20] I2S interface enable. */ + __IM uint32_t : 5; + __IOM uint32_t PDMCLK : 1; /*!< [26..26] Enable the serial clock. */ + __IOM uint32_t PDMCLKSEL : 3; /*!< [29..27] Select the PDM input clock. */ + __IOM uint32_t RSTB : 1; /*!< [30..30] Reset the IP core. */ + __IOM uint32_t IOCLKEN : 1; /*!< [31..31] Enable the IO clock. */ + } VCFG_b; + } ; + + union { + __IOM uint32_t FR; /*!< (@ 0x00000008) Voice Status Register */ + + struct { + __IOM uint32_t FIFOCNT : 9; /*!< [8..0] Valid 32-bit entries currently in the FIFO. */ + } FR_b; + } ; + + union { + __IOM uint32_t FRD; /*!< (@ 0x0000000C) FIFO Read */ + + struct { + __IOM uint32_t FIFOREAD : 32; /*!< [31..0] FIFO read data. */ + } FRD_b; + } ; + + union { + __IOM uint32_t FLUSH; /*!< (@ 0x00000010) FIFO Flush */ + + struct { + __IOM uint32_t FIFOFLUSH : 1; /*!< [0..0] FIFO FLUSH. */ + } FLUSH_b; + } ; + + union { + __IOM uint32_t FTHR; /*!< (@ 0x00000014) FIFO Threshold */ + + struct { + __IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO interrupt threshold. */ + } FTHR_b; + } ; + __IM uint32_t RESERVED[122]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + } INTSET_b; + } ; +} PDM_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PWR Controller Register Bank (PWRCTRL) + */ + +typedef struct { /*!< (@ 0x40021000) PWRCTRL Structure */ + + union { + __IOM uint32_t SUPPLYSRC; /*!< (@ 0x00000000) Memory and Core Voltage Supply Source Select + Register */ + + struct { + __IOM uint32_t MEMBUCKEN : 1; /*!< [0..0] Enables and select the Memory Buck as the supply for + the Flash and SRAM power domain. */ + __IOM uint32_t COREBUCKEN : 1; /*!< [1..1] Enables and Selects the Core Buck as the supply for the + low-voltage power domain. */ + __IOM uint32_t SWITCH_LDO_IN_SLEEP : 1; /*!< [2..2] Switches the CORE DOMAIN from BUCK mode (if enabled) + to LDO when CPU is in DEEP SLEEP. If all the devices are + off then this does not matter and LDO (low power mode) + is used */ + } SUPPLYSRC_b; + } ; + + union { + __IOM uint32_t POWERSTATUS; /*!< (@ 0x00000004) Power Status Register for MCU supplies and peripherals */ + + struct { + __IOM uint32_t MEMBUCKON : 1; /*!< [0..0] Indicate whether the Memory power domain is supplied + from the LDO or the Buck. */ + __IOM uint32_t COREBUCKON : 1; /*!< [1..1] Indicates whether the Core low-voltage domain is supplied + from the LDO or the Buck. */ + } POWERSTATUS_b; + } ; + + union { + __IOM uint32_t DEVICEEN; /*!< (@ 0x00000008) DEVICE ENABLES for SHELBY */ + + struct { + __IOM uint32_t IO_SLAVE : 1; /*!< [0..0] Enable IO SLAVE */ + __IOM uint32_t IO_MASTER0 : 1; /*!< [1..1] Enable IO MASTER 0 */ + __IOM uint32_t IO_MASTER1 : 1; /*!< [2..2] Enable IO MASTER 1 */ + __IOM uint32_t IO_MASTER2 : 1; /*!< [3..3] Enable IO MASTER 2 */ + __IOM uint32_t IO_MASTER3 : 1; /*!< [4..4] Enable IO MASTER 3 */ + __IOM uint32_t IO_MASTER4 : 1; /*!< [5..5] Enable IO MASTER 4 */ + __IOM uint32_t IO_MASTER5 : 1; /*!< [6..6] Enable IO MASTER 5 */ + __IOM uint32_t PWRUART0 : 1; /*!< [7..7] Enable UART 0 */ + __IOM uint32_t PWRUART1 : 1; /*!< [8..8] Enable UART 1 */ + __IOM uint32_t PWRADC : 1; /*!< [9..9] Enable ADC Digital Block */ + __IOM uint32_t PWRPDM : 1; /*!< [10..10] Enable PDM Digital Block */ + } DEVICEEN_b; + } ; + + union { + __IOM uint32_t SRAMPWDINSLEEP; /*!< (@ 0x0000000C) Powerdown an SRAM Banks in Deep Sleep mode */ + + struct { + __IOM uint32_t SRAMSLEEPPOWERDOWN : 11; /*!< [10..0] Selects which SRAM banks are powered down in deep sleep + mode, causing the contents of the bank to be lost. */ + __IM uint32_t : 20; + __IOM uint32_t CACHE_PWD_SLP : 1; /*!< [31..31] Enable CACHE BANKS to power down in deep sleep */ + } SRAMPWDINSLEEP_b; + } ; + + union { + __IOM uint32_t MEMEN; /*!< (@ 0x00000010) Disables individual banks of the MEMORY array */ + + struct { + __IOM uint32_t SRAMEN : 11; /*!< [10..0] Enables power for selected SRAM banks (else an access + to its address space to generate a Hard Fault). */ + __IOM uint32_t FLASH0 : 1; /*!< [11..11] Enable FLASH 0 */ + __IOM uint32_t FLASH1 : 1; /*!< [12..12] Enable FLASH1 */ + __IM uint32_t : 16; + __IOM uint32_t CACHEB0 : 1; /*!< [29..29] Enable CACHE BANK 0 */ + __IM uint32_t : 1; + __IOM uint32_t CACHEB2 : 1; /*!< [31..31] Enable CACHE BANK 2 */ + } MEMEN_b; + } ; + + union { + __IOM uint32_t PWRONSTATUS; /*!< (@ 0x00000014) POWER ON Status */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t PDA : 1; /*!< [1..1] This bit is 1 if power is supplied to power domain A, + which supplies IOS and UART0,1. */ + __IOM uint32_t PDB : 1; /*!< [2..2] This bit is 1 if power is supplied to power domain B, + which supplies IOM0-2. */ + __IOM uint32_t PDC : 1; /*!< [3..3] This bit is 1 if power is supplied to power domain C, + which supplies IOM3-5. */ + __IOM uint32_t PD_PDM : 1; /*!< [4..4] This bit is 1 if power is supplied to domain PD_PDM */ + __IOM uint32_t PD_FLAM0 : 1; /*!< [5..5] This bit is 1 if power is supplied to domain PD_FLAM0 */ + __IOM uint32_t PD_FLAM1 : 1; /*!< [6..6] This bit is 1 if power is supplied to domain PD_FLAM1 */ + __IOM uint32_t PDADC : 1; /*!< [7..7] This bit is 1 if power is supplied to domain PD_ADC */ + __IOM uint32_t PD_GRP0_SRAM0 : 1; /*!< [8..8] This bit is 1 if power is supplied to SRAM domain SRAM0_0 */ + __IOM uint32_t PD_GRP0_SRAM1 : 1; /*!< [9..9] This bit is 1 if power is supplied to SRAM domain SRAM0_1 */ + __IOM uint32_t PD_GRP0_SRAM2 : 1; /*!< [10..10] This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2 */ + __IOM uint32_t PD_GRP0_SRAM3 : 1; /*!< [11..11] This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3 */ + __IOM uint32_t PD_GRP1_SRAM : 1; /*!< [12..12] This bit is 1 if power is supplied to SRAM domain PD_GRP1 */ + __IOM uint32_t PD_GRP2_SRAM : 1; /*!< [13..13] This bit is 1 if power is supplied to SRAM domain PD_GRP2 */ + __IOM uint32_t PD_GRP3_SRAM : 1; /*!< [14..14] This bit is 1 if power is supplied to SRAM domain PD_GRP3 */ + __IOM uint32_t PD_GRP4_SRAM : 1; /*!< [15..15] This bit is 1 if power is supplied to SRAM domain PD_GRP4 */ + __IOM uint32_t PD_GRP5_SRAM : 1; /*!< [16..16] This bit is 1 if power is supplied to SRAM domain PD_GRP5 */ + __IOM uint32_t PD_GRP6_SRAM : 1; /*!< [17..17] This bit is 1 if power is supplied to SRAM domain PD_GRP6 */ + __IOM uint32_t PD_GRP7_SRAM : 1; /*!< [18..18] This bit is 1 if power is supplied to SRAM domain PD_GRP7 */ + __IOM uint32_t PD_CACHEB0 : 1; /*!< [19..19] This bit is 1 if power is supplied to CACHE BANK 0 */ + __IM uint32_t : 1; + __IOM uint32_t PD_CACHEB2 : 1; /*!< [21..21] This bit is 1 if power is supplied to CACHE BANK 2 */ + } PWRONSTATUS_b; + } ; + + union { + __IOM uint32_t SRAMCTRL; /*!< (@ 0x00000018) SRAM Control register */ + + struct { + __IOM uint32_t SRAM_LIGHT_SLEEP : 1; /*!< [0..0] Enable LS (light sleep) of cache RAMs. When this bit + is set, the RAMS will be put into light sleep mode while + inactive. NOTE: if the SRAM is actively used, this may + have an adverse affect on power since entering/exiting + LS mode may consume more power than would be saved. */ + __IOM uint32_t SRAM_CLKGATE : 1; /*!< [1..1] Enables individual per-RAM clock gating in the SRAM block. + This bit should be enabled for lowest power operation. */ + __IOM uint32_t SRAM_MASTER_CLKGATE : 1; /*!< [2..2] Enables top-level clock gating in the SRAM block. This + bit should be enabled for lowest power operation. */ + } SRAMCTRL_b; + } ; + + union { + __IOM uint32_t ADCSTATUS; /*!< (@ 0x0000001C) Power Status Register for ADC Block */ + + struct { + __IOM uint32_t ADC_PWD : 1; /*!< [0..0] This bit indicates that the ADC is powered down */ + __IOM uint32_t ADC_BGT_PWD : 1; /*!< [1..1] This bit indicates that the ADC Band Gap is powered down */ + __IOM uint32_t ADC_VPTAT_PWD : 1; /*!< [2..2] This bit indicates that the ADC temperature sensor input + buffer is powered down */ + __IOM uint32_t ADC_VBAT_PWD : 1; /*!< [3..3] This bit indicates that the ADC VBAT resistor divider + is powered down */ + __IOM uint32_t ADC_REFKEEP_PWD : 1; /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down */ + __IOM uint32_t ADC_REFBUF_PWD : 1; /*!< [5..5] This bit indicates that the ADC REFBUF is powered down */ + } ADCSTATUS_b; + } ; + + union { + __IOM uint32_t MISCOPT; /*!< (@ 0x00000020) Power Optimization Control Bits */ + + struct { + __IM uint32_t : 2; + __IOM uint32_t DIS_LDOLPMODE_TIMERS : 1; /*!< [2..2] Setting this bit will enable the MEM LDO to be in LPMODE + during deep sleep even when the ctimers or stimers are + running */ + } MISCOPT_b; + } ; +} PWRCTRL_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU Reset Generator (RSTGEN) + */ + +typedef struct { /*!< (@ 0x40000000) RSTGEN Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t BODHREN : 1; /*!< [0..0] Brown out high (2.1v) reset enable. */ + __IOM uint32_t WDREN : 1; /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must + also be configured for WDT reset. */ + } CFG_b; + } ; + + union { + __IOM uint32_t SWPOI; /*!< (@ 0x00000004) Software POI Reset */ + + struct { + __IOM uint32_t SWPOIKEY : 8; /*!< [7..0] 0x1B generates a software POI reset. */ + } SWPOI_b; + } ; + + union { + __IOM uint32_t SWPOR; /*!< (@ 0x00000008) Software POR Reset */ + + struct { + __IOM uint32_t SWPORKEY : 8; /*!< [7..0] 0xD4 generates a software POR reset. */ + } SWPOR_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x0000000C) Status Register */ + + struct { + __IOM uint32_t EXRSTAT : 1; /*!< [0..0] Reset was initiated by an External Reset. */ + __IOM uint32_t PORSTAT : 1; /*!< [1..1] Reset was initiated by a Power-On Reset. */ + __IOM uint32_t BORSTAT : 1; /*!< [2..2] Reset was initiated by a Brown-Out Reset. */ + __IOM uint32_t SWRSTAT : 1; /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset. */ + __IOM uint32_t POIRSTAT : 1; /*!< [4..4] Reset was a initiated by Software POI Reset. */ + __IOM uint32_t DBGRSTAT : 1; /*!< [5..5] Reset was a initiated by Debugger Reset. */ + __IOM uint32_t WDRSTAT : 1; /*!< [6..6] Reset was initiated by a Watchdog Timer Reset. */ + } STAT_b; + } ; + + union { + __IOM uint32_t CLRSTAT; /*!< (@ 0x00000010) Clear the status register */ + + struct { + __IOM uint32_t CLRSTAT : 1; /*!< [0..0] Writing a 1 to this bit clears all bits in the RST_STAT. */ + } CLRSTAT_b; + } ; + + union { + __IOM uint32_t TPIU_RST; /*!< (@ 0x00000014) TPIU reset */ + + struct { + __IOM uint32_t TPIURST : 1; /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset + to TPIU. Write to '0' to clear the reset. */ + } TPIU_RST_b; + } ; + __IM uint32_t RESERVED[122]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Reset Interrupt register: Enable */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Reset Interrupt register: Status */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Reset Interrupt register: Clear */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Reset Interrupt register: Set */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTSET_b; + } ; +} RSTGEN_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real Time Clock (RTC) + */ + +typedef struct { /*!< (@ 0x40004040) RTC Structure */ + + union { + __IOM uint32_t CTRLOW; /*!< (@ 0x00000000) RTC Counters Lower */ + + struct { + __IOM uint32_t CTR100 : 8; /*!< [7..0] 100ths of a second Counter */ + __IOM uint32_t CTRSEC : 7; /*!< [14..8] Seconds Counter */ + __IM uint32_t : 1; + __IOM uint32_t CTRMIN : 7; /*!< [22..16] Minutes Counter */ + __IM uint32_t : 1; + __IOM uint32_t CTRHR : 6; /*!< [29..24] Hours Counter */ + } CTRLOW_b; + } ; + + union { + __IOM uint32_t CTRUP; /*!< (@ 0x00000004) RTC Counters Upper */ + + struct { + __IOM uint32_t CTRDATE : 6; /*!< [5..0] Date Counter */ + __IM uint32_t : 2; + __IOM uint32_t CTRMO : 5; /*!< [12..8] Months Counter */ + __IM uint32_t : 3; + __IOM uint32_t CTRYR : 8; /*!< [23..16] Years Counter */ + __IOM uint32_t CTRWKDY : 3; /*!< [26..24] Weekdays Counter */ + __IOM uint32_t CB : 1; /*!< [27..27] Century */ + __IOM uint32_t CEB : 1; /*!< [28..28] Century enable */ + __IM uint32_t : 2; + __IOM uint32_t CTERR : 1; /*!< [31..31] Counter read error status */ + } CTRUP_b; + } ; + + union { + __IOM uint32_t ALMLOW; /*!< (@ 0x00000008) RTC Alarms Lower */ + + struct { + __IOM uint32_t ALM100 : 8; /*!< [7..0] 100ths of a second Alarm */ + __IOM uint32_t ALMSEC : 7; /*!< [14..8] Seconds Alarm */ + __IM uint32_t : 1; + __IOM uint32_t ALMMIN : 7; /*!< [22..16] Minutes Alarm */ + __IM uint32_t : 1; + __IOM uint32_t ALMHR : 6; /*!< [29..24] Hours Alarm */ + } ALMLOW_b; + } ; + + union { + __IOM uint32_t ALMUP; /*!< (@ 0x0000000C) RTC Alarms Upper */ + + struct { + __IOM uint32_t ALMDATE : 6; /*!< [5..0] Date Alarm */ + __IM uint32_t : 2; + __IOM uint32_t ALMMO : 5; /*!< [12..8] Months Alarm */ + __IM uint32_t : 3; + __IOM uint32_t ALMWKDY : 3; /*!< [18..16] Weekdays Alarm */ + } ALMUP_b; + } ; + + union { + __IOM uint32_t RTCCTL; /*!< (@ 0x00000010) RTC Control Register */ + + struct { + __IOM uint32_t WRTC : 1; /*!< [0..0] Counter write control */ + __IOM uint32_t RPT : 3; /*!< [3..1] Alarm repeat interval */ + __IOM uint32_t RSTOP : 1; /*!< [4..4] RTC input clock control */ + __IOM uint32_t HR1224 : 1; /*!< [5..5] Hours Counter mode */ + } RTCCTL_b; + } ; + __IM uint32_t RESERVED[43]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x000000C0) RTC Interrupt Register: Enable */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x000000C4) RTC Interrupt Register: Status */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x000000C8) RTC Interrupt Register: Clear */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x000000CC) RTC Interrupt Register: Set */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + __IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */ + } INTSET_b; + } ; +} RTC_Type; /*!< Size = 208 (0xd0) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial UART (UART0) + */ + +typedef struct { /*!< (@ 0x4001C000) UART0 Structure */ + + union { + __IOM uint32_t DR; /*!< (@ 0x00000000) UART Data Register */ + + struct { + __IOM uint32_t DATA : 8; /*!< [7..0] This is the UART data port. */ + __IOM uint32_t FEDATA : 1; /*!< [8..8] This is the framing error indicator. */ + __IOM uint32_t PEDATA : 1; /*!< [9..9] This is the parity error indicator. */ + __IOM uint32_t BEDATA : 1; /*!< [10..10] This is the break error indicator. */ + __IOM uint32_t OEDATA : 1; /*!< [11..11] This is the overrun error indicator. */ + } DR_b; + } ; + + union { + __IOM uint32_t RSR; /*!< (@ 0x00000004) UART Status Register */ + + struct { + __IOM uint32_t FESTAT : 1; /*!< [0..0] This is the framing error indicator. */ + __IOM uint32_t PESTAT : 1; /*!< [1..1] This is the parity error indicator. */ + __IOM uint32_t BESTAT : 1; /*!< [2..2] This is the break error indicator. */ + __IOM uint32_t OESTAT : 1; /*!< [3..3] This is the overrun error indicator. */ + } RSR_b; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t FR; /*!< (@ 0x00000018) Flag Register */ + + struct { + __IOM uint32_t CTS : 1; /*!< [0..0] This bit holds the clear to send indicator. */ + __IOM uint32_t DSR : 1; /*!< [1..1] This bit holds the data set ready indicator. */ + __IOM uint32_t DCD : 1; /*!< [2..2] This bit holds the data carrier detect indicator. */ + __IOM uint32_t BUSY : 1; /*!< [3..3] This bit holds the busy indicator. */ + __IOM uint32_t RXFE : 1; /*!< [4..4] This bit holds the receive FIFO empty indicator. */ + __IOM uint32_t TXFF : 1; /*!< [5..5] This bit holds the transmit FIFO full indicator. */ + __IOM uint32_t RXFF : 1; /*!< [6..6] This bit holds the receive FIFO full indicator. */ + __IOM uint32_t TXFE : 1; /*!< [7..7] This bit holds the transmit FIFO empty indicator. */ + __IOM uint32_t TXBUSY : 1; /*!< [8..8] This bit holds the transmit BUSY indicator. */ + } FR_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t ILPR; /*!< (@ 0x00000020) IrDA Counter */ + + struct { + __IOM uint32_t ILPDVSR : 8; /*!< [7..0] These bits hold the IrDA counter divisor. */ + } ILPR_b; + } ; + + union { + __IOM uint32_t IBRD; /*!< (@ 0x00000024) Integer Baud Rate Divisor */ + + struct { + __IOM uint32_t DIVINT : 16; /*!< [15..0] These bits hold the baud integer divisor. */ + } IBRD_b; + } ; + + union { + __IOM uint32_t FBRD; /*!< (@ 0x00000028) Fractional Baud Rate Divisor */ + + struct { + __IOM uint32_t DIVFRAC : 6; /*!< [5..0] These bits hold the baud fractional divisor. */ + } FBRD_b; + } ; + + union { + __IOM uint32_t LCRH; /*!< (@ 0x0000002C) Line Control High */ + + struct { + __IOM uint32_t BRK : 1; /*!< [0..0] This bit holds the break set. */ + __IOM uint32_t PEN : 1; /*!< [1..1] This bit holds the parity enable. */ + __IOM uint32_t EPS : 1; /*!< [2..2] This bit holds the even parity select. */ + __IOM uint32_t STP2 : 1; /*!< [3..3] This bit holds the two stop bits select. */ + __IOM uint32_t FEN : 1; /*!< [4..4] This bit holds the FIFO enable. */ + __IOM uint32_t WLEN : 2; /*!< [6..5] These bits hold the write length. */ + __IOM uint32_t SPS : 1; /*!< [7..7] This bit holds the stick parity select. */ + } LCRH_b; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000030) Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] This bit is the UART enable. */ + __IOM uint32_t SIREN : 1; /*!< [1..1] This bit is the SIR ENDEC enable. */ + __IOM uint32_t SIRLP : 1; /*!< [2..2] This bit is the SIR low power select. */ + __IOM uint32_t CLKEN : 1; /*!< [3..3] This bit is the UART clock enable. */ + __IOM uint32_t CLKSEL : 3; /*!< [6..4] This bitfield is the UART clock select. */ + __IOM uint32_t LBE : 1; /*!< [7..7] This bit is the loopback enable. */ + __IOM uint32_t TXE : 1; /*!< [8..8] This bit is the transmit enable. */ + __IOM uint32_t RXE : 1; /*!< [9..9] This bit is the receive enable. */ + __IOM uint32_t DTR : 1; /*!< [10..10] This bit enables data transmit ready. */ + __IOM uint32_t RTS : 1; /*!< [11..11] This bit enables request to send. */ + __IOM uint32_t OUT1 : 1; /*!< [12..12] This bit holds modem Out1. */ + __IOM uint32_t OUT2 : 1; /*!< [13..13] This bit holds modem Out2. */ + __IOM uint32_t RTSEN : 1; /*!< [14..14] This bit enables RTS hardware flow control. */ + __IOM uint32_t CTSEN : 1; /*!< [15..15] This bit enables CTS hardware flow control. */ + } CR_b; + } ; + + union { + __IOM uint32_t IFLS; /*!< (@ 0x00000034) FIFO Interrupt Level Select */ + + struct { + __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] These bits hold the transmit FIFO interrupt level. */ + __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] These bits hold the receive FIFO interrupt level. */ + } IFLS_b; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000038) Interrupt Enable */ + + struct { + __IOM uint32_t TXCMPMIM : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt enable. */ + __IOM uint32_t CTSMIM : 1; /*!< [1..1] This bit holds the modem CTS interrupt enable. */ + __IOM uint32_t DCDMIM : 1; /*!< [2..2] This bit holds the modem DCD interrupt enable. */ + __IOM uint32_t DSRMIM : 1; /*!< [3..3] This bit holds the modem DSR interrupt enable. */ + __IOM uint32_t RXIM : 1; /*!< [4..4] This bit holds the receive interrupt enable. */ + __IOM uint32_t TXIM : 1; /*!< [5..5] This bit holds the transmit interrupt enable. */ + __IOM uint32_t RTIM : 1; /*!< [6..6] This bit holds the receive timeout interrupt enable. */ + __IOM uint32_t FEIM : 1; /*!< [7..7] This bit holds the framing error interrupt enable. */ + __IOM uint32_t PEIM : 1; /*!< [8..8] This bit holds the parity error interrupt enable. */ + __IOM uint32_t BEIM : 1; /*!< [9..9] This bit holds the break error interrupt enable. */ + __IOM uint32_t OEIM : 1; /*!< [10..10] This bit holds the overflow interrupt enable. */ + } IER_b; + } ; + + union { + __IOM uint32_t IES; /*!< (@ 0x0000003C) Interrupt Status */ + + struct { + __IOM uint32_t TXCMPMRIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status. */ + __IOM uint32_t CTSMRIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status. */ + __IOM uint32_t DCDMRIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status. */ + __IOM uint32_t DSRMRIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status. */ + __IOM uint32_t RXRIS : 1; /*!< [4..4] This bit holds the receive interrupt status. */ + __IOM uint32_t TXRIS : 1; /*!< [5..5] This bit holds the transmit interrupt status. */ + __IOM uint32_t RTRIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status. */ + __IOM uint32_t FERIS : 1; /*!< [7..7] This bit holds the framing error interrupt status. */ + __IOM uint32_t PERIS : 1; /*!< [8..8] This bit holds the parity error interrupt status. */ + __IOM uint32_t BERIS : 1; /*!< [9..9] This bit holds the break error interrupt status. */ + __IOM uint32_t OERIS : 1; /*!< [10..10] This bit holds the overflow interrupt status. */ + } IES_b; + } ; + + union { + __IOM uint32_t MIS; /*!< (@ 0x00000040) Masked Interrupt Status */ + + struct { + __IOM uint32_t TXCMPMMIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status masked. */ + __IOM uint32_t CTSMMIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status masked. */ + __IOM uint32_t DCDMMIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status masked. */ + __IOM uint32_t DSRMMIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status masked. */ + __IOM uint32_t RXMIS : 1; /*!< [4..4] This bit holds the receive interrupt status masked. */ + __IOM uint32_t TXMIS : 1; /*!< [5..5] This bit holds the transmit interrupt status masked. */ + __IOM uint32_t RTMIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status masked. */ + __IOM uint32_t FEMIS : 1; /*!< [7..7] This bit holds the framing error interrupt status masked. */ + __IOM uint32_t PEMIS : 1; /*!< [8..8] This bit holds the parity error interrupt status masked. */ + __IOM uint32_t BEMIS : 1; /*!< [9..9] This bit holds the break error interrupt status masked. */ + __IOM uint32_t OEMIS : 1; /*!< [10..10] This bit holds the overflow interrupt status masked. */ + } MIS_b; + } ; + + union { + __IOM uint32_t IEC; /*!< (@ 0x00000044) Interrupt Clear */ + + struct { + __IOM uint32_t TXCMPMIC : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt clear. */ + __IOM uint32_t CTSMIC : 1; /*!< [1..1] This bit holds the modem CTS interrupt clear. */ + __IOM uint32_t DCDMIC : 1; /*!< [2..2] This bit holds the modem DCD interrupt clear. */ + __IOM uint32_t DSRMIC : 1; /*!< [3..3] This bit holds the modem DSR interrupt clear. */ + __IOM uint32_t RXIC : 1; /*!< [4..4] This bit holds the receive interrupt clear. */ + __IOM uint32_t TXIC : 1; /*!< [5..5] This bit holds the transmit interrupt clear. */ + __IOM uint32_t RTIC : 1; /*!< [6..6] This bit holds the receive timeout interrupt clear. */ + __IOM uint32_t FEIC : 1; /*!< [7..7] This bit holds the framing error interrupt clear. */ + __IOM uint32_t PEIC : 1; /*!< [8..8] This bit holds the parity error interrupt clear. */ + __IOM uint32_t BEIC : 1; /*!< [9..9] This bit holds the break error interrupt clear. */ + __IOM uint32_t OEIC : 1; /*!< [10..10] This bit holds the overflow interrupt clear. */ + } IEC_b; + } ; +} UART0_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Voltage Comparator (VCOMP) + */ + +typedef struct { /*!< (@ 0x4000C000) VCOMP Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t PSEL : 2; /*!< [1..0] This bitfield selects the positive input to the comparator. */ + __IM uint32_t : 6; + __IOM uint32_t NSEL : 2; /*!< [9..8] This bitfield selects the negative input to the comparator. */ + __IM uint32_t : 6; + __IOM uint32_t LVLSEL : 4; /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this + bitfield selects the voltage level for the negative input + to the comparator. */ + } CFG_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Status Register */ + + struct { + __IOM uint32_t CMPOUT : 1; /*!< [0..0] This bit is 1 if the positive input of the comparator + is greater than the negative input. */ + __IOM uint32_t PWDSTAT : 1; /*!< [1..1] This bit indicates the power down state of the voltage + comparator. */ + } STAT_b; + } ; + + union { + __IOM uint32_t PWDKEY; /*!< (@ 0x00000008) Key Register for Powering Down the Voltage Comparator */ + + struct { + __IOM uint32_t PWDKEY : 32; /*!< [31..0] Key register value. */ + } PWDKEY_b; + } ; + __IM uint32_t RESERVED[125]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Voltage Comparator Interrupt registers: Enable */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Voltage Comparator Interrupt registers: Status */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Voltage Comparator Interrupt registers: Clear */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Voltage Comparator Interrupt registers: Set */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTSET_b; + } ; +} VCOMP_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40024000) WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] This bitfield enables the WDT. */ + __IOM uint32_t INTEN : 1; /*!< [1..1] This bitfield enables the WDT interrupt. Note : This + bit must be set before the interrupt status bit will reflect + a watchdog timer expiration. The IER interrupt register + must also be enabled for a WDT interrupt to be sent to + the NVIC. */ + __IOM uint32_t RESEN : 1; /*!< [2..2] This bitfield enables the WDT reset. */ + __IM uint32_t : 5; + __IOM uint32_t RESVAL : 8; /*!< [15..8] This bitfield is the compare value for counter bits + 7:0 to generate a watchdog reset. */ + __IOM uint32_t INTVAL : 8; /*!< [23..16] This bitfield is the compare value for counter bits + 7:0 to generate a watchdog interrupt. */ + __IOM uint32_t CLKSEL : 3; /*!< [26..24] Select the frequency for the WDT. All values not enumerated + below are undefined. */ + } CFG_b; + } ; + + union { + __IOM uint32_t RSTRT; /*!< (@ 0x00000004) Restart the watchdog timer */ + + struct { + __IOM uint32_t RSTRT : 8; /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer. */ + } RSTRT_b; + } ; + + union { + __IOM uint32_t LOCK; /*!< (@ 0x00000008) Locks the WDT */ + + struct { + __IOM uint32_t LOCK : 8; /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the + WDTCFG reg cannot be written and WDTEN is set. */ + } LOCK_b; + } ; + + union { + __IOM uint32_t COUNT; /*!< (@ 0x0000000C) Current Counter Value for WDT */ + + struct { + __IOM uint32_t COUNT : 8; /*!< [7..0] Read-Only current value of the WDT counter */ + } COUNT_b; + } ; + __IM uint32_t RESERVED[124]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) WDT Interrupt register: Enable */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) WDT Interrupt register: Status */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) WDT Interrupt register: Clear */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) WDT Interrupt register: Set */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTSET_b; + } ; +} WDT_Type; /*!< Size = 528 (0x210) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC_BASE 0x50010000UL +#define CACHECTRL_BASE 0x40018000UL +#define CLKGEN_BASE 0x40004000UL +#define CTIMER_BASE 0x40008000UL +#define GPIO_BASE 0x40010000UL +#define IOMSTR0_BASE 0x50004000UL +#define IOMSTR1_BASE 0x50005000UL +#define IOMSTR2_BASE 0x50006000UL +#define IOMSTR3_BASE 0x50007000UL +#define IOMSTR4_BASE 0x50008000UL +#define IOMSTR5_BASE 0x50009000UL +#define IOSLAVE_BASE 0x50000000UL +#define MCUCTRL_BASE 0x40020000UL +#define PDM_BASE 0x50011000UL +#define PWRCTRL_BASE 0x40021000UL +#define RSTGEN_BASE 0x40000000UL +#define RTC_BASE 0x40004040UL +#define UART0_BASE 0x4001C000UL +#define UART1_BASE 0x4001D000UL +#define VCOMP_BASE 0x4000C000UL +#define WDT_BASE 0x40024000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define ADC ((ADC_Type*) ADC_BASE) +#define CACHECTRL ((CACHECTRL_Type*) CACHECTRL_BASE) +#define CLKGEN ((CLKGEN_Type*) CLKGEN_BASE) +#define CTIMER ((CTIMER_Type*) CTIMER_BASE) +#define GPIO ((GPIO_Type*) GPIO_BASE) +#define IOMSTR0 ((IOMSTR0_Type*) IOMSTR0_BASE) +#define IOMSTR1 ((IOMSTR0_Type*) IOMSTR1_BASE) +#define IOMSTR2 ((IOMSTR0_Type*) IOMSTR2_BASE) +#define IOMSTR3 ((IOMSTR0_Type*) IOMSTR3_BASE) +#define IOMSTR4 ((IOMSTR0_Type*) IOMSTR4_BASE) +#define IOMSTR5 ((IOMSTR0_Type*) IOMSTR5_BASE) +#define IOSLAVE ((IOSLAVE_Type*) IOSLAVE_BASE) +#define MCUCTRL ((MCUCTRL_Type*) MCUCTRL_BASE) +#define PDM ((PDM_Type*) PDM_BASE) +#define PWRCTRL ((PWRCTRL_Type*) PWRCTRL_BASE) +#define RSTGEN ((RSTGEN_Type*) RSTGEN_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define VCOMP ((VCOMP_Type*) VCOMP_BASE) +#define WDT ((WDT_Type*) WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define ADC_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */ +#define ADC_CFG_CLKSEL_Msk (0x3000000UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ +#define ADC_CFG_TRIGPOL_Pos (19UL) /*!< TRIGPOL (Bit 19) */ +#define ADC_CFG_TRIGPOL_Msk (0x80000UL) /*!< TRIGPOL (Bitfield-Mask: 0x01) */ +#define ADC_CFG_TRIGSEL_Pos (16UL) /*!< TRIGSEL (Bit 16) */ +#define ADC_CFG_TRIGSEL_Msk (0x70000UL) /*!< TRIGSEL (Bitfield-Mask: 0x07) */ +#define ADC_CFG_REFSEL_Pos (8UL) /*!< REFSEL (Bit 8) */ +#define ADC_CFG_REFSEL_Msk (0x300UL) /*!< REFSEL (Bitfield-Mask: 0x03) */ +#define ADC_CFG_CKMODE_Pos (4UL) /*!< CKMODE (Bit 4) */ +#define ADC_CFG_CKMODE_Msk (0x10UL) /*!< CKMODE (Bitfield-Mask: 0x01) */ +#define ADC_CFG_LPMODE_Pos (3UL) /*!< LPMODE (Bit 3) */ +#define ADC_CFG_LPMODE_Msk (0x8UL) /*!< LPMODE (Bitfield-Mask: 0x01) */ +#define ADC_CFG_RPTEN_Pos (2UL) /*!< RPTEN (Bit 2) */ +#define ADC_CFG_RPTEN_Msk (0x4UL) /*!< RPTEN (Bitfield-Mask: 0x01) */ +#define ADC_CFG_ADCEN_Pos (0UL) /*!< ADCEN (Bit 0) */ +#define ADC_CFG_ADCEN_Msk (0x1UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define ADC_STAT_PWDSTAT_Pos (0UL) /*!< PWDSTAT (Bit 0) */ +#define ADC_STAT_PWDSTAT_Msk (0x1UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== SWT ========================================================== */ +#define ADC_SWT_SWT_Pos (0UL) /*!< SWT (Bit 0) */ +#define ADC_SWT_SWT_Msk (0xffUL) /*!< SWT (Bitfield-Mask: 0xff) */ +/* ======================================================== SL0CFG ========================================================= */ +#define ADC_SL0CFG_ADSEL0_Pos (24UL) /*!< ADSEL0 (Bit 24) */ +#define ADC_SL0CFG_ADSEL0_Msk (0x7000000UL) /*!< ADSEL0 (Bitfield-Mask: 0x07) */ +#define ADC_SL0CFG_PRMODE0_Pos (16UL) /*!< PRMODE0 (Bit 16) */ +#define ADC_SL0CFG_PRMODE0_Msk (0x30000UL) /*!< PRMODE0 (Bitfield-Mask: 0x03) */ +#define ADC_SL0CFG_CHSEL0_Pos (8UL) /*!< CHSEL0 (Bit 8) */ +#define ADC_SL0CFG_CHSEL0_Msk (0xf00UL) /*!< CHSEL0 (Bitfield-Mask: 0x0f) */ +#define ADC_SL0CFG_WCEN0_Pos (1UL) /*!< WCEN0 (Bit 1) */ +#define ADC_SL0CFG_WCEN0_Msk (0x2UL) /*!< WCEN0 (Bitfield-Mask: 0x01) */ +#define ADC_SL0CFG_SLEN0_Pos (0UL) /*!< SLEN0 (Bit 0) */ +#define ADC_SL0CFG_SLEN0_Msk (0x1UL) /*!< SLEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL1CFG ========================================================= */ +#define ADC_SL1CFG_ADSEL1_Pos (24UL) /*!< ADSEL1 (Bit 24) */ +#define ADC_SL1CFG_ADSEL1_Msk (0x7000000UL) /*!< ADSEL1 (Bitfield-Mask: 0x07) */ +#define ADC_SL1CFG_PRMODE1_Pos (16UL) /*!< PRMODE1 (Bit 16) */ +#define ADC_SL1CFG_PRMODE1_Msk (0x30000UL) /*!< PRMODE1 (Bitfield-Mask: 0x03) */ +#define ADC_SL1CFG_CHSEL1_Pos (8UL) /*!< CHSEL1 (Bit 8) */ +#define ADC_SL1CFG_CHSEL1_Msk (0xf00UL) /*!< CHSEL1 (Bitfield-Mask: 0x0f) */ +#define ADC_SL1CFG_WCEN1_Pos (1UL) /*!< WCEN1 (Bit 1) */ +#define ADC_SL1CFG_WCEN1_Msk (0x2UL) /*!< WCEN1 (Bitfield-Mask: 0x01) */ +#define ADC_SL1CFG_SLEN1_Pos (0UL) /*!< SLEN1 (Bit 0) */ +#define ADC_SL1CFG_SLEN1_Msk (0x1UL) /*!< SLEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL2CFG ========================================================= */ +#define ADC_SL2CFG_ADSEL2_Pos (24UL) /*!< ADSEL2 (Bit 24) */ +#define ADC_SL2CFG_ADSEL2_Msk (0x7000000UL) /*!< ADSEL2 (Bitfield-Mask: 0x07) */ +#define ADC_SL2CFG_PRMODE2_Pos (16UL) /*!< PRMODE2 (Bit 16) */ +#define ADC_SL2CFG_PRMODE2_Msk (0x30000UL) /*!< PRMODE2 (Bitfield-Mask: 0x03) */ +#define ADC_SL2CFG_CHSEL2_Pos (8UL) /*!< CHSEL2 (Bit 8) */ +#define ADC_SL2CFG_CHSEL2_Msk (0xf00UL) /*!< CHSEL2 (Bitfield-Mask: 0x0f) */ +#define ADC_SL2CFG_WCEN2_Pos (1UL) /*!< WCEN2 (Bit 1) */ +#define ADC_SL2CFG_WCEN2_Msk (0x2UL) /*!< WCEN2 (Bitfield-Mask: 0x01) */ +#define ADC_SL2CFG_SLEN2_Pos (0UL) /*!< SLEN2 (Bit 0) */ +#define ADC_SL2CFG_SLEN2_Msk (0x1UL) /*!< SLEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL3CFG ========================================================= */ +#define ADC_SL3CFG_ADSEL3_Pos (24UL) /*!< ADSEL3 (Bit 24) */ +#define ADC_SL3CFG_ADSEL3_Msk (0x7000000UL) /*!< ADSEL3 (Bitfield-Mask: 0x07) */ +#define ADC_SL3CFG_PRMODE3_Pos (16UL) /*!< PRMODE3 (Bit 16) */ +#define ADC_SL3CFG_PRMODE3_Msk (0x30000UL) /*!< PRMODE3 (Bitfield-Mask: 0x03) */ +#define ADC_SL3CFG_CHSEL3_Pos (8UL) /*!< CHSEL3 (Bit 8) */ +#define ADC_SL3CFG_CHSEL3_Msk (0xf00UL) /*!< CHSEL3 (Bitfield-Mask: 0x0f) */ +#define ADC_SL3CFG_WCEN3_Pos (1UL) /*!< WCEN3 (Bit 1) */ +#define ADC_SL3CFG_WCEN3_Msk (0x2UL) /*!< WCEN3 (Bitfield-Mask: 0x01) */ +#define ADC_SL3CFG_SLEN3_Pos (0UL) /*!< SLEN3 (Bit 0) */ +#define ADC_SL3CFG_SLEN3_Msk (0x1UL) /*!< SLEN3 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL4CFG ========================================================= */ +#define ADC_SL4CFG_ADSEL4_Pos (24UL) /*!< ADSEL4 (Bit 24) */ +#define ADC_SL4CFG_ADSEL4_Msk (0x7000000UL) /*!< ADSEL4 (Bitfield-Mask: 0x07) */ +#define ADC_SL4CFG_PRMODE4_Pos (16UL) /*!< PRMODE4 (Bit 16) */ +#define ADC_SL4CFG_PRMODE4_Msk (0x30000UL) /*!< PRMODE4 (Bitfield-Mask: 0x03) */ +#define ADC_SL4CFG_CHSEL4_Pos (8UL) /*!< CHSEL4 (Bit 8) */ +#define ADC_SL4CFG_CHSEL4_Msk (0xf00UL) /*!< CHSEL4 (Bitfield-Mask: 0x0f) */ +#define ADC_SL4CFG_WCEN4_Pos (1UL) /*!< WCEN4 (Bit 1) */ +#define ADC_SL4CFG_WCEN4_Msk (0x2UL) /*!< WCEN4 (Bitfield-Mask: 0x01) */ +#define ADC_SL4CFG_SLEN4_Pos (0UL) /*!< SLEN4 (Bit 0) */ +#define ADC_SL4CFG_SLEN4_Msk (0x1UL) /*!< SLEN4 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL5CFG ========================================================= */ +#define ADC_SL5CFG_ADSEL5_Pos (24UL) /*!< ADSEL5 (Bit 24) */ +#define ADC_SL5CFG_ADSEL5_Msk (0x7000000UL) /*!< ADSEL5 (Bitfield-Mask: 0x07) */ +#define ADC_SL5CFG_PRMODE5_Pos (16UL) /*!< PRMODE5 (Bit 16) */ +#define ADC_SL5CFG_PRMODE5_Msk (0x30000UL) /*!< PRMODE5 (Bitfield-Mask: 0x03) */ +#define ADC_SL5CFG_CHSEL5_Pos (8UL) /*!< CHSEL5 (Bit 8) */ +#define ADC_SL5CFG_CHSEL5_Msk (0xf00UL) /*!< CHSEL5 (Bitfield-Mask: 0x0f) */ +#define ADC_SL5CFG_WCEN5_Pos (1UL) /*!< WCEN5 (Bit 1) */ +#define ADC_SL5CFG_WCEN5_Msk (0x2UL) /*!< WCEN5 (Bitfield-Mask: 0x01) */ +#define ADC_SL5CFG_SLEN5_Pos (0UL) /*!< SLEN5 (Bit 0) */ +#define ADC_SL5CFG_SLEN5_Msk (0x1UL) /*!< SLEN5 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL6CFG ========================================================= */ +#define ADC_SL6CFG_ADSEL6_Pos (24UL) /*!< ADSEL6 (Bit 24) */ +#define ADC_SL6CFG_ADSEL6_Msk (0x7000000UL) /*!< ADSEL6 (Bitfield-Mask: 0x07) */ +#define ADC_SL6CFG_PRMODE6_Pos (16UL) /*!< PRMODE6 (Bit 16) */ +#define ADC_SL6CFG_PRMODE6_Msk (0x30000UL) /*!< PRMODE6 (Bitfield-Mask: 0x03) */ +#define ADC_SL6CFG_CHSEL6_Pos (8UL) /*!< CHSEL6 (Bit 8) */ +#define ADC_SL6CFG_CHSEL6_Msk (0xf00UL) /*!< CHSEL6 (Bitfield-Mask: 0x0f) */ +#define ADC_SL6CFG_WCEN6_Pos (1UL) /*!< WCEN6 (Bit 1) */ +#define ADC_SL6CFG_WCEN6_Msk (0x2UL) /*!< WCEN6 (Bitfield-Mask: 0x01) */ +#define ADC_SL6CFG_SLEN6_Pos (0UL) /*!< SLEN6 (Bit 0) */ +#define ADC_SL6CFG_SLEN6_Msk (0x1UL) /*!< SLEN6 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL7CFG ========================================================= */ +#define ADC_SL7CFG_ADSEL7_Pos (24UL) /*!< ADSEL7 (Bit 24) */ +#define ADC_SL7CFG_ADSEL7_Msk (0x7000000UL) /*!< ADSEL7 (Bitfield-Mask: 0x07) */ +#define ADC_SL7CFG_PRMODE7_Pos (16UL) /*!< PRMODE7 (Bit 16) */ +#define ADC_SL7CFG_PRMODE7_Msk (0x30000UL) /*!< PRMODE7 (Bitfield-Mask: 0x03) */ +#define ADC_SL7CFG_CHSEL7_Pos (8UL) /*!< CHSEL7 (Bit 8) */ +#define ADC_SL7CFG_CHSEL7_Msk (0xf00UL) /*!< CHSEL7 (Bitfield-Mask: 0x0f) */ +#define ADC_SL7CFG_WCEN7_Pos (1UL) /*!< WCEN7 (Bit 1) */ +#define ADC_SL7CFG_WCEN7_Msk (0x2UL) /*!< WCEN7 (Bitfield-Mask: 0x01) */ +#define ADC_SL7CFG_SLEN7_Pos (0UL) /*!< SLEN7 (Bit 0) */ +#define ADC_SL7CFG_SLEN7_Msk (0x1UL) /*!< SLEN7 (Bitfield-Mask: 0x01) */ +/* ========================================================= WULIM ========================================================= */ +#define ADC_WULIM_ULIM_Pos (0UL) /*!< ULIM (Bit 0) */ +#define ADC_WULIM_ULIM_Msk (0xfffffUL) /*!< ULIM (Bitfield-Mask: 0xfffff) */ +/* ========================================================= WLLIM ========================================================= */ +#define ADC_WLLIM_LLIM_Pos (0UL) /*!< LLIM (Bit 0) */ +#define ADC_WLLIM_LLIM_Msk (0xfffffUL) /*!< LLIM (Bitfield-Mask: 0xfffff) */ +/* ========================================================= FIFO ========================================================== */ +#define ADC_FIFO_RSVD_Pos (31UL) /*!< RSVD (Bit 31) */ +#define ADC_FIFO_RSVD_Msk (0x80000000UL) /*!< RSVD (Bitfield-Mask: 0x01) */ +#define ADC_FIFO_SLOTNUM_Pos (28UL) /*!< SLOTNUM (Bit 28) */ +#define ADC_FIFO_SLOTNUM_Msk (0x70000000UL) /*!< SLOTNUM (Bitfield-Mask: 0x07) */ +#define ADC_FIFO_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */ +#define ADC_FIFO_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */ +#define ADC_FIFO_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define ADC_FIFO_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */ +/* ========================================================= INTEN ========================================================= */ +#define ADC_INTEN_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTEN_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTEN_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTEN_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTEN_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTEN_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTEN_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define ADC_INTSTAT_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTSTAT_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTSTAT_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTSTAT_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTSTAT_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTSTAT_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTSTAT_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define ADC_INTCLR_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTCLR_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTCLR_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTCLR_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTCLR_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTCLR_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTCLR_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define ADC_INTSET_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTSET_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTSET_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTSET_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTSET_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTSET_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTSET_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CACHECFG ======================================================== */ +#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL) /*!< ENABLE_MONITOR (Bit 24) */ +#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL) /*!< ENABLE_MONITOR (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL) /*!< DATA_CLKGATE (Bit 20) */ +#define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL) /*!< DATA_CLKGATE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_SMDLY_Pos (16UL) /*!< SMDLY (Bit 16) */ +#define CACHECTRL_CACHECFG_SMDLY_Msk (0xf0000UL) /*!< SMDLY (Bitfield-Mask: 0x0f) */ +#define CACHECTRL_CACHECFG_DLY_Pos (12UL) /*!< DLY (Bit 12) */ +#define CACHECTRL_CACHECFG_DLY_Msk (0xf000UL) /*!< DLY (Bitfield-Mask: 0x0f) */ +#define CACHECTRL_CACHECFG_CACHE_LS_Pos (11UL) /*!< CACHE_LS (Bit 11) */ +#define CACHECTRL_CACHECFG_CACHE_LS_Msk (0x800UL) /*!< CACHE_LS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL) /*!< CACHE_CLKGATE (Bit 10) */ +#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL) /*!< CACHE_CLKGATE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL) /*!< DCACHE_ENABLE (Bit 9) */ +#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL) /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL) /*!< ICACHE_ENABLE (Bit 8) */ +#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL) /*!< ICACHE_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_SERIAL_Pos (7UL) /*!< SERIAL (Bit 7) */ +#define CACHECTRL_CACHECFG_SERIAL_Msk (0x80UL) /*!< SERIAL (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CONFIG_Pos (4UL) /*!< CONFIG (Bit 4) */ +#define CACHECTRL_CACHECFG_CONFIG_Msk (0x70UL) /*!< CONFIG (Bitfield-Mask: 0x07) */ +#define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL) /*!< ENABLE_NC1 (Bit 3) */ +#define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL) /*!< ENABLE_NC1 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL) /*!< ENABLE_NC0 (Bit 2) */ +#define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL) /*!< ENABLE_NC0 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_LRU_Pos (1UL) /*!< LRU (Bit 1) */ +#define CACHECTRL_CACHECFG_LRU_Msk (0x2UL) /*!< LRU (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define CACHECTRL_CACHECFG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= FLASHCFG ======================================================== */ +#define CACHECTRL_FLASHCFG_RD_WAIT_Pos (0UL) /*!< RD_WAIT (Bit 0) */ +#define CACHECTRL_FLASHCFG_RD_WAIT_Msk (0x7UL) /*!< RD_WAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= CTRL ========================================================== */ +#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL) /*!< FLASH1_SLM_ENABLE (Bit 10) */ +#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL) /*!< FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL) /*!< FLASH1_SLM_DISABLE (Bit 9) */ +#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL) /*!< FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL) /*!< FLASH1_SLM_STATUS (Bit 8) */ +#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL) /*!< FLASH1_SLM_STATUS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL) /*!< FLASH0_SLM_ENABLE (Bit 6) */ +#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL) /*!< FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL) /*!< FLASH0_SLM_DISABLE (Bit 5) */ +#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL) /*!< FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL) /*!< FLASH0_SLM_STATUS (Bit 4) */ +#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL) /*!< FLASH0_SLM_STATUS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_CACHE_READY_Pos (2UL) /*!< CACHE_READY (Bit 2) */ +#define CACHECTRL_CTRL_CACHE_READY_Msk (0x4UL) /*!< CACHE_READY (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_RESET_STAT_Pos (1UL) /*!< RESET_STAT (Bit 1) */ +#define CACHECTRL_CTRL_RESET_STAT_Msk (0x2UL) /*!< RESET_STAT (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_INVALIDATE_Pos (0UL) /*!< INVALIDATE (Bit 0) */ +#define CACHECTRL_CTRL_INVALIDATE_Msk (0x1UL) /*!< INVALIDATE (Bitfield-Mask: 0x01) */ +/* ======================================================= NCR0START ======================================================= */ +#define CACHECTRL_NCR0START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR0START_ADDR_Msk (0xffff0UL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== NCR0END ======================================================== */ +#define CACHECTRL_NCR0END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR0END_ADDR_Msk (0xffff0UL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================= NCR1START ======================================================= */ +#define CACHECTRL_NCR1START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR1START_ADDR_Msk (0xffff0UL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== NCR1END ======================================================== */ +#define CACHECTRL_NCR1END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR1END_ADDR_Msk (0xffff0UL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================= CACHEMODE ======================================================= */ +#define CACHECTRL_CACHEMODE_THROTTLE6_Pos (5UL) /*!< THROTTLE6 (Bit 5) */ +#define CACHECTRL_CACHEMODE_THROTTLE6_Msk (0x20UL) /*!< THROTTLE6 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHEMODE_THROTTLE5_Pos (4UL) /*!< THROTTLE5 (Bit 4) */ +#define CACHECTRL_CACHEMODE_THROTTLE5_Msk (0x10UL) /*!< THROTTLE5 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHEMODE_THROTTLE4_Pos (3UL) /*!< THROTTLE4 (Bit 3) */ +#define CACHECTRL_CACHEMODE_THROTTLE4_Msk (0x8UL) /*!< THROTTLE4 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHEMODE_THROTTLE3_Pos (2UL) /*!< THROTTLE3 (Bit 2) */ +#define CACHECTRL_CACHEMODE_THROTTLE3_Msk (0x4UL) /*!< THROTTLE3 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHEMODE_THROTTLE2_Pos (1UL) /*!< THROTTLE2 (Bit 1) */ +#define CACHECTRL_CACHEMODE_THROTTLE2_Msk (0x2UL) /*!< THROTTLE2 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHEMODE_THROTTLE1_Pos (0UL) /*!< THROTTLE1 (Bit 0) */ +#define CACHECTRL_CACHEMODE_THROTTLE1_Msk (0x1UL) /*!< THROTTLE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= DMON0 ========================================================= */ +#define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL) /*!< DACCESS_COUNT (Bit 0) */ +#define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL) /*!< DACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON1 ========================================================= */ +#define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL) /*!< DLOOKUP_COUNT (Bit 0) */ +#define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL) /*!< DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON2 ========================================================= */ +#define CACHECTRL_DMON2_DHIT_COUNT_Pos (0UL) /*!< DHIT_COUNT (Bit 0) */ +#define CACHECTRL_DMON2_DHIT_COUNT_Msk (0xffffffffUL) /*!< DHIT_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON3 ========================================================= */ +#define CACHECTRL_DMON3_DLINE_COUNT_Pos (0UL) /*!< DLINE_COUNT (Bit 0) */ +#define CACHECTRL_DMON3_DLINE_COUNT_Msk (0xffffffffUL) /*!< DLINE_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON0 ========================================================= */ +#define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL) /*!< IACCESS_COUNT (Bit 0) */ +#define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL) /*!< IACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON1 ========================================================= */ +#define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL) /*!< ILOOKUP_COUNT (Bit 0) */ +#define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL) /*!< ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON2 ========================================================= */ +#define CACHECTRL_IMON2_IHIT_COUNT_Pos (0UL) /*!< IHIT_COUNT (Bit 0) */ +#define CACHECTRL_IMON2_IHIT_COUNT_Msk (0xffffffffUL) /*!< IHIT_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON3 ========================================================= */ +#define CACHECTRL_IMON3_ILINE_COUNT_Pos (0UL) /*!< ILINE_COUNT (Bit 0) */ +#define CACHECTRL_IMON3_ILINE_COUNT_Msk (0xffffffffUL) /*!< ILINE_COUNT (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CALXT ========================================================= */ +#define CLKGEN_CALXT_CALXT_Pos (0UL) /*!< CALXT (Bit 0) */ +#define CLKGEN_CALXT_CALXT_Msk (0x7ffUL) /*!< CALXT (Bitfield-Mask: 0x7ff) */ +/* ========================================================= CALRC ========================================================= */ +#define CLKGEN_CALRC_CALRC_Pos (0UL) /*!< CALRC (Bit 0) */ +#define CLKGEN_CALRC_CALRC_Msk (0x3ffffUL) /*!< CALRC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== ACALCTR ======================================================== */ +#define CLKGEN_ACALCTR_ACALCTR_Pos (0UL) /*!< ACALCTR (Bit 0) */ +#define CLKGEN_ACALCTR_ACALCTR_Msk (0xffffffUL) /*!< ACALCTR (Bitfield-Mask: 0xffffff) */ +/* ========================================================= OCTRL ========================================================= */ +#define CLKGEN_OCTRL_ACAL_Pos (8UL) /*!< ACAL (Bit 8) */ +#define CLKGEN_OCTRL_ACAL_Msk (0x700UL) /*!< ACAL (Bitfield-Mask: 0x07) */ +#define CLKGEN_OCTRL_OSEL_Pos (7UL) /*!< OSEL (Bit 7) */ +#define CLKGEN_OCTRL_OSEL_Msk (0x80UL) /*!< OSEL (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_FOS_Pos (6UL) /*!< FOS (Bit 6) */ +#define CLKGEN_OCTRL_FOS_Msk (0x40UL) /*!< FOS (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_STOPRC_Pos (1UL) /*!< STOPRC (Bit 1) */ +#define CLKGEN_OCTRL_STOPRC_Msk (0x2UL) /*!< STOPRC (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_STOPXT_Pos (0UL) /*!< STOPXT (Bit 0) */ +#define CLKGEN_OCTRL_STOPXT_Msk (0x1UL) /*!< STOPXT (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKOUT ========================================================= */ +#define CLKGEN_CLKOUT_CKEN_Pos (7UL) /*!< CKEN (Bit 7) */ +#define CLKGEN_CLKOUT_CKEN_Msk (0x80UL) /*!< CKEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_CLKOUT_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ +#define CLKGEN_CLKOUT_CKSEL_Msk (0x3fUL) /*!< CKSEL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CLKKEY ========================================================= */ +#define CLKGEN_CLKKEY_CLKKEY_Pos (0UL) /*!< CLKKEY (Bit 0) */ +#define CLKGEN_CLKKEY_CLKKEY_Msk (0xffffffffUL) /*!< CLKKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CCTRL ========================================================= */ +#define CLKGEN_CCTRL_CORESEL_Pos (0UL) /*!< CORESEL (Bit 0) */ +#define CLKGEN_CCTRL_CORESEL_Msk (0x1UL) /*!< CORESEL (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ +#define CLKGEN_STATUS_OSCF_Pos (1UL) /*!< OSCF (Bit 1) */ +#define CLKGEN_STATUS_OSCF_Msk (0x2UL) /*!< OSCF (Bitfield-Mask: 0x01) */ +#define CLKGEN_STATUS_OMODE_Pos (0UL) /*!< OMODE (Bit 0) */ +#define CLKGEN_STATUS_OMODE_Msk (0x1UL) /*!< OMODE (Bitfield-Mask: 0x01) */ +/* ========================================================= HFADJ ========================================================= */ +#define CLKGEN_HFADJ_HFADJ_GAIN_Pos (21UL) /*!< HFADJ_GAIN (Bit 21) */ +#define CLKGEN_HFADJ_HFADJ_GAIN_Msk (0xe00000UL) /*!< HFADJ_GAIN (Bitfield-Mask: 0x07) */ +#define CLKGEN_HFADJ_HFWARMUP_Pos (20UL) /*!< HFWARMUP (Bit 20) */ +#define CLKGEN_HFADJ_HFWARMUP_Msk (0x100000UL) /*!< HFWARMUP (Bitfield-Mask: 0x01) */ +#define CLKGEN_HFADJ_HFXTADJ_Pos (8UL) /*!< HFXTADJ (Bit 8) */ +#define CLKGEN_HFADJ_HFXTADJ_Msk (0xfff00UL) /*!< HFXTADJ (Bitfield-Mask: 0xfff) */ +#define CLKGEN_HFADJ_HFADJCK_Pos (1UL) /*!< HFADJCK (Bit 1) */ +#define CLKGEN_HFADJ_HFADJCK_Msk (0xeUL) /*!< HFADJCK (Bitfield-Mask: 0x07) */ +#define CLKGEN_HFADJ_HFADJEN_Pos (0UL) /*!< HFADJEN (Bit 0) */ +#define CLKGEN_HFADJ_HFADJEN_Msk (0x1UL) /*!< HFADJEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CLOCKEN ======================================================== */ +#define CLKGEN_CLOCKEN_CLOCKEN_Pos (0UL) /*!< CLOCKEN (Bit 0) */ +#define CLKGEN_CLOCKEN_CLOCKEN_Msk (0xffffffffUL) /*!< CLOCKEN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CLOCKEN2 ======================================================== */ +#define CLKGEN_CLOCKEN2_CLOCKEN2_Pos (0UL) /*!< CLOCKEN2 (Bit 0) */ +#define CLKGEN_CLOCKEN2_CLOCKEN2_Msk (0xffffffffUL) /*!< CLOCKEN2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CLOCKEN3 ======================================================== */ +#define CLKGEN_CLOCKEN3_CLOCKEN3_Pos (0UL) /*!< CLOCKEN3 (Bit 0) */ +#define CLKGEN_CLOCKEN3_CLOCKEN3_Msk (0xffffffffUL) /*!< CLOCKEN3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== UARTEN ========================================================= */ +#define CLKGEN_UARTEN_UART1EN_Pos (8UL) /*!< UART1EN (Bit 8) */ +#define CLKGEN_UARTEN_UART1EN_Msk (0x300UL) /*!< UART1EN (Bitfield-Mask: 0x03) */ +#define CLKGEN_UARTEN_UART0EN_Pos (0UL) /*!< UART0EN (Bit 0) */ +#define CLKGEN_UARTEN_UART0EN_Msk (0x3UL) /*!< UART0EN (Bitfield-Mask: 0x03) */ +/* ========================================================= INTEN ========================================================= */ +#define CLKGEN_INTEN_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define CLKGEN_INTEN_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTEN_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define CLKGEN_INTSTAT_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define CLKGEN_INTSTAT_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define CLKGEN_INTCLR_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define CLKGEN_INTCLR_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define CLKGEN_INTSET_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define CLKGEN_INTSET_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTSET_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TMR0 ========================================================== */ +#define CTIMER_TMR0_CTTMRB0_Pos (16UL) /*!< CTTMRB0 (Bit 16) */ +#define CTIMER_TMR0_CTTMRB0_Msk (0xffff0000UL) /*!< CTTMRB0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR0_CTTMRA0_Pos (0UL) /*!< CTTMRA0 (Bit 0) */ +#define CTIMER_TMR0_CTTMRA0_Msk (0xffffUL) /*!< CTTMRA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA0 ========================================================= */ +#define CTIMER_CMPRA0_CMPR1A0_Pos (16UL) /*!< CMPR1A0 (Bit 16) */ +#define CTIMER_CMPRA0_CMPR1A0_Msk (0xffff0000UL) /*!< CMPR1A0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA0_CMPR0A0_Pos (0UL) /*!< CMPR0A0 (Bit 0) */ +#define CTIMER_CMPRA0_CMPR0A0_Msk (0xffffUL) /*!< CMPR0A0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB0 ========================================================= */ +#define CTIMER_CMPRB0_CMPR1B0_Pos (16UL) /*!< CMPR1B0 (Bit 16) */ +#define CTIMER_CMPRB0_CMPR1B0_Msk (0xffff0000UL) /*!< CMPR1B0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB0_CMPR0B0_Pos (0UL) /*!< CMPR0B0 (Bit 0) */ +#define CTIMER_CMPRB0_CMPR0B0_Msk (0xffffUL) /*!< CMPR0B0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL0 ========================================================= */ +#define CTIMER_CTRL0_CTLINK0_Pos (31UL) /*!< CTLINK0 (Bit 31) */ +#define CTIMER_CTRL0_CTLINK0_Msk (0x80000000UL) /*!< CTLINK0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0PE_Pos (29UL) /*!< TMRB0PE (Bit 29) */ +#define CTIMER_CTRL0_TMRB0PE_Msk (0x20000000UL) /*!< TMRB0PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0POL_Pos (28UL) /*!< TMRB0POL (Bit 28) */ +#define CTIMER_CTRL0_TMRB0POL_Msk (0x10000000UL) /*!< TMRB0POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0CLR_Pos (27UL) /*!< TMRB0CLR (Bit 27) */ +#define CTIMER_CTRL0_TMRB0CLR_Msk (0x8000000UL) /*!< TMRB0CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0IE1_Pos (26UL) /*!< TMRB0IE1 (Bit 26) */ +#define CTIMER_CTRL0_TMRB0IE1_Msk (0x4000000UL) /*!< TMRB0IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0IE0_Pos (25UL) /*!< TMRB0IE0 (Bit 25) */ +#define CTIMER_CTRL0_TMRB0IE0_Msk (0x2000000UL) /*!< TMRB0IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0FN_Pos (22UL) /*!< TMRB0FN (Bit 22) */ +#define CTIMER_CTRL0_TMRB0FN_Msk (0x1c00000UL) /*!< TMRB0FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL0_TMRB0CLK_Pos (17UL) /*!< TMRB0CLK (Bit 17) */ +#define CTIMER_CTRL0_TMRB0CLK_Msk (0x3e0000UL) /*!< TMRB0CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL0_TMRB0EN_Pos (16UL) /*!< TMRB0EN (Bit 16) */ +#define CTIMER_CTRL0_TMRB0EN_Msk (0x10000UL) /*!< TMRB0EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0PE_Pos (13UL) /*!< TMRA0PE (Bit 13) */ +#define CTIMER_CTRL0_TMRA0PE_Msk (0x2000UL) /*!< TMRA0PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0POL_Pos (12UL) /*!< TMRA0POL (Bit 12) */ +#define CTIMER_CTRL0_TMRA0POL_Msk (0x1000UL) /*!< TMRA0POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0CLR_Pos (11UL) /*!< TMRA0CLR (Bit 11) */ +#define CTIMER_CTRL0_TMRA0CLR_Msk (0x800UL) /*!< TMRA0CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0IE1_Pos (10UL) /*!< TMRA0IE1 (Bit 10) */ +#define CTIMER_CTRL0_TMRA0IE1_Msk (0x400UL) /*!< TMRA0IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0IE0_Pos (9UL) /*!< TMRA0IE0 (Bit 9) */ +#define CTIMER_CTRL0_TMRA0IE0_Msk (0x200UL) /*!< TMRA0IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0FN_Pos (6UL) /*!< TMRA0FN (Bit 6) */ +#define CTIMER_CTRL0_TMRA0FN_Msk (0x1c0UL) /*!< TMRA0FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL0_TMRA0CLK_Pos (1UL) /*!< TMRA0CLK (Bit 1) */ +#define CTIMER_CTRL0_TMRA0CLK_Msk (0x3eUL) /*!< TMRA0CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL0_TMRA0EN_Pos (0UL) /*!< TMRA0EN (Bit 0) */ +#define CTIMER_CTRL0_TMRA0EN_Msk (0x1UL) /*!< TMRA0EN (Bitfield-Mask: 0x01) */ +/* ========================================================= TMR1 ========================================================== */ +#define CTIMER_TMR1_CTTMRB1_Pos (16UL) /*!< CTTMRB1 (Bit 16) */ +#define CTIMER_TMR1_CTTMRB1_Msk (0xffff0000UL) /*!< CTTMRB1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR1_CTTMRA1_Pos (0UL) /*!< CTTMRA1 (Bit 0) */ +#define CTIMER_TMR1_CTTMRA1_Msk (0xffffUL) /*!< CTTMRA1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA1 ========================================================= */ +#define CTIMER_CMPRA1_CMPR1A1_Pos (16UL) /*!< CMPR1A1 (Bit 16) */ +#define CTIMER_CMPRA1_CMPR1A1_Msk (0xffff0000UL) /*!< CMPR1A1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA1_CMPR0A1_Pos (0UL) /*!< CMPR0A1 (Bit 0) */ +#define CTIMER_CMPRA1_CMPR0A1_Msk (0xffffUL) /*!< CMPR0A1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB1 ========================================================= */ +#define CTIMER_CMPRB1_CMPR1B1_Pos (16UL) /*!< CMPR1B1 (Bit 16) */ +#define CTIMER_CMPRB1_CMPR1B1_Msk (0xffff0000UL) /*!< CMPR1B1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB1_CMPR0B1_Pos (0UL) /*!< CMPR0B1 (Bit 0) */ +#define CTIMER_CMPRB1_CMPR0B1_Msk (0xffffUL) /*!< CMPR0B1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL1 ========================================================= */ +#define CTIMER_CTRL1_CTLINK1_Pos (31UL) /*!< CTLINK1 (Bit 31) */ +#define CTIMER_CTRL1_CTLINK1_Msk (0x80000000UL) /*!< CTLINK1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1PE_Pos (29UL) /*!< TMRB1PE (Bit 29) */ +#define CTIMER_CTRL1_TMRB1PE_Msk (0x20000000UL) /*!< TMRB1PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1POL_Pos (28UL) /*!< TMRB1POL (Bit 28) */ +#define CTIMER_CTRL1_TMRB1POL_Msk (0x10000000UL) /*!< TMRB1POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1CLR_Pos (27UL) /*!< TMRB1CLR (Bit 27) */ +#define CTIMER_CTRL1_TMRB1CLR_Msk (0x8000000UL) /*!< TMRB1CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1IE1_Pos (26UL) /*!< TMRB1IE1 (Bit 26) */ +#define CTIMER_CTRL1_TMRB1IE1_Msk (0x4000000UL) /*!< TMRB1IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1IE0_Pos (25UL) /*!< TMRB1IE0 (Bit 25) */ +#define CTIMER_CTRL1_TMRB1IE0_Msk (0x2000000UL) /*!< TMRB1IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1FN_Pos (22UL) /*!< TMRB1FN (Bit 22) */ +#define CTIMER_CTRL1_TMRB1FN_Msk (0x1c00000UL) /*!< TMRB1FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL1_TMRB1CLK_Pos (17UL) /*!< TMRB1CLK (Bit 17) */ +#define CTIMER_CTRL1_TMRB1CLK_Msk (0x3e0000UL) /*!< TMRB1CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL1_TMRB1EN_Pos (16UL) /*!< TMRB1EN (Bit 16) */ +#define CTIMER_CTRL1_TMRB1EN_Msk (0x10000UL) /*!< TMRB1EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1PE_Pos (13UL) /*!< TMRA1PE (Bit 13) */ +#define CTIMER_CTRL1_TMRA1PE_Msk (0x2000UL) /*!< TMRA1PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1POL_Pos (12UL) /*!< TMRA1POL (Bit 12) */ +#define CTIMER_CTRL1_TMRA1POL_Msk (0x1000UL) /*!< TMRA1POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1CLR_Pos (11UL) /*!< TMRA1CLR (Bit 11) */ +#define CTIMER_CTRL1_TMRA1CLR_Msk (0x800UL) /*!< TMRA1CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1IE1_Pos (10UL) /*!< TMRA1IE1 (Bit 10) */ +#define CTIMER_CTRL1_TMRA1IE1_Msk (0x400UL) /*!< TMRA1IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1IE0_Pos (9UL) /*!< TMRA1IE0 (Bit 9) */ +#define CTIMER_CTRL1_TMRA1IE0_Msk (0x200UL) /*!< TMRA1IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1FN_Pos (6UL) /*!< TMRA1FN (Bit 6) */ +#define CTIMER_CTRL1_TMRA1FN_Msk (0x1c0UL) /*!< TMRA1FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL1_TMRA1CLK_Pos (1UL) /*!< TMRA1CLK (Bit 1) */ +#define CTIMER_CTRL1_TMRA1CLK_Msk (0x3eUL) /*!< TMRA1CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL1_TMRA1EN_Pos (0UL) /*!< TMRA1EN (Bit 0) */ +#define CTIMER_CTRL1_TMRA1EN_Msk (0x1UL) /*!< TMRA1EN (Bitfield-Mask: 0x01) */ +/* ========================================================= TMR2 ========================================================== */ +#define CTIMER_TMR2_CTTMRB2_Pos (16UL) /*!< CTTMRB2 (Bit 16) */ +#define CTIMER_TMR2_CTTMRB2_Msk (0xffff0000UL) /*!< CTTMRB2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR2_CTTMRA2_Pos (0UL) /*!< CTTMRA2 (Bit 0) */ +#define CTIMER_TMR2_CTTMRA2_Msk (0xffffUL) /*!< CTTMRA2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA2 ========================================================= */ +#define CTIMER_CMPRA2_CMPR1A2_Pos (16UL) /*!< CMPR1A2 (Bit 16) */ +#define CTIMER_CMPRA2_CMPR1A2_Msk (0xffff0000UL) /*!< CMPR1A2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA2_CMPR0A2_Pos (0UL) /*!< CMPR0A2 (Bit 0) */ +#define CTIMER_CMPRA2_CMPR0A2_Msk (0xffffUL) /*!< CMPR0A2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB2 ========================================================= */ +#define CTIMER_CMPRB2_CMPR1B2_Pos (16UL) /*!< CMPR1B2 (Bit 16) */ +#define CTIMER_CMPRB2_CMPR1B2_Msk (0xffff0000UL) /*!< CMPR1B2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB2_CMPR0B2_Pos (0UL) /*!< CMPR0B2 (Bit 0) */ +#define CTIMER_CMPRB2_CMPR0B2_Msk (0xffffUL) /*!< CMPR0B2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL2 ========================================================= */ +#define CTIMER_CTRL2_CTLINK2_Pos (31UL) /*!< CTLINK2 (Bit 31) */ +#define CTIMER_CTRL2_CTLINK2_Msk (0x80000000UL) /*!< CTLINK2 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2PE_Pos (29UL) /*!< TMRB2PE (Bit 29) */ +#define CTIMER_CTRL2_TMRB2PE_Msk (0x20000000UL) /*!< TMRB2PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2POL_Pos (28UL) /*!< TMRB2POL (Bit 28) */ +#define CTIMER_CTRL2_TMRB2POL_Msk (0x10000000UL) /*!< TMRB2POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2CLR_Pos (27UL) /*!< TMRB2CLR (Bit 27) */ +#define CTIMER_CTRL2_TMRB2CLR_Msk (0x8000000UL) /*!< TMRB2CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2IE1_Pos (26UL) /*!< TMRB2IE1 (Bit 26) */ +#define CTIMER_CTRL2_TMRB2IE1_Msk (0x4000000UL) /*!< TMRB2IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2IE0_Pos (25UL) /*!< TMRB2IE0 (Bit 25) */ +#define CTIMER_CTRL2_TMRB2IE0_Msk (0x2000000UL) /*!< TMRB2IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2FN_Pos (22UL) /*!< TMRB2FN (Bit 22) */ +#define CTIMER_CTRL2_TMRB2FN_Msk (0x1c00000UL) /*!< TMRB2FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL2_TMRB2CLK_Pos (17UL) /*!< TMRB2CLK (Bit 17) */ +#define CTIMER_CTRL2_TMRB2CLK_Msk (0x3e0000UL) /*!< TMRB2CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL2_TMRB2EN_Pos (16UL) /*!< TMRB2EN (Bit 16) */ +#define CTIMER_CTRL2_TMRB2EN_Msk (0x10000UL) /*!< TMRB2EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2PE_Pos (13UL) /*!< TMRA2PE (Bit 13) */ +#define CTIMER_CTRL2_TMRA2PE_Msk (0x2000UL) /*!< TMRA2PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2POL_Pos (12UL) /*!< TMRA2POL (Bit 12) */ +#define CTIMER_CTRL2_TMRA2POL_Msk (0x1000UL) /*!< TMRA2POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2CLR_Pos (11UL) /*!< TMRA2CLR (Bit 11) */ +#define CTIMER_CTRL2_TMRA2CLR_Msk (0x800UL) /*!< TMRA2CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2IE1_Pos (10UL) /*!< TMRA2IE1 (Bit 10) */ +#define CTIMER_CTRL2_TMRA2IE1_Msk (0x400UL) /*!< TMRA2IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2IE0_Pos (9UL) /*!< TMRA2IE0 (Bit 9) */ +#define CTIMER_CTRL2_TMRA2IE0_Msk (0x200UL) /*!< TMRA2IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2FN_Pos (6UL) /*!< TMRA2FN (Bit 6) */ +#define CTIMER_CTRL2_TMRA2FN_Msk (0x1c0UL) /*!< TMRA2FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL2_TMRA2CLK_Pos (1UL) /*!< TMRA2CLK (Bit 1) */ +#define CTIMER_CTRL2_TMRA2CLK_Msk (0x3eUL) /*!< TMRA2CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL2_TMRA2EN_Pos (0UL) /*!< TMRA2EN (Bit 0) */ +#define CTIMER_CTRL2_TMRA2EN_Msk (0x1UL) /*!< TMRA2EN (Bitfield-Mask: 0x01) */ +/* ========================================================= TMR3 ========================================================== */ +#define CTIMER_TMR3_CTTMRB3_Pos (16UL) /*!< CTTMRB3 (Bit 16) */ +#define CTIMER_TMR3_CTTMRB3_Msk (0xffff0000UL) /*!< CTTMRB3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR3_CTTMRA3_Pos (0UL) /*!< CTTMRA3 (Bit 0) */ +#define CTIMER_TMR3_CTTMRA3_Msk (0xffffUL) /*!< CTTMRA3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA3 ========================================================= */ +#define CTIMER_CMPRA3_CMPR1A3_Pos (16UL) /*!< CMPR1A3 (Bit 16) */ +#define CTIMER_CMPRA3_CMPR1A3_Msk (0xffff0000UL) /*!< CMPR1A3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA3_CMPR0A3_Pos (0UL) /*!< CMPR0A3 (Bit 0) */ +#define CTIMER_CMPRA3_CMPR0A3_Msk (0xffffUL) /*!< CMPR0A3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB3 ========================================================= */ +#define CTIMER_CMPRB3_CMPR1B3_Pos (16UL) /*!< CMPR1B3 (Bit 16) */ +#define CTIMER_CMPRB3_CMPR1B3_Msk (0xffff0000UL) /*!< CMPR1B3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB3_CMPR0B3_Pos (0UL) /*!< CMPR0B3 (Bit 0) */ +#define CTIMER_CMPRB3_CMPR0B3_Msk (0xffffUL) /*!< CMPR0B3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL3 ========================================================= */ +#define CTIMER_CTRL3_CTLINK3_Pos (31UL) /*!< CTLINK3 (Bit 31) */ +#define CTIMER_CTRL3_CTLINK3_Msk (0x80000000UL) /*!< CTLINK3 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3PE_Pos (29UL) /*!< TMRB3PE (Bit 29) */ +#define CTIMER_CTRL3_TMRB3PE_Msk (0x20000000UL) /*!< TMRB3PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3POL_Pos (28UL) /*!< TMRB3POL (Bit 28) */ +#define CTIMER_CTRL3_TMRB3POL_Msk (0x10000000UL) /*!< TMRB3POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3CLR_Pos (27UL) /*!< TMRB3CLR (Bit 27) */ +#define CTIMER_CTRL3_TMRB3CLR_Msk (0x8000000UL) /*!< TMRB3CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3IE1_Pos (26UL) /*!< TMRB3IE1 (Bit 26) */ +#define CTIMER_CTRL3_TMRB3IE1_Msk (0x4000000UL) /*!< TMRB3IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3IE0_Pos (25UL) /*!< TMRB3IE0 (Bit 25) */ +#define CTIMER_CTRL3_TMRB3IE0_Msk (0x2000000UL) /*!< TMRB3IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3FN_Pos (22UL) /*!< TMRB3FN (Bit 22) */ +#define CTIMER_CTRL3_TMRB3FN_Msk (0x1c00000UL) /*!< TMRB3FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL3_TMRB3CLK_Pos (17UL) /*!< TMRB3CLK (Bit 17) */ +#define CTIMER_CTRL3_TMRB3CLK_Msk (0x3e0000UL) /*!< TMRB3CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL3_TMRB3EN_Pos (16UL) /*!< TMRB3EN (Bit 16) */ +#define CTIMER_CTRL3_TMRB3EN_Msk (0x10000UL) /*!< TMRB3EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_ADCEN_Pos (15UL) /*!< ADCEN (Bit 15) */ +#define CTIMER_CTRL3_ADCEN_Msk (0x8000UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3PE_Pos (13UL) /*!< TMRA3PE (Bit 13) */ +#define CTIMER_CTRL3_TMRA3PE_Msk (0x2000UL) /*!< TMRA3PE (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3POL_Pos (12UL) /*!< TMRA3POL (Bit 12) */ +#define CTIMER_CTRL3_TMRA3POL_Msk (0x1000UL) /*!< TMRA3POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3CLR_Pos (11UL) /*!< TMRA3CLR (Bit 11) */ +#define CTIMER_CTRL3_TMRA3CLR_Msk (0x800UL) /*!< TMRA3CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3IE1_Pos (10UL) /*!< TMRA3IE1 (Bit 10) */ +#define CTIMER_CTRL3_TMRA3IE1_Msk (0x400UL) /*!< TMRA3IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3IE0_Pos (9UL) /*!< TMRA3IE0 (Bit 9) */ +#define CTIMER_CTRL3_TMRA3IE0_Msk (0x200UL) /*!< TMRA3IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3FN_Pos (6UL) /*!< TMRA3FN (Bit 6) */ +#define CTIMER_CTRL3_TMRA3FN_Msk (0x1c0UL) /*!< TMRA3FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL3_TMRA3CLK_Pos (1UL) /*!< TMRA3CLK (Bit 1) */ +#define CTIMER_CTRL3_TMRA3CLK_Msk (0x3eUL) /*!< TMRA3CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL3_TMRA3EN_Pos (0UL) /*!< TMRA3EN (Bit 0) */ +#define CTIMER_CTRL3_TMRA3EN_Msk (0x1UL) /*!< TMRA3EN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCFG ========================================================= */ +#define CTIMER_STCFG_FREEZE_Pos (31UL) /*!< FREEZE (Bit 31) */ +#define CTIMER_STCFG_FREEZE_Msk (0x80000000UL) /*!< FREEZE (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_CLEAR_Pos (30UL) /*!< CLEAR (Bit 30) */ +#define CTIMER_STCFG_CLEAR_Msk (0x40000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_H_EN_Pos (15UL) /*!< COMPARE_H_EN (Bit 15) */ +#define CTIMER_STCFG_COMPARE_H_EN_Msk (0x8000UL) /*!< COMPARE_H_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_G_EN_Pos (14UL) /*!< COMPARE_G_EN (Bit 14) */ +#define CTIMER_STCFG_COMPARE_G_EN_Msk (0x4000UL) /*!< COMPARE_G_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_F_EN_Pos (13UL) /*!< COMPARE_F_EN (Bit 13) */ +#define CTIMER_STCFG_COMPARE_F_EN_Msk (0x2000UL) /*!< COMPARE_F_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_E_EN_Pos (12UL) /*!< COMPARE_E_EN (Bit 12) */ +#define CTIMER_STCFG_COMPARE_E_EN_Msk (0x1000UL) /*!< COMPARE_E_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_D_EN_Pos (11UL) /*!< COMPARE_D_EN (Bit 11) */ +#define CTIMER_STCFG_COMPARE_D_EN_Msk (0x800UL) /*!< COMPARE_D_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_C_EN_Pos (10UL) /*!< COMPARE_C_EN (Bit 10) */ +#define CTIMER_STCFG_COMPARE_C_EN_Msk (0x400UL) /*!< COMPARE_C_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_B_EN_Pos (9UL) /*!< COMPARE_B_EN (Bit 9) */ +#define CTIMER_STCFG_COMPARE_B_EN_Msk (0x200UL) /*!< COMPARE_B_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_A_EN_Pos (8UL) /*!< COMPARE_A_EN (Bit 8) */ +#define CTIMER_STCFG_COMPARE_A_EN_Msk (0x100UL) /*!< COMPARE_A_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ +#define CTIMER_STCFG_CLKSEL_Msk (0xfUL) /*!< CLKSEL (Bitfield-Mask: 0x0f) */ +/* ========================================================= STTMR ========================================================= */ +#define CTIMER_STTMR_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_STTMR_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CAPTURE_CONTROL ==================================================== */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_D_Pos (3UL) /*!< CAPTURE_D (Bit 3) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_D_Msk (0x8UL) /*!< CAPTURE_D (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_C_Pos (2UL) /*!< CAPTURE_C (Bit 2) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_C_Msk (0x4UL) /*!< CAPTURE_C (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_B_Pos (1UL) /*!< CAPTURE_B (Bit 1) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_B_Msk (0x2UL) /*!< CAPTURE_B (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_A_Pos (0UL) /*!< CAPTURE_A (Bit 0) */ +#define CTIMER_CAPTURE_CONTROL_CAPTURE_A_Msk (0x1UL) /*!< CAPTURE_A (Bitfield-Mask: 0x01) */ +/* ======================================================== SCMPR0 ========================================================= */ +#define CTIMER_SCMPR0_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR0_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR1 ========================================================= */ +#define CTIMER_SCMPR1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR1_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR2 ========================================================= */ +#define CTIMER_SCMPR2_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR2_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR3 ========================================================= */ +#define CTIMER_SCMPR3_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR3_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR4 ========================================================= */ +#define CTIMER_SCMPR4_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR4_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR5 ========================================================= */ +#define CTIMER_SCMPR5_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR5_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR6 ========================================================= */ +#define CTIMER_SCMPR6_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR6_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR7 ========================================================= */ +#define CTIMER_SCMPR7_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCMPR7_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT0 ========================================================= */ +#define CTIMER_SCAPT0_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCAPT0_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT1 ========================================================= */ +#define CTIMER_SCAPT1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCAPT1_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT2 ========================================================= */ +#define CTIMER_SCAPT2_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCAPT2_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT3 ========================================================= */ +#define CTIMER_SCAPT3_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SCAPT3_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR0 ========================================================= */ +#define CTIMER_SNVR0_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SNVR0_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR1 ========================================================= */ +#define CTIMER_SNVR1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SNVR1_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR2 ========================================================= */ +#define CTIMER_SNVR2_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define CTIMER_SNVR2_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTEN ========================================================= */ +#define CTIMER_INTEN_CTMRB3C1INT_Pos (15UL) /*!< CTMRB3C1INT (Bit 15) */ +#define CTIMER_INTEN_CTMRB3C1INT_Msk (0x8000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA3C1INT_Pos (14UL) /*!< CTMRA3C1INT (Bit 14) */ +#define CTIMER_INTEN_CTMRA3C1INT_Msk (0x4000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB2C1INT_Pos (13UL) /*!< CTMRB2C1INT (Bit 13) */ +#define CTIMER_INTEN_CTMRB2C1INT_Msk (0x2000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA2C1INT_Pos (12UL) /*!< CTMRA2C1INT (Bit 12) */ +#define CTIMER_INTEN_CTMRA2C1INT_Msk (0x1000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB1C1INT_Pos (11UL) /*!< CTMRB1C1INT (Bit 11) */ +#define CTIMER_INTEN_CTMRB1C1INT_Msk (0x800UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA1C1INT_Pos (10UL) /*!< CTMRA1C1INT (Bit 10) */ +#define CTIMER_INTEN_CTMRA1C1INT_Msk (0x400UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB0C1INT_Pos (9UL) /*!< CTMRB0C1INT (Bit 9) */ +#define CTIMER_INTEN_CTMRB0C1INT_Msk (0x200UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA0C1INT_Pos (8UL) /*!< CTMRA0C1INT (Bit 8) */ +#define CTIMER_INTEN_CTMRA0C1INT_Msk (0x100UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTEN_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTEN_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTEN_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTEN_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTEN_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTEN_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTEN_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTEN_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define CTIMER_INTSTAT_CTMRB3C1INT_Pos (15UL) /*!< CTMRB3C1INT (Bit 15) */ +#define CTIMER_INTSTAT_CTMRB3C1INT_Msk (0x8000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA3C1INT_Pos (14UL) /*!< CTMRA3C1INT (Bit 14) */ +#define CTIMER_INTSTAT_CTMRA3C1INT_Msk (0x4000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB2C1INT_Pos (13UL) /*!< CTMRB2C1INT (Bit 13) */ +#define CTIMER_INTSTAT_CTMRB2C1INT_Msk (0x2000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA2C1INT_Pos (12UL) /*!< CTMRA2C1INT (Bit 12) */ +#define CTIMER_INTSTAT_CTMRA2C1INT_Msk (0x1000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB1C1INT_Pos (11UL) /*!< CTMRB1C1INT (Bit 11) */ +#define CTIMER_INTSTAT_CTMRB1C1INT_Msk (0x800UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA1C1INT_Pos (10UL) /*!< CTMRA1C1INT (Bit 10) */ +#define CTIMER_INTSTAT_CTMRA1C1INT_Msk (0x400UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB0C1INT_Pos (9UL) /*!< CTMRB0C1INT (Bit 9) */ +#define CTIMER_INTSTAT_CTMRB0C1INT_Msk (0x200UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA0C1INT_Pos (8UL) /*!< CTMRA0C1INT (Bit 8) */ +#define CTIMER_INTSTAT_CTMRA0C1INT_Msk (0x100UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTSTAT_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTSTAT_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTSTAT_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTSTAT_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTSTAT_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTSTAT_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTSTAT_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTSTAT_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define CTIMER_INTCLR_CTMRB3C1INT_Pos (15UL) /*!< CTMRB3C1INT (Bit 15) */ +#define CTIMER_INTCLR_CTMRB3C1INT_Msk (0x8000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA3C1INT_Pos (14UL) /*!< CTMRA3C1INT (Bit 14) */ +#define CTIMER_INTCLR_CTMRA3C1INT_Msk (0x4000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB2C1INT_Pos (13UL) /*!< CTMRB2C1INT (Bit 13) */ +#define CTIMER_INTCLR_CTMRB2C1INT_Msk (0x2000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA2C1INT_Pos (12UL) /*!< CTMRA2C1INT (Bit 12) */ +#define CTIMER_INTCLR_CTMRA2C1INT_Msk (0x1000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB1C1INT_Pos (11UL) /*!< CTMRB1C1INT (Bit 11) */ +#define CTIMER_INTCLR_CTMRB1C1INT_Msk (0x800UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA1C1INT_Pos (10UL) /*!< CTMRA1C1INT (Bit 10) */ +#define CTIMER_INTCLR_CTMRA1C1INT_Msk (0x400UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB0C1INT_Pos (9UL) /*!< CTMRB0C1INT (Bit 9) */ +#define CTIMER_INTCLR_CTMRB0C1INT_Msk (0x200UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA0C1INT_Pos (8UL) /*!< CTMRA0C1INT (Bit 8) */ +#define CTIMER_INTCLR_CTMRA0C1INT_Msk (0x100UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTCLR_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTCLR_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTCLR_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTCLR_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTCLR_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTCLR_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTCLR_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTCLR_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define CTIMER_INTSET_CTMRB3C1INT_Pos (15UL) /*!< CTMRB3C1INT (Bit 15) */ +#define CTIMER_INTSET_CTMRB3C1INT_Msk (0x8000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA3C1INT_Pos (14UL) /*!< CTMRA3C1INT (Bit 14) */ +#define CTIMER_INTSET_CTMRA3C1INT_Msk (0x4000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB2C1INT_Pos (13UL) /*!< CTMRB2C1INT (Bit 13) */ +#define CTIMER_INTSET_CTMRB2C1INT_Msk (0x2000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA2C1INT_Pos (12UL) /*!< CTMRA2C1INT (Bit 12) */ +#define CTIMER_INTSET_CTMRA2C1INT_Msk (0x1000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB1C1INT_Pos (11UL) /*!< CTMRB1C1INT (Bit 11) */ +#define CTIMER_INTSET_CTMRB1C1INT_Msk (0x800UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA1C1INT_Pos (10UL) /*!< CTMRA1C1INT (Bit 10) */ +#define CTIMER_INTSET_CTMRA1C1INT_Msk (0x400UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB0C1INT_Pos (9UL) /*!< CTMRB0C1INT (Bit 9) */ +#define CTIMER_INTSET_CTMRB0C1INT_Msk (0x200UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA0C1INT_Pos (8UL) /*!< CTMRA0C1INT (Bit 8) */ +#define CTIMER_INTSET_CTMRA0C1INT_Msk (0x100UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTSET_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTSET_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTSET_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTSET_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTSET_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTSET_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTSET_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTSET_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTEN ======================================================== */ +#define CTIMER_STMINTEN_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTEN_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTEN_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTEN_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTEN_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTEN_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTEN_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTEN_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTEN_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTEN_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTEN_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTEN_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTEN_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTEN_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ====================================================== STMINTSTAT ======================================================= */ +#define CTIMER_STMINTSTAT_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTSTAT_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTSTAT_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTSTAT_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTSTAT_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTSTAT_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTSTAT_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTSTAT_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTSTAT_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTSTAT_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTSTAT_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTSTAT_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTSTAT_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTSTAT_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTCLR ======================================================= */ +#define CTIMER_STMINTCLR_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTCLR_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTCLR_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTCLR_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTCLR_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTCLR_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTCLR_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTCLR_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTCLR_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTCLR_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTCLR_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTCLR_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTCLR_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTCLR_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTSET ======================================================= */ +#define CTIMER_STMINTSET_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTSET_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTSET_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTSET_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTSET_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTSET_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTSET_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTSET_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTSET_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTSET_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTSET_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTSET_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTSET_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTSET_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PADREGA ======================================================== */ +#define GPIO_PADREGA_PAD3FNCSEL_Pos (27UL) /*!< PAD3FNCSEL (Bit 27) */ +#define GPIO_PADREGA_PAD3FNCSEL_Msk (0x38000000UL) /*!< PAD3FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD3STRNG_Pos (26UL) /*!< PAD3STRNG (Bit 26) */ +#define GPIO_PADREGA_PAD3STRNG_Msk (0x4000000UL) /*!< PAD3STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3INPEN_Pos (25UL) /*!< PAD3INPEN (Bit 25) */ +#define GPIO_PADREGA_PAD3INPEN_Msk (0x2000000UL) /*!< PAD3INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3PULL_Pos (24UL) /*!< PAD3PULL (Bit 24) */ +#define GPIO_PADREGA_PAD3PULL_Msk (0x1000000UL) /*!< PAD3PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2FNCSEL_Pos (19UL) /*!< PAD2FNCSEL (Bit 19) */ +#define GPIO_PADREGA_PAD2FNCSEL_Msk (0x380000UL) /*!< PAD2FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD2STRNG_Pos (18UL) /*!< PAD2STRNG (Bit 18) */ +#define GPIO_PADREGA_PAD2STRNG_Msk (0x40000UL) /*!< PAD2STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2INPEN_Pos (17UL) /*!< PAD2INPEN (Bit 17) */ +#define GPIO_PADREGA_PAD2INPEN_Msk (0x20000UL) /*!< PAD2INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2PULL_Pos (16UL) /*!< PAD2PULL (Bit 16) */ +#define GPIO_PADREGA_PAD2PULL_Msk (0x10000UL) /*!< PAD2PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1RSEL_Pos (14UL) /*!< PAD1RSEL (Bit 14) */ +#define GPIO_PADREGA_PAD1RSEL_Msk (0xc000UL) /*!< PAD1RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGA_PAD1FNCSEL_Pos (11UL) /*!< PAD1FNCSEL (Bit 11) */ +#define GPIO_PADREGA_PAD1FNCSEL_Msk (0x3800UL) /*!< PAD1FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD1STRNG_Pos (10UL) /*!< PAD1STRNG (Bit 10) */ +#define GPIO_PADREGA_PAD1STRNG_Msk (0x400UL) /*!< PAD1STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1INPEN_Pos (9UL) /*!< PAD1INPEN (Bit 9) */ +#define GPIO_PADREGA_PAD1INPEN_Msk (0x200UL) /*!< PAD1INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1PULL_Pos (8UL) /*!< PAD1PULL (Bit 8) */ +#define GPIO_PADREGA_PAD1PULL_Msk (0x100UL) /*!< PAD1PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0RSEL_Pos (6UL) /*!< PAD0RSEL (Bit 6) */ +#define GPIO_PADREGA_PAD0RSEL_Msk (0xc0UL) /*!< PAD0RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGA_PAD0FNCSEL_Pos (3UL) /*!< PAD0FNCSEL (Bit 3) */ +#define GPIO_PADREGA_PAD0FNCSEL_Msk (0x38UL) /*!< PAD0FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD0STRNG_Pos (2UL) /*!< PAD0STRNG (Bit 2) */ +#define GPIO_PADREGA_PAD0STRNG_Msk (0x4UL) /*!< PAD0STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0INPEN_Pos (1UL) /*!< PAD0INPEN (Bit 1) */ +#define GPIO_PADREGA_PAD0INPEN_Msk (0x2UL) /*!< PAD0INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0PULL_Pos (0UL) /*!< PAD0PULL (Bit 0) */ +#define GPIO_PADREGA_PAD0PULL_Msk (0x1UL) /*!< PAD0PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGB ======================================================== */ +#define GPIO_PADREGB_PAD7FNCSEL_Pos (27UL) /*!< PAD7FNCSEL (Bit 27) */ +#define GPIO_PADREGB_PAD7FNCSEL_Msk (0x38000000UL) /*!< PAD7FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD7STRNG_Pos (26UL) /*!< PAD7STRNG (Bit 26) */ +#define GPIO_PADREGB_PAD7STRNG_Msk (0x4000000UL) /*!< PAD7STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD7INPEN_Pos (25UL) /*!< PAD7INPEN (Bit 25) */ +#define GPIO_PADREGB_PAD7INPEN_Msk (0x2000000UL) /*!< PAD7INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD7PULL_Pos (24UL) /*!< PAD7PULL (Bit 24) */ +#define GPIO_PADREGB_PAD7PULL_Msk (0x1000000UL) /*!< PAD7PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6RSEL_Pos (22UL) /*!< PAD6RSEL (Bit 22) */ +#define GPIO_PADREGB_PAD6RSEL_Msk (0xc00000UL) /*!< PAD6RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGB_PAD6FNCSEL_Pos (19UL) /*!< PAD6FNCSEL (Bit 19) */ +#define GPIO_PADREGB_PAD6FNCSEL_Msk (0x380000UL) /*!< PAD6FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD6STRNG_Pos (18UL) /*!< PAD6STRNG (Bit 18) */ +#define GPIO_PADREGB_PAD6STRNG_Msk (0x40000UL) /*!< PAD6STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6INPEN_Pos (17UL) /*!< PAD6INPEN (Bit 17) */ +#define GPIO_PADREGB_PAD6INPEN_Msk (0x20000UL) /*!< PAD6INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6PULL_Pos (16UL) /*!< PAD6PULL (Bit 16) */ +#define GPIO_PADREGB_PAD6PULL_Msk (0x10000UL) /*!< PAD6PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5RSEL_Pos (14UL) /*!< PAD5RSEL (Bit 14) */ +#define GPIO_PADREGB_PAD5RSEL_Msk (0xc000UL) /*!< PAD5RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGB_PAD5FNCSEL_Pos (11UL) /*!< PAD5FNCSEL (Bit 11) */ +#define GPIO_PADREGB_PAD5FNCSEL_Msk (0x3800UL) /*!< PAD5FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD5STRNG_Pos (10UL) /*!< PAD5STRNG (Bit 10) */ +#define GPIO_PADREGB_PAD5STRNG_Msk (0x400UL) /*!< PAD5STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5INPEN_Pos (9UL) /*!< PAD5INPEN (Bit 9) */ +#define GPIO_PADREGB_PAD5INPEN_Msk (0x200UL) /*!< PAD5INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5PULL_Pos (8UL) /*!< PAD5PULL (Bit 8) */ +#define GPIO_PADREGB_PAD5PULL_Msk (0x100UL) /*!< PAD5PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4PWRDN_Pos (7UL) /*!< PAD4PWRDN (Bit 7) */ +#define GPIO_PADREGB_PAD4PWRDN_Msk (0x80UL) /*!< PAD4PWRDN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4FNCSEL_Pos (3UL) /*!< PAD4FNCSEL (Bit 3) */ +#define GPIO_PADREGB_PAD4FNCSEL_Msk (0x38UL) /*!< PAD4FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD4STRNG_Pos (2UL) /*!< PAD4STRNG (Bit 2) */ +#define GPIO_PADREGB_PAD4STRNG_Msk (0x4UL) /*!< PAD4STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4INPEN_Pos (1UL) /*!< PAD4INPEN (Bit 1) */ +#define GPIO_PADREGB_PAD4INPEN_Msk (0x2UL) /*!< PAD4INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4PULL_Pos (0UL) /*!< PAD4PULL (Bit 0) */ +#define GPIO_PADREGB_PAD4PULL_Msk (0x1UL) /*!< PAD4PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGC ======================================================== */ +#define GPIO_PADREGC_PAD11FNCSEL_Pos (27UL) /*!< PAD11FNCSEL (Bit 27) */ +#define GPIO_PADREGC_PAD11FNCSEL_Msk (0x38000000UL) /*!< PAD11FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD11STRNG_Pos (26UL) /*!< PAD11STRNG (Bit 26) */ +#define GPIO_PADREGC_PAD11STRNG_Msk (0x4000000UL) /*!< PAD11STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD11INPEN_Pos (25UL) /*!< PAD11INPEN (Bit 25) */ +#define GPIO_PADREGC_PAD11INPEN_Msk (0x2000000UL) /*!< PAD11INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD11PULL_Pos (24UL) /*!< PAD11PULL (Bit 24) */ +#define GPIO_PADREGC_PAD11PULL_Msk (0x1000000UL) /*!< PAD11PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10FNCSEL_Pos (19UL) /*!< PAD10FNCSEL (Bit 19) */ +#define GPIO_PADREGC_PAD10FNCSEL_Msk (0x380000UL) /*!< PAD10FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD10STRNG_Pos (18UL) /*!< PAD10STRNG (Bit 18) */ +#define GPIO_PADREGC_PAD10STRNG_Msk (0x40000UL) /*!< PAD10STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10INPEN_Pos (17UL) /*!< PAD10INPEN (Bit 17) */ +#define GPIO_PADREGC_PAD10INPEN_Msk (0x20000UL) /*!< PAD10INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10PULL_Pos (16UL) /*!< PAD10PULL (Bit 16) */ +#define GPIO_PADREGC_PAD10PULL_Msk (0x10000UL) /*!< PAD10PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9RSEL_Pos (14UL) /*!< PAD9RSEL (Bit 14) */ +#define GPIO_PADREGC_PAD9RSEL_Msk (0xc000UL) /*!< PAD9RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGC_PAD9FNCSEL_Pos (11UL) /*!< PAD9FNCSEL (Bit 11) */ +#define GPIO_PADREGC_PAD9FNCSEL_Msk (0x3800UL) /*!< PAD9FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD9STRNG_Pos (10UL) /*!< PAD9STRNG (Bit 10) */ +#define GPIO_PADREGC_PAD9STRNG_Msk (0x400UL) /*!< PAD9STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9INPEN_Pos (9UL) /*!< PAD9INPEN (Bit 9) */ +#define GPIO_PADREGC_PAD9INPEN_Msk (0x200UL) /*!< PAD9INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9PULL_Pos (8UL) /*!< PAD9PULL (Bit 8) */ +#define GPIO_PADREGC_PAD9PULL_Msk (0x100UL) /*!< PAD9PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8RSEL_Pos (6UL) /*!< PAD8RSEL (Bit 6) */ +#define GPIO_PADREGC_PAD8RSEL_Msk (0xc0UL) /*!< PAD8RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGC_PAD8FNCSEL_Pos (3UL) /*!< PAD8FNCSEL (Bit 3) */ +#define GPIO_PADREGC_PAD8FNCSEL_Msk (0x38UL) /*!< PAD8FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD8STRNG_Pos (2UL) /*!< PAD8STRNG (Bit 2) */ +#define GPIO_PADREGC_PAD8STRNG_Msk (0x4UL) /*!< PAD8STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8INPEN_Pos (1UL) /*!< PAD8INPEN (Bit 1) */ +#define GPIO_PADREGC_PAD8INPEN_Msk (0x2UL) /*!< PAD8INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8PULL_Pos (0UL) /*!< PAD8PULL (Bit 0) */ +#define GPIO_PADREGC_PAD8PULL_Msk (0x1UL) /*!< PAD8PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGD ======================================================== */ +#define GPIO_PADREGD_PAD15FNCSEL_Pos (27UL) /*!< PAD15FNCSEL (Bit 27) */ +#define GPIO_PADREGD_PAD15FNCSEL_Msk (0x38000000UL) /*!< PAD15FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD15STRNG_Pos (26UL) /*!< PAD15STRNG (Bit 26) */ +#define GPIO_PADREGD_PAD15STRNG_Msk (0x4000000UL) /*!< PAD15STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD15INPEN_Pos (25UL) /*!< PAD15INPEN (Bit 25) */ +#define GPIO_PADREGD_PAD15INPEN_Msk (0x2000000UL) /*!< PAD15INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD15PULL_Pos (24UL) /*!< PAD15PULL (Bit 24) */ +#define GPIO_PADREGD_PAD15PULL_Msk (0x1000000UL) /*!< PAD15PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14FNCSEL_Pos (19UL) /*!< PAD14FNCSEL (Bit 19) */ +#define GPIO_PADREGD_PAD14FNCSEL_Msk (0x380000UL) /*!< PAD14FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD14STRNG_Pos (18UL) /*!< PAD14STRNG (Bit 18) */ +#define GPIO_PADREGD_PAD14STRNG_Msk (0x40000UL) /*!< PAD14STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14INPEN_Pos (17UL) /*!< PAD14INPEN (Bit 17) */ +#define GPIO_PADREGD_PAD14INPEN_Msk (0x20000UL) /*!< PAD14INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14PULL_Pos (16UL) /*!< PAD14PULL (Bit 16) */ +#define GPIO_PADREGD_PAD14PULL_Msk (0x10000UL) /*!< PAD14PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13FNCSEL_Pos (11UL) /*!< PAD13FNCSEL (Bit 11) */ +#define GPIO_PADREGD_PAD13FNCSEL_Msk (0x3800UL) /*!< PAD13FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD13STRNG_Pos (10UL) /*!< PAD13STRNG (Bit 10) */ +#define GPIO_PADREGD_PAD13STRNG_Msk (0x400UL) /*!< PAD13STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13INPEN_Pos (9UL) /*!< PAD13INPEN (Bit 9) */ +#define GPIO_PADREGD_PAD13INPEN_Msk (0x200UL) /*!< PAD13INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13PULL_Pos (8UL) /*!< PAD13PULL (Bit 8) */ +#define GPIO_PADREGD_PAD13PULL_Msk (0x100UL) /*!< PAD13PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12FNCSEL_Pos (3UL) /*!< PAD12FNCSEL (Bit 3) */ +#define GPIO_PADREGD_PAD12FNCSEL_Msk (0x38UL) /*!< PAD12FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD12STRNG_Pos (2UL) /*!< PAD12STRNG (Bit 2) */ +#define GPIO_PADREGD_PAD12STRNG_Msk (0x4UL) /*!< PAD12STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12INPEN_Pos (1UL) /*!< PAD12INPEN (Bit 1) */ +#define GPIO_PADREGD_PAD12INPEN_Msk (0x2UL) /*!< PAD12INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12PULL_Pos (0UL) /*!< PAD12PULL (Bit 0) */ +#define GPIO_PADREGD_PAD12PULL_Msk (0x1UL) /*!< PAD12PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGE ======================================================== */ +#define GPIO_PADREGE_PAD19FNCSEL_Pos (27UL) /*!< PAD19FNCSEL (Bit 27) */ +#define GPIO_PADREGE_PAD19FNCSEL_Msk (0x38000000UL) /*!< PAD19FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD19STRNG_Pos (26UL) /*!< PAD19STRNG (Bit 26) */ +#define GPIO_PADREGE_PAD19STRNG_Msk (0x4000000UL) /*!< PAD19STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD19INPEN_Pos (25UL) /*!< PAD19INPEN (Bit 25) */ +#define GPIO_PADREGE_PAD19INPEN_Msk (0x2000000UL) /*!< PAD19INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD19PULL_Pos (24UL) /*!< PAD19PULL (Bit 24) */ +#define GPIO_PADREGE_PAD19PULL_Msk (0x1000000UL) /*!< PAD19PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18FNCSEL_Pos (19UL) /*!< PAD18FNCSEL (Bit 19) */ +#define GPIO_PADREGE_PAD18FNCSEL_Msk (0x380000UL) /*!< PAD18FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD18STRNG_Pos (18UL) /*!< PAD18STRNG (Bit 18) */ +#define GPIO_PADREGE_PAD18STRNG_Msk (0x40000UL) /*!< PAD18STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18INPEN_Pos (17UL) /*!< PAD18INPEN (Bit 17) */ +#define GPIO_PADREGE_PAD18INPEN_Msk (0x20000UL) /*!< PAD18INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18PULL_Pos (16UL) /*!< PAD18PULL (Bit 16) */ +#define GPIO_PADREGE_PAD18PULL_Msk (0x10000UL) /*!< PAD18PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17FNCSEL_Pos (11UL) /*!< PAD17FNCSEL (Bit 11) */ +#define GPIO_PADREGE_PAD17FNCSEL_Msk (0x3800UL) /*!< PAD17FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD17STRNG_Pos (10UL) /*!< PAD17STRNG (Bit 10) */ +#define GPIO_PADREGE_PAD17STRNG_Msk (0x400UL) /*!< PAD17STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17INPEN_Pos (9UL) /*!< PAD17INPEN (Bit 9) */ +#define GPIO_PADREGE_PAD17INPEN_Msk (0x200UL) /*!< PAD17INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17PULL_Pos (8UL) /*!< PAD17PULL (Bit 8) */ +#define GPIO_PADREGE_PAD17PULL_Msk (0x100UL) /*!< PAD17PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16FNCSEL_Pos (3UL) /*!< PAD16FNCSEL (Bit 3) */ +#define GPIO_PADREGE_PAD16FNCSEL_Msk (0x38UL) /*!< PAD16FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD16STRNG_Pos (2UL) /*!< PAD16STRNG (Bit 2) */ +#define GPIO_PADREGE_PAD16STRNG_Msk (0x4UL) /*!< PAD16STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16INPEN_Pos (1UL) /*!< PAD16INPEN (Bit 1) */ +#define GPIO_PADREGE_PAD16INPEN_Msk (0x2UL) /*!< PAD16INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16PULL_Pos (0UL) /*!< PAD16PULL (Bit 0) */ +#define GPIO_PADREGE_PAD16PULL_Msk (0x1UL) /*!< PAD16PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGF ======================================================== */ +#define GPIO_PADREGF_PAD23FNCSEL_Pos (27UL) /*!< PAD23FNCSEL (Bit 27) */ +#define GPIO_PADREGF_PAD23FNCSEL_Msk (0x38000000UL) /*!< PAD23FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD23STRNG_Pos (26UL) /*!< PAD23STRNG (Bit 26) */ +#define GPIO_PADREGF_PAD23STRNG_Msk (0x4000000UL) /*!< PAD23STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD23INPEN_Pos (25UL) /*!< PAD23INPEN (Bit 25) */ +#define GPIO_PADREGF_PAD23INPEN_Msk (0x2000000UL) /*!< PAD23INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD23PULL_Pos (24UL) /*!< PAD23PULL (Bit 24) */ +#define GPIO_PADREGF_PAD23PULL_Msk (0x1000000UL) /*!< PAD23PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22PWRUP_Pos (23UL) /*!< PAD22PWRUP (Bit 23) */ +#define GPIO_PADREGF_PAD22PWRUP_Msk (0x800000UL) /*!< PAD22PWRUP (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22FNCSEL_Pos (19UL) /*!< PAD22FNCSEL (Bit 19) */ +#define GPIO_PADREGF_PAD22FNCSEL_Msk (0x380000UL) /*!< PAD22FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD22STRNG_Pos (18UL) /*!< PAD22STRNG (Bit 18) */ +#define GPIO_PADREGF_PAD22STRNG_Msk (0x40000UL) /*!< PAD22STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22INPEN_Pos (17UL) /*!< PAD22INPEN (Bit 17) */ +#define GPIO_PADREGF_PAD22INPEN_Msk (0x20000UL) /*!< PAD22INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22PULL_Pos (16UL) /*!< PAD22PULL (Bit 16) */ +#define GPIO_PADREGF_PAD22PULL_Msk (0x10000UL) /*!< PAD22PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21FNCSEL_Pos (11UL) /*!< PAD21FNCSEL (Bit 11) */ +#define GPIO_PADREGF_PAD21FNCSEL_Msk (0x3800UL) /*!< PAD21FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD21STRNG_Pos (10UL) /*!< PAD21STRNG (Bit 10) */ +#define GPIO_PADREGF_PAD21STRNG_Msk (0x400UL) /*!< PAD21STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21INPEN_Pos (9UL) /*!< PAD21INPEN (Bit 9) */ +#define GPIO_PADREGF_PAD21INPEN_Msk (0x200UL) /*!< PAD21INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21PULL_Pos (8UL) /*!< PAD21PULL (Bit 8) */ +#define GPIO_PADREGF_PAD21PULL_Msk (0x100UL) /*!< PAD21PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20FNCSEL_Pos (3UL) /*!< PAD20FNCSEL (Bit 3) */ +#define GPIO_PADREGF_PAD20FNCSEL_Msk (0x38UL) /*!< PAD20FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD20STRNG_Pos (2UL) /*!< PAD20STRNG (Bit 2) */ +#define GPIO_PADREGF_PAD20STRNG_Msk (0x4UL) /*!< PAD20STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20INPEN_Pos (1UL) /*!< PAD20INPEN (Bit 1) */ +#define GPIO_PADREGF_PAD20INPEN_Msk (0x2UL) /*!< PAD20INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20PULL_Pos (0UL) /*!< PAD20PULL (Bit 0) */ +#define GPIO_PADREGF_PAD20PULL_Msk (0x1UL) /*!< PAD20PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGG ======================================================== */ +#define GPIO_PADREGG_PAD27RSEL_Pos (30UL) /*!< PAD27RSEL (Bit 30) */ +#define GPIO_PADREGG_PAD27RSEL_Msk (0xc0000000UL) /*!< PAD27RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGG_PAD27FNCSEL_Pos (27UL) /*!< PAD27FNCSEL (Bit 27) */ +#define GPIO_PADREGG_PAD27FNCSEL_Msk (0x38000000UL) /*!< PAD27FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD27STRNG_Pos (26UL) /*!< PAD27STRNG (Bit 26) */ +#define GPIO_PADREGG_PAD27STRNG_Msk (0x4000000UL) /*!< PAD27STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD27INPEN_Pos (25UL) /*!< PAD27INPEN (Bit 25) */ +#define GPIO_PADREGG_PAD27INPEN_Msk (0x2000000UL) /*!< PAD27INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD27PULL_Pos (24UL) /*!< PAD27PULL (Bit 24) */ +#define GPIO_PADREGG_PAD27PULL_Msk (0x1000000UL) /*!< PAD27PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26FNCSEL_Pos (19UL) /*!< PAD26FNCSEL (Bit 19) */ +#define GPIO_PADREGG_PAD26FNCSEL_Msk (0x380000UL) /*!< PAD26FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD26STRNG_Pos (18UL) /*!< PAD26STRNG (Bit 18) */ +#define GPIO_PADREGG_PAD26STRNG_Msk (0x40000UL) /*!< PAD26STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26INPEN_Pos (17UL) /*!< PAD26INPEN (Bit 17) */ +#define GPIO_PADREGG_PAD26INPEN_Msk (0x20000UL) /*!< PAD26INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26PULL_Pos (16UL) /*!< PAD26PULL (Bit 16) */ +#define GPIO_PADREGG_PAD26PULL_Msk (0x10000UL) /*!< PAD26PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25RSEL_Pos (14UL) /*!< PAD25RSEL (Bit 14) */ +#define GPIO_PADREGG_PAD25RSEL_Msk (0xc000UL) /*!< PAD25RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGG_PAD25FNCSEL_Pos (11UL) /*!< PAD25FNCSEL (Bit 11) */ +#define GPIO_PADREGG_PAD25FNCSEL_Msk (0x3800UL) /*!< PAD25FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD25STRNG_Pos (10UL) /*!< PAD25STRNG (Bit 10) */ +#define GPIO_PADREGG_PAD25STRNG_Msk (0x400UL) /*!< PAD25STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25INPEN_Pos (9UL) /*!< PAD25INPEN (Bit 9) */ +#define GPIO_PADREGG_PAD25INPEN_Msk (0x200UL) /*!< PAD25INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25PULL_Pos (8UL) /*!< PAD25PULL (Bit 8) */ +#define GPIO_PADREGG_PAD25PULL_Msk (0x100UL) /*!< PAD25PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24FNCSEL_Pos (3UL) /*!< PAD24FNCSEL (Bit 3) */ +#define GPIO_PADREGG_PAD24FNCSEL_Msk (0x38UL) /*!< PAD24FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD24STRNG_Pos (2UL) /*!< PAD24STRNG (Bit 2) */ +#define GPIO_PADREGG_PAD24STRNG_Msk (0x4UL) /*!< PAD24STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24INPEN_Pos (1UL) /*!< PAD24INPEN (Bit 1) */ +#define GPIO_PADREGG_PAD24INPEN_Msk (0x2UL) /*!< PAD24INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24PULL_Pos (0UL) /*!< PAD24PULL (Bit 0) */ +#define GPIO_PADREGG_PAD24PULL_Msk (0x1UL) /*!< PAD24PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGH ======================================================== */ +#define GPIO_PADREGH_PAD31FNCSEL_Pos (27UL) /*!< PAD31FNCSEL (Bit 27) */ +#define GPIO_PADREGH_PAD31FNCSEL_Msk (0x38000000UL) /*!< PAD31FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD31STRNG_Pos (26UL) /*!< PAD31STRNG (Bit 26) */ +#define GPIO_PADREGH_PAD31STRNG_Msk (0x4000000UL) /*!< PAD31STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD31INPEN_Pos (25UL) /*!< PAD31INPEN (Bit 25) */ +#define GPIO_PADREGH_PAD31INPEN_Msk (0x2000000UL) /*!< PAD31INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD31PULL_Pos (24UL) /*!< PAD31PULL (Bit 24) */ +#define GPIO_PADREGH_PAD31PULL_Msk (0x1000000UL) /*!< PAD31PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30FNCSEL_Pos (19UL) /*!< PAD30FNCSEL (Bit 19) */ +#define GPIO_PADREGH_PAD30FNCSEL_Msk (0x380000UL) /*!< PAD30FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD30STRNG_Pos (18UL) /*!< PAD30STRNG (Bit 18) */ +#define GPIO_PADREGH_PAD30STRNG_Msk (0x40000UL) /*!< PAD30STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30INPEN_Pos (17UL) /*!< PAD30INPEN (Bit 17) */ +#define GPIO_PADREGH_PAD30INPEN_Msk (0x20000UL) /*!< PAD30INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30PULL_Pos (16UL) /*!< PAD30PULL (Bit 16) */ +#define GPIO_PADREGH_PAD30PULL_Msk (0x10000UL) /*!< PAD30PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29FNCSEL_Pos (11UL) /*!< PAD29FNCSEL (Bit 11) */ +#define GPIO_PADREGH_PAD29FNCSEL_Msk (0x3800UL) /*!< PAD29FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD29STRNG_Pos (10UL) /*!< PAD29STRNG (Bit 10) */ +#define GPIO_PADREGH_PAD29STRNG_Msk (0x400UL) /*!< PAD29STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29INPEN_Pos (9UL) /*!< PAD29INPEN (Bit 9) */ +#define GPIO_PADREGH_PAD29INPEN_Msk (0x200UL) /*!< PAD29INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29PULL_Pos (8UL) /*!< PAD29PULL (Bit 8) */ +#define GPIO_PADREGH_PAD29PULL_Msk (0x100UL) /*!< PAD29PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28FNCSEL_Pos (3UL) /*!< PAD28FNCSEL (Bit 3) */ +#define GPIO_PADREGH_PAD28FNCSEL_Msk (0x38UL) /*!< PAD28FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD28STRNG_Pos (2UL) /*!< PAD28STRNG (Bit 2) */ +#define GPIO_PADREGH_PAD28STRNG_Msk (0x4UL) /*!< PAD28STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28INPEN_Pos (1UL) /*!< PAD28INPEN (Bit 1) */ +#define GPIO_PADREGH_PAD28INPEN_Msk (0x2UL) /*!< PAD28INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28PULL_Pos (0UL) /*!< PAD28PULL (Bit 0) */ +#define GPIO_PADREGH_PAD28PULL_Msk (0x1UL) /*!< PAD28PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGI ======================================================== */ +#define GPIO_PADREGI_PAD35FNCSEL_Pos (27UL) /*!< PAD35FNCSEL (Bit 27) */ +#define GPIO_PADREGI_PAD35FNCSEL_Msk (0x38000000UL) /*!< PAD35FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD35STRNG_Pos (26UL) /*!< PAD35STRNG (Bit 26) */ +#define GPIO_PADREGI_PAD35STRNG_Msk (0x4000000UL) /*!< PAD35STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD35INPEN_Pos (25UL) /*!< PAD35INPEN (Bit 25) */ +#define GPIO_PADREGI_PAD35INPEN_Msk (0x2000000UL) /*!< PAD35INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD35PULL_Pos (24UL) /*!< PAD35PULL (Bit 24) */ +#define GPIO_PADREGI_PAD35PULL_Msk (0x1000000UL) /*!< PAD35PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34FNCSEL_Pos (19UL) /*!< PAD34FNCSEL (Bit 19) */ +#define GPIO_PADREGI_PAD34FNCSEL_Msk (0x380000UL) /*!< PAD34FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD34STRNG_Pos (18UL) /*!< PAD34STRNG (Bit 18) */ +#define GPIO_PADREGI_PAD34STRNG_Msk (0x40000UL) /*!< PAD34STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34INPEN_Pos (17UL) /*!< PAD34INPEN (Bit 17) */ +#define GPIO_PADREGI_PAD34INPEN_Msk (0x20000UL) /*!< PAD34INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34PULL_Pos (16UL) /*!< PAD34PULL (Bit 16) */ +#define GPIO_PADREGI_PAD34PULL_Msk (0x10000UL) /*!< PAD34PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33FNCSEL_Pos (11UL) /*!< PAD33FNCSEL (Bit 11) */ +#define GPIO_PADREGI_PAD33FNCSEL_Msk (0x3800UL) /*!< PAD33FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD33STRNG_Pos (10UL) /*!< PAD33STRNG (Bit 10) */ +#define GPIO_PADREGI_PAD33STRNG_Msk (0x400UL) /*!< PAD33STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33INPEN_Pos (9UL) /*!< PAD33INPEN (Bit 9) */ +#define GPIO_PADREGI_PAD33INPEN_Msk (0x200UL) /*!< PAD33INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33PULL_Pos (8UL) /*!< PAD33PULL (Bit 8) */ +#define GPIO_PADREGI_PAD33PULL_Msk (0x100UL) /*!< PAD33PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32FNCSEL_Pos (3UL) /*!< PAD32FNCSEL (Bit 3) */ +#define GPIO_PADREGI_PAD32FNCSEL_Msk (0x38UL) /*!< PAD32FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD32STRNG_Pos (2UL) /*!< PAD32STRNG (Bit 2) */ +#define GPIO_PADREGI_PAD32STRNG_Msk (0x4UL) /*!< PAD32STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32INPEN_Pos (1UL) /*!< PAD32INPEN (Bit 1) */ +#define GPIO_PADREGI_PAD32INPEN_Msk (0x2UL) /*!< PAD32INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32PULL_Pos (0UL) /*!< PAD32PULL (Bit 0) */ +#define GPIO_PADREGI_PAD32PULL_Msk (0x1UL) /*!< PAD32PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGJ ======================================================== */ +#define GPIO_PADREGJ_PAD39RSEL_Pos (30UL) /*!< PAD39RSEL (Bit 30) */ +#define GPIO_PADREGJ_PAD39RSEL_Msk (0xc0000000UL) /*!< PAD39RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGJ_PAD39FNCSEL_Pos (27UL) /*!< PAD39FNCSEL (Bit 27) */ +#define GPIO_PADREGJ_PAD39FNCSEL_Msk (0x38000000UL) /*!< PAD39FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD39STRNG_Pos (26UL) /*!< PAD39STRNG (Bit 26) */ +#define GPIO_PADREGJ_PAD39STRNG_Msk (0x4000000UL) /*!< PAD39STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD39INPEN_Pos (25UL) /*!< PAD39INPEN (Bit 25) */ +#define GPIO_PADREGJ_PAD39INPEN_Msk (0x2000000UL) /*!< PAD39INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD39PULL_Pos (24UL) /*!< PAD39PULL (Bit 24) */ +#define GPIO_PADREGJ_PAD39PULL_Msk (0x1000000UL) /*!< PAD39PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38FNCSEL_Pos (19UL) /*!< PAD38FNCSEL (Bit 19) */ +#define GPIO_PADREGJ_PAD38FNCSEL_Msk (0x380000UL) /*!< PAD38FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD38STRNG_Pos (18UL) /*!< PAD38STRNG (Bit 18) */ +#define GPIO_PADREGJ_PAD38STRNG_Msk (0x40000UL) /*!< PAD38STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38INPEN_Pos (17UL) /*!< PAD38INPEN (Bit 17) */ +#define GPIO_PADREGJ_PAD38INPEN_Msk (0x20000UL) /*!< PAD38INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38PULL_Pos (16UL) /*!< PAD38PULL (Bit 16) */ +#define GPIO_PADREGJ_PAD38PULL_Msk (0x10000UL) /*!< PAD38PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37FNCSEL_Pos (11UL) /*!< PAD37FNCSEL (Bit 11) */ +#define GPIO_PADREGJ_PAD37FNCSEL_Msk (0x3800UL) /*!< PAD37FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD37STRNG_Pos (10UL) /*!< PAD37STRNG (Bit 10) */ +#define GPIO_PADREGJ_PAD37STRNG_Msk (0x400UL) /*!< PAD37STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37INPEN_Pos (9UL) /*!< PAD37INPEN (Bit 9) */ +#define GPIO_PADREGJ_PAD37INPEN_Msk (0x200UL) /*!< PAD37INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37PULL_Pos (8UL) /*!< PAD37PULL (Bit 8) */ +#define GPIO_PADREGJ_PAD37PULL_Msk (0x100UL) /*!< PAD37PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36FNCSEL_Pos (3UL) /*!< PAD36FNCSEL (Bit 3) */ +#define GPIO_PADREGJ_PAD36FNCSEL_Msk (0x38UL) /*!< PAD36FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD36STRNG_Pos (2UL) /*!< PAD36STRNG (Bit 2) */ +#define GPIO_PADREGJ_PAD36STRNG_Msk (0x4UL) /*!< PAD36STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36INPEN_Pos (1UL) /*!< PAD36INPEN (Bit 1) */ +#define GPIO_PADREGJ_PAD36INPEN_Msk (0x2UL) /*!< PAD36INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36PULL_Pos (0UL) /*!< PAD36PULL (Bit 0) */ +#define GPIO_PADREGJ_PAD36PULL_Msk (0x1UL) /*!< PAD36PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGK ======================================================== */ +#define GPIO_PADREGK_PAD43RSEL_Pos (30UL) /*!< PAD43RSEL (Bit 30) */ +#define GPIO_PADREGK_PAD43RSEL_Msk (0xc0000000UL) /*!< PAD43RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD43FNCSEL_Pos (27UL) /*!< PAD43FNCSEL (Bit 27) */ +#define GPIO_PADREGK_PAD43FNCSEL_Msk (0x38000000UL) /*!< PAD43FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD43STRNG_Pos (26UL) /*!< PAD43STRNG (Bit 26) */ +#define GPIO_PADREGK_PAD43STRNG_Msk (0x4000000UL) /*!< PAD43STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD43INPEN_Pos (25UL) /*!< PAD43INPEN (Bit 25) */ +#define GPIO_PADREGK_PAD43INPEN_Msk (0x2000000UL) /*!< PAD43INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD43PULL_Pos (24UL) /*!< PAD43PULL (Bit 24) */ +#define GPIO_PADREGK_PAD43PULL_Msk (0x1000000UL) /*!< PAD43PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42RSEL_Pos (22UL) /*!< PAD42RSEL (Bit 22) */ +#define GPIO_PADREGK_PAD42RSEL_Msk (0xc00000UL) /*!< PAD42RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD42FNCSEL_Pos (19UL) /*!< PAD42FNCSEL (Bit 19) */ +#define GPIO_PADREGK_PAD42FNCSEL_Msk (0x380000UL) /*!< PAD42FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD42STRNG_Pos (18UL) /*!< PAD42STRNG (Bit 18) */ +#define GPIO_PADREGK_PAD42STRNG_Msk (0x40000UL) /*!< PAD42STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42INPEN_Pos (17UL) /*!< PAD42INPEN (Bit 17) */ +#define GPIO_PADREGK_PAD42INPEN_Msk (0x20000UL) /*!< PAD42INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42PULL_Pos (16UL) /*!< PAD42PULL (Bit 16) */ +#define GPIO_PADREGK_PAD42PULL_Msk (0x10000UL) /*!< PAD42PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41PWRUP_Pos (15UL) /*!< PAD41PWRUP (Bit 15) */ +#define GPIO_PADREGK_PAD41PWRUP_Msk (0x8000UL) /*!< PAD41PWRUP (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41FNCSEL_Pos (11UL) /*!< PAD41FNCSEL (Bit 11) */ +#define GPIO_PADREGK_PAD41FNCSEL_Msk (0x3800UL) /*!< PAD41FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD41STRNG_Pos (10UL) /*!< PAD41STRNG (Bit 10) */ +#define GPIO_PADREGK_PAD41STRNG_Msk (0x400UL) /*!< PAD41STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41INPEN_Pos (9UL) /*!< PAD41INPEN (Bit 9) */ +#define GPIO_PADREGK_PAD41INPEN_Msk (0x200UL) /*!< PAD41INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41PULL_Pos (8UL) /*!< PAD41PULL (Bit 8) */ +#define GPIO_PADREGK_PAD41PULL_Msk (0x100UL) /*!< PAD41PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40RSEL_Pos (6UL) /*!< PAD40RSEL (Bit 6) */ +#define GPIO_PADREGK_PAD40RSEL_Msk (0xc0UL) /*!< PAD40RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD40FNCSEL_Pos (3UL) /*!< PAD40FNCSEL (Bit 3) */ +#define GPIO_PADREGK_PAD40FNCSEL_Msk (0x38UL) /*!< PAD40FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD40STRNG_Pos (2UL) /*!< PAD40STRNG (Bit 2) */ +#define GPIO_PADREGK_PAD40STRNG_Msk (0x4UL) /*!< PAD40STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40INPEN_Pos (1UL) /*!< PAD40INPEN (Bit 1) */ +#define GPIO_PADREGK_PAD40INPEN_Msk (0x2UL) /*!< PAD40INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40PULL_Pos (0UL) /*!< PAD40PULL (Bit 0) */ +#define GPIO_PADREGK_PAD40PULL_Msk (0x1UL) /*!< PAD40PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGL ======================================================== */ +#define GPIO_PADREGL_PAD47FNCSEL_Pos (27UL) /*!< PAD47FNCSEL (Bit 27) */ +#define GPIO_PADREGL_PAD47FNCSEL_Msk (0x38000000UL) /*!< PAD47FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD47STRNG_Pos (26UL) /*!< PAD47STRNG (Bit 26) */ +#define GPIO_PADREGL_PAD47STRNG_Msk (0x4000000UL) /*!< PAD47STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD47INPEN_Pos (25UL) /*!< PAD47INPEN (Bit 25) */ +#define GPIO_PADREGL_PAD47INPEN_Msk (0x2000000UL) /*!< PAD47INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD47PULL_Pos (24UL) /*!< PAD47PULL (Bit 24) */ +#define GPIO_PADREGL_PAD47PULL_Msk (0x1000000UL) /*!< PAD47PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46FNCSEL_Pos (19UL) /*!< PAD46FNCSEL (Bit 19) */ +#define GPIO_PADREGL_PAD46FNCSEL_Msk (0x380000UL) /*!< PAD46FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD46STRNG_Pos (18UL) /*!< PAD46STRNG (Bit 18) */ +#define GPIO_PADREGL_PAD46STRNG_Msk (0x40000UL) /*!< PAD46STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46INPEN_Pos (17UL) /*!< PAD46INPEN (Bit 17) */ +#define GPIO_PADREGL_PAD46INPEN_Msk (0x20000UL) /*!< PAD46INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46PULL_Pos (16UL) /*!< PAD46PULL (Bit 16) */ +#define GPIO_PADREGL_PAD46PULL_Msk (0x10000UL) /*!< PAD46PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45FNCSEL_Pos (11UL) /*!< PAD45FNCSEL (Bit 11) */ +#define GPIO_PADREGL_PAD45FNCSEL_Msk (0x3800UL) /*!< PAD45FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD45STRNG_Pos (10UL) /*!< PAD45STRNG (Bit 10) */ +#define GPIO_PADREGL_PAD45STRNG_Msk (0x400UL) /*!< PAD45STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45INPEN_Pos (9UL) /*!< PAD45INPEN (Bit 9) */ +#define GPIO_PADREGL_PAD45INPEN_Msk (0x200UL) /*!< PAD45INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45PULL_Pos (8UL) /*!< PAD45PULL (Bit 8) */ +#define GPIO_PADREGL_PAD45PULL_Msk (0x100UL) /*!< PAD45PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44FNCSEL_Pos (3UL) /*!< PAD44FNCSEL (Bit 3) */ +#define GPIO_PADREGL_PAD44FNCSEL_Msk (0x38UL) /*!< PAD44FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD44STRNG_Pos (2UL) /*!< PAD44STRNG (Bit 2) */ +#define GPIO_PADREGL_PAD44STRNG_Msk (0x4UL) /*!< PAD44STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44INPEN_Pos (1UL) /*!< PAD44INPEN (Bit 1) */ +#define GPIO_PADREGL_PAD44INPEN_Msk (0x2UL) /*!< PAD44INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44PULL_Pos (0UL) /*!< PAD44PULL (Bit 0) */ +#define GPIO_PADREGL_PAD44PULL_Msk (0x1UL) /*!< PAD44PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGM ======================================================== */ +#define GPIO_PADREGM_PAD49RSEL_Pos (14UL) /*!< PAD49RSEL (Bit 14) */ +#define GPIO_PADREGM_PAD49RSEL_Msk (0xc000UL) /*!< PAD49RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGM_PAD49FNCSEL_Pos (11UL) /*!< PAD49FNCSEL (Bit 11) */ +#define GPIO_PADREGM_PAD49FNCSEL_Msk (0x3800UL) /*!< PAD49FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGM_PAD49STRNG_Pos (10UL) /*!< PAD49STRNG (Bit 10) */ +#define GPIO_PADREGM_PAD49STRNG_Msk (0x400UL) /*!< PAD49STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD49INPEN_Pos (9UL) /*!< PAD49INPEN (Bit 9) */ +#define GPIO_PADREGM_PAD49INPEN_Msk (0x200UL) /*!< PAD49INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD49PULL_Pos (8UL) /*!< PAD49PULL (Bit 8) */ +#define GPIO_PADREGM_PAD49PULL_Msk (0x100UL) /*!< PAD49PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48RSEL_Pos (6UL) /*!< PAD48RSEL (Bit 6) */ +#define GPIO_PADREGM_PAD48RSEL_Msk (0xc0UL) /*!< PAD48RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGM_PAD48FNCSEL_Pos (3UL) /*!< PAD48FNCSEL (Bit 3) */ +#define GPIO_PADREGM_PAD48FNCSEL_Msk (0x38UL) /*!< PAD48FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGM_PAD48STRNG_Pos (2UL) /*!< PAD48STRNG (Bit 2) */ +#define GPIO_PADREGM_PAD48STRNG_Msk (0x4UL) /*!< PAD48STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48INPEN_Pos (1UL) /*!< PAD48INPEN (Bit 1) */ +#define GPIO_PADREGM_PAD48INPEN_Msk (0x2UL) /*!< PAD48INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48PULL_Pos (0UL) /*!< PAD48PULL (Bit 0) */ +#define GPIO_PADREGM_PAD48PULL_Msk (0x1UL) /*!< PAD48PULL (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGA ========================================================== */ +#define GPIO_CFGA_GPIO7INTD_Pos (31UL) /*!< GPIO7INTD (Bit 31) */ +#define GPIO_CFGA_GPIO7INTD_Msk (0x80000000UL) /*!< GPIO7INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO7OUTCFG_Pos (29UL) /*!< GPIO7OUTCFG (Bit 29) */ +#define GPIO_CFGA_GPIO7OUTCFG_Msk (0x60000000UL) /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO7INCFG_Pos (28UL) /*!< GPIO7INCFG (Bit 28) */ +#define GPIO_CFGA_GPIO7INCFG_Msk (0x10000000UL) /*!< GPIO7INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO6INTD_Pos (27UL) /*!< GPIO6INTD (Bit 27) */ +#define GPIO_CFGA_GPIO6INTD_Msk (0x8000000UL) /*!< GPIO6INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO6OUTCFG_Pos (25UL) /*!< GPIO6OUTCFG (Bit 25) */ +#define GPIO_CFGA_GPIO6OUTCFG_Msk (0x6000000UL) /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO6INCFG_Pos (24UL) /*!< GPIO6INCFG (Bit 24) */ +#define GPIO_CFGA_GPIO6INCFG_Msk (0x1000000UL) /*!< GPIO6INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO5INTD_Pos (23UL) /*!< GPIO5INTD (Bit 23) */ +#define GPIO_CFGA_GPIO5INTD_Msk (0x800000UL) /*!< GPIO5INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO5OUTCFG_Pos (21UL) /*!< GPIO5OUTCFG (Bit 21) */ +#define GPIO_CFGA_GPIO5OUTCFG_Msk (0x600000UL) /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO5INCFG_Pos (20UL) /*!< GPIO5INCFG (Bit 20) */ +#define GPIO_CFGA_GPIO5INCFG_Msk (0x100000UL) /*!< GPIO5INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO4INTD_Pos (19UL) /*!< GPIO4INTD (Bit 19) */ +#define GPIO_CFGA_GPIO4INTD_Msk (0x80000UL) /*!< GPIO4INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO4OUTCFG_Pos (17UL) /*!< GPIO4OUTCFG (Bit 17) */ +#define GPIO_CFGA_GPIO4OUTCFG_Msk (0x60000UL) /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO4INCFG_Pos (16UL) /*!< GPIO4INCFG (Bit 16) */ +#define GPIO_CFGA_GPIO4INCFG_Msk (0x10000UL) /*!< GPIO4INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO3INTD_Pos (15UL) /*!< GPIO3INTD (Bit 15) */ +#define GPIO_CFGA_GPIO3INTD_Msk (0x8000UL) /*!< GPIO3INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO3OUTCFG_Pos (13UL) /*!< GPIO3OUTCFG (Bit 13) */ +#define GPIO_CFGA_GPIO3OUTCFG_Msk (0x6000UL) /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO3INCFG_Pos (12UL) /*!< GPIO3INCFG (Bit 12) */ +#define GPIO_CFGA_GPIO3INCFG_Msk (0x1000UL) /*!< GPIO3INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO2INTD_Pos (11UL) /*!< GPIO2INTD (Bit 11) */ +#define GPIO_CFGA_GPIO2INTD_Msk (0x800UL) /*!< GPIO2INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO2OUTCFG_Pos (9UL) /*!< GPIO2OUTCFG (Bit 9) */ +#define GPIO_CFGA_GPIO2OUTCFG_Msk (0x600UL) /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO2INCFG_Pos (8UL) /*!< GPIO2INCFG (Bit 8) */ +#define GPIO_CFGA_GPIO2INCFG_Msk (0x100UL) /*!< GPIO2INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO1INTD_Pos (7UL) /*!< GPIO1INTD (Bit 7) */ +#define GPIO_CFGA_GPIO1INTD_Msk (0x80UL) /*!< GPIO1INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO1OUTCFG_Pos (5UL) /*!< GPIO1OUTCFG (Bit 5) */ +#define GPIO_CFGA_GPIO1OUTCFG_Msk (0x60UL) /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO1INCFG_Pos (4UL) /*!< GPIO1INCFG (Bit 4) */ +#define GPIO_CFGA_GPIO1INCFG_Msk (0x10UL) /*!< GPIO1INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO0INTD_Pos (3UL) /*!< GPIO0INTD (Bit 3) */ +#define GPIO_CFGA_GPIO0INTD_Msk (0x8UL) /*!< GPIO0INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO0OUTCFG_Pos (1UL) /*!< GPIO0OUTCFG (Bit 1) */ +#define GPIO_CFGA_GPIO0OUTCFG_Msk (0x6UL) /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO0INCFG_Pos (0UL) /*!< GPIO0INCFG (Bit 0) */ +#define GPIO_CFGA_GPIO0INCFG_Msk (0x1UL) /*!< GPIO0INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGB ========================================================== */ +#define GPIO_CFGB_GPIO15INTD_Pos (31UL) /*!< GPIO15INTD (Bit 31) */ +#define GPIO_CFGB_GPIO15INTD_Msk (0x80000000UL) /*!< GPIO15INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO15OUTCFG_Pos (29UL) /*!< GPIO15OUTCFG (Bit 29) */ +#define GPIO_CFGB_GPIO15OUTCFG_Msk (0x60000000UL) /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO15INCFG_Pos (28UL) /*!< GPIO15INCFG (Bit 28) */ +#define GPIO_CFGB_GPIO15INCFG_Msk (0x10000000UL) /*!< GPIO15INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO14INTD_Pos (27UL) /*!< GPIO14INTD (Bit 27) */ +#define GPIO_CFGB_GPIO14INTD_Msk (0x8000000UL) /*!< GPIO14INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO14OUTCFG_Pos (25UL) /*!< GPIO14OUTCFG (Bit 25) */ +#define GPIO_CFGB_GPIO14OUTCFG_Msk (0x6000000UL) /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO14INCFG_Pos (24UL) /*!< GPIO14INCFG (Bit 24) */ +#define GPIO_CFGB_GPIO14INCFG_Msk (0x1000000UL) /*!< GPIO14INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO13INTD_Pos (23UL) /*!< GPIO13INTD (Bit 23) */ +#define GPIO_CFGB_GPIO13INTD_Msk (0x800000UL) /*!< GPIO13INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO13OUTCFG_Pos (21UL) /*!< GPIO13OUTCFG (Bit 21) */ +#define GPIO_CFGB_GPIO13OUTCFG_Msk (0x600000UL) /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO13INCFG_Pos (20UL) /*!< GPIO13INCFG (Bit 20) */ +#define GPIO_CFGB_GPIO13INCFG_Msk (0x100000UL) /*!< GPIO13INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO12INTD_Pos (19UL) /*!< GPIO12INTD (Bit 19) */ +#define GPIO_CFGB_GPIO12INTD_Msk (0x80000UL) /*!< GPIO12INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO12OUTCFG_Pos (17UL) /*!< GPIO12OUTCFG (Bit 17) */ +#define GPIO_CFGB_GPIO12OUTCFG_Msk (0x60000UL) /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO12INCFG_Pos (16UL) /*!< GPIO12INCFG (Bit 16) */ +#define GPIO_CFGB_GPIO12INCFG_Msk (0x10000UL) /*!< GPIO12INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO11INTD_Pos (15UL) /*!< GPIO11INTD (Bit 15) */ +#define GPIO_CFGB_GPIO11INTD_Msk (0x8000UL) /*!< GPIO11INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO11OUTCFG_Pos (13UL) /*!< GPIO11OUTCFG (Bit 13) */ +#define GPIO_CFGB_GPIO11OUTCFG_Msk (0x6000UL) /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO11INCFG_Pos (12UL) /*!< GPIO11INCFG (Bit 12) */ +#define GPIO_CFGB_GPIO11INCFG_Msk (0x1000UL) /*!< GPIO11INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO10INTD_Pos (11UL) /*!< GPIO10INTD (Bit 11) */ +#define GPIO_CFGB_GPIO10INTD_Msk (0x800UL) /*!< GPIO10INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO10OUTCFG_Pos (9UL) /*!< GPIO10OUTCFG (Bit 9) */ +#define GPIO_CFGB_GPIO10OUTCFG_Msk (0x600UL) /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO10INCFG_Pos (8UL) /*!< GPIO10INCFG (Bit 8) */ +#define GPIO_CFGB_GPIO10INCFG_Msk (0x100UL) /*!< GPIO10INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO9INTD_Pos (7UL) /*!< GPIO9INTD (Bit 7) */ +#define GPIO_CFGB_GPIO9INTD_Msk (0x80UL) /*!< GPIO9INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO9OUTCFG_Pos (5UL) /*!< GPIO9OUTCFG (Bit 5) */ +#define GPIO_CFGB_GPIO9OUTCFG_Msk (0x60UL) /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO9INCFG_Pos (4UL) /*!< GPIO9INCFG (Bit 4) */ +#define GPIO_CFGB_GPIO9INCFG_Msk (0x10UL) /*!< GPIO9INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO8INTD_Pos (3UL) /*!< GPIO8INTD (Bit 3) */ +#define GPIO_CFGB_GPIO8INTD_Msk (0x8UL) /*!< GPIO8INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO8OUTCFG_Pos (1UL) /*!< GPIO8OUTCFG (Bit 1) */ +#define GPIO_CFGB_GPIO8OUTCFG_Msk (0x6UL) /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO8INCFG_Pos (0UL) /*!< GPIO8INCFG (Bit 0) */ +#define GPIO_CFGB_GPIO8INCFG_Msk (0x1UL) /*!< GPIO8INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGC ========================================================== */ +#define GPIO_CFGC_GPIO23INTD_Pos (31UL) /*!< GPIO23INTD (Bit 31) */ +#define GPIO_CFGC_GPIO23INTD_Msk (0x80000000UL) /*!< GPIO23INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO23OUTCFG_Pos (29UL) /*!< GPIO23OUTCFG (Bit 29) */ +#define GPIO_CFGC_GPIO23OUTCFG_Msk (0x60000000UL) /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO23INCFG_Pos (28UL) /*!< GPIO23INCFG (Bit 28) */ +#define GPIO_CFGC_GPIO23INCFG_Msk (0x10000000UL) /*!< GPIO23INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO22INTD_Pos (27UL) /*!< GPIO22INTD (Bit 27) */ +#define GPIO_CFGC_GPIO22INTD_Msk (0x8000000UL) /*!< GPIO22INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO22OUTCFG_Pos (25UL) /*!< GPIO22OUTCFG (Bit 25) */ +#define GPIO_CFGC_GPIO22OUTCFG_Msk (0x6000000UL) /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO22INCFG_Pos (24UL) /*!< GPIO22INCFG (Bit 24) */ +#define GPIO_CFGC_GPIO22INCFG_Msk (0x1000000UL) /*!< GPIO22INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO21INTD_Pos (23UL) /*!< GPIO21INTD (Bit 23) */ +#define GPIO_CFGC_GPIO21INTD_Msk (0x800000UL) /*!< GPIO21INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO21OUTCFG_Pos (21UL) /*!< GPIO21OUTCFG (Bit 21) */ +#define GPIO_CFGC_GPIO21OUTCFG_Msk (0x600000UL) /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO21INCFG_Pos (20UL) /*!< GPIO21INCFG (Bit 20) */ +#define GPIO_CFGC_GPIO21INCFG_Msk (0x100000UL) /*!< GPIO21INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO20INTD_Pos (19UL) /*!< GPIO20INTD (Bit 19) */ +#define GPIO_CFGC_GPIO20INTD_Msk (0x80000UL) /*!< GPIO20INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO20OUTCFG_Pos (17UL) /*!< GPIO20OUTCFG (Bit 17) */ +#define GPIO_CFGC_GPIO20OUTCFG_Msk (0x60000UL) /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO20INCFG_Pos (16UL) /*!< GPIO20INCFG (Bit 16) */ +#define GPIO_CFGC_GPIO20INCFG_Msk (0x10000UL) /*!< GPIO20INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO19INTD_Pos (15UL) /*!< GPIO19INTD (Bit 15) */ +#define GPIO_CFGC_GPIO19INTD_Msk (0x8000UL) /*!< GPIO19INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO19OUTCFG_Pos (13UL) /*!< GPIO19OUTCFG (Bit 13) */ +#define GPIO_CFGC_GPIO19OUTCFG_Msk (0x6000UL) /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO19INCFG_Pos (12UL) /*!< GPIO19INCFG (Bit 12) */ +#define GPIO_CFGC_GPIO19INCFG_Msk (0x1000UL) /*!< GPIO19INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO18INTD_Pos (11UL) /*!< GPIO18INTD (Bit 11) */ +#define GPIO_CFGC_GPIO18INTD_Msk (0x800UL) /*!< GPIO18INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO18OUTCFG_Pos (9UL) /*!< GPIO18OUTCFG (Bit 9) */ +#define GPIO_CFGC_GPIO18OUTCFG_Msk (0x600UL) /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO18INCFG_Pos (8UL) /*!< GPIO18INCFG (Bit 8) */ +#define GPIO_CFGC_GPIO18INCFG_Msk (0x100UL) /*!< GPIO18INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO17INTD_Pos (7UL) /*!< GPIO17INTD (Bit 7) */ +#define GPIO_CFGC_GPIO17INTD_Msk (0x80UL) /*!< GPIO17INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO17OUTCFG_Pos (5UL) /*!< GPIO17OUTCFG (Bit 5) */ +#define GPIO_CFGC_GPIO17OUTCFG_Msk (0x60UL) /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO17INCFG_Pos (4UL) /*!< GPIO17INCFG (Bit 4) */ +#define GPIO_CFGC_GPIO17INCFG_Msk (0x10UL) /*!< GPIO17INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO16INTD_Pos (3UL) /*!< GPIO16INTD (Bit 3) */ +#define GPIO_CFGC_GPIO16INTD_Msk (0x8UL) /*!< GPIO16INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO16OUTCFG_Pos (1UL) /*!< GPIO16OUTCFG (Bit 1) */ +#define GPIO_CFGC_GPIO16OUTCFG_Msk (0x6UL) /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO16INCFG_Pos (0UL) /*!< GPIO16INCFG (Bit 0) */ +#define GPIO_CFGC_GPIO16INCFG_Msk (0x1UL) /*!< GPIO16INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGD ========================================================== */ +#define GPIO_CFGD_GPIO31INTD_Pos (31UL) /*!< GPIO31INTD (Bit 31) */ +#define GPIO_CFGD_GPIO31INTD_Msk (0x80000000UL) /*!< GPIO31INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO31OUTCFG_Pos (29UL) /*!< GPIO31OUTCFG (Bit 29) */ +#define GPIO_CFGD_GPIO31OUTCFG_Msk (0x60000000UL) /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO31INCFG_Pos (28UL) /*!< GPIO31INCFG (Bit 28) */ +#define GPIO_CFGD_GPIO31INCFG_Msk (0x10000000UL) /*!< GPIO31INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO30INTD_Pos (27UL) /*!< GPIO30INTD (Bit 27) */ +#define GPIO_CFGD_GPIO30INTD_Msk (0x8000000UL) /*!< GPIO30INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO30OUTCFG_Pos (25UL) /*!< GPIO30OUTCFG (Bit 25) */ +#define GPIO_CFGD_GPIO30OUTCFG_Msk (0x6000000UL) /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO30INCFG_Pos (24UL) /*!< GPIO30INCFG (Bit 24) */ +#define GPIO_CFGD_GPIO30INCFG_Msk (0x1000000UL) /*!< GPIO30INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO29INTD_Pos (23UL) /*!< GPIO29INTD (Bit 23) */ +#define GPIO_CFGD_GPIO29INTD_Msk (0x800000UL) /*!< GPIO29INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO29OUTCFG_Pos (21UL) /*!< GPIO29OUTCFG (Bit 21) */ +#define GPIO_CFGD_GPIO29OUTCFG_Msk (0x600000UL) /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO29INCFG_Pos (20UL) /*!< GPIO29INCFG (Bit 20) */ +#define GPIO_CFGD_GPIO29INCFG_Msk (0x100000UL) /*!< GPIO29INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO28INTD_Pos (19UL) /*!< GPIO28INTD (Bit 19) */ +#define GPIO_CFGD_GPIO28INTD_Msk (0x80000UL) /*!< GPIO28INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO28OUTCFG_Pos (17UL) /*!< GPIO28OUTCFG (Bit 17) */ +#define GPIO_CFGD_GPIO28OUTCFG_Msk (0x60000UL) /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO28INCFG_Pos (16UL) /*!< GPIO28INCFG (Bit 16) */ +#define GPIO_CFGD_GPIO28INCFG_Msk (0x10000UL) /*!< GPIO28INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO27INTD_Pos (15UL) /*!< GPIO27INTD (Bit 15) */ +#define GPIO_CFGD_GPIO27INTD_Msk (0x8000UL) /*!< GPIO27INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO27OUTCFG_Pos (13UL) /*!< GPIO27OUTCFG (Bit 13) */ +#define GPIO_CFGD_GPIO27OUTCFG_Msk (0x6000UL) /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO27INCFG_Pos (12UL) /*!< GPIO27INCFG (Bit 12) */ +#define GPIO_CFGD_GPIO27INCFG_Msk (0x1000UL) /*!< GPIO27INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO26INTD_Pos (11UL) /*!< GPIO26INTD (Bit 11) */ +#define GPIO_CFGD_GPIO26INTD_Msk (0x800UL) /*!< GPIO26INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO26OUTCFG_Pos (9UL) /*!< GPIO26OUTCFG (Bit 9) */ +#define GPIO_CFGD_GPIO26OUTCFG_Msk (0x600UL) /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO26INCFG_Pos (8UL) /*!< GPIO26INCFG (Bit 8) */ +#define GPIO_CFGD_GPIO26INCFG_Msk (0x100UL) /*!< GPIO26INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO25INTD_Pos (7UL) /*!< GPIO25INTD (Bit 7) */ +#define GPIO_CFGD_GPIO25INTD_Msk (0x80UL) /*!< GPIO25INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO25OUTCFG_Pos (5UL) /*!< GPIO25OUTCFG (Bit 5) */ +#define GPIO_CFGD_GPIO25OUTCFG_Msk (0x60UL) /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO25INCFG_Pos (4UL) /*!< GPIO25INCFG (Bit 4) */ +#define GPIO_CFGD_GPIO25INCFG_Msk (0x10UL) /*!< GPIO25INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO24INTD_Pos (3UL) /*!< GPIO24INTD (Bit 3) */ +#define GPIO_CFGD_GPIO24INTD_Msk (0x8UL) /*!< GPIO24INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO24OUTCFG_Pos (1UL) /*!< GPIO24OUTCFG (Bit 1) */ +#define GPIO_CFGD_GPIO24OUTCFG_Msk (0x6UL) /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO24INCFG_Pos (0UL) /*!< GPIO24INCFG (Bit 0) */ +#define GPIO_CFGD_GPIO24INCFG_Msk (0x1UL) /*!< GPIO24INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGE ========================================================== */ +#define GPIO_CFGE_GPIO39INTD_Pos (31UL) /*!< GPIO39INTD (Bit 31) */ +#define GPIO_CFGE_GPIO39INTD_Msk (0x80000000UL) /*!< GPIO39INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO39OUTCFG_Pos (29UL) /*!< GPIO39OUTCFG (Bit 29) */ +#define GPIO_CFGE_GPIO39OUTCFG_Msk (0x60000000UL) /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO39INCFG_Pos (28UL) /*!< GPIO39INCFG (Bit 28) */ +#define GPIO_CFGE_GPIO39INCFG_Msk (0x10000000UL) /*!< GPIO39INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO38INTD_Pos (27UL) /*!< GPIO38INTD (Bit 27) */ +#define GPIO_CFGE_GPIO38INTD_Msk (0x8000000UL) /*!< GPIO38INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO38OUTCFG_Pos (25UL) /*!< GPIO38OUTCFG (Bit 25) */ +#define GPIO_CFGE_GPIO38OUTCFG_Msk (0x6000000UL) /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO38INCFG_Pos (24UL) /*!< GPIO38INCFG (Bit 24) */ +#define GPIO_CFGE_GPIO38INCFG_Msk (0x1000000UL) /*!< GPIO38INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO37INTD_Pos (23UL) /*!< GPIO37INTD (Bit 23) */ +#define GPIO_CFGE_GPIO37INTD_Msk (0x800000UL) /*!< GPIO37INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO37OUTCFG_Pos (21UL) /*!< GPIO37OUTCFG (Bit 21) */ +#define GPIO_CFGE_GPIO37OUTCFG_Msk (0x600000UL) /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO37INCFG_Pos (20UL) /*!< GPIO37INCFG (Bit 20) */ +#define GPIO_CFGE_GPIO37INCFG_Msk (0x100000UL) /*!< GPIO37INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO36INTD_Pos (19UL) /*!< GPIO36INTD (Bit 19) */ +#define GPIO_CFGE_GPIO36INTD_Msk (0x80000UL) /*!< GPIO36INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO36OUTCFG_Pos (17UL) /*!< GPIO36OUTCFG (Bit 17) */ +#define GPIO_CFGE_GPIO36OUTCFG_Msk (0x60000UL) /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO36INCFG_Pos (16UL) /*!< GPIO36INCFG (Bit 16) */ +#define GPIO_CFGE_GPIO36INCFG_Msk (0x10000UL) /*!< GPIO36INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO35INTD_Pos (15UL) /*!< GPIO35INTD (Bit 15) */ +#define GPIO_CFGE_GPIO35INTD_Msk (0x8000UL) /*!< GPIO35INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO35OUTCFG_Pos (13UL) /*!< GPIO35OUTCFG (Bit 13) */ +#define GPIO_CFGE_GPIO35OUTCFG_Msk (0x6000UL) /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO35INCFG_Pos (12UL) /*!< GPIO35INCFG (Bit 12) */ +#define GPIO_CFGE_GPIO35INCFG_Msk (0x1000UL) /*!< GPIO35INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO34INTD_Pos (11UL) /*!< GPIO34INTD (Bit 11) */ +#define GPIO_CFGE_GPIO34INTD_Msk (0x800UL) /*!< GPIO34INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO34OUTCFG_Pos (9UL) /*!< GPIO34OUTCFG (Bit 9) */ +#define GPIO_CFGE_GPIO34OUTCFG_Msk (0x600UL) /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO34INCFG_Pos (8UL) /*!< GPIO34INCFG (Bit 8) */ +#define GPIO_CFGE_GPIO34INCFG_Msk (0x100UL) /*!< GPIO34INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO33INTD_Pos (7UL) /*!< GPIO33INTD (Bit 7) */ +#define GPIO_CFGE_GPIO33INTD_Msk (0x80UL) /*!< GPIO33INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO33OUTCFG_Pos (5UL) /*!< GPIO33OUTCFG (Bit 5) */ +#define GPIO_CFGE_GPIO33OUTCFG_Msk (0x60UL) /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO33INCFG_Pos (4UL) /*!< GPIO33INCFG (Bit 4) */ +#define GPIO_CFGE_GPIO33INCFG_Msk (0x10UL) /*!< GPIO33INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO32INTD_Pos (3UL) /*!< GPIO32INTD (Bit 3) */ +#define GPIO_CFGE_GPIO32INTD_Msk (0x8UL) /*!< GPIO32INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO32OUTCFG_Pos (1UL) /*!< GPIO32OUTCFG (Bit 1) */ +#define GPIO_CFGE_GPIO32OUTCFG_Msk (0x6UL) /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO32INCFG_Pos (0UL) /*!< GPIO32INCFG (Bit 0) */ +#define GPIO_CFGE_GPIO32INCFG_Msk (0x1UL) /*!< GPIO32INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGF ========================================================== */ +#define GPIO_CFGF_GPIO47INTD_Pos (31UL) /*!< GPIO47INTD (Bit 31) */ +#define GPIO_CFGF_GPIO47INTD_Msk (0x80000000UL) /*!< GPIO47INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO47OUTCFG_Pos (29UL) /*!< GPIO47OUTCFG (Bit 29) */ +#define GPIO_CFGF_GPIO47OUTCFG_Msk (0x60000000UL) /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO47INCFG_Pos (28UL) /*!< GPIO47INCFG (Bit 28) */ +#define GPIO_CFGF_GPIO47INCFG_Msk (0x10000000UL) /*!< GPIO47INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO46INTD_Pos (27UL) /*!< GPIO46INTD (Bit 27) */ +#define GPIO_CFGF_GPIO46INTD_Msk (0x8000000UL) /*!< GPIO46INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO46OUTCFG_Pos (25UL) /*!< GPIO46OUTCFG (Bit 25) */ +#define GPIO_CFGF_GPIO46OUTCFG_Msk (0x6000000UL) /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO46INCFG_Pos (24UL) /*!< GPIO46INCFG (Bit 24) */ +#define GPIO_CFGF_GPIO46INCFG_Msk (0x1000000UL) /*!< GPIO46INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO45INTD_Pos (23UL) /*!< GPIO45INTD (Bit 23) */ +#define GPIO_CFGF_GPIO45INTD_Msk (0x800000UL) /*!< GPIO45INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO45OUTCFG_Pos (21UL) /*!< GPIO45OUTCFG (Bit 21) */ +#define GPIO_CFGF_GPIO45OUTCFG_Msk (0x600000UL) /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO45INCFG_Pos (20UL) /*!< GPIO45INCFG (Bit 20) */ +#define GPIO_CFGF_GPIO45INCFG_Msk (0x100000UL) /*!< GPIO45INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO44INTD_Pos (19UL) /*!< GPIO44INTD (Bit 19) */ +#define GPIO_CFGF_GPIO44INTD_Msk (0x80000UL) /*!< GPIO44INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO44OUTCFG_Pos (17UL) /*!< GPIO44OUTCFG (Bit 17) */ +#define GPIO_CFGF_GPIO44OUTCFG_Msk (0x60000UL) /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO44INCFG_Pos (16UL) /*!< GPIO44INCFG (Bit 16) */ +#define GPIO_CFGF_GPIO44INCFG_Msk (0x10000UL) /*!< GPIO44INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO43INTD_Pos (15UL) /*!< GPIO43INTD (Bit 15) */ +#define GPIO_CFGF_GPIO43INTD_Msk (0x8000UL) /*!< GPIO43INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO43OUTCFG_Pos (13UL) /*!< GPIO43OUTCFG (Bit 13) */ +#define GPIO_CFGF_GPIO43OUTCFG_Msk (0x6000UL) /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO43INCFG_Pos (12UL) /*!< GPIO43INCFG (Bit 12) */ +#define GPIO_CFGF_GPIO43INCFG_Msk (0x1000UL) /*!< GPIO43INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO42INTD_Pos (11UL) /*!< GPIO42INTD (Bit 11) */ +#define GPIO_CFGF_GPIO42INTD_Msk (0x800UL) /*!< GPIO42INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO42OUTCFG_Pos (9UL) /*!< GPIO42OUTCFG (Bit 9) */ +#define GPIO_CFGF_GPIO42OUTCFG_Msk (0x600UL) /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO42INCFG_Pos (8UL) /*!< GPIO42INCFG (Bit 8) */ +#define GPIO_CFGF_GPIO42INCFG_Msk (0x100UL) /*!< GPIO42INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO41INTD_Pos (7UL) /*!< GPIO41INTD (Bit 7) */ +#define GPIO_CFGF_GPIO41INTD_Msk (0x80UL) /*!< GPIO41INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO41OUTCFG_Pos (5UL) /*!< GPIO41OUTCFG (Bit 5) */ +#define GPIO_CFGF_GPIO41OUTCFG_Msk (0x60UL) /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO41INCFG_Pos (4UL) /*!< GPIO41INCFG (Bit 4) */ +#define GPIO_CFGF_GPIO41INCFG_Msk (0x10UL) /*!< GPIO41INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO40INTD_Pos (3UL) /*!< GPIO40INTD (Bit 3) */ +#define GPIO_CFGF_GPIO40INTD_Msk (0x8UL) /*!< GPIO40INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO40OUTCFG_Pos (1UL) /*!< GPIO40OUTCFG (Bit 1) */ +#define GPIO_CFGF_GPIO40OUTCFG_Msk (0x6UL) /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO40INCFG_Pos (0UL) /*!< GPIO40INCFG (Bit 0) */ +#define GPIO_CFGF_GPIO40INCFG_Msk (0x1UL) /*!< GPIO40INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGG ========================================================== */ +#define GPIO_CFGG_GPIO49INTD_Pos (7UL) /*!< GPIO49INTD (Bit 7) */ +#define GPIO_CFGG_GPIO49INTD_Msk (0x80UL) /*!< GPIO49INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO49OUTCFG_Pos (5UL) /*!< GPIO49OUTCFG (Bit 5) */ +#define GPIO_CFGG_GPIO49OUTCFG_Msk (0x60UL) /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGG_GPIO49INCFG_Pos (4UL) /*!< GPIO49INCFG (Bit 4) */ +#define GPIO_CFGG_GPIO49INCFG_Msk (0x10UL) /*!< GPIO49INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO48INTD_Pos (3UL) /*!< GPIO48INTD (Bit 3) */ +#define GPIO_CFGG_GPIO48INTD_Msk (0x8UL) /*!< GPIO48INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO48OUTCFG_Pos (1UL) /*!< GPIO48OUTCFG (Bit 1) */ +#define GPIO_CFGG_GPIO48OUTCFG_Msk (0x6UL) /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGG_GPIO48INCFG_Pos (0UL) /*!< GPIO48INCFG (Bit 0) */ +#define GPIO_CFGG_GPIO48INCFG_Msk (0x1UL) /*!< GPIO48INCFG (Bitfield-Mask: 0x01) */ +/* ======================================================== PADKEY ========================================================= */ +#define GPIO_PADKEY_PADKEY_Pos (0UL) /*!< PADKEY (Bit 0) */ +#define GPIO_PADKEY_PADKEY_Msk (0xffffffffUL) /*!< PADKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RDA ========================================================== */ +#define GPIO_RDA_RDA_Pos (0UL) /*!< RDA (Bit 0) */ +#define GPIO_RDA_RDA_Msk (0xffffffffUL) /*!< RDA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RDB ========================================================== */ +#define GPIO_RDB_RDB_Pos (0UL) /*!< RDB (Bit 0) */ +#define GPIO_RDB_RDB_Msk (0x3ffffUL) /*!< RDB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== WTA ========================================================== */ +#define GPIO_WTA_WTA_Pos (0UL) /*!< WTA (Bit 0) */ +#define GPIO_WTA_WTA_Msk (0xffffffffUL) /*!< WTA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== WTB ========================================================== */ +#define GPIO_WTB_WTB_Pos (0UL) /*!< WTB (Bit 0) */ +#define GPIO_WTB_WTB_Msk (0x3ffffUL) /*!< WTB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= WTSA ========================================================== */ +#define GPIO_WTSA_WTSA_Pos (0UL) /*!< WTSA (Bit 0) */ +#define GPIO_WTSA_WTSA_Msk (0xffffffffUL) /*!< WTSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= WTSB ========================================================== */ +#define GPIO_WTSB_WTSB_Pos (0UL) /*!< WTSB (Bit 0) */ +#define GPIO_WTSB_WTSB_Msk (0x3ffffUL) /*!< WTSB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= WTCA ========================================================== */ +#define GPIO_WTCA_WTCA_Pos (0UL) /*!< WTCA (Bit 0) */ +#define GPIO_WTCA_WTCA_Msk (0xffffffffUL) /*!< WTCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= WTCB ========================================================== */ +#define GPIO_WTCB_WTCB_Pos (0UL) /*!< WTCB (Bit 0) */ +#define GPIO_WTCB_WTCB_Msk (0x3ffffUL) /*!< WTCB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== ENA ========================================================== */ +#define GPIO_ENA_ENA_Pos (0UL) /*!< ENA (Bit 0) */ +#define GPIO_ENA_ENA_Msk (0xffffffffUL) /*!< ENA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ENB ========================================================== */ +#define GPIO_ENB_ENB_Pos (0UL) /*!< ENB (Bit 0) */ +#define GPIO_ENB_ENB_Msk (0x3ffffUL) /*!< ENB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= ENSA ========================================================== */ +#define GPIO_ENSA_ENSA_Pos (0UL) /*!< ENSA (Bit 0) */ +#define GPIO_ENSA_ENSA_Msk (0xffffffffUL) /*!< ENSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ENSB ========================================================== */ +#define GPIO_ENSB_ENSB_Pos (0UL) /*!< ENSB (Bit 0) */ +#define GPIO_ENSB_ENSB_Msk (0x3ffffUL) /*!< ENSB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= ENCA ========================================================== */ +#define GPIO_ENCA_ENCA_Pos (0UL) /*!< ENCA (Bit 0) */ +#define GPIO_ENCA_ENCA_Msk (0xffffffffUL) /*!< ENCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ENCB ========================================================== */ +#define GPIO_ENCB_ENCB_Pos (0UL) /*!< ENCB (Bit 0) */ +#define GPIO_ENCB_ENCB_Msk (0x3ffffUL) /*!< ENCB (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== STMRCAP ======================================================== */ +#define GPIO_STMRCAP_STPOL3_Pos (30UL) /*!< STPOL3 (Bit 30) */ +#define GPIO_STMRCAP_STPOL3_Msk (0x40000000UL) /*!< STPOL3 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL3_Pos (24UL) /*!< STSEL3 (Bit 24) */ +#define GPIO_STMRCAP_STSEL3_Msk (0x3f000000UL) /*!< STSEL3 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL2_Pos (22UL) /*!< STPOL2 (Bit 22) */ +#define GPIO_STMRCAP_STPOL2_Msk (0x400000UL) /*!< STPOL2 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL2_Pos (16UL) /*!< STSEL2 (Bit 16) */ +#define GPIO_STMRCAP_STSEL2_Msk (0x3f0000UL) /*!< STSEL2 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL1_Pos (14UL) /*!< STPOL1 (Bit 14) */ +#define GPIO_STMRCAP_STPOL1_Msk (0x4000UL) /*!< STPOL1 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL1_Pos (8UL) /*!< STSEL1 (Bit 8) */ +#define GPIO_STMRCAP_STSEL1_Msk (0x3f00UL) /*!< STSEL1 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL0_Pos (6UL) /*!< STPOL0 (Bit 6) */ +#define GPIO_STMRCAP_STPOL0_Msk (0x40UL) /*!< STPOL0 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL0_Pos (0UL) /*!< STSEL0 (Bit 0) */ +#define GPIO_STMRCAP_STSEL0_Msk (0x3fUL) /*!< STSEL0 (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM0IRQ ======================================================== */ +#define GPIO_IOM0IRQ_IOM0IRQ_Pos (0UL) /*!< IOM0IRQ (Bit 0) */ +#define GPIO_IOM0IRQ_IOM0IRQ_Msk (0x3fUL) /*!< IOM0IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM1IRQ ======================================================== */ +#define GPIO_IOM1IRQ_IOM1IRQ_Pos (0UL) /*!< IOM1IRQ (Bit 0) */ +#define GPIO_IOM1IRQ_IOM1IRQ_Msk (0x3fUL) /*!< IOM1IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM2IRQ ======================================================== */ +#define GPIO_IOM2IRQ_IOM2IRQ_Pos (0UL) /*!< IOM2IRQ (Bit 0) */ +#define GPIO_IOM2IRQ_IOM2IRQ_Msk (0x3fUL) /*!< IOM2IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM3IRQ ======================================================== */ +#define GPIO_IOM3IRQ_IOM3IRQ_Pos (0UL) /*!< IOM3IRQ (Bit 0) */ +#define GPIO_IOM3IRQ_IOM3IRQ_Msk (0x3fUL) /*!< IOM3IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM4IRQ ======================================================== */ +#define GPIO_IOM4IRQ_IOM4IRQ_Pos (0UL) /*!< IOM4IRQ (Bit 0) */ +#define GPIO_IOM4IRQ_IOM4IRQ_Msk (0x3fUL) /*!< IOM4IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM5IRQ ======================================================== */ +#define GPIO_IOM5IRQ_IOM5IRQ_Pos (0UL) /*!< IOM5IRQ (Bit 0) */ +#define GPIO_IOM5IRQ_IOM5IRQ_Msk (0x3fUL) /*!< IOM5IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================= LOOPBACK ======================================================== */ +#define GPIO_LOOPBACK_LOOPBACK_Pos (0UL) /*!< LOOPBACK (Bit 0) */ +#define GPIO_LOOPBACK_LOOPBACK_Msk (0x7UL) /*!< LOOPBACK (Bitfield-Mask: 0x07) */ +/* ======================================================== GPIOOBS ======================================================== */ +#define GPIO_GPIOOBS_OBS_DATA_Pos (0UL) /*!< OBS_DATA (Bit 0) */ +#define GPIO_GPIOOBS_OBS_DATA_Msk (0xffffUL) /*!< OBS_DATA (Bitfield-Mask: 0xffff) */ +/* ====================================================== ALTPADCFGA ======================================================= */ +#define GPIO_ALTPADCFGA_PAD3_SR_Pos (28UL) /*!< PAD3_SR (Bit 28) */ +#define GPIO_ALTPADCFGA_PAD3_SR_Msk (0x10000000UL) /*!< PAD3_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD3_DS1_Pos (24UL) /*!< PAD3_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGA_PAD3_DS1_Msk (0x1000000UL) /*!< PAD3_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD2_SR_Pos (20UL) /*!< PAD2_SR (Bit 20) */ +#define GPIO_ALTPADCFGA_PAD2_SR_Msk (0x100000UL) /*!< PAD2_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD2_DS1_Pos (16UL) /*!< PAD2_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGA_PAD2_DS1_Msk (0x10000UL) /*!< PAD2_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD1_SR_Pos (12UL) /*!< PAD1_SR (Bit 12) */ +#define GPIO_ALTPADCFGA_PAD1_SR_Msk (0x1000UL) /*!< PAD1_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD1_DS1_Pos (8UL) /*!< PAD1_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGA_PAD1_DS1_Msk (0x100UL) /*!< PAD1_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD0_SR_Pos (4UL) /*!< PAD0_SR (Bit 4) */ +#define GPIO_ALTPADCFGA_PAD0_SR_Msk (0x10UL) /*!< PAD0_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD0_DS1_Pos (0UL) /*!< PAD0_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGA_PAD0_DS1_Msk (0x1UL) /*!< PAD0_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGB ======================================================= */ +#define GPIO_ALTPADCFGB_PAD7_SR_Pos (28UL) /*!< PAD7_SR (Bit 28) */ +#define GPIO_ALTPADCFGB_PAD7_SR_Msk (0x10000000UL) /*!< PAD7_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD7_DS1_Pos (24UL) /*!< PAD7_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGB_PAD7_DS1_Msk (0x1000000UL) /*!< PAD7_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD6_SR_Pos (20UL) /*!< PAD6_SR (Bit 20) */ +#define GPIO_ALTPADCFGB_PAD6_SR_Msk (0x100000UL) /*!< PAD6_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD6_DS1_Pos (16UL) /*!< PAD6_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGB_PAD6_DS1_Msk (0x10000UL) /*!< PAD6_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD5_SR_Pos (12UL) /*!< PAD5_SR (Bit 12) */ +#define GPIO_ALTPADCFGB_PAD5_SR_Msk (0x1000UL) /*!< PAD5_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD5_DS1_Pos (8UL) /*!< PAD5_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGB_PAD5_DS1_Msk (0x100UL) /*!< PAD5_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD4_SR_Pos (4UL) /*!< PAD4_SR (Bit 4) */ +#define GPIO_ALTPADCFGB_PAD4_SR_Msk (0x10UL) /*!< PAD4_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD4_DS1_Pos (0UL) /*!< PAD4_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGB_PAD4_DS1_Msk (0x1UL) /*!< PAD4_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGC ======================================================= */ +#define GPIO_ALTPADCFGC_PAD11_SR_Pos (28UL) /*!< PAD11_SR (Bit 28) */ +#define GPIO_ALTPADCFGC_PAD11_SR_Msk (0x10000000UL) /*!< PAD11_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD11_DS1_Pos (24UL) /*!< PAD11_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGC_PAD11_DS1_Msk (0x1000000UL) /*!< PAD11_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD10_SR_Pos (20UL) /*!< PAD10_SR (Bit 20) */ +#define GPIO_ALTPADCFGC_PAD10_SR_Msk (0x100000UL) /*!< PAD10_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD10_DS1_Pos (16UL) /*!< PAD10_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGC_PAD10_DS1_Msk (0x10000UL) /*!< PAD10_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD9_SR_Pos (12UL) /*!< PAD9_SR (Bit 12) */ +#define GPIO_ALTPADCFGC_PAD9_SR_Msk (0x1000UL) /*!< PAD9_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD9_DS1_Pos (8UL) /*!< PAD9_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGC_PAD9_DS1_Msk (0x100UL) /*!< PAD9_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD8_SR_Pos (4UL) /*!< PAD8_SR (Bit 4) */ +#define GPIO_ALTPADCFGC_PAD8_SR_Msk (0x10UL) /*!< PAD8_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD8_DS1_Pos (0UL) /*!< PAD8_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGC_PAD8_DS1_Msk (0x1UL) /*!< PAD8_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGD ======================================================= */ +#define GPIO_ALTPADCFGD_PAD15_SR_Pos (28UL) /*!< PAD15_SR (Bit 28) */ +#define GPIO_ALTPADCFGD_PAD15_SR_Msk (0x10000000UL) /*!< PAD15_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD15_DS1_Pos (24UL) /*!< PAD15_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGD_PAD15_DS1_Msk (0x1000000UL) /*!< PAD15_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD14_SR_Pos (20UL) /*!< PAD14_SR (Bit 20) */ +#define GPIO_ALTPADCFGD_PAD14_SR_Msk (0x100000UL) /*!< PAD14_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD14_DS1_Pos (16UL) /*!< PAD14_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGD_PAD14_DS1_Msk (0x10000UL) /*!< PAD14_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD13_SR_Pos (12UL) /*!< PAD13_SR (Bit 12) */ +#define GPIO_ALTPADCFGD_PAD13_SR_Msk (0x1000UL) /*!< PAD13_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD13_DS1_Pos (8UL) /*!< PAD13_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGD_PAD13_DS1_Msk (0x100UL) /*!< PAD13_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD12_SR_Pos (4UL) /*!< PAD12_SR (Bit 4) */ +#define GPIO_ALTPADCFGD_PAD12_SR_Msk (0x10UL) /*!< PAD12_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD12_DS1_Pos (0UL) /*!< PAD12_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGD_PAD12_DS1_Msk (0x1UL) /*!< PAD12_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGE ======================================================= */ +#define GPIO_ALTPADCFGE_PAD19_SR_Pos (28UL) /*!< PAD19_SR (Bit 28) */ +#define GPIO_ALTPADCFGE_PAD19_SR_Msk (0x10000000UL) /*!< PAD19_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD19_DS1_Pos (24UL) /*!< PAD19_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGE_PAD19_DS1_Msk (0x1000000UL) /*!< PAD19_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD18_SR_Pos (20UL) /*!< PAD18_SR (Bit 20) */ +#define GPIO_ALTPADCFGE_PAD18_SR_Msk (0x100000UL) /*!< PAD18_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD18_DS1_Pos (16UL) /*!< PAD18_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGE_PAD18_DS1_Msk (0x10000UL) /*!< PAD18_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD17_SR_Pos (12UL) /*!< PAD17_SR (Bit 12) */ +#define GPIO_ALTPADCFGE_PAD17_SR_Msk (0x1000UL) /*!< PAD17_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD17_DS1_Pos (8UL) /*!< PAD17_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGE_PAD17_DS1_Msk (0x100UL) /*!< PAD17_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD16_SR_Pos (4UL) /*!< PAD16_SR (Bit 4) */ +#define GPIO_ALTPADCFGE_PAD16_SR_Msk (0x10UL) /*!< PAD16_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD16_DS1_Pos (0UL) /*!< PAD16_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGE_PAD16_DS1_Msk (0x1UL) /*!< PAD16_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGF ======================================================= */ +#define GPIO_ALTPADCFGF_PAD23_SR_Pos (28UL) /*!< PAD23_SR (Bit 28) */ +#define GPIO_ALTPADCFGF_PAD23_SR_Msk (0x10000000UL) /*!< PAD23_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD23_DS1_Pos (24UL) /*!< PAD23_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGF_PAD23_DS1_Msk (0x1000000UL) /*!< PAD23_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD22_SR_Pos (20UL) /*!< PAD22_SR (Bit 20) */ +#define GPIO_ALTPADCFGF_PAD22_SR_Msk (0x100000UL) /*!< PAD22_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD22_DS1_Pos (16UL) /*!< PAD22_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGF_PAD22_DS1_Msk (0x10000UL) /*!< PAD22_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD21_SR_Pos (12UL) /*!< PAD21_SR (Bit 12) */ +#define GPIO_ALTPADCFGF_PAD21_SR_Msk (0x1000UL) /*!< PAD21_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD21_DS1_Pos (8UL) /*!< PAD21_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGF_PAD21_DS1_Msk (0x100UL) /*!< PAD21_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD20_SR_Pos (4UL) /*!< PAD20_SR (Bit 4) */ +#define GPIO_ALTPADCFGF_PAD20_SR_Msk (0x10UL) /*!< PAD20_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD20_DS1_Pos (0UL) /*!< PAD20_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGF_PAD20_DS1_Msk (0x1UL) /*!< PAD20_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGG ======================================================= */ +#define GPIO_ALTPADCFGG_PAD27_SR_Pos (28UL) /*!< PAD27_SR (Bit 28) */ +#define GPIO_ALTPADCFGG_PAD27_SR_Msk (0x10000000UL) /*!< PAD27_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD27_DS1_Pos (24UL) /*!< PAD27_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGG_PAD27_DS1_Msk (0x1000000UL) /*!< PAD27_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD26_SR_Pos (20UL) /*!< PAD26_SR (Bit 20) */ +#define GPIO_ALTPADCFGG_PAD26_SR_Msk (0x100000UL) /*!< PAD26_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD26_DS1_Pos (16UL) /*!< PAD26_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGG_PAD26_DS1_Msk (0x10000UL) /*!< PAD26_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD25_SR_Pos (12UL) /*!< PAD25_SR (Bit 12) */ +#define GPIO_ALTPADCFGG_PAD25_SR_Msk (0x1000UL) /*!< PAD25_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD25_DS1_Pos (8UL) /*!< PAD25_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGG_PAD25_DS1_Msk (0x100UL) /*!< PAD25_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD24_SR_Pos (4UL) /*!< PAD24_SR (Bit 4) */ +#define GPIO_ALTPADCFGG_PAD24_SR_Msk (0x10UL) /*!< PAD24_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD24_DS1_Pos (0UL) /*!< PAD24_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGG_PAD24_DS1_Msk (0x1UL) /*!< PAD24_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGH ======================================================= */ +#define GPIO_ALTPADCFGH_PAD31_SR_Pos (28UL) /*!< PAD31_SR (Bit 28) */ +#define GPIO_ALTPADCFGH_PAD31_SR_Msk (0x10000000UL) /*!< PAD31_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD31_DS1_Pos (24UL) /*!< PAD31_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGH_PAD31_DS1_Msk (0x1000000UL) /*!< PAD31_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD30_SR_Pos (20UL) /*!< PAD30_SR (Bit 20) */ +#define GPIO_ALTPADCFGH_PAD30_SR_Msk (0x100000UL) /*!< PAD30_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD30_DS1_Pos (16UL) /*!< PAD30_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGH_PAD30_DS1_Msk (0x10000UL) /*!< PAD30_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD29_SR_Pos (12UL) /*!< PAD29_SR (Bit 12) */ +#define GPIO_ALTPADCFGH_PAD29_SR_Msk (0x1000UL) /*!< PAD29_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD29_DS1_Pos (8UL) /*!< PAD29_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGH_PAD29_DS1_Msk (0x100UL) /*!< PAD29_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD28_SR_Pos (4UL) /*!< PAD28_SR (Bit 4) */ +#define GPIO_ALTPADCFGH_PAD28_SR_Msk (0x10UL) /*!< PAD28_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD28_DS1_Pos (0UL) /*!< PAD28_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGH_PAD28_DS1_Msk (0x1UL) /*!< PAD28_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGI ======================================================= */ +#define GPIO_ALTPADCFGI_PAD35_SR_Pos (28UL) /*!< PAD35_SR (Bit 28) */ +#define GPIO_ALTPADCFGI_PAD35_SR_Msk (0x10000000UL) /*!< PAD35_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD35_DS1_Pos (24UL) /*!< PAD35_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGI_PAD35_DS1_Msk (0x1000000UL) /*!< PAD35_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD34_SR_Pos (20UL) /*!< PAD34_SR (Bit 20) */ +#define GPIO_ALTPADCFGI_PAD34_SR_Msk (0x100000UL) /*!< PAD34_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD34_DS1_Pos (16UL) /*!< PAD34_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGI_PAD34_DS1_Msk (0x10000UL) /*!< PAD34_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD33_SR_Pos (12UL) /*!< PAD33_SR (Bit 12) */ +#define GPIO_ALTPADCFGI_PAD33_SR_Msk (0x1000UL) /*!< PAD33_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD33_DS1_Pos (8UL) /*!< PAD33_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGI_PAD33_DS1_Msk (0x100UL) /*!< PAD33_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD32_SR_Pos (4UL) /*!< PAD32_SR (Bit 4) */ +#define GPIO_ALTPADCFGI_PAD32_SR_Msk (0x10UL) /*!< PAD32_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD32_DS1_Pos (0UL) /*!< PAD32_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGI_PAD32_DS1_Msk (0x1UL) /*!< PAD32_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGJ ======================================================= */ +#define GPIO_ALTPADCFGJ_PAD39_SR_Pos (28UL) /*!< PAD39_SR (Bit 28) */ +#define GPIO_ALTPADCFGJ_PAD39_SR_Msk (0x10000000UL) /*!< PAD39_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD39_DS1_Pos (24UL) /*!< PAD39_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGJ_PAD39_DS1_Msk (0x1000000UL) /*!< PAD39_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD38_SR_Pos (20UL) /*!< PAD38_SR (Bit 20) */ +#define GPIO_ALTPADCFGJ_PAD38_SR_Msk (0x100000UL) /*!< PAD38_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD38_DS1_Pos (16UL) /*!< PAD38_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGJ_PAD38_DS1_Msk (0x10000UL) /*!< PAD38_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD37_SR_Pos (12UL) /*!< PAD37_SR (Bit 12) */ +#define GPIO_ALTPADCFGJ_PAD37_SR_Msk (0x1000UL) /*!< PAD37_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD37_DS1_Pos (8UL) /*!< PAD37_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGJ_PAD37_DS1_Msk (0x100UL) /*!< PAD37_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD36_SR_Pos (4UL) /*!< PAD36_SR (Bit 4) */ +#define GPIO_ALTPADCFGJ_PAD36_SR_Msk (0x10UL) /*!< PAD36_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD36_DS1_Pos (0UL) /*!< PAD36_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGJ_PAD36_DS1_Msk (0x1UL) /*!< PAD36_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGK ======================================================= */ +#define GPIO_ALTPADCFGK_PAD43_SR_Pos (28UL) /*!< PAD43_SR (Bit 28) */ +#define GPIO_ALTPADCFGK_PAD43_SR_Msk (0x10000000UL) /*!< PAD43_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD43_DS1_Pos (24UL) /*!< PAD43_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGK_PAD43_DS1_Msk (0x1000000UL) /*!< PAD43_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD42_SR_Pos (20UL) /*!< PAD42_SR (Bit 20) */ +#define GPIO_ALTPADCFGK_PAD42_SR_Msk (0x100000UL) /*!< PAD42_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD42_DS1_Pos (16UL) /*!< PAD42_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGK_PAD42_DS1_Msk (0x10000UL) /*!< PAD42_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD41_SR_Pos (12UL) /*!< PAD41_SR (Bit 12) */ +#define GPIO_ALTPADCFGK_PAD41_SR_Msk (0x1000UL) /*!< PAD41_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD41_DS1_Pos (8UL) /*!< PAD41_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGK_PAD41_DS1_Msk (0x100UL) /*!< PAD41_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD40_SR_Pos (4UL) /*!< PAD40_SR (Bit 4) */ +#define GPIO_ALTPADCFGK_PAD40_SR_Msk (0x10UL) /*!< PAD40_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD40_DS1_Pos (0UL) /*!< PAD40_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGK_PAD40_DS1_Msk (0x1UL) /*!< PAD40_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGL ======================================================= */ +#define GPIO_ALTPADCFGL_PAD47_SR_Pos (28UL) /*!< PAD47_SR (Bit 28) */ +#define GPIO_ALTPADCFGL_PAD47_SR_Msk (0x10000000UL) /*!< PAD47_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD47_DS1_Pos (24UL) /*!< PAD47_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGL_PAD47_DS1_Msk (0x1000000UL) /*!< PAD47_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD46_SR_Pos (20UL) /*!< PAD46_SR (Bit 20) */ +#define GPIO_ALTPADCFGL_PAD46_SR_Msk (0x100000UL) /*!< PAD46_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD46_DS1_Pos (16UL) /*!< PAD46_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGL_PAD46_DS1_Msk (0x10000UL) /*!< PAD46_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD45_SR_Pos (12UL) /*!< PAD45_SR (Bit 12) */ +#define GPIO_ALTPADCFGL_PAD45_SR_Msk (0x1000UL) /*!< PAD45_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD45_DS1_Pos (8UL) /*!< PAD45_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGL_PAD45_DS1_Msk (0x100UL) /*!< PAD45_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD44_SR_Pos (4UL) /*!< PAD44_SR (Bit 4) */ +#define GPIO_ALTPADCFGL_PAD44_SR_Msk (0x10UL) /*!< PAD44_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD44_DS1_Pos (0UL) /*!< PAD44_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGL_PAD44_DS1_Msk (0x1UL) /*!< PAD44_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGM ======================================================= */ +#define GPIO_ALTPADCFGM_PAD49_SR_Pos (12UL) /*!< PAD49_SR (Bit 12) */ +#define GPIO_ALTPADCFGM_PAD49_SR_Msk (0x1000UL) /*!< PAD49_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD49_DS1_Pos (8UL) /*!< PAD49_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGM_PAD49_DS1_Msk (0x100UL) /*!< PAD49_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD48_SR_Pos (4UL) /*!< PAD48_SR (Bit 4) */ +#define GPIO_ALTPADCFGM_PAD48_SR_Msk (0x10UL) /*!< PAD48_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD48_DS1_Pos (0UL) /*!< PAD48_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGM_PAD48_DS1_Msk (0x1UL) /*!< PAD48_DS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0EN ========================================================= */ +#define GPIO_INT0EN_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0EN_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0EN_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0EN_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0EN_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0EN_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0EN_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0EN_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0EN_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0EN_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0EN_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0EN_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0EN_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0EN_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0EN_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0EN_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0EN_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0EN_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0EN_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0EN_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0EN_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0EN_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0EN_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0EN_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0EN_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0EN_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0EN_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0EN_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0EN_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0EN_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0EN_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0EN_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0EN_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================= INT0STAT ======================================================== */ +#define GPIO_INT0STAT_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0STAT_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0STAT_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0STAT_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0STAT_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0STAT_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0STAT_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0STAT_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0STAT_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0STAT_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0STAT_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0STAT_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0STAT_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0STAT_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0STAT_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0STAT_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0STAT_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0STAT_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0STAT_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0STAT_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0STAT_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0STAT_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0STAT_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0STAT_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0STAT_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0STAT_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0STAT_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0STAT_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0STAT_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0STAT_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0STAT_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0STAT_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0STAT_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0CLR ======================================================== */ +#define GPIO_INT0CLR_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0CLR_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0CLR_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0CLR_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0CLR_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0CLR_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0CLR_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0CLR_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0CLR_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0CLR_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0CLR_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0CLR_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0CLR_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0CLR_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0CLR_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0CLR_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0CLR_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0CLR_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0CLR_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0CLR_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0CLR_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0CLR_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0CLR_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0CLR_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0CLR_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0CLR_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0CLR_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0CLR_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0CLR_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0CLR_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0CLR_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0CLR_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0CLR_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0SET ======================================================== */ +#define GPIO_INT0SET_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0SET_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0SET_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0SET_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0SET_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0SET_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0SET_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0SET_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0SET_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0SET_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0SET_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0SET_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0SET_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0SET_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0SET_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0SET_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0SET_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0SET_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0SET_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0SET_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0SET_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0SET_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0SET_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0SET_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0SET_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0SET_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0SET_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0SET_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0SET_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0SET_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0SET_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0SET_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0SET_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1EN ========================================================= */ +#define GPIO_INT1EN_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1EN_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1EN_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1EN_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1EN_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1EN_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1EN_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1EN_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1EN_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1EN_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1EN_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1EN_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1EN_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1EN_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1EN_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1EN_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1EN_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1EN_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1EN_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================= INT1STAT ======================================================== */ +#define GPIO_INT1STAT_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1STAT_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1STAT_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1STAT_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1STAT_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1STAT_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1STAT_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1STAT_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1STAT_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1STAT_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1STAT_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1STAT_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1STAT_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1STAT_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1STAT_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1STAT_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1STAT_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1STAT_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1STAT_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1CLR ======================================================== */ +#define GPIO_INT1CLR_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1CLR_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1CLR_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1CLR_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1CLR_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1CLR_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1CLR_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1CLR_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1CLR_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1CLR_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1CLR_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1CLR_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1CLR_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1CLR_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1CLR_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1CLR_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1CLR_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1CLR_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1CLR_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1SET ======================================================== */ +#define GPIO_INT1SET_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1SET_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1SET_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1SET_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1SET_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1SET_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1SET_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1SET_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1SET_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1SET_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1SET_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1SET_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1SET_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1SET_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1SET_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1SET_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1SET_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1SET_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1SET_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IOMSTR0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +#define IOMSTR0_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define IOMSTR0_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FIFOPTR ======================================================== */ +#define IOMSTR0_FIFOPTR_FIFOREM_Pos (16UL) /*!< FIFOREM (Bit 16) */ +#define IOMSTR0_FIFOPTR_FIFOREM_Msk (0xff0000UL) /*!< FIFOREM (Bitfield-Mask: 0xff) */ +#define IOMSTR0_FIFOPTR_FIFOSIZ_Pos (0UL) /*!< FIFOSIZ (Bit 0) */ +#define IOMSTR0_FIFOPTR_FIFOSIZ_Msk (0xffUL) /*!< FIFOSIZ (Bitfield-Mask: 0xff) */ +/* ======================================================== TLNGTH ========================================================= */ +#define IOMSTR0_TLNGTH_TLNGTH_Pos (0UL) /*!< TLNGTH (Bit 0) */ +#define IOMSTR0_TLNGTH_TLNGTH_Msk (0xfffUL) /*!< TLNGTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define IOMSTR0_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */ +#define IOMSTR0_FIFOTHR_FIFOWTHR_Msk (0x7f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x7f) */ +#define IOMSTR0_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */ +#define IOMSTR0_FIFOTHR_FIFORTHR_Msk (0x7fUL) /*!< FIFORTHR (Bitfield-Mask: 0x7f) */ +/* ======================================================== CLKCFG ========================================================= */ +#define IOMSTR0_CLKCFG_TOTPER_Pos (24UL) /*!< TOTPER (Bit 24) */ +#define IOMSTR0_CLKCFG_TOTPER_Msk (0xff000000UL) /*!< TOTPER (Bitfield-Mask: 0xff) */ +#define IOMSTR0_CLKCFG_LOWPER_Pos (16UL) /*!< LOWPER (Bit 16) */ +#define IOMSTR0_CLKCFG_LOWPER_Msk (0xff0000UL) /*!< LOWPER (Bitfield-Mask: 0xff) */ +#define IOMSTR0_CLKCFG_DIVEN_Pos (12UL) /*!< DIVEN (Bit 12) */ +#define IOMSTR0_CLKCFG_DIVEN_Msk (0x1000UL) /*!< DIVEN (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CLKCFG_DIV3_Pos (11UL) /*!< DIV3 (Bit 11) */ +#define IOMSTR0_CLKCFG_DIV3_Msk (0x800UL) /*!< DIV3 (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */ +#define IOMSTR0_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */ +/* ========================================================== CMD ========================================================== */ +#define IOMSTR0_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */ +#define IOMSTR0_CMD_CMD_Msk (0xffffffffUL) /*!< CMD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CMDRPT ========================================================= */ +#define IOMSTR0_CMDRPT_CMDRPT_Pos (0UL) /*!< CMDRPT (Bit 0) */ +#define IOMSTR0_CMDRPT_CMDRPT_Msk (0x1fUL) /*!< CMDRPT (Bitfield-Mask: 0x1f) */ +/* ======================================================== STATUS ========================================================= */ +#define IOMSTR0_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */ +#define IOMSTR0_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */ +#define IOMSTR0_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */ +#define IOMSTR0_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */ +#define IOMSTR0_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */ +#define IOMSTR0_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define IOMSTR0_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */ +#define IOMSTR0_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_RDFCPOL_Pos (14UL) /*!< RDFCPOL (Bit 14) */ +#define IOMSTR0_CFG_RDFCPOL_Msk (0x4000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_WTFCPOL_Pos (13UL) /*!< WTFCPOL (Bit 13) */ +#define IOMSTR0_CFG_WTFCPOL_Msk (0x2000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_WTFCIRQ_Pos (12UL) /*!< WTFCIRQ (Bit 12) */ +#define IOMSTR0_CFG_WTFCIRQ_Msk (0x1000UL) /*!< WTFCIRQ (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_FCDEL_Pos (11UL) /*!< FCDEL (Bit 11) */ +#define IOMSTR0_CFG_FCDEL_Msk (0x800UL) /*!< FCDEL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_MOSIINV_Pos (10UL) /*!< MOSIINV (Bit 10) */ +#define IOMSTR0_CFG_MOSIINV_Msk (0x400UL) /*!< MOSIINV (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_RDFC_Pos (9UL) /*!< RDFC (Bit 9) */ +#define IOMSTR0_CFG_RDFC_Msk (0x200UL) /*!< RDFC (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_WTFC_Pos (8UL) /*!< WTFC (Bit 8) */ +#define IOMSTR0_CFG_WTFC_Msk (0x100UL) /*!< WTFC (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_STARTRD_Pos (4UL) /*!< STARTRD (Bit 4) */ +#define IOMSTR0_CFG_STARTRD_Msk (0x30UL) /*!< STARTRD (Bitfield-Mask: 0x03) */ +#define IOMSTR0_CFG_FULLDUP_Pos (3UL) /*!< FULLDUP (Bit 3) */ +#define IOMSTR0_CFG_FULLDUP_Msk (0x8UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_SPHA_Pos (2UL) /*!< SPHA (Bit 2) */ +#define IOMSTR0_CFG_SPHA_Msk (0x4UL) /*!< SPHA (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */ +#define IOMSTR0_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */ +#define IOMSTR0_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define IOMSTR0_INTEN_ARB_Pos (10UL) /*!< ARB (Bit 10) */ +#define IOMSTR0_INTEN_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define IOMSTR0_INTEN_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_START_Pos (8UL) /*!< START (Bit 8) */ +#define IOMSTR0_INTEN_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */ +#define IOMSTR0_INTEN_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_IACC_Pos (6UL) /*!< IACC (Bit 6) */ +#define IOMSTR0_INTEN_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */ +#define IOMSTR0_INTEN_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOMSTR0_INTEN_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOMSTR0_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOMSTR0_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOMSTR0_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOMSTR0_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define IOMSTR0_INTSTAT_ARB_Pos (10UL) /*!< ARB (Bit 10) */ +#define IOMSTR0_INTSTAT_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define IOMSTR0_INTSTAT_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_START_Pos (8UL) /*!< START (Bit 8) */ +#define IOMSTR0_INTSTAT_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */ +#define IOMSTR0_INTSTAT_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_IACC_Pos (6UL) /*!< IACC (Bit 6) */ +#define IOMSTR0_INTSTAT_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */ +#define IOMSTR0_INTSTAT_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOMSTR0_INTSTAT_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOMSTR0_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOMSTR0_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOMSTR0_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOMSTR0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define IOMSTR0_INTCLR_ARB_Pos (10UL) /*!< ARB (Bit 10) */ +#define IOMSTR0_INTCLR_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define IOMSTR0_INTCLR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_START_Pos (8UL) /*!< START (Bit 8) */ +#define IOMSTR0_INTCLR_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */ +#define IOMSTR0_INTCLR_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_IACC_Pos (6UL) /*!< IACC (Bit 6) */ +#define IOMSTR0_INTCLR_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */ +#define IOMSTR0_INTCLR_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOMSTR0_INTCLR_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOMSTR0_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOMSTR0_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOMSTR0_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOMSTR0_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define IOMSTR0_INTSET_ARB_Pos (10UL) /*!< ARB (Bit 10) */ +#define IOMSTR0_INTSET_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define IOMSTR0_INTSET_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_START_Pos (8UL) /*!< START (Bit 8) */ +#define IOMSTR0_INTSET_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */ +#define IOMSTR0_INTSET_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_IACC_Pos (6UL) /*!< IACC (Bit 6) */ +#define IOMSTR0_INTSET_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */ +#define IOMSTR0_INTSET_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOMSTR0_INTSET_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOMSTR0_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOMSTR0_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOMSTR0_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOMSTR0_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOMSTR0_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FIFOPTR ======================================================== */ +#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos (8UL) /*!< FIFOSIZ (Bit 8) */ +#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk (0xff00UL) /*!< FIFOSIZ (Bitfield-Mask: 0xff) */ +#define IOSLAVE_FIFOPTR_FIFOPTR_Pos (0UL) /*!< FIFOPTR (Bit 0) */ +#define IOSLAVE_FIFOPTR_FIFOPTR_Msk (0xffUL) /*!< FIFOPTR (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOCFG ======================================================== */ +#define IOSLAVE_FIFOCFG_ROBASE_Pos (24UL) /*!< ROBASE (Bit 24) */ +#define IOSLAVE_FIFOCFG_ROBASE_Msk (0x3f000000UL) /*!< ROBASE (Bitfield-Mask: 0x3f) */ +#define IOSLAVE_FIFOCFG_FIFOMAX_Pos (8UL) /*!< FIFOMAX (Bit 8) */ +#define IOSLAVE_FIFOCFG_FIFOMAX_Msk (0x3f00UL) /*!< FIFOMAX (Bitfield-Mask: 0x3f) */ +#define IOSLAVE_FIFOCFG_FIFOBASE_Pos (0UL) /*!< FIFOBASE (Bit 0) */ +#define IOSLAVE_FIFOCFG_FIFOBASE_Msk (0x1fUL) /*!< FIFOBASE (Bitfield-Mask: 0x1f) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define IOSLAVE_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */ +#define IOSLAVE_FIFOTHR_FIFOTHR_Msk (0xffUL) /*!< FIFOTHR (Bitfield-Mask: 0xff) */ +/* ========================================================= FUPD ========================================================== */ +#define IOSLAVE_FUPD_IOREAD_Pos (1UL) /*!< IOREAD (Bit 1) */ +#define IOSLAVE_FUPD_IOREAD_Msk (0x2UL) /*!< IOREAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_FUPD_FIFOUPD_Pos (0UL) /*!< FIFOUPD (Bit 0) */ +#define IOSLAVE_FUPD_FIFOUPD_Msk (0x1UL) /*!< FIFOUPD (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOCTR ======================================================== */ +#define IOSLAVE_FIFOCTR_FIFOCTR_Pos (0UL) /*!< FIFOCTR (Bit 0) */ +#define IOSLAVE_FIFOCTR_FIFOCTR_Msk (0x3ffUL) /*!< FIFOCTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FIFOINC ======================================================== */ +#define IOSLAVE_FIFOINC_FIFOINC_Pos (0UL) /*!< FIFOINC (Bit 0) */ +#define IOSLAVE_FIFOINC_FIFOINC_Msk (0x3ffUL) /*!< FIFOINC (Bitfield-Mask: 0x3ff) */ +/* ========================================================== CFG ========================================================== */ +#define IOSLAVE_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */ +#define IOSLAVE_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_I2CADDR_Pos (8UL) /*!< I2CADDR (Bit 8) */ +#define IOSLAVE_CFG_I2CADDR_Msk (0xfff00UL) /*!< I2CADDR (Bitfield-Mask: 0xfff) */ +#define IOSLAVE_CFG_STARTRD_Pos (4UL) /*!< STARTRD (Bit 4) */ +#define IOSLAVE_CFG_STARTRD_Msk (0x10UL) /*!< STARTRD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_LSB_Pos (2UL) /*!< LSB (Bit 2) */ +#define IOSLAVE_CFG_LSB_Msk (0x4UL) /*!< LSB (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */ +#define IOSLAVE_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */ +#define IOSLAVE_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PRENC ========================================================= */ +#define IOSLAVE_PRENC_PRENC_Pos (0UL) /*!< PRENC (Bit 0) */ +#define IOSLAVE_PRENC_PRENC_Msk (0x1fUL) /*!< PRENC (Bitfield-Mask: 0x1f) */ +/* ======================================================= IOINTCTL ======================================================== */ +#define IOSLAVE_IOINTCTL_IOINTSET_Pos (24UL) /*!< IOINTSET (Bit 24) */ +#define IOSLAVE_IOINTCTL_IOINTSET_Msk (0xff000000UL) /*!< IOINTSET (Bitfield-Mask: 0xff) */ +#define IOSLAVE_IOINTCTL_IOINTCLR_Pos (16UL) /*!< IOINTCLR (Bit 16) */ +#define IOSLAVE_IOINTCTL_IOINTCLR_Msk (0x10000UL) /*!< IOINTCLR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_IOINTCTL_IOINT_Pos (8UL) /*!< IOINT (Bit 8) */ +#define IOSLAVE_IOINTCTL_IOINT_Msk (0xff00UL) /*!< IOINT (Bitfield-Mask: 0xff) */ +#define IOSLAVE_IOINTCTL_IOINTEN_Pos (0UL) /*!< IOINTEN (Bit 0) */ +#define IOSLAVE_IOINTCTL_IOINTEN_Msk (0xffUL) /*!< IOINTEN (Bitfield-Mask: 0xff) */ +/* ======================================================== GENADD ========================================================= */ +#define IOSLAVE_GENADD_GADATA_Pos (0UL) /*!< GADATA (Bit 0) */ +#define IOSLAVE_GENADD_GADATA_Msk (0xffUL) /*!< GADATA (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define IOSLAVE_INTEN_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTEN_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTEN_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTEN_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTEN_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTEN_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTEN_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTEN_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTEN_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTEN_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define IOSLAVE_INTSTAT_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTSTAT_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTSTAT_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTSTAT_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTSTAT_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTSTAT_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTSTAT_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTSTAT_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTSTAT_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTSTAT_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define IOSLAVE_INTCLR_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTCLR_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTCLR_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTCLR_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTCLR_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTCLR_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTCLR_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTCLR_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTCLR_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTCLR_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define IOSLAVE_INTSET_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTSET_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTSET_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTSET_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTSET_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTSET_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTSET_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTSET_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTSET_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTSET_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ====================================================== REGACCINTEN ====================================================== */ +#define IOSLAVE_REGACCINTEN_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTEN_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTSTAT ===================================================== */ +#define IOSLAVE_REGACCINTSTAT_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTSTAT_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTCLR ====================================================== */ +#define IOSLAVE_REGACCINTCLR_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTCLR_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTSET ====================================================== */ +#define IOSLAVE_REGACCINTSET_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTSET_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CHIP_INFO ======================================================= */ +#define MCUCTRL_CHIP_INFO_PARTNUM_Pos (0UL) /*!< PARTNUM (Bit 0) */ +#define MCUCTRL_CHIP_INFO_PARTNUM_Msk (0xffffffffUL) /*!< PARTNUM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPID0 ======================================================== */ +#define MCUCTRL_CHIPID0_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define MCUCTRL_CHIPID0_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPID1 ======================================================== */ +#define MCUCTRL_CHIPID1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define MCUCTRL_CHIPID1_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPREV ======================================================== */ +#define MCUCTRL_CHIPREV_REVMAJ_Pos (4UL) /*!< REVMAJ (Bit 4) */ +#define MCUCTRL_CHIPREV_REVMAJ_Msk (0xf0UL) /*!< REVMAJ (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_CHIPREV_REVMIN_Pos (0UL) /*!< REVMIN (Bit 0) */ +#define MCUCTRL_CHIPREV_REVMIN_Msk (0xfUL) /*!< REVMIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= VENDORID ======================================================== */ +#define MCUCTRL_VENDORID_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define MCUCTRL_VENDORID_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DEBUGGER ======================================================== */ +#define MCUCTRL_DEBUGGER_LOCKOUT_Pos (0UL) /*!< LOCKOUT (Bit 0) */ +#define MCUCTRL_DEBUGGER_LOCKOUT_Msk (0x1UL) /*!< LOCKOUT (Bitfield-Mask: 0x01) */ +/* ========================================================= BUCK ========================================================== */ +#define MCUCTRL_BUCK_MEMBUCKRST_Pos (7UL) /*!< MEMBUCKRST (Bit 7) */ +#define MCUCTRL_BUCK_MEMBUCKRST_Msk (0x80UL) /*!< MEMBUCKRST (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_COREBUCKRST_Pos (6UL) /*!< COREBUCKRST (Bit 6) */ +#define MCUCTRL_BUCK_COREBUCKRST_Msk (0x40UL) /*!< COREBUCKRST (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_BYPBUCKMEM_Pos (5UL) /*!< BYPBUCKMEM (Bit 5) */ +#define MCUCTRL_BUCK_BYPBUCKMEM_Msk (0x20UL) /*!< BYPBUCKMEM (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_MEMBUCKPWD_Pos (4UL) /*!< MEMBUCKPWD (Bit 4) */ +#define MCUCTRL_BUCK_MEMBUCKPWD_Msk (0x10UL) /*!< MEMBUCKPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_SLEEPBUCKANA_Pos (3UL) /*!< SLEEPBUCKANA (Bit 3) */ +#define MCUCTRL_BUCK_SLEEPBUCKANA_Msk (0x8UL) /*!< SLEEPBUCKANA (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_COREBUCKPWD_Pos (2UL) /*!< COREBUCKPWD (Bit 2) */ +#define MCUCTRL_BUCK_COREBUCKPWD_Msk (0x4UL) /*!< COREBUCKPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_BYPBUCKCORE_Pos (1UL) /*!< BYPBUCKCORE (Bit 1) */ +#define MCUCTRL_BUCK_BYPBUCKCORE_Msk (0x2UL) /*!< BYPBUCKCORE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK_BUCKSWE_Pos (0UL) /*!< BUCKSWE (Bit 0) */ +#define MCUCTRL_BUCK_BUCKSWE_Msk (0x1UL) /*!< BUCKSWE (Bitfield-Mask: 0x01) */ +/* ========================================================= BUCK3 ========================================================= */ +#define MCUCTRL_BUCK3_MEMBUCKLOTON_Pos (18UL) /*!< MEMBUCKLOTON (Bit 18) */ +#define MCUCTRL_BUCK3_MEMBUCKLOTON_Msk (0x3c0000UL) /*!< MEMBUCKLOTON (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_BUCK3_MEMBUCKBURSTEN_Pos (17UL) /*!< MEMBUCKBURSTEN (Bit 17) */ +#define MCUCTRL_BUCK3_MEMBUCKBURSTEN_Msk (0x20000UL) /*!< MEMBUCKBURSTEN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK3_MEMBUCKZXTRIM_Pos (13UL) /*!< MEMBUCKZXTRIM (Bit 13) */ +#define MCUCTRL_BUCK3_MEMBUCKZXTRIM_Msk (0x1e000UL) /*!< MEMBUCKZXTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_Pos (11UL) /*!< MEMBUCKHYSTTRIM (Bit 11) */ +#define MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_Msk (0x1800UL) /*!< MEMBUCKHYSTTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BUCK3_COREBUCKLOTON_Pos (7UL) /*!< COREBUCKLOTON (Bit 7) */ +#define MCUCTRL_BUCK3_COREBUCKLOTON_Msk (0x780UL) /*!< COREBUCKLOTON (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_BUCK3_COREBUCKBURSTEN_Pos (6UL) /*!< COREBUCKBURSTEN (Bit 6) */ +#define MCUCTRL_BUCK3_COREBUCKBURSTEN_Msk (0x40UL) /*!< COREBUCKBURSTEN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BUCK3_COREBUCKZXTRIM_Pos (2UL) /*!< COREBUCKZXTRIM (Bit 2) */ +#define MCUCTRL_BUCK3_COREBUCKZXTRIM_Msk (0x3cUL) /*!< COREBUCKZXTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_BUCK3_COREBUCKHYSTTRIM_Pos (0UL) /*!< COREBUCKHYSTTRIM (Bit 0) */ +#define MCUCTRL_BUCK3_COREBUCKHYSTTRIM_Msk (0x3UL) /*!< COREBUCKHYSTTRIM (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOREG1 ======================================================== */ +#define MCUCTRL_LDOREG1_CORELDOIBSTRM_Pos (20UL) /*!< CORELDOIBSTRM (Bit 20) */ +#define MCUCTRL_LDOREG1_CORELDOIBSTRM_Msk (0x100000UL) /*!< CORELDOIBSTRM (Bitfield-Mask: 0x01) */ +#define MCUCTRL_LDOREG1_CORELDOLPTRIM_Pos (14UL) /*!< CORELDOLPTRIM (Bit 14) */ +#define MCUCTRL_LDOREG1_CORELDOLPTRIM_Msk (0xfc000UL) /*!< CORELDOLPTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_LDOREG1_TRIMCORELDOR3_Pos (10UL) /*!< TRIMCORELDOR3 (Bit 10) */ +#define MCUCTRL_LDOREG1_TRIMCORELDOR3_Msk (0x3c00UL) /*!< TRIMCORELDOR3 (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_LDOREG1_TRIMCORELDOR1_Pos (0UL) /*!< TRIMCORELDOR1 (Bit 0) */ +#define MCUCTRL_LDOREG1_TRIMCORELDOR1_Msk (0x3ffUL) /*!< TRIMCORELDOR1 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== LDOREG3 ======================================================== */ +#define MCUCTRL_LDOREG3_TRIMMEMLDOR1_Pos (12UL) /*!< TRIMMEMLDOR1 (Bit 12) */ +#define MCUCTRL_LDOREG3_TRIMMEMLDOR1_Msk (0x3f000UL) /*!< TRIMMEMLDOR1 (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_Pos (6UL) /*!< MEMLDOLPALTTRIM (Bit 6) */ +#define MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_Msk (0xfc0UL) /*!< MEMLDOLPALTTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_LDOREG3_MEMLDOLPTRIM_Pos (0UL) /*!< MEMLDOLPTRIM (Bit 0) */ +#define MCUCTRL_LDOREG3_MEMLDOLPTRIM_Msk (0x3fUL) /*!< MEMLDOLPTRIM (Bitfield-Mask: 0x3f) */ +/* ====================================================== BODPORCTRL ======================================================= */ +#define MCUCTRL_BODPORCTRL_BODEXTREFSEL_Pos (3UL) /*!< BODEXTREFSEL (Bit 3) */ +#define MCUCTRL_BODPORCTRL_BODEXTREFSEL_Msk (0x8UL) /*!< BODEXTREFSEL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODPORCTRL_PDREXTREFSEL_Pos (2UL) /*!< PDREXTREFSEL (Bit 2) */ +#define MCUCTRL_BODPORCTRL_PDREXTREFSEL_Msk (0x4UL) /*!< PDREXTREFSEL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODPORCTRL_PWDBOD_Pos (1UL) /*!< PWDBOD (Bit 1) */ +#define MCUCTRL_BODPORCTRL_PWDBOD_Msk (0x2UL) /*!< PWDBOD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODPORCTRL_PWDPDR_Pos (0UL) /*!< PWDPDR (Bit 0) */ +#define MCUCTRL_BODPORCTRL_PWDPDR_Msk (0x1UL) /*!< PWDPDR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCPWRDLY ======================================================= */ +#define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos (8UL) /*!< ADCPWR1 (Bit 8) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk (0xff00UL) /*!< ADCPWR1 (Bitfield-Mask: 0xff) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos (0UL) /*!< ADCPWR0 (Bit 0) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk (0xffUL) /*!< ADCPWR0 (Bitfield-Mask: 0xff) */ +/* ======================================================== ADCCAL ========================================================= */ +#define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos (1UL) /*!< ADCCALIBRATED (Bit 1) */ +#define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk (0x2UL) /*!< ADCCALIBRATED (Bitfield-Mask: 0x01) */ +#define MCUCTRL_ADCCAL_CALONPWRUP_Pos (0UL) /*!< CALONPWRUP (Bit 0) */ +#define MCUCTRL_ADCCAL_CALONPWRUP_Msk (0x1UL) /*!< CALONPWRUP (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCBATTLOAD ====================================================== */ +#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos (0UL) /*!< BATTLOAD (Bit 0) */ +#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk (0x1UL) /*!< BATTLOAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUCKTRIM ======================================================== */ +#define MCUCTRL_BUCKTRIM_RSVD2_Pos (24UL) /*!< RSVD2 (Bit 24) */ +#define MCUCTRL_BUCKTRIM_RSVD2_Msk (0x3f000000UL) /*!< RSVD2 (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_BUCKTRIM_COREBUCKR1_HI_Pos (16UL) /*!< COREBUCKR1_HI (Bit 16) */ +#define MCUCTRL_BUCKTRIM_COREBUCKR1_HI_Msk (0xf0000UL) /*!< COREBUCKR1_HI (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_BUCKTRIM_COREBUCKR1_LO_Pos (8UL) /*!< COREBUCKR1_LO (Bit 8) */ +#define MCUCTRL_BUCKTRIM_COREBUCKR1_LO_Msk (0x3f00UL) /*!< COREBUCKR1_LO (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_BUCKTRIM_MEMBUCKR1_Pos (0UL) /*!< MEMBUCKR1 (Bit 0) */ +#define MCUCTRL_BUCKTRIM_MEMBUCKR1_Msk (0x3fUL) /*!< MEMBUCKR1 (Bitfield-Mask: 0x3f) */ +/* ====================================================== XTALGENCTRL ====================================================== */ +#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL) /*!< XTALKSBIASTRIM (Bit 8) */ +#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL) /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL) /*!< XTALBIASTRIM (Bit 2) */ +#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL) /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos (0UL) /*!< ACWARMUP (Bit 0) */ +#define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk (0x3UL) /*!< ACWARMUP (Bitfield-Mask: 0x03) */ +/* ===================================================== BOOTLOADERLOW ===================================================== */ +#define MCUCTRL_BOOTLOADERLOW_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define MCUCTRL_BOOTLOADERLOW_VALUE_Msk (0x1UL) /*!< VALUE (Bitfield-Mask: 0x01) */ +/* ====================================================== SHADOWVALID ====================================================== */ +#define MCUCTRL_SHADOWVALID_BL_DSLEEP_Pos (1UL) /*!< BL_DSLEEP (Bit 1) */ +#define MCUCTRL_SHADOWVALID_BL_DSLEEP_Msk (0x2UL) /*!< BL_DSLEEP (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SHADOWVALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define MCUCTRL_SHADOWVALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ==================================================== ICODEFAULTADDR ===================================================== */ +#define MCUCTRL_ICODEFAULTADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define MCUCTRL_ICODEFAULTADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DCODEFAULTADDR ===================================================== */ +#define MCUCTRL_DCODEFAULTADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define MCUCTRL_DCODEFAULTADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SYSFAULTADDR ====================================================== */ +#define MCUCTRL_SYSFAULTADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define MCUCTRL_SYSFAULTADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FAULTSTATUS ====================================================== */ +#define MCUCTRL_FAULTSTATUS_SYS_Pos (2UL) /*!< SYS (Bit 2) */ +#define MCUCTRL_FAULTSTATUS_SYS_Msk (0x4UL) /*!< SYS (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FAULTSTATUS_DCODE_Pos (1UL) /*!< DCODE (Bit 1) */ +#define MCUCTRL_FAULTSTATUS_DCODE_Msk (0x2UL) /*!< DCODE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FAULTSTATUS_ICODE_Pos (0UL) /*!< ICODE (Bit 0) */ +#define MCUCTRL_FAULTSTATUS_ICODE_Msk (0x1UL) /*!< ICODE (Bitfield-Mask: 0x01) */ +/* ==================================================== FAULTCAPTUREEN ===================================================== */ +#define MCUCTRL_FAULTCAPTUREEN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_FAULTCAPTUREEN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= DBGR1 ========================================================= */ +#define MCUCTRL_DBGR1_ONETO8_Pos (0UL) /*!< ONETO8 (Bit 0) */ +#define MCUCTRL_DBGR1_ONETO8_Msk (0xffffffffUL) /*!< ONETO8 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBGR2 ========================================================= */ +#define MCUCTRL_DBGR2_COOLCODE_Pos (0UL) /*!< COOLCODE (Bit 0) */ +#define MCUCTRL_DBGR2_COOLCODE_Msk (0xffffffffUL) /*!< COOLCODE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMUENABLE ======================================================= */ +#define MCUCTRL_PMUENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_PMUENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= TPIUCTRL ======================================================== */ +#define MCUCTRL_TPIUCTRL_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ +#define MCUCTRL_TPIUCTRL_CLKSEL_Msk (0x700UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define MCUCTRL_TPIUCTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_TPIUCTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCFG ========================================================== */ +#define PDM_PCFG_LRSWAP_Pos (31UL) /*!< LRSWAP (Bit 31) */ +#define PDM_PCFG_LRSWAP_Msk (0x80000000UL) /*!< LRSWAP (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_PGARIGHT_Pos (27UL) /*!< PGARIGHT (Bit 27) */ +#define PDM_PCFG_PGARIGHT_Msk (0x78000000UL) /*!< PGARIGHT (Bitfield-Mask: 0x0f) */ +#define PDM_PCFG_PGALEFT_Pos (23UL) /*!< PGALEFT (Bit 23) */ +#define PDM_PCFG_PGALEFT_Msk (0x7800000UL) /*!< PGALEFT (Bitfield-Mask: 0x0f) */ +#define PDM_PCFG_MCLKDIV_Pos (17UL) /*!< MCLKDIV (Bit 17) */ +#define PDM_PCFG_MCLKDIV_Msk (0x60000UL) /*!< MCLKDIV (Bitfield-Mask: 0x03) */ +#define PDM_PCFG_SINCRATE_Pos (10UL) /*!< SINCRATE (Bit 10) */ +#define PDM_PCFG_SINCRATE_Msk (0x1fc00UL) /*!< SINCRATE (Bitfield-Mask: 0x7f) */ +#define PDM_PCFG_ADCHPD_Pos (9UL) /*!< ADCHPD (Bit 9) */ +#define PDM_PCFG_ADCHPD_Msk (0x200UL) /*!< ADCHPD (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_HPCUTOFF_Pos (5UL) /*!< HPCUTOFF (Bit 5) */ +#define PDM_PCFG_HPCUTOFF_Msk (0x1e0UL) /*!< HPCUTOFF (Bitfield-Mask: 0x0f) */ +#define PDM_PCFG_CYCLES_Pos (2UL) /*!< CYCLES (Bit 2) */ +#define PDM_PCFG_CYCLES_Msk (0x1cUL) /*!< CYCLES (Bitfield-Mask: 0x07) */ +#define PDM_PCFG_SOFTMUTE_Pos (1UL) /*!< SOFTMUTE (Bit 1) */ +#define PDM_PCFG_SOFTMUTE_Msk (0x2UL) /*!< SOFTMUTE (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_PDMCORE_Pos (0UL) /*!< PDMCORE (Bit 0) */ +#define PDM_PCFG_PDMCORE_Msk (0x1UL) /*!< PDMCORE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCFG ========================================================== */ +#define PDM_VCFG_IOCLKEN_Pos (31UL) /*!< IOCLKEN (Bit 31) */ +#define PDM_VCFG_IOCLKEN_Msk (0x80000000UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_RSTB_Pos (30UL) /*!< RSTB (Bit 30) */ +#define PDM_VCFG_RSTB_Msk (0x40000000UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_PDMCLKSEL_Pos (27UL) /*!< PDMCLKSEL (Bit 27) */ +#define PDM_VCFG_PDMCLKSEL_Msk (0x38000000UL) /*!< PDMCLKSEL (Bitfield-Mask: 0x07) */ +#define PDM_VCFG_PDMCLK_Pos (26UL) /*!< PDMCLK (Bit 26) */ +#define PDM_VCFG_PDMCLK_Msk (0x4000000UL) /*!< PDMCLK (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_I2SMODE_Pos (20UL) /*!< I2SMODE (Bit 20) */ +#define PDM_VCFG_I2SMODE_Msk (0x100000UL) /*!< I2SMODE (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_BCLKINV_Pos (19UL) /*!< BCLKINV (Bit 19) */ +#define PDM_VCFG_BCLKINV_Msk (0x80000UL) /*!< BCLKINV (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_DMICKDEL_Pos (17UL) /*!< DMICKDEL (Bit 17) */ +#define PDM_VCFG_DMICKDEL_Msk (0x20000UL) /*!< DMICKDEL (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_SELAP_Pos (16UL) /*!< SELAP (Bit 16) */ +#define PDM_VCFG_SELAP_Msk (0x10000UL) /*!< SELAP (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_PCMPACK_Pos (8UL) /*!< PCMPACK (Bit 8) */ +#define PDM_VCFG_PCMPACK_Msk (0x100UL) /*!< PCMPACK (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_CHSET_Pos (3UL) /*!< CHSET (Bit 3) */ +#define PDM_VCFG_CHSET_Msk (0x18UL) /*!< CHSET (Bitfield-Mask: 0x03) */ +/* ========================================================== FR =========================================================== */ +#define PDM_FR_FIFOCNT_Pos (0UL) /*!< FIFOCNT (Bit 0) */ +#define PDM_FR_FIFOCNT_Msk (0x1ffUL) /*!< FIFOCNT (Bitfield-Mask: 0x1ff) */ +/* ========================================================== FRD ========================================================== */ +#define PDM_FRD_FIFOREAD_Pos (0UL) /*!< FIFOREAD (Bit 0) */ +#define PDM_FRD_FIFOREAD_Msk (0xffffffffUL) /*!< FIFOREAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLUSH ========================================================= */ +#define PDM_FLUSH_FIFOFLUSH_Pos (0UL) /*!< FIFOFLUSH (Bit 0) */ +#define PDM_FLUSH_FIFOFLUSH_Msk (0x1UL) /*!< FIFOFLUSH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTHR ========================================================== */ +#define PDM_FTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */ +#define PDM_FTHR_FIFOTHR_Msk (0xffUL) /*!< FIFOTHR (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define PDM_INTEN_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTEN_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTEN_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTEN_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define PDM_INTSTAT_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTSTAT_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTSTAT_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTSTAT_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define PDM_INTCLR_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTCLR_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTCLR_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTCLR_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define PDM_INTSET_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTSET_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTSET_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTSET_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SUPPLYSRC ======================================================= */ +#define PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_Pos (2UL) /*!< SWITCH_LDO_IN_SLEEP (Bit 2) */ +#define PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_Msk (0x4UL) /*!< SWITCH_LDO_IN_SLEEP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SUPPLYSRC_COREBUCKEN_Pos (1UL) /*!< COREBUCKEN (Bit 1) */ +#define PWRCTRL_SUPPLYSRC_COREBUCKEN_Msk (0x2UL) /*!< COREBUCKEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SUPPLYSRC_MEMBUCKEN_Pos (0UL) /*!< MEMBUCKEN (Bit 0) */ +#define PWRCTRL_SUPPLYSRC_MEMBUCKEN_Msk (0x1UL) /*!< MEMBUCKEN (Bitfield-Mask: 0x01) */ +/* ====================================================== POWERSTATUS ====================================================== */ +#define PWRCTRL_POWERSTATUS_COREBUCKON_Pos (1UL) /*!< COREBUCKON (Bit 1) */ +#define PWRCTRL_POWERSTATUS_COREBUCKON_Msk (0x2UL) /*!< COREBUCKON (Bitfield-Mask: 0x01) */ +#define PWRCTRL_POWERSTATUS_MEMBUCKON_Pos (0UL) /*!< MEMBUCKON (Bit 0) */ +#define PWRCTRL_POWERSTATUS_MEMBUCKON_Msk (0x1UL) /*!< MEMBUCKON (Bitfield-Mask: 0x01) */ +/* ======================================================= DEVICEEN ======================================================== */ +#define PWRCTRL_DEVICEEN_PWRPDM_Pos (10UL) /*!< PWRPDM (Bit 10) */ +#define PWRCTRL_DEVICEEN_PWRPDM_Msk (0x400UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_PWRADC_Pos (9UL) /*!< PWRADC (Bit 9) */ +#define PWRCTRL_DEVICEEN_PWRADC_Msk (0x200UL) /*!< PWRADC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_PWRUART1_Pos (8UL) /*!< PWRUART1 (Bit 8) */ +#define PWRCTRL_DEVICEEN_PWRUART1_Msk (0x100UL) /*!< PWRUART1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_PWRUART0_Pos (7UL) /*!< PWRUART0 (Bit 7) */ +#define PWRCTRL_DEVICEEN_PWRUART0_Msk (0x80UL) /*!< PWRUART0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_MASTER5_Pos (6UL) /*!< IO_MASTER5 (Bit 6) */ +#define PWRCTRL_DEVICEEN_IO_MASTER5_Msk (0x40UL) /*!< IO_MASTER5 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_MASTER4_Pos (5UL) /*!< IO_MASTER4 (Bit 5) */ +#define PWRCTRL_DEVICEEN_IO_MASTER4_Msk (0x20UL) /*!< IO_MASTER4 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_MASTER3_Pos (4UL) /*!< IO_MASTER3 (Bit 4) */ +#define PWRCTRL_DEVICEEN_IO_MASTER3_Msk (0x10UL) /*!< IO_MASTER3 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_MASTER2_Pos (3UL) /*!< IO_MASTER2 (Bit 3) */ +#define PWRCTRL_DEVICEEN_IO_MASTER2_Msk (0x8UL) /*!< IO_MASTER2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_MASTER1_Pos (2UL) /*!< IO_MASTER1 (Bit 2) */ +#define PWRCTRL_DEVICEEN_IO_MASTER1_Msk (0x4UL) /*!< IO_MASTER1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_MASTER0_Pos (1UL) /*!< IO_MASTER0 (Bit 1) */ +#define PWRCTRL_DEVICEEN_IO_MASTER0_Msk (0x2UL) /*!< IO_MASTER0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVICEEN_IO_SLAVE_Pos (0UL) /*!< IO_SLAVE (Bit 0) */ +#define PWRCTRL_DEVICEEN_IO_SLAVE_Msk (0x1UL) /*!< IO_SLAVE (Bitfield-Mask: 0x01) */ +/* ==================================================== SRAMPWDINSLEEP ===================================================== */ +#define PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_Pos (31UL) /*!< CACHE_PWD_SLP (Bit 31) */ +#define PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_Msk (0x80000000UL) /*!< CACHE_PWD_SLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_Pos (0UL) /*!< SRAMSLEEPPOWERDOWN (Bit 0) */ +#define PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_Msk (0x7ffUL) /*!< SRAMSLEEPPOWERDOWN (Bitfield-Mask: 0x7ff) */ +/* ========================================================= MEMEN ========================================================= */ +#define PWRCTRL_MEMEN_CACHEB2_Pos (31UL) /*!< CACHEB2 (Bit 31) */ +#define PWRCTRL_MEMEN_CACHEB2_Msk (0x80000000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMEN_CACHEB0_Pos (29UL) /*!< CACHEB0 (Bit 29) */ +#define PWRCTRL_MEMEN_CACHEB0_Msk (0x20000000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMEN_FLASH1_Pos (12UL) /*!< FLASH1 (Bit 12) */ +#define PWRCTRL_MEMEN_FLASH1_Msk (0x1000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMEN_FLASH0_Pos (11UL) /*!< FLASH0 (Bit 11) */ +#define PWRCTRL_MEMEN_FLASH0_Msk (0x800UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMEN_SRAMEN_Pos (0UL) /*!< SRAMEN (Bit 0) */ +#define PWRCTRL_MEMEN_SRAMEN_Msk (0x7ffUL) /*!< SRAMEN (Bitfield-Mask: 0x7ff) */ +/* ====================================================== PWRONSTATUS ====================================================== */ +#define PWRCTRL_PWRONSTATUS_PD_CACHEB2_Pos (21UL) /*!< PD_CACHEB2 (Bit 21) */ +#define PWRCTRL_PWRONSTATUS_PD_CACHEB2_Msk (0x200000UL) /*!< PD_CACHEB2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_CACHEB0_Pos (19UL) /*!< PD_CACHEB0 (Bit 19) */ +#define PWRCTRL_PWRONSTATUS_PD_CACHEB0_Msk (0x80000UL) /*!< PD_CACHEB0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_Pos (18UL) /*!< PD_GRP7_SRAM (Bit 18) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_Msk (0x40000UL) /*!< PD_GRP7_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_Pos (17UL) /*!< PD_GRP6_SRAM (Bit 17) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_Msk (0x20000UL) /*!< PD_GRP6_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_Pos (16UL) /*!< PD_GRP5_SRAM (Bit 16) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_Msk (0x10000UL) /*!< PD_GRP5_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_Pos (15UL) /*!< PD_GRP4_SRAM (Bit 15) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_Msk (0x8000UL) /*!< PD_GRP4_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_Pos (14UL) /*!< PD_GRP3_SRAM (Bit 14) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_Msk (0x4000UL) /*!< PD_GRP3_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_Pos (13UL) /*!< PD_GRP2_SRAM (Bit 13) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_Msk (0x2000UL) /*!< PD_GRP2_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_Pos (12UL) /*!< PD_GRP1_SRAM (Bit 12) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_Msk (0x1000UL) /*!< PD_GRP1_SRAM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_Pos (11UL) /*!< PD_GRP0_SRAM3 (Bit 11) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_Msk (0x800UL) /*!< PD_GRP0_SRAM3 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_Pos (10UL) /*!< PD_GRP0_SRAM2 (Bit 10) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_Msk (0x400UL) /*!< PD_GRP0_SRAM2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_Pos (9UL) /*!< PD_GRP0_SRAM1 (Bit 9) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_Msk (0x200UL) /*!< PD_GRP0_SRAM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_Pos (8UL) /*!< PD_GRP0_SRAM0 (Bit 8) */ +#define PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_Msk (0x100UL) /*!< PD_GRP0_SRAM0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PDADC_Pos (7UL) /*!< PDADC (Bit 7) */ +#define PWRCTRL_PWRONSTATUS_PDADC_Msk (0x80UL) /*!< PDADC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_FLAM1_Pos (6UL) /*!< PD_FLAM1 (Bit 6) */ +#define PWRCTRL_PWRONSTATUS_PD_FLAM1_Msk (0x40UL) /*!< PD_FLAM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_FLAM0_Pos (5UL) /*!< PD_FLAM0 (Bit 5) */ +#define PWRCTRL_PWRONSTATUS_PD_FLAM0_Msk (0x20UL) /*!< PD_FLAM0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PD_PDM_Pos (4UL) /*!< PD_PDM (Bit 4) */ +#define PWRCTRL_PWRONSTATUS_PD_PDM_Msk (0x10UL) /*!< PD_PDM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PDC_Pos (3UL) /*!< PDC (Bit 3) */ +#define PWRCTRL_PWRONSTATUS_PDC_Msk (0x8UL) /*!< PDC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PDB_Pos (2UL) /*!< PDB (Bit 2) */ +#define PWRCTRL_PWRONSTATUS_PDB_Msk (0x4UL) /*!< PDB (Bitfield-Mask: 0x01) */ +#define PWRCTRL_PWRONSTATUS_PDA_Pos (1UL) /*!< PDA (Bit 1) */ +#define PWRCTRL_PWRONSTATUS_PDA_Msk (0x2UL) /*!< PDA (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMCTRL ======================================================== */ +#define PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_Pos (2UL) /*!< SRAM_MASTER_CLKGATE (Bit 2) */ +#define PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_Msk (0x4UL) /*!< SRAM_MASTER_CLKGATE (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SRAMCTRL_SRAM_CLKGATE_Pos (1UL) /*!< SRAM_CLKGATE (Bit 1) */ +#define PWRCTRL_SRAMCTRL_SRAM_CLKGATE_Msk (0x2UL) /*!< SRAM_CLKGATE (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_Pos (0UL) /*!< SRAM_LIGHT_SLEEP (Bit 0) */ +#define PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_Msk (0x1UL) /*!< SRAM_LIGHT_SLEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCSTATUS ======================================================= */ +#define PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_Pos (5UL) /*!< ADC_REFBUF_PWD (Bit 5) */ +#define PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_Msk (0x20UL) /*!< ADC_REFBUF_PWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_Pos (4UL) /*!< ADC_REFKEEP_PWD (Bit 4) */ +#define PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_Msk (0x10UL) /*!< ADC_REFKEEP_PWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_Pos (3UL) /*!< ADC_VBAT_PWD (Bit 3) */ +#define PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_Msk (0x8UL) /*!< ADC_VBAT_PWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_Pos (2UL) /*!< ADC_VPTAT_PWD (Bit 2) */ +#define PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_Msk (0x4UL) /*!< ADC_VPTAT_PWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADC_BGT_PWD_Pos (1UL) /*!< ADC_BGT_PWD (Bit 1) */ +#define PWRCTRL_ADCSTATUS_ADC_BGT_PWD_Msk (0x2UL) /*!< ADC_BGT_PWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADC_PWD_Pos (0UL) /*!< ADC_PWD (Bit 0) */ +#define PWRCTRL_ADCSTATUS_ADC_PWD_Msk (0x1UL) /*!< ADC_PWD (Bitfield-Mask: 0x01) */ +/* ======================================================== MISCOPT ======================================================== */ +#define PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_Pos (2UL) /*!< DIS_LDOLPMODE_TIMERS (Bit 2) */ +#define PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_Msk (0x4UL) /*!< DIS_LDOLPMODE_TIMERS (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define RSTGEN_CFG_WDREN_Pos (1UL) /*!< WDREN (Bit 1) */ +#define RSTGEN_CFG_WDREN_Msk (0x2UL) /*!< WDREN (Bitfield-Mask: 0x01) */ +#define RSTGEN_CFG_BODHREN_Pos (0UL) /*!< BODHREN (Bit 0) */ +#define RSTGEN_CFG_BODHREN_Msk (0x1UL) /*!< BODHREN (Bitfield-Mask: 0x01) */ +/* ========================================================= SWPOI ========================================================= */ +#define RSTGEN_SWPOI_SWPOIKEY_Pos (0UL) /*!< SWPOIKEY (Bit 0) */ +#define RSTGEN_SWPOI_SWPOIKEY_Msk (0xffUL) /*!< SWPOIKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= SWPOR ========================================================= */ +#define RSTGEN_SWPOR_SWPORKEY_Pos (0UL) /*!< SWPORKEY (Bit 0) */ +#define RSTGEN_SWPOR_SWPORKEY_Msk (0xffUL) /*!< SWPORKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= STAT ========================================================== */ +#define RSTGEN_STAT_WDRSTAT_Pos (6UL) /*!< WDRSTAT (Bit 6) */ +#define RSTGEN_STAT_WDRSTAT_Msk (0x40UL) /*!< WDRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_DBGRSTAT_Pos (5UL) /*!< DBGRSTAT (Bit 5) */ +#define RSTGEN_STAT_DBGRSTAT_Msk (0x20UL) /*!< DBGRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_POIRSTAT_Pos (4UL) /*!< POIRSTAT (Bit 4) */ +#define RSTGEN_STAT_POIRSTAT_Msk (0x10UL) /*!< POIRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_SWRSTAT_Pos (3UL) /*!< SWRSTAT (Bit 3) */ +#define RSTGEN_STAT_SWRSTAT_Msk (0x8UL) /*!< SWRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BORSTAT_Pos (2UL) /*!< BORSTAT (Bit 2) */ +#define RSTGEN_STAT_BORSTAT_Msk (0x4UL) /*!< BORSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_PORSTAT_Pos (1UL) /*!< PORSTAT (Bit 1) */ +#define RSTGEN_STAT_PORSTAT_Msk (0x2UL) /*!< PORSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_EXRSTAT_Pos (0UL) /*!< EXRSTAT (Bit 0) */ +#define RSTGEN_STAT_EXRSTAT_Msk (0x1UL) /*!< EXRSTAT (Bitfield-Mask: 0x01) */ +/* ======================================================== CLRSTAT ======================================================== */ +#define RSTGEN_CLRSTAT_CLRSTAT_Pos (0UL) /*!< CLRSTAT (Bit 0) */ +#define RSTGEN_CLRSTAT_CLRSTAT_Msk (0x1UL) /*!< CLRSTAT (Bitfield-Mask: 0x01) */ +/* ======================================================= TPIU_RST ======================================================== */ +#define RSTGEN_TPIU_RST_TPIURST_Pos (0UL) /*!< TPIURST (Bit 0) */ +#define RSTGEN_TPIU_RST_TPIURST_Msk (0x1UL) /*!< TPIURST (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define RSTGEN_INTEN_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTEN_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define RSTGEN_INTSTAT_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTSTAT_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define RSTGEN_INTCLR_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTCLR_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define RSTGEN_INTSET_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTSET_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLOW ========================================================= */ +#define RTC_CTRLOW_CTRHR_Pos (24UL) /*!< CTRHR (Bit 24) */ +#define RTC_CTRLOW_CTRHR_Msk (0x3f000000UL) /*!< CTRHR (Bitfield-Mask: 0x3f) */ +#define RTC_CTRLOW_CTRMIN_Pos (16UL) /*!< CTRMIN (Bit 16) */ +#define RTC_CTRLOW_CTRMIN_Msk (0x7f0000UL) /*!< CTRMIN (Bitfield-Mask: 0x7f) */ +#define RTC_CTRLOW_CTRSEC_Pos (8UL) /*!< CTRSEC (Bit 8) */ +#define RTC_CTRLOW_CTRSEC_Msk (0x7f00UL) /*!< CTRSEC (Bitfield-Mask: 0x7f) */ +#define RTC_CTRLOW_CTR100_Pos (0UL) /*!< CTR100 (Bit 0) */ +#define RTC_CTRLOW_CTR100_Msk (0xffUL) /*!< CTR100 (Bitfield-Mask: 0xff) */ +/* ========================================================= CTRUP ========================================================= */ +#define RTC_CTRUP_CTERR_Pos (31UL) /*!< CTERR (Bit 31) */ +#define RTC_CTRUP_CTERR_Msk (0x80000000UL) /*!< CTERR (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CEB_Pos (28UL) /*!< CEB (Bit 28) */ +#define RTC_CTRUP_CEB_Msk (0x10000000UL) /*!< CEB (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CB_Pos (27UL) /*!< CB (Bit 27) */ +#define RTC_CTRUP_CB_Msk (0x8000000UL) /*!< CB (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CTRWKDY_Pos (24UL) /*!< CTRWKDY (Bit 24) */ +#define RTC_CTRUP_CTRWKDY_Msk (0x7000000UL) /*!< CTRWKDY (Bitfield-Mask: 0x07) */ +#define RTC_CTRUP_CTRYR_Pos (16UL) /*!< CTRYR (Bit 16) */ +#define RTC_CTRUP_CTRYR_Msk (0xff0000UL) /*!< CTRYR (Bitfield-Mask: 0xff) */ +#define RTC_CTRUP_CTRMO_Pos (8UL) /*!< CTRMO (Bit 8) */ +#define RTC_CTRUP_CTRMO_Msk (0x1f00UL) /*!< CTRMO (Bitfield-Mask: 0x1f) */ +#define RTC_CTRUP_CTRDATE_Pos (0UL) /*!< CTRDATE (Bit 0) */ +#define RTC_CTRUP_CTRDATE_Msk (0x3fUL) /*!< CTRDATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== ALMLOW ========================================================= */ +#define RTC_ALMLOW_ALMHR_Pos (24UL) /*!< ALMHR (Bit 24) */ +#define RTC_ALMLOW_ALMHR_Msk (0x3f000000UL) /*!< ALMHR (Bitfield-Mask: 0x3f) */ +#define RTC_ALMLOW_ALMMIN_Pos (16UL) /*!< ALMMIN (Bit 16) */ +#define RTC_ALMLOW_ALMMIN_Msk (0x7f0000UL) /*!< ALMMIN (Bitfield-Mask: 0x7f) */ +#define RTC_ALMLOW_ALMSEC_Pos (8UL) /*!< ALMSEC (Bit 8) */ +#define RTC_ALMLOW_ALMSEC_Msk (0x7f00UL) /*!< ALMSEC (Bitfield-Mask: 0x7f) */ +#define RTC_ALMLOW_ALM100_Pos (0UL) /*!< ALM100 (Bit 0) */ +#define RTC_ALMLOW_ALM100_Msk (0xffUL) /*!< ALM100 (Bitfield-Mask: 0xff) */ +/* ========================================================= ALMUP ========================================================= */ +#define RTC_ALMUP_ALMWKDY_Pos (16UL) /*!< ALMWKDY (Bit 16) */ +#define RTC_ALMUP_ALMWKDY_Msk (0x70000UL) /*!< ALMWKDY (Bitfield-Mask: 0x07) */ +#define RTC_ALMUP_ALMMO_Pos (8UL) /*!< ALMMO (Bit 8) */ +#define RTC_ALMUP_ALMMO_Msk (0x1f00UL) /*!< ALMMO (Bitfield-Mask: 0x1f) */ +#define RTC_ALMUP_ALMDATE_Pos (0UL) /*!< ALMDATE (Bit 0) */ +#define RTC_ALMUP_ALMDATE_Msk (0x3fUL) /*!< ALMDATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== RTCCTL ========================================================= */ +#define RTC_RTCCTL_HR1224_Pos (5UL) /*!< HR1224 (Bit 5) */ +#define RTC_RTCCTL_HR1224_Msk (0x20UL) /*!< HR1224 (Bitfield-Mask: 0x01) */ +#define RTC_RTCCTL_RSTOP_Pos (4UL) /*!< RSTOP (Bit 4) */ +#define RTC_RTCCTL_RSTOP_Msk (0x10UL) /*!< RSTOP (Bitfield-Mask: 0x01) */ +#define RTC_RTCCTL_RPT_Pos (1UL) /*!< RPT (Bit 1) */ +#define RTC_RTCCTL_RPT_Msk (0xeUL) /*!< RPT (Bitfield-Mask: 0x07) */ +#define RTC_RTCCTL_WRTC_Pos (0UL) /*!< WRTC (Bit 0) */ +#define RTC_RTCCTL_WRTC_Msk (0x1UL) /*!< WRTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define RTC_INTEN_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define RTC_INTEN_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define RTC_INTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define RTC_INTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define RTC_INTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define RTC_INTSTAT_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define RTC_INTSTAT_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define RTC_INTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define RTC_INTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define RTC_INTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define RTC_INTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define RTC_INTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define RTC_INTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define RTC_INTCLR_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define RTC_INTCLR_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define RTC_INTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define RTC_INTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define RTC_INTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define RTC_INTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define RTC_INTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define RTC_INTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define RTC_INTSET_ALM_Pos (3UL) /*!< ALM (Bit 3) */ +#define RTC_INTSET_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */ +#define RTC_INTSET_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define RTC_INTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define RTC_INTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define RTC_INTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define RTC_INTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define RTC_INTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DR =========================================================== */ +#define UART0_DR_OEDATA_Pos (11UL) /*!< OEDATA (Bit 11) */ +#define UART0_DR_OEDATA_Msk (0x800UL) /*!< OEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_BEDATA_Pos (10UL) /*!< BEDATA (Bit 10) */ +#define UART0_DR_BEDATA_Msk (0x400UL) /*!< BEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_PEDATA_Pos (9UL) /*!< PEDATA (Bit 9) */ +#define UART0_DR_PEDATA_Msk (0x200UL) /*!< PEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_FEDATA_Pos (8UL) /*!< FEDATA (Bit 8) */ +#define UART0_DR_FEDATA_Msk (0x100UL) /*!< FEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define UART0_DR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== RSR ========================================================== */ +#define UART0_RSR_OESTAT_Pos (3UL) /*!< OESTAT (Bit 3) */ +#define UART0_RSR_OESTAT_Msk (0x8UL) /*!< OESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_BESTAT_Pos (2UL) /*!< BESTAT (Bit 2) */ +#define UART0_RSR_BESTAT_Msk (0x4UL) /*!< BESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_PESTAT_Pos (1UL) /*!< PESTAT (Bit 1) */ +#define UART0_RSR_PESTAT_Msk (0x2UL) /*!< PESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_FESTAT_Pos (0UL) /*!< FESTAT (Bit 0) */ +#define UART0_RSR_FESTAT_Msk (0x1UL) /*!< FESTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== FR =========================================================== */ +#define UART0_FR_TXBUSY_Pos (8UL) /*!< TXBUSY (Bit 8) */ +#define UART0_FR_TXBUSY_Msk (0x100UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UART0_FR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define UART0_FR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define UART0_FR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ +#define UART0_FR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ +#define UART0_FR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ +#define UART0_FR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ +#define UART0_FR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ +#define UART0_FR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +#define UART0_FR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ +#define UART0_FR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define UART0_FR_DCD_Pos (2UL) /*!< DCD (Bit 2) */ +#define UART0_FR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ +#define UART0_FR_DSR_Pos (1UL) /*!< DSR (Bit 1) */ +#define UART0_FR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ +#define UART0_FR_CTS_Pos (0UL) /*!< CTS (Bit 0) */ +#define UART0_FR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ========================================================= ILPR ========================================================== */ +#define UART0_ILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */ +#define UART0_ILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */ +/* ========================================================= IBRD ========================================================== */ +#define UART0_IBRD_DIVINT_Pos (0UL) /*!< DIVINT (Bit 0) */ +#define UART0_IBRD_DIVINT_Msk (0xffffUL) /*!< DIVINT (Bitfield-Mask: 0xffff) */ +/* ========================================================= FBRD ========================================================== */ +#define UART0_FBRD_DIVFRAC_Pos (0UL) /*!< DIVFRAC (Bit 0) */ +#define UART0_FBRD_DIVFRAC_Msk (0x3fUL) /*!< DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ========================================================= LCRH ========================================================== */ +#define UART0_LCRH_SPS_Pos (7UL) /*!< SPS (Bit 7) */ +#define UART0_LCRH_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ +#define UART0_LCRH_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ +#define UART0_LCRH_FEN_Pos (4UL) /*!< FEN (Bit 4) */ +#define UART0_LCRH_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ +#define UART0_LCRH_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_EPS_Pos (2UL) /*!< EPS (Bit 2) */ +#define UART0_LCRH_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_PEN_Pos (1UL) /*!< PEN (Bit 1) */ +#define UART0_LCRH_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_BRK_Pos (0UL) /*!< BRK (Bit 0) */ +#define UART0_LCRH_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ========================================================== CR =========================================================== */ +#define UART0_CR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */ +#define UART0_CR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */ +#define UART0_CR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */ +#define UART0_CR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */ +#define UART0_CR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */ +#define UART0_CR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */ +#define UART0_CR_RTS_Pos (11UL) /*!< RTS (Bit 11) */ +#define UART0_CR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ +#define UART0_CR_DTR_Pos (10UL) /*!< DTR (Bit 10) */ +#define UART0_CR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define UART0_CR_RXE_Pos (9UL) /*!< RXE (Bit 9) */ +#define UART0_CR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ +#define UART0_CR_TXE_Pos (8UL) /*!< TXE (Bit 8) */ +#define UART0_CR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define UART0_CR_LBE_Pos (7UL) /*!< LBE (Bit 7) */ +#define UART0_CR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ +#define UART0_CR_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ +#define UART0_CR_CLKSEL_Msk (0x70UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define UART0_CR_CLKEN_Pos (3UL) /*!< CLKEN (Bit 3) */ +#define UART0_CR_CLKEN_Msk (0x8UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */ +#define UART0_CR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */ +#define UART0_CR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */ +#define UART0_CR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */ +#define UART0_CR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ +#define UART0_CR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IFLS ========================================================== */ +#define UART0_IFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ +#define UART0_IFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ +#define UART0_IFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ +#define UART0_IFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define UART0_IER_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ +#define UART0_IER_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ +#define UART0_IER_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ +#define UART0_IER_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ +#define UART0_IER_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ +#define UART0_IER_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ +#define UART0_IER_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ +#define UART0_IER_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ +#define UART0_IER_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ +#define UART0_IER_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ +#define UART0_IER_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_TXCMPMIM_Pos (0UL) /*!< TXCMPMIM (Bit 0) */ +#define UART0_IER_TXCMPMIM_Msk (0x1UL) /*!< TXCMPMIM (Bitfield-Mask: 0x01) */ +/* ========================================================== IES ========================================================== */ +#define UART0_IES_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ +#define UART0_IES_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ +#define UART0_IES_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ +#define UART0_IES_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ +#define UART0_IES_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ +#define UART0_IES_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ +#define UART0_IES_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ +#define UART0_IES_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_DSRMRIS_Pos (3UL) /*!< DSRMRIS (Bit 3) */ +#define UART0_IES_DSRMRIS_Msk (0x8UL) /*!< DSRMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_DCDMRIS_Pos (2UL) /*!< DCDMRIS (Bit 2) */ +#define UART0_IES_DCDMRIS_Msk (0x4UL) /*!< DCDMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_CTSMRIS_Pos (1UL) /*!< CTSMRIS (Bit 1) */ +#define UART0_IES_CTSMRIS_Msk (0x2UL) /*!< CTSMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_TXCMPMRIS_Pos (0UL) /*!< TXCMPMRIS (Bit 0) */ +#define UART0_IES_TXCMPMRIS_Msk (0x1UL) /*!< TXCMPMRIS (Bitfield-Mask: 0x01) */ +/* ========================================================== MIS ========================================================== */ +#define UART0_MIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ +#define UART0_MIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ +#define UART0_MIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ +#define UART0_MIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ +#define UART0_MIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ +#define UART0_MIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ +#define UART0_MIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ +#define UART0_MIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ +#define UART0_MIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ +#define UART0_MIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ +#define UART0_MIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_TXCMPMMIS_Pos (0UL) /*!< TXCMPMMIS (Bit 0) */ +#define UART0_MIS_TXCMPMMIS_Msk (0x1UL) /*!< TXCMPMMIS (Bitfield-Mask: 0x01) */ +/* ========================================================== IEC ========================================================== */ +#define UART0_IEC_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ +#define UART0_IEC_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ +#define UART0_IEC_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ +#define UART0_IEC_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ +#define UART0_IEC_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ +#define UART0_IEC_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ +#define UART0_IEC_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ +#define UART0_IEC_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ +#define UART0_IEC_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ +#define UART0_IEC_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ +#define UART0_IEC_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_TXCMPMIC_Pos (0UL) /*!< TXCMPMIC (Bit 0) */ +#define UART0_IEC_TXCMPMIC_Msk (0x1UL) /*!< TXCMPMIC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define VCOMP_CFG_LVLSEL_Pos (16UL) /*!< LVLSEL (Bit 16) */ +#define VCOMP_CFG_LVLSEL_Msk (0xf0000UL) /*!< LVLSEL (Bitfield-Mask: 0x0f) */ +#define VCOMP_CFG_NSEL_Pos (8UL) /*!< NSEL (Bit 8) */ +#define VCOMP_CFG_NSEL_Msk (0x300UL) /*!< NSEL (Bitfield-Mask: 0x03) */ +#define VCOMP_CFG_PSEL_Pos (0UL) /*!< PSEL (Bit 0) */ +#define VCOMP_CFG_PSEL_Msk (0x3UL) /*!< PSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= STAT ========================================================== */ +#define VCOMP_STAT_PWDSTAT_Pos (1UL) /*!< PWDSTAT (Bit 1) */ +#define VCOMP_STAT_PWDSTAT_Msk (0x2UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */ +#define VCOMP_STAT_CMPOUT_Pos (0UL) /*!< CMPOUT (Bit 0) */ +#define VCOMP_STAT_CMPOUT_Msk (0x1UL) /*!< CMPOUT (Bitfield-Mask: 0x01) */ +/* ======================================================== PWDKEY ========================================================= */ +#define VCOMP_PWDKEY_PWDKEY_Pos (0UL) /*!< PWDKEY (Bit 0) */ +#define VCOMP_PWDKEY_PWDKEY_Msk (0xffffffffUL) /*!< PWDKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTEN ========================================================= */ +#define VCOMP_INTEN_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTEN_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTEN_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTEN_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define VCOMP_INTSTAT_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTSTAT_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTSTAT_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTSTAT_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define VCOMP_INTCLR_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTCLR_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTCLR_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTCLR_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define VCOMP_INTSET_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTSET_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTSET_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTSET_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define WDT_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */ +#define WDT_CFG_CLKSEL_Msk (0x7000000UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define WDT_CFG_INTVAL_Pos (16UL) /*!< INTVAL (Bit 16) */ +#define WDT_CFG_INTVAL_Msk (0xff0000UL) /*!< INTVAL (Bitfield-Mask: 0xff) */ +#define WDT_CFG_RESVAL_Pos (8UL) /*!< RESVAL (Bit 8) */ +#define WDT_CFG_RESVAL_Msk (0xff00UL) /*!< RESVAL (Bitfield-Mask: 0xff) */ +#define WDT_CFG_RESEN_Pos (2UL) /*!< RESEN (Bit 2) */ +#define WDT_CFG_RESEN_Msk (0x4UL) /*!< RESEN (Bitfield-Mask: 0x01) */ +#define WDT_CFG_INTEN_Pos (1UL) /*!< INTEN (Bit 1) */ +#define WDT_CFG_INTEN_Msk (0x2UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +#define WDT_CFG_WDTEN_Pos (0UL) /*!< WDTEN (Bit 0) */ +#define WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTRT ========================================================= */ +#define WDT_RSTRT_RSTRT_Pos (0UL) /*!< RSTRT (Bit 0) */ +#define WDT_RSTRT_RSTRT_Msk (0xffUL) /*!< RSTRT (Bitfield-Mask: 0xff) */ +/* ========================================================= LOCK ========================================================== */ +#define WDT_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ +#define WDT_LOCK_LOCK_Msk (0xffUL) /*!< LOCK (Bitfield-Mask: 0xff) */ +/* ========================================================= COUNT ========================================================= */ +#define WDT_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define WDT_COUNT_COUNT_Msk (0xffUL) /*!< COUNT (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define WDT_INTEN_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTEN_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define WDT_INTSTAT_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTSTAT_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define WDT_INTCLR_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTCLR_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define WDT_INTSET_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTSET_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Enumerated Values Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup EnumValue_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ================================================ ADC CFG CLKSEL [24..25] ================================================ */ +typedef enum { /*!< ADC_CFG_CLKSEL */ + ADC_CFG_CLKSEL_OFF = 0, /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected + for the ADC to function. The ADC controller + automatically shuts off the clock in it's + low power modes. When setting ADCEN to '0', + the CLKSEL should remain set to one of the + two clock selects for proper power down + sequencing. */ + ADC_CFG_CLKSEL_HFRC = 1, /*!< HFRC : HFRC Core Clock Frequency */ + ADC_CFG_CLKSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : HFRC Core Clock / 2 */ +} ADC_CFG_CLKSEL_Enum; + +/* =============================================== ADC CFG TRIGPOL [19..19] ================================================ */ +typedef enum { /*!< ADC_CFG_TRIGPOL */ + ADC_CFG_TRIGPOL_RISING_EDGE = 0, /*!< RISING_EDGE : Trigger on rising edge. */ + ADC_CFG_TRIGPOL_FALLING_EDGE = 1, /*!< FALLING_EDGE : Trigger on falling edge. */ +} ADC_CFG_TRIGPOL_Enum; + +/* =============================================== ADC CFG TRIGSEL [16..18] ================================================ */ +typedef enum { /*!< ADC_CFG_TRIGSEL */ + ADC_CFG_TRIGSEL_EXT0 = 0, /*!< EXT0 : Off chip External Trigger0 (ADC_ET0) */ + ADC_CFG_TRIGSEL_EXT1 = 1, /*!< EXT1 : Off chip External Trigger1 (ADC_ET1) */ + ADC_CFG_TRIGSEL_EXT2 = 2, /*!< EXT2 : Off chip External Trigger2 (ADC_ET2) */ + ADC_CFG_TRIGSEL_EXT3 = 3, /*!< EXT3 : Off chip External Trigger3 (ADC_ET3) */ + ADC_CFG_TRIGSEL_VCOMP = 4, /*!< VCOMP : Voltage Comparator Output */ + ADC_CFG_TRIGSEL_SWT = 7, /*!< SWT : Software Trigger */ +} ADC_CFG_TRIGSEL_Enum; + +/* ================================================= ADC CFG REFSEL [8..9] ================================================= */ +typedef enum { /*!< ADC_CFG_REFSEL */ + ADC_CFG_REFSEL_INT2P0 = 0, /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage */ + ADC_CFG_REFSEL_INT1P5 = 1, /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage */ + ADC_CFG_REFSEL_EXT2P0 = 2, /*!< EXT2P0 : Off Chip 2.0V Reference */ + ADC_CFG_REFSEL_EXT1P5 = 3, /*!< EXT1P5 : Off Chip 1.5V Reference */ +} ADC_CFG_REFSEL_Enum; + +/* ================================================= ADC CFG CKMODE [4..4] ================================================= */ +typedef enum { /*!< ADC_CFG_CKMODE */ + ADC_CFG_CKMODE_LPCKMODE = 0, /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set + LPCKMODE to 0x1 while configuring the ADC. */ + ADC_CFG_CKMODE_LLCKMODE = 1, /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk + will remain on while in functioning in LPMODE0. */ +} ADC_CFG_CKMODE_Enum; + +/* ================================================= ADC CFG LPMODE [3..3] ================================================= */ +typedef enum { /*!< ADC_CFG_LPMODE */ + ADC_CFG_LPMODE_MODE0 = 0, /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between + scans with minimum latency between a trigger event and + sample data collection. */ + ADC_CFG_LPMODE_MODE1 = 1, /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks + associated with the ADC until the next trigger event. Between + scans, the reference buffer requires up to 50us of delay + from a scan trigger event before the conversion will commence + while operating in this mode. */ +} ADC_CFG_LPMODE_Enum; + +/* ================================================= ADC CFG RPTEN [2..2] ================================================== */ +typedef enum { /*!< ADC_CFG_RPTEN */ + ADC_CFG_RPTEN_SINGLE_SCAN = 0, /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single + scan upon each trigger event. */ + ADC_CFG_RPTEN_REPEATING_SCAN = 1, /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete + it's first scan upon the initial trigger event and all + subsequent scans will occur at regular intervals defined + by the configuration programmed for the CTTMRA3 internal + timer until the timer is disabled or the ADC is disabled. + When disabling the ADC (setting ADCEN to '0'), the RPTEN + bit should be cleared. */ +} ADC_CFG_RPTEN_Enum; + +/* ================================================= ADC CFG ADCEN [0..0] ================================================== */ +typedef enum { /*!< ADC_CFG_ADCEN */ + ADC_CFG_ADCEN_DIS = 0, /*!< DIS : Disable the ADC module. */ + ADC_CFG_ADCEN_EN = 1, /*!< EN : Enable the ADC module. */ +} ADC_CFG_ADCEN_Enum; + +/* ========================================================= STAT ========================================================== */ +/* ================================================ ADC STAT PWDSTAT [0..0] ================================================ */ +typedef enum { /*!< ADC_STAT_PWDSTAT */ + ADC_STAT_PWDSTAT_ON = 0, /*!< ON : Powered on. */ + ADC_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : ADC Low Power Mode 1. */ +} ADC_STAT_PWDSTAT_Enum; + +/* ========================================================== SWT ========================================================== */ +/* ================================================== ADC SWT SWT [0..7] =================================================== */ +typedef enum { /*!< ADC_SWT_SWT */ + ADC_SWT_SWT_GEN_SW_TRIGGER = 55, /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger. */ +} ADC_SWT_SWT_Enum; + +/* ======================================================== SL0CFG ========================================================= */ +/* ============================================== ADC SL0CFG ADSEL0 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL0CFG_ADSEL0 */ + ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL0CFG_ADSEL0_Enum; + +/* ============================================== ADC SL0CFG PRMODE0 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL0CFG_PRMODE0 */ + ADC_SL0CFG_PRMODE0_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL0CFG_PRMODE0_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL0CFG_PRMODE0_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL0CFG_PRMODE0_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL0CFG_PRMODE0_Enum; + +/* =============================================== ADC SL0CFG CHSEL0 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL0CFG_CHSEL0 */ + ADC_SL0CFG_CHSEL0_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL0CFG_CHSEL0_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL0CFG_CHSEL0_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL0CFG_CHSEL0_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL0CFG_CHSEL0_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL0CFG_CHSEL0_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL0CFG_CHSEL0_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL0CFG_CHSEL0_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL0CFG_CHSEL0_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL0CFG_CHSEL0_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL0CFG_CHSEL0_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL0CFG_CHSEL0_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL0CFG_CHSEL0_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL0CFG_CHSEL0_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL0CFG_CHSEL0_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL0CFG_CHSEL0_Enum; + +/* ================================================ ADC SL0CFG WCEN0 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL0CFG_WCEN0 */ + ADC_SL0CFG_WCEN0_WCEN = 1, /*!< WCEN : Enable the window compare for slot 0. */ +} ADC_SL0CFG_WCEN0_Enum; + +/* ================================================ ADC SL0CFG SLEN0 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL0CFG_SLEN0 */ + ADC_SL0CFG_SLEN0_SLEN = 1, /*!< SLEN : Enable slot 0 for ADC conversions. */ +} ADC_SL0CFG_SLEN0_Enum; + +/* ======================================================== SL1CFG ========================================================= */ +/* ============================================== ADC SL1CFG ADSEL1 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL1CFG_ADSEL1 */ + ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL1CFG_ADSEL1_Enum; + +/* ============================================== ADC SL1CFG PRMODE1 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL1CFG_PRMODE1 */ + ADC_SL1CFG_PRMODE1_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL1CFG_PRMODE1_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL1CFG_PRMODE1_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL1CFG_PRMODE1_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL1CFG_PRMODE1_Enum; + +/* =============================================== ADC SL1CFG CHSEL1 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL1CFG_CHSEL1 */ + ADC_SL1CFG_CHSEL1_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL1CFG_CHSEL1_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL1CFG_CHSEL1_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL1CFG_CHSEL1_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL1CFG_CHSEL1_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL1CFG_CHSEL1_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL1CFG_CHSEL1_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL1CFG_CHSEL1_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL1CFG_CHSEL1_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL1CFG_CHSEL1_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL1CFG_CHSEL1_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL1CFG_CHSEL1_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL1CFG_CHSEL1_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL1CFG_CHSEL1_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL1CFG_CHSEL1_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL1CFG_CHSEL1_Enum; + +/* ================================================ ADC SL1CFG WCEN1 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL1CFG_WCEN1 */ + ADC_SL1CFG_WCEN1_WCEN = 1, /*!< WCEN : Enable the window compare for slot 1. */ +} ADC_SL1CFG_WCEN1_Enum; + +/* ================================================ ADC SL1CFG SLEN1 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL1CFG_SLEN1 */ + ADC_SL1CFG_SLEN1_SLEN = 1, /*!< SLEN : Enable slot 1 for ADC conversions. */ +} ADC_SL1CFG_SLEN1_Enum; + +/* ======================================================== SL2CFG ========================================================= */ +/* ============================================== ADC SL2CFG ADSEL2 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL2CFG_ADSEL2 */ + ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL2CFG_ADSEL2_Enum; + +/* ============================================== ADC SL2CFG PRMODE2 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL2CFG_PRMODE2 */ + ADC_SL2CFG_PRMODE2_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL2CFG_PRMODE2_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL2CFG_PRMODE2_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL2CFG_PRMODE2_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL2CFG_PRMODE2_Enum; + +/* =============================================== ADC SL2CFG CHSEL2 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL2CFG_CHSEL2 */ + ADC_SL2CFG_CHSEL2_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL2CFG_CHSEL2_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL2CFG_CHSEL2_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL2CFG_CHSEL2_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL2CFG_CHSEL2_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL2CFG_CHSEL2_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL2CFG_CHSEL2_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL2CFG_CHSEL2_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL2CFG_CHSEL2_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL2CFG_CHSEL2_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL2CFG_CHSEL2_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL2CFG_CHSEL2_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL2CFG_CHSEL2_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL2CFG_CHSEL2_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL2CFG_CHSEL2_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL2CFG_CHSEL2_Enum; + +/* ================================================ ADC SL2CFG WCEN2 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL2CFG_WCEN2 */ + ADC_SL2CFG_WCEN2_WCEN = 1, /*!< WCEN : Enable the window compare for slot 2. */ +} ADC_SL2CFG_WCEN2_Enum; + +/* ================================================ ADC SL2CFG SLEN2 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL2CFG_SLEN2 */ + ADC_SL2CFG_SLEN2_SLEN = 1, /*!< SLEN : Enable slot 2 for ADC conversions. */ +} ADC_SL2CFG_SLEN2_Enum; + +/* ======================================================== SL3CFG ========================================================= */ +/* ============================================== ADC SL3CFG ADSEL3 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL3CFG_ADSEL3 */ + ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL3CFG_ADSEL3_Enum; + +/* ============================================== ADC SL3CFG PRMODE3 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL3CFG_PRMODE3 */ + ADC_SL3CFG_PRMODE3_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL3CFG_PRMODE3_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL3CFG_PRMODE3_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL3CFG_PRMODE3_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL3CFG_PRMODE3_Enum; + +/* =============================================== ADC SL3CFG CHSEL3 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL3CFG_CHSEL3 */ + ADC_SL3CFG_CHSEL3_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL3CFG_CHSEL3_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL3CFG_CHSEL3_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL3CFG_CHSEL3_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL3CFG_CHSEL3_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL3CFG_CHSEL3_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL3CFG_CHSEL3_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL3CFG_CHSEL3_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL3CFG_CHSEL3_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL3CFG_CHSEL3_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL3CFG_CHSEL3_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL3CFG_CHSEL3_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL3CFG_CHSEL3_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL3CFG_CHSEL3_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL3CFG_CHSEL3_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL3CFG_CHSEL3_Enum; + +/* ================================================ ADC SL3CFG WCEN3 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL3CFG_WCEN3 */ + ADC_SL3CFG_WCEN3_WCEN = 1, /*!< WCEN : Enable the window compare for slot 3. */ +} ADC_SL3CFG_WCEN3_Enum; + +/* ================================================ ADC SL3CFG SLEN3 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL3CFG_SLEN3 */ + ADC_SL3CFG_SLEN3_SLEN = 1, /*!< SLEN : Enable slot 3 for ADC conversions. */ +} ADC_SL3CFG_SLEN3_Enum; + +/* ======================================================== SL4CFG ========================================================= */ +/* ============================================== ADC SL4CFG ADSEL4 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL4CFG_ADSEL4 */ + ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL4CFG_ADSEL4_Enum; + +/* ============================================== ADC SL4CFG PRMODE4 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL4CFG_PRMODE4 */ + ADC_SL4CFG_PRMODE4_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL4CFG_PRMODE4_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL4CFG_PRMODE4_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL4CFG_PRMODE4_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL4CFG_PRMODE4_Enum; + +/* =============================================== ADC SL4CFG CHSEL4 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL4CFG_CHSEL4 */ + ADC_SL4CFG_CHSEL4_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL4CFG_CHSEL4_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL4CFG_CHSEL4_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL4CFG_CHSEL4_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL4CFG_CHSEL4_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL4CFG_CHSEL4_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL4CFG_CHSEL4_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL4CFG_CHSEL4_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL4CFG_CHSEL4_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL4CFG_CHSEL4_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL4CFG_CHSEL4_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL4CFG_CHSEL4_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL4CFG_CHSEL4_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL4CFG_CHSEL4_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL4CFG_CHSEL4_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL4CFG_CHSEL4_Enum; + +/* ================================================ ADC SL4CFG WCEN4 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL4CFG_WCEN4 */ + ADC_SL4CFG_WCEN4_WCEN = 1, /*!< WCEN : Enable the window compare for slot 4. */ +} ADC_SL4CFG_WCEN4_Enum; + +/* ================================================ ADC SL4CFG SLEN4 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL4CFG_SLEN4 */ + ADC_SL4CFG_SLEN4_SLEN = 1, /*!< SLEN : Enable slot 4 for ADC conversions. */ +} ADC_SL4CFG_SLEN4_Enum; + +/* ======================================================== SL5CFG ========================================================= */ +/* ============================================== ADC SL5CFG ADSEL5 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL5CFG_ADSEL5 */ + ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL5CFG_ADSEL5_Enum; + +/* ============================================== ADC SL5CFG PRMODE5 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL5CFG_PRMODE5 */ + ADC_SL5CFG_PRMODE5_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL5CFG_PRMODE5_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL5CFG_PRMODE5_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL5CFG_PRMODE5_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL5CFG_PRMODE5_Enum; + +/* =============================================== ADC SL5CFG CHSEL5 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL5CFG_CHSEL5 */ + ADC_SL5CFG_CHSEL5_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL5CFG_CHSEL5_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL5CFG_CHSEL5_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL5CFG_CHSEL5_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL5CFG_CHSEL5_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL5CFG_CHSEL5_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL5CFG_CHSEL5_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL5CFG_CHSEL5_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL5CFG_CHSEL5_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL5CFG_CHSEL5_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL5CFG_CHSEL5_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL5CFG_CHSEL5_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL5CFG_CHSEL5_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL5CFG_CHSEL5_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL5CFG_CHSEL5_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL5CFG_CHSEL5_Enum; + +/* ================================================ ADC SL5CFG WCEN5 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL5CFG_WCEN5 */ + ADC_SL5CFG_WCEN5_WCEN = 1, /*!< WCEN : Enable the window compare for slot 5. */ +} ADC_SL5CFG_WCEN5_Enum; + +/* ================================================ ADC SL5CFG SLEN5 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL5CFG_SLEN5 */ + ADC_SL5CFG_SLEN5_SLEN = 1, /*!< SLEN : Enable slot 5 for ADC conversions. */ +} ADC_SL5CFG_SLEN5_Enum; + +/* ======================================================== SL6CFG ========================================================= */ +/* ============================================== ADC SL6CFG ADSEL6 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL6CFG_ADSEL6 */ + ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL6CFG_ADSEL6_Enum; + +/* ============================================== ADC SL6CFG PRMODE6 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL6CFG_PRMODE6 */ + ADC_SL6CFG_PRMODE6_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL6CFG_PRMODE6_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL6CFG_PRMODE6_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL6CFG_PRMODE6_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL6CFG_PRMODE6_Enum; + +/* =============================================== ADC SL6CFG CHSEL6 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL6CFG_CHSEL6 */ + ADC_SL6CFG_CHSEL6_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL6CFG_CHSEL6_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL6CFG_CHSEL6_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL6CFG_CHSEL6_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL6CFG_CHSEL6_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL6CFG_CHSEL6_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL6CFG_CHSEL6_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL6CFG_CHSEL6_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL6CFG_CHSEL6_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL6CFG_CHSEL6_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL6CFG_CHSEL6_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL6CFG_CHSEL6_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL6CFG_CHSEL6_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL6CFG_CHSEL6_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL6CFG_CHSEL6_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL6CFG_CHSEL6_Enum; + +/* ================================================ ADC SL6CFG WCEN6 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL6CFG_WCEN6 */ + ADC_SL6CFG_WCEN6_WCEN = 1, /*!< WCEN : Enable the window compare for slot 6. */ +} ADC_SL6CFG_WCEN6_Enum; + +/* ================================================ ADC SL6CFG SLEN6 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL6CFG_SLEN6 */ + ADC_SL6CFG_SLEN6_SLEN = 1, /*!< SLEN : Enable slot 6 for ADC conversions. */ +} ADC_SL6CFG_SLEN6_Enum; + +/* ======================================================== SL7CFG ========================================================= */ +/* ============================================== ADC SL7CFG ADSEL7 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL7CFG_ADSEL7 */ + ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL7CFG_ADSEL7_Enum; + +/* ============================================== ADC SL7CFG PRMODE7 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL7CFG_PRMODE7 */ + ADC_SL7CFG_PRMODE7_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL7CFG_PRMODE7_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL7CFG_PRMODE7_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL7CFG_PRMODE7_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL7CFG_PRMODE7_Enum; + +/* =============================================== ADC SL7CFG CHSEL7 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL7CFG_CHSEL7 */ + ADC_SL7CFG_CHSEL7_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL7CFG_CHSEL7_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL7CFG_CHSEL7_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL7CFG_CHSEL7_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL7CFG_CHSEL7_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL7CFG_CHSEL7_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL7CFG_CHSEL7_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL7CFG_CHSEL7_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL7CFG_CHSEL7_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL7CFG_CHSEL7_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL7CFG_CHSEL7_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL7CFG_CHSEL7_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL7CFG_CHSEL7_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL7CFG_CHSEL7_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL7CFG_CHSEL7_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL7CFG_CHSEL7_Enum; + +/* ================================================ ADC SL7CFG WCEN7 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL7CFG_WCEN7 */ + ADC_SL7CFG_WCEN7_WCEN = 1, /*!< WCEN : Enable the window compare for slot 7. */ +} ADC_SL7CFG_WCEN7_Enum; + +/* ================================================ ADC SL7CFG SLEN7 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL7CFG_SLEN7 */ + ADC_SL7CFG_SLEN7_SLEN = 1, /*!< SLEN : Enable slot 7 for ADC conversions. */ +} ADC_SL7CFG_SLEN7_Enum; + +/* ========================================================= WULIM ========================================================= */ +/* ========================================================= WLLIM ========================================================= */ +/* ========================================================= FIFO ========================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ================================================ ADC INTEN WCINC [5..5] ================================================= */ +typedef enum { /*!< ADC_INTEN_WCINC */ + ADC_INTEN_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTEN_WCINC_Enum; + +/* ================================================ ADC INTEN WCEXC [4..4] ================================================= */ +typedef enum { /*!< ADC_INTEN_WCEXC */ + ADC_INTEN_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTEN_WCEXC_Enum; + +/* =============================================== ADC INTEN FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTEN_FIFOOVR2 */ + ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTEN_FIFOOVR2_Enum; + +/* =============================================== ADC INTEN FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTEN_FIFOOVR1 */ + ADC_INTEN_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTEN_FIFOOVR1_Enum; + +/* ================================================ ADC INTEN SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTEN_SCNCMP */ + ADC_INTEN_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTEN_SCNCMP_Enum; + +/* ================================================ ADC INTEN CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTEN_CNVCMP */ + ADC_INTEN_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTEN_CNVCMP_Enum; + +/* ======================================================== INTSTAT ======================================================== */ +/* =============================================== ADC INTSTAT WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_WCINC */ + ADC_INTSTAT_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTSTAT_WCINC_Enum; + +/* =============================================== ADC INTSTAT WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_WCEXC */ + ADC_INTSTAT_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTSTAT_WCEXC_Enum; + +/* ============================================== ADC INTSTAT FIFOOVR2 [3..3] ============================================== */ +typedef enum { /*!< ADC_INTSTAT_FIFOOVR2 */ + ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTSTAT_FIFOOVR2_Enum; + +/* ============================================== ADC INTSTAT FIFOOVR1 [2..2] ============================================== */ +typedef enum { /*!< ADC_INTSTAT_FIFOOVR1 */ + ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTSTAT_FIFOOVR1_Enum; + +/* =============================================== ADC INTSTAT SCNCMP [1..1] =============================================== */ +typedef enum { /*!< ADC_INTSTAT_SCNCMP */ + ADC_INTSTAT_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTSTAT_SCNCMP_Enum; + +/* =============================================== ADC INTSTAT CNVCMP [0..0] =============================================== */ +typedef enum { /*!< ADC_INTSTAT_CNVCMP */ + ADC_INTSTAT_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTSTAT_CNVCMP_Enum; + +/* ======================================================== INTCLR ========================================================= */ +/* ================================================ ADC INTCLR WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTCLR_WCINC */ + ADC_INTCLR_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTCLR_WCINC_Enum; + +/* ================================================ ADC INTCLR WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTCLR_WCEXC */ + ADC_INTCLR_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTCLR_WCEXC_Enum; + +/* ============================================== ADC INTCLR FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTCLR_FIFOOVR2 */ + ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTCLR_FIFOOVR2_Enum; + +/* ============================================== ADC INTCLR FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTCLR_FIFOOVR1 */ + ADC_INTCLR_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTCLR_FIFOOVR1_Enum; + +/* =============================================== ADC INTCLR SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTCLR_SCNCMP */ + ADC_INTCLR_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTCLR_SCNCMP_Enum; + +/* =============================================== ADC INTCLR CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTCLR_CNVCMP */ + ADC_INTCLR_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTCLR_CNVCMP_Enum; + +/* ======================================================== INTSET ========================================================= */ +/* ================================================ ADC INTSET WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTSET_WCINC */ + ADC_INTSET_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTSET_WCINC_Enum; + +/* ================================================ ADC INTSET WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTSET_WCEXC */ + ADC_INTSET_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTSET_WCEXC_Enum; + +/* ============================================== ADC INTSET FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTSET_FIFOOVR2 */ + ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTSET_FIFOOVR2_Enum; + +/* ============================================== ADC INTSET FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTSET_FIFOOVR1 */ + ADC_INTSET_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTSET_FIFOOVR1_Enum; + +/* =============================================== ADC INTSET SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTSET_SCNCMP */ + ADC_INTSET_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTSET_SCNCMP_Enum; + +/* =============================================== ADC INTSET CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTSET_CNVCMP */ + ADC_INTSET_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTSET_CNVCMP_Enum; + + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CACHECFG ======================================================== */ +/* =========================================== CACHECTRL CACHECFG CONFIG [4..6] ============================================ */ +typedef enum { /*!< CACHECTRL_CACHECFG_CONFIG */ + CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5, /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512 + entries (8 SRAMs active) */ +} CACHECTRL_CACHECFG_CONFIG_Enum; + +/* ======================================================= FLASHCFG ======================================================== */ +/* ========================================================= CTRL ========================================================== */ +/* =========================================== CACHECTRL CTRL RESET_STAT [1..1] ============================================ */ +typedef enum { /*!< CACHECTRL_CTRL_RESET_STAT */ + CACHECTRL_CTRL_RESET_STAT_CLEAR = 1, /*!< CLEAR : Clear Cache Stats */ +} CACHECTRL_CTRL_RESET_STAT_Enum; + +/* =========================================== CACHECTRL CTRL INVALIDATE [0..0] ============================================ */ +typedef enum { /*!< CACHECTRL_CTRL_INVALIDATE */ + CACHECTRL_CTRL_INVALIDATE_GO = 1, /*!< GO : Initiate a programming operation to flash info. */ +} CACHECTRL_CTRL_INVALIDATE_Enum; + +/* ======================================================= NCR0START ======================================================= */ +/* ======================================================== NCR0END ======================================================== */ +/* ======================================================= NCR1START ======================================================= */ +/* ======================================================== NCR1END ======================================================== */ +/* ======================================================= CACHEMODE ======================================================= */ +/* ========================================================= DMON0 ========================================================= */ +/* ========================================================= DMON1 ========================================================= */ +/* ========================================================= DMON2 ========================================================= */ +/* ========================================================= DMON3 ========================================================= */ +/* ========================================================= IMON0 ========================================================= */ +/* ========================================================= IMON1 ========================================================= */ +/* ========================================================= IMON2 ========================================================= */ +/* ========================================================= IMON3 ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CALXT ========================================================= */ +/* ========================================================= CALRC ========================================================= */ +/* ======================================================== ACALCTR ======================================================== */ +/* ========================================================= OCTRL ========================================================= */ +/* =============================================== CLKGEN OCTRL ACAL [8..10] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_ACAL */ + CLKGEN_OCTRL_ACAL_DIS = 0, /*!< DIS : Disable Autocalibration */ + CLKGEN_OCTRL_ACAL_1024SEC = 2, /*!< 1024SEC : Autocalibrate every 1024 seconds */ + CLKGEN_OCTRL_ACAL_512SEC = 3, /*!< 512SEC : Autocalibrate every 512 seconds */ + CLKGEN_OCTRL_ACAL_XTFREQ = 6, /*!< XTFREQ : Frequency measurement using XT */ + CLKGEN_OCTRL_ACAL_EXTFREQ = 7, /*!< EXTFREQ : Frequency measurement using external clock */ +} CLKGEN_OCTRL_ACAL_Enum; + +/* =============================================== CLKGEN OCTRL OSEL [7..7] ================================================ */ +typedef enum { /*!< CLKGEN_OCTRL_OSEL */ + CLKGEN_OCTRL_OSEL_RTC_XT = 0, /*!< RTC_XT : RTC uses the XT */ + CLKGEN_OCTRL_OSEL_RTC_LFRC = 1, /*!< RTC_LFRC : RTC uses the LFRC */ +} CLKGEN_OCTRL_OSEL_Enum; + +/* ================================================ CLKGEN OCTRL FOS [6..6] ================================================ */ +typedef enum { /*!< CLKGEN_OCTRL_FOS */ + CLKGEN_OCTRL_FOS_DIS = 0, /*!< DIS : Disable the oscillator switch on failure function */ + CLKGEN_OCTRL_FOS_EN = 1, /*!< EN : Enable the oscillator switch on failure function */ +} CLKGEN_OCTRL_FOS_Enum; + +/* ============================================== CLKGEN OCTRL STOPRC [1..1] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_STOPRC */ + CLKGEN_OCTRL_STOPRC_EN = 0, /*!< EN : Enable the LFRC Oscillator to drive the RTC */ + CLKGEN_OCTRL_STOPRC_STOP = 1, /*!< STOP : Stop the LFRC Oscillator when driving the RTC */ +} CLKGEN_OCTRL_STOPRC_Enum; + +/* ============================================== CLKGEN OCTRL STOPXT [0..0] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_STOPXT */ + CLKGEN_OCTRL_STOPXT_EN = 0, /*!< EN : Enable the XT Oscillator to drive the RTC */ + CLKGEN_OCTRL_STOPXT_STOP = 1, /*!< STOP : Stop the XT Oscillator when driving the RTC */ +} CLKGEN_OCTRL_STOPXT_Enum; + +/* ======================================================== CLKOUT ========================================================= */ +/* =============================================== CLKGEN CLKOUT CKEN [7..7] =============================================== */ +typedef enum { /*!< CLKGEN_CLKOUT_CKEN */ + CLKGEN_CLKOUT_CKEN_DIS = 0, /*!< DIS : Disable CLKOUT */ + CLKGEN_CLKOUT_CKEN_EN = 1, /*!< EN : Enable CLKOUT */ +} CLKGEN_CLKOUT_CKEN_Enum; + +/* ============================================== CLKGEN CLKOUT CKSEL [0..5] =============================================== */ +typedef enum { /*!< CLKGEN_CLKOUT_CKSEL */ + CLKGEN_CLKOUT_CKSEL_LFRC = 0, /*!< LFRC : LFRC */ + CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1, /*!< XT_DIV2 : XT / 2 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2, /*!< XT_DIV4 : XT / 4 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3, /*!< XT_DIV8 : XT / 8 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4, /*!< XT_DIV16 : XT / 16 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5, /*!< XT_DIV32 : XT / 32 */ + CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16, /*!< RTC_1Hz : 1 Hz as selected in RTC */ + CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22, /*!< XT_DIV2M : XT / 2^21 */ + CLKGEN_CLKOUT_CKSEL_XT = 23, /*!< XT : XT */ + CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24, /*!< CG_100Hz : 100 Hz as selected in CLKGEN */ + CLKGEN_CLKOUT_CKSEL_HFRC = 25, /*!< HFRC : HFRC */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 26, /*!< HFRC_DIV4 : HFRC / 4 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 27, /*!< HFRC_DIV8 : HFRC / 8 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 = 28, /*!< HFRC_DIV16 : HFRC / 16 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 29, /*!< HFRC_DIV64 : HFRC / 64 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 30, /*!< HFRC_DIV128 : HFRC / 128 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 31, /*!< HFRC_DIV256 : HFRC / 256 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 = 32, /*!< HFRC_DIV512 : HFRC / 512 */ + CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34, /*!< FLASH_CLK : Flash Clock */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35, /*!< LFRC_DIV2 : LFRC / 2 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36, /*!< LFRC_DIV32 : LFRC / 32 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37, /*!< LFRC_DIV512 : LFRC / 512 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38, /*!< LFRC_DIV32K : LFRC / 32768 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39, /*!< XT_DIV256 : XT / 256 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40, /*!< XT_DIV8K : XT / 8192 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41, /*!< XT_DIV64K : XT / 2^16 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42, /*!< ULFRC_DIV16 : Uncal LFRC / 16 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43, /*!< ULFRC_DIV128 : Uncal LFRC / 128 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44, /*!< ULFRC_1Hz : Uncal LFRC / 1024 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45, /*!< ULFRC_DIV4K : Uncal LFRC / 4096 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46, /*!< ULFRC_DIV1M : Uncal LFRC / 2^20 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47, /*!< HFRC_DIV64K : HFRC / 2^16 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48, /*!< HFRC_DIV16M : HFRC / 2^24 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M = 49, /*!< LFRC_DIV2M : LFRC / 2^20 */ + CLKGEN_CLKOUT_CKSEL_HFRCNE = 50, /*!< HFRCNE : HFRC (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51, /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_XTNE = 53, /*!< XTNE : XT (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54, /*!< XTNE_DIV16 : XT / 16 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55, /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_LFRCNE = 57, /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values */ +} CLKGEN_CLKOUT_CKSEL_Enum; + +/* ======================================================== CLKKEY ========================================================= */ +/* ============================================= CLKGEN CLKKEY CLKKEY [0..31] ============================================== */ +typedef enum { /*!< CLKGEN_CLKKEY_CLKKEY */ + CLKGEN_CLKKEY_CLKKEY_Key = 71, /*!< Key : Key */ +} CLKGEN_CLKKEY_CLKKEY_Enum; + +/* ========================================================= CCTRL ========================================================= */ +/* ============================================== CLKGEN CCTRL CORESEL [0..0] ============================================== */ +typedef enum { /*!< CLKGEN_CCTRL_CORESEL */ + CLKGEN_CCTRL_CORESEL_HFRC = 0, /*!< HFRC : Core Clock is HFRC */ + CLKGEN_CCTRL_CORESEL_HFRC_DIV2 = 1, /*!< HFRC_DIV2 : Core Clock is HFRC / 2 */ +} CLKGEN_CCTRL_CORESEL_Enum; + +/* ======================================================== STATUS ========================================================= */ +/* ========================================================= HFADJ ========================================================= */ +/* =========================================== CLKGEN HFADJ HFADJ_GAIN [21..23] ============================================ */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJ_GAIN */ + CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1 = 0, /*!< Gain_of_1 : HF Adjust with Gain of 1 */ + CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 = 1, /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5 */ + CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_4 = 2, /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25 */ + CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_8 = 3, /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125 */ + CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_16 = 4, /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625 */ + CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_32 = 5, /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125 */ +} CLKGEN_HFADJ_HFADJ_GAIN_Enum; + +/* ============================================ CLKGEN HFADJ HFWARMUP [20..20] ============================================= */ +typedef enum { /*!< CLKGEN_HFADJ_HFWARMUP */ + CLKGEN_HFADJ_HFWARMUP_1SEC = 0, /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds */ + CLKGEN_HFADJ_HFWARMUP_2SEC = 1, /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds */ +} CLKGEN_HFADJ_HFWARMUP_Enum; + +/* ============================================== CLKGEN HFADJ HFADJCK [1..3] ============================================== */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJCK */ + CLKGEN_HFADJ_HFADJCK_4SEC = 0, /*!< 4SEC : Autoadjust repeat period = 4 seconds */ + CLKGEN_HFADJ_HFADJCK_16SEC = 1, /*!< 16SEC : Autoadjust repeat period = 16 seconds */ + CLKGEN_HFADJ_HFADJCK_32SEC = 2, /*!< 32SEC : Autoadjust repeat period = 32 seconds */ + CLKGEN_HFADJ_HFADJCK_64SEC = 3, /*!< 64SEC : Autoadjust repeat period = 64 seconds */ + CLKGEN_HFADJ_HFADJCK_128SEC = 4, /*!< 128SEC : Autoadjust repeat period = 128 seconds */ + CLKGEN_HFADJ_HFADJCK_256SEC = 5, /*!< 256SEC : Autoadjust repeat period = 256 seconds */ + CLKGEN_HFADJ_HFADJCK_512SEC = 6, /*!< 512SEC : Autoadjust repeat period = 512 seconds */ + CLKGEN_HFADJ_HFADJCK_1024SEC = 7, /*!< 1024SEC : Autoadjust repeat period = 1024 seconds */ +} CLKGEN_HFADJ_HFADJCK_Enum; + +/* ============================================== CLKGEN HFADJ HFADJEN [0..0] ============================================== */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJEN */ + CLKGEN_HFADJ_HFADJEN_DIS = 0, /*!< DIS : Disable the HFRC adjustment */ + CLKGEN_HFADJ_HFADJEN_EN = 1, /*!< EN : Enable the HFRC adjustment */ +} CLKGEN_HFADJ_HFADJEN_Enum; + +/* ======================================================== CLOCKEN ======================================================== */ +/* ============================================ CLKGEN CLOCKEN CLOCKEN [0..31] ============================================= */ +typedef enum { /*!< CLKGEN_CLOCKEN_CLOCKEN */ + CLKGEN_CLOCKEN_CLOCKEN_ADC_CLKEN = 1, /*!< ADC_CLKEN : Clock enable for the ADC. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER_CLKEN = 2, /*!< CTIMER_CLKEN : Clock enable for the CTIMER. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER0A_CLKEN = 4, /*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER0B_CLKEN = 8, /*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER1A_CLKEN = 16, /*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER1B_CLKEN = 32, /*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER2A_CLKEN = 64, /*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER2B_CLKEN = 128, /*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER3A_CLKEN = 256, /*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A. */ + CLKGEN_CLOCKEN_CLOCKEN_CTIMER3B_CLKEN = 512, /*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTR0_CLKEN = 1024, /*!< IOMSTR0_CLKEN : Clock enable for the IO Master 0. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTR1_CLKEN = 2048, /*!< IOMSTR1_CLKEN : Clock enable for the IO Master 1. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTR2_CLKEN = 4096, /*!< IOMSTR2_CLKEN : Clock enable for the IO Master 2. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTR3_CLKEN = 8192, /*!< IOMSTR3_CLKEN : Clock enable for the IO Master 3. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTR4_CLKEN = 16384, /*!< IOMSTR4_CLKEN : Clock enable for the IO Master 4. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTR5_CLKEN = 32768, /*!< IOMSTR5_CLKEN : Clock enable for the IO Master 5. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC0_CLKEN = 65536,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IO Master IFC0. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC1_CLKEN = 131072,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO Master IFC1. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC2_CLKEN = 262144,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO Master IFC2. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC3_CLKEN = 524288,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO Master IFC3. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC4_CLKEN = 1048576,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO Master IFC4. */ + CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC5_CLKEN = 2097152,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO Master IFC5. */ + CLKGEN_CLOCKEN_CLOCKEN_IOSLAVE_CLKEN = 4194304,/*!< IOSLAVE_CLKEN : Clock enable for the IO Slave. */ + CLKGEN_CLOCKEN_CLOCKEN_PDM_CLKEN = 8388608,/*!< PDM_CLKEN : Clock enable for the PDM. */ + CLKGEN_CLOCKEN_CLOCKEN_PDMIFC_CLKEN = 16777216,/*!< PDMIFC_CLKEN : Clock enable for the PDM IFC. */ + CLKGEN_CLOCKEN_CLOCKEN_RSTGEN_CLKEN = 33554432,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN. */ + CLKGEN_CLOCKEN_CLOCKEN_SRAM_WIPE_CLKEN = 67108864,/*!< SRAM_WIPE_CLKEN : Clock enable for the SRAM_WIPE. */ + CLKGEN_CLOCKEN_CLOCKEN_STIMER_CLKEN = 134217728,/*!< STIMER_CLKEN : Clock enable for the STIMER. */ + CLKGEN_CLOCKEN_CLOCKEN_STIMER_CNT_CLKEN = 268435456,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT. */ + CLKGEN_CLOCKEN_CLOCKEN_TPIU_CLKEN = 536870912,/*!< TPIU_CLKEN : Clock enable for the TPIU. */ + CLKGEN_CLOCKEN_CLOCKEN_UART0_HCLK_CLKEN = 1073741824,/*!< UART0_HCLK_CLKEN : Clock enable for the UART0_HCLK. */ + CLKGEN_CLOCKEN_CLOCKEN_UART0HF_CLKEN = -2147483648,/*!< UART0HF_CLKEN : Clock enable for the UART0HF. */ +} CLKGEN_CLOCKEN_CLOCKEN_Enum; + +/* ======================================================= CLOCKEN2 ======================================================== */ +/* =========================================== CLKGEN CLOCKEN2 CLOCKEN2 [0..31] ============================================ */ +typedef enum { /*!< CLKGEN_CLOCKEN2_CLOCKEN2 */ + CLKGEN_CLOCKEN2_CLOCKEN2_UART1_HCLK_CLKEN = 1,/*!< UART1_HCLK_CLKEN : Clock enable for the UART1_HCLK. */ + CLKGEN_CLOCKEN2_CLOCKEN2_UART1HF_CLKEN = 2, /*!< UART1HF_CLKEN : Clock enable for the UART1HF. */ + CLKGEN_CLOCKEN2_CLOCKEN2_WDT_CLKEN = 4, /*!< WDT_CLKEN : Clock enable for the WDT. */ + CLKGEN_CLOCKEN2_CLOCKEN2_XT_32KHz_EN = 1073741824,/*!< XT_32KHz_EN : Clock enable for the XT_32KHz. */ + CLKGEN_CLOCKEN2_CLOCKEN2_FRCHFRC = -2147483648,/*!< FRCHFRC : Force HFRC On Status. */ +} CLKGEN_CLOCKEN2_CLOCKEN2_Enum; + +/* ======================================================= CLOCKEN3 ======================================================== */ +/* =========================================== CLKGEN CLOCKEN3 CLOCKEN3 [0..31] ============================================ */ +typedef enum { /*!< CLKGEN_CLOCKEN3_CLOCKEN3 */ + CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_xtal_en = 16777216,/*!< periph_all_xtal_en : At least 1 peripherial is requesting for + XTAL Clock */ + CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_hfrc_en = 33554432,/*!< periph_all_hfrc_en : At least 1 peripherial is requesting for + HFRC Clock */ + CLKGEN_CLOCKEN3_CLOCKEN3_HFADJEN = 67108864,/*!< HFADJEN : HFRC Adjust Enable Status */ + CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_en_out = 134217728,/*!< HFRC_en_out : HFRC is enabled during adjustment status */ + CLKGEN_CLOCKEN3_CLOCKEN3_RTC_SOURCE = 268435456,/*!< RTC_SOURCE : Selects the RTC oscillator (0 => LFRC, 1 => XT) */ + CLKGEN_CLOCKEN3_CLOCKEN3_XTAL_EN = 536870912,/*!< XTAL_EN : XT is enabled Status */ + CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_EN = 1073741824,/*!< HFRC_EN : HFRC is enabled Status */ + CLKGEN_CLOCKEN3_CLOCKEN3_FLASHCLK_EN = -2147483648,/*!< FLASHCLK_EN : Flash Clock is enabled Status */ +} CLKGEN_CLOCKEN3_CLOCKEN3_Enum; + +/* ======================================================== UARTEN ========================================================= */ +/* ============================================= CLKGEN UARTEN UART1EN [8..9] ============================================== */ +typedef enum { /*!< CLKGEN_UARTEN_UART1EN */ + CLKGEN_UARTEN_UART1EN_DIS = 0, /*!< DIS : Disable the UART1 system clock */ + CLKGEN_UARTEN_UART1EN_EN = 1, /*!< EN : Enable the UART1 system clock */ + CLKGEN_UARTEN_UART1EN_REDUCE_FREQ = 2, /*!< REDUCE_FREQ : Run UART_Hclk at the same frequency as UART_hfclk */ + CLKGEN_UARTEN_UART1EN_EN_POWER_SAV = 3, /*!< EN_POWER_SAV : Enable UART_hclk to reduce to UART_hfclk at low + power mode */ +} CLKGEN_UARTEN_UART1EN_Enum; + +/* ============================================= CLKGEN UARTEN UART0EN [0..1] ============================================== */ +typedef enum { /*!< CLKGEN_UARTEN_UART0EN */ + CLKGEN_UARTEN_UART0EN_DIS = 0, /*!< DIS : Disable the UART0 system clock */ + CLKGEN_UARTEN_UART0EN_EN = 1, /*!< EN : Enable the UART0 system clock */ + CLKGEN_UARTEN_UART0EN_REDUCE_FREQ = 2, /*!< REDUCE_FREQ : Run UART_Hclk at the same frequency as UART_hfclk */ + CLKGEN_UARTEN_UART0EN_EN_POWER_SAV = 3, /*!< EN_POWER_SAV : Enable UART_hclk to reduce to UART_hfclk at low + power mode */ +} CLKGEN_UARTEN_UART0EN_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TMR0 ========================================================== */ +/* ======================================================== CMPRA0 ========================================================= */ +/* ======================================================== CMPRB0 ========================================================= */ +/* ========================================================= CTRL0 ========================================================= */ +/* ============================================= CTIMER CTRL0 CTLINK0 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_CTLINK0 */ + CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL0_CTLINK0_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer. */ +} CTIMER_CTRL0_CTLINK0_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0PE [29..29] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0PE */ + CTIMER_CTRL0_TMRB0PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value + TMRB0POL. */ + CTIMER_CTRL0_TMRB0PE_EN = 1, /*!< EN : Enable counter/timer B0 to generate a signal on TMRPINB. */ +} CTIMER_CTRL0_TMRB0PE_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0POL */ + CTIMER_CTRL0_TMRB0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the + timer output. */ + CTIMER_CTRL0_TMRB0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of + the timer output. */ +} CTIMER_CTRL0_TMRB0POL_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0CLR */ + CTIMER_CTRL0_TMRB0CLR_RUN = 0, /*!< RUN : Allow counter/timer B0 to run */ + CTIMER_CTRL0_TMRB0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B0 at 0x0000. */ +} CTIMER_CTRL0_TMRB0CLR_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0IE1 */ + CTIMER_CTRL0_TMRB0IE1_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL0_TMRB0IE1_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL0_TMRB0IE1_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0IE0 */ + CTIMER_CTRL0_TMRB0IE0_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL0_TMRB0IE0_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL0_TMRB0IE0_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0FN */ + CTIMER_CTRL0_TMRB0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B0, stop. */ + CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B0, restart. */ + CTIMER_CTRL0_TMRB0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert, + count to CMPR1B0, deassert, stop. */ + CTIMER_CTRL0_TMRB0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B0, assert, count + to CMPR1B0, deassert, restart. */ + CTIMER_CTRL0_TMRB0FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL0_TMRB0FN_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0CLK */ + CTIMER_CTRL0_TMRB0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL0_TMRB0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL0_TMRB0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL0_TMRB0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL0_TMRB0CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL0_TMRB0CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream from CORE Buck. */ +} CTIMER_CTRL0_TMRB0CLK_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0EN */ + CTIMER_CTRL0_TMRB0EN_DIS = 0, /*!< DIS : Counter/Timer B0 Disable. */ + CTIMER_CTRL0_TMRB0EN_EN = 1, /*!< EN : Counter/Timer B0 Enable. */ +} CTIMER_CTRL0_TMRB0EN_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0PE [13..13] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0PE */ + CTIMER_CTRL0_TMRA0PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value + TMRA0POL. */ + CTIMER_CTRL0_TMRA0PE_EN = 1, /*!< EN : Enable counter/timer A0 to generate a signal on TMRPINA. */ +} CTIMER_CTRL0_TMRA0PE_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0POL */ + CTIMER_CTRL0_TMRA0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the + timer output. */ + CTIMER_CTRL0_TMRA0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of + the timer output. */ +} CTIMER_CTRL0_TMRA0POL_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0CLR */ + CTIMER_CTRL0_TMRA0CLR_RUN = 0, /*!< RUN : Allow counter/timer A0 to run */ + CTIMER_CTRL0_TMRA0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A0 at 0x0000. */ +} CTIMER_CTRL0_TMRA0CLR_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0IE1 */ + CTIMER_CTRL0_TMRA0IE1_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL0_TMRA0IE1_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL0_TMRA0IE1_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0IE0 */ + CTIMER_CTRL0_TMRA0IE0_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL0_TMRA0IE0_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL0_TMRA0IE0_Enum; + +/* ============================================== CTIMER CTRL0 TMRA0FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0FN */ + CTIMER_CTRL0_TMRA0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A0, stop. */ + CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A0, restart. */ + CTIMER_CTRL0_TMRA0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert, + count to CMPR1A0, deassert, stop. */ + CTIMER_CTRL0_TMRA0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A0, assert, count + to CMPR1A0, deassert, restart. */ + CTIMER_CTRL0_TMRA0FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL0_TMRA0FN_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0CLK */ + CTIMER_CTRL0_TMRA0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL0_TMRA0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL0_TMRA0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL0_TMRA0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4. */ + CTIMER_CTRL0_TMRA0CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream from MEM Buck. */ +} CTIMER_CTRL0_TMRA0CLK_Enum; + +/* ============================================== CTIMER CTRL0 TMRA0EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0EN */ + CTIMER_CTRL0_TMRA0EN_DIS = 0, /*!< DIS : Counter/Timer A0 Disable. */ + CTIMER_CTRL0_TMRA0EN_EN = 1, /*!< EN : Counter/Timer A0 Enable. */ +} CTIMER_CTRL0_TMRA0EN_Enum; + +/* ========================================================= TMR1 ========================================================== */ +/* ======================================================== CMPRA1 ========================================================= */ +/* ======================================================== CMPRB1 ========================================================= */ +/* ========================================================= CTRL1 ========================================================= */ +/* ============================================= CTIMER CTRL1 CTLINK1 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_CTLINK1 */ + CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL1_CTLINK1_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer. */ +} CTIMER_CTRL1_CTLINK1_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1PE [29..29] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1PE */ + CTIMER_CTRL1_TMRB1PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value + TMRB1POL. */ + CTIMER_CTRL1_TMRB1PE_EN = 1, /*!< EN : Enable counter/timer B1 to generate a signal on TMRPINB. */ +} CTIMER_CTRL1_TMRB1PE_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1POL */ + CTIMER_CTRL1_TMRB1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the + timer output. */ + CTIMER_CTRL1_TMRB1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of + the timer output. */ +} CTIMER_CTRL1_TMRB1POL_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1CLR */ + CTIMER_CTRL1_TMRB1CLR_RUN = 0, /*!< RUN : Allow counter/timer B1 to run */ + CTIMER_CTRL1_TMRB1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B1 at 0x0000. */ +} CTIMER_CTRL1_TMRB1CLR_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1IE1 */ + CTIMER_CTRL1_TMRB1IE1_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL1_TMRB1IE1_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL1_TMRB1IE1_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1IE0 */ + CTIMER_CTRL1_TMRB1IE0_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL1_TMRB1IE0_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL1_TMRB1IE0_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1FN */ + CTIMER_CTRL1_TMRB1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B1, stop. */ + CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B1, restart. */ + CTIMER_CTRL1_TMRB1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert, + count to CMPR1B1, deassert, stop. */ + CTIMER_CTRL1_TMRB1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B1, assert, count + to CMPR1B1, deassert, restart. */ + CTIMER_CTRL1_TMRB1FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL1_TMRB1FN_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1CLK */ + CTIMER_CTRL1_TMRB1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL1_TMRB1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL1_TMRB1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL1_TMRB1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL1_TMRB1CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL1_TMRB1CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream from CORE Buck. */ +} CTIMER_CTRL1_TMRB1CLK_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1EN */ + CTIMER_CTRL1_TMRB1EN_DIS = 0, /*!< DIS : Counter/Timer B1 Disable. */ + CTIMER_CTRL1_TMRB1EN_EN = 1, /*!< EN : Counter/Timer B1 Enable. */ +} CTIMER_CTRL1_TMRB1EN_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1PE [13..13] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1PE */ + CTIMER_CTRL1_TMRA1PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value + TMRA1POL. */ + CTIMER_CTRL1_TMRA1PE_EN = 1, /*!< EN : Enable counter/timer A1 to generate a signal on TMRPINA. */ +} CTIMER_CTRL1_TMRA1PE_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1POL */ + CTIMER_CTRL1_TMRA1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the + timer output. */ + CTIMER_CTRL1_TMRA1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of + the timer output. */ +} CTIMER_CTRL1_TMRA1POL_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1CLR */ + CTIMER_CTRL1_TMRA1CLR_RUN = 0, /*!< RUN : Allow counter/timer A1 to run */ + CTIMER_CTRL1_TMRA1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A1 at 0x0000. */ +} CTIMER_CTRL1_TMRA1CLR_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1IE1 */ + CTIMER_CTRL1_TMRA1IE1_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL1_TMRA1IE1_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL1_TMRA1IE1_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1IE0 */ + CTIMER_CTRL1_TMRA1IE0_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL1_TMRA1IE0_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL1_TMRA1IE0_Enum; + +/* ============================================== CTIMER CTRL1 TMRA1FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1FN */ + CTIMER_CTRL1_TMRA1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A1, stop. */ + CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A1, restart. */ + CTIMER_CTRL1_TMRA1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert, + count to CMPR1A1, deassert, stop. */ + CTIMER_CTRL1_TMRA1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A1, assert, count + to CMPR1A1, deassert, restart. */ + CTIMER_CTRL1_TMRA1FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL1_TMRA1FN_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1CLK */ + CTIMER_CTRL1_TMRA1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL1_TMRA1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL1_TMRA1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL1_TMRA1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL1_TMRA1CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL1_TMRA1CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream from MEM Buck. */ +} CTIMER_CTRL1_TMRA1CLK_Enum; + +/* ============================================== CTIMER CTRL1 TMRA1EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1EN */ + CTIMER_CTRL1_TMRA1EN_DIS = 0, /*!< DIS : Counter/Timer A1 Disable. */ + CTIMER_CTRL1_TMRA1EN_EN = 1, /*!< EN : Counter/Timer A1 Enable. */ +} CTIMER_CTRL1_TMRA1EN_Enum; + +/* ========================================================= TMR2 ========================================================== */ +/* ======================================================== CMPRA2 ========================================================= */ +/* ======================================================== CMPRB2 ========================================================= */ +/* ========================================================= CTRL2 ========================================================= */ +/* ============================================= CTIMER CTRL2 CTLINK2 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_CTLINK2 */ + CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL2_CTLINK2_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer. */ +} CTIMER_CTRL2_CTLINK2_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2PE [29..29] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2PE */ + CTIMER_CTRL2_TMRB2PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value + TMRB2POL. */ + CTIMER_CTRL2_TMRB2PE_EN = 1, /*!< EN : Enable counter/timer B2 to generate a signal on TMRPINB. */ +} CTIMER_CTRL2_TMRB2PE_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2POL */ + CTIMER_CTRL2_TMRB2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the + timer output. */ + CTIMER_CTRL2_TMRB2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of + the timer output. */ +} CTIMER_CTRL2_TMRB2POL_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2CLR */ + CTIMER_CTRL2_TMRB2CLR_RUN = 0, /*!< RUN : Allow counter/timer B2 to run */ + CTIMER_CTRL2_TMRB2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B2 at 0x0000. */ +} CTIMER_CTRL2_TMRB2CLR_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2IE1 */ + CTIMER_CTRL2_TMRB2IE1_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL2_TMRB2IE1_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL2_TMRB2IE1_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2IE0 */ + CTIMER_CTRL2_TMRB2IE0_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL2_TMRB2IE0_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL2_TMRB2IE0_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2FN */ + CTIMER_CTRL2_TMRB2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B2, stop. */ + CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B2, restart. */ + CTIMER_CTRL2_TMRB2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert, + count to CMPR1B2, deassert, stop. */ + CTIMER_CTRL2_TMRB2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B2, assert, count + to CMPR1B2, deassert, restart. */ + CTIMER_CTRL2_TMRB2FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL2_TMRB2FN_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2CLK */ + CTIMER_CTRL2_TMRB2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL2_TMRB2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL2_TMRB2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL2_TMRB2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL2_TMRB2CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL2_TMRB2CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream from MEM Buck. */ +} CTIMER_CTRL2_TMRB2CLK_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2EN */ + CTIMER_CTRL2_TMRB2EN_DIS = 0, /*!< DIS : Counter/Timer B2 Disable. */ + CTIMER_CTRL2_TMRB2EN_EN = 1, /*!< EN : Counter/Timer B2 Enable. */ +} CTIMER_CTRL2_TMRB2EN_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2PE [13..13] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2PE */ + CTIMER_CTRL2_TMRA2PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value + TMRA2POL. */ + CTIMER_CTRL2_TMRA2PE_EN = 1, /*!< EN : Enable counter/timer A2 to generate a signal on TMRPINA. */ +} CTIMER_CTRL2_TMRA2PE_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2POL */ + CTIMER_CTRL2_TMRA2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the + timer output. */ + CTIMER_CTRL2_TMRA2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of + the timer output. */ +} CTIMER_CTRL2_TMRA2POL_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2CLR */ + CTIMER_CTRL2_TMRA2CLR_RUN = 0, /*!< RUN : Allow counter/timer A2 to run */ + CTIMER_CTRL2_TMRA2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A2 at 0x0000. */ +} CTIMER_CTRL2_TMRA2CLR_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2IE1 */ + CTIMER_CTRL2_TMRA2IE1_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL2_TMRA2IE1_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL2_TMRA2IE1_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2IE0 */ + CTIMER_CTRL2_TMRA2IE0_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL2_TMRA2IE0_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL2_TMRA2IE0_Enum; + +/* ============================================== CTIMER CTRL2 TMRA2FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2FN */ + CTIMER_CTRL2_TMRA2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A2, stop. */ + CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A2, restart. */ + CTIMER_CTRL2_TMRA2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert, + count to CMPR1A2, deassert, stop. */ + CTIMER_CTRL2_TMRA2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A2, assert, count + to CMPR1A2, deassert, restart. */ + CTIMER_CTRL2_TMRA2FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL2_TMRA2FN_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2CLK */ + CTIMER_CTRL2_TMRA2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL2_TMRA2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL2_TMRA2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL2_TMRA2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL2_TMRA2CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL2_TMRA2CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream from CORE Buck. */ +} CTIMER_CTRL2_TMRA2CLK_Enum; + +/* ============================================== CTIMER CTRL2 TMRA2EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2EN */ + CTIMER_CTRL2_TMRA2EN_DIS = 0, /*!< DIS : Counter/Timer A2 Disable. */ + CTIMER_CTRL2_TMRA2EN_EN = 1, /*!< EN : Counter/Timer A2 Enable. */ +} CTIMER_CTRL2_TMRA2EN_Enum; + +/* ========================================================= TMR3 ========================================================== */ +/* ======================================================== CMPRA3 ========================================================= */ +/* ======================================================== CMPRB3 ========================================================= */ +/* ========================================================= CTRL3 ========================================================= */ +/* ============================================= CTIMER CTRL3 CTLINK3 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_CTLINK3 */ + CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL3_CTLINK3_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer. */ +} CTIMER_CTRL3_CTLINK3_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3PE [29..29] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3PE */ + CTIMER_CTRL3_TMRB3PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value + TMRB3POL. */ + CTIMER_CTRL3_TMRB3PE_EN = 1, /*!< EN : Enable counter/timer B3 to generate a signal on TMRPINB. */ +} CTIMER_CTRL3_TMRB3PE_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3POL */ + CTIMER_CTRL3_TMRB3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the + timer output. */ + CTIMER_CTRL3_TMRB3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of + the timer output. */ +} CTIMER_CTRL3_TMRB3POL_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3CLR */ + CTIMER_CTRL3_TMRB3CLR_RUN = 0, /*!< RUN : Allow counter/timer B3 to run */ + CTIMER_CTRL3_TMRB3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B3 at 0x0000. */ +} CTIMER_CTRL3_TMRB3CLR_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3IE1 */ + CTIMER_CTRL3_TMRB3IE1_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL3_TMRB3IE1_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL3_TMRB3IE1_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3IE0 */ + CTIMER_CTRL3_TMRB3IE0_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL3_TMRB3IE0_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL3_TMRB3IE0_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3FN */ + CTIMER_CTRL3_TMRB3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B3, stop. */ + CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B3, restart. */ + CTIMER_CTRL3_TMRB3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert, + count to CMPR1B3, deassert, stop. */ + CTIMER_CTRL3_TMRB3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B3, assert, count + to CMPR1B3, deassert, restart. */ + CTIMER_CTRL3_TMRB3FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL3_TMRB3FN_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3CLK */ + CTIMER_CTRL3_TMRB3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL3_TMRB3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL3_TMRB3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL3_TMRB3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL3_TMRB3CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL3_TMRB3CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream from MEM Buck. */ +} CTIMER_CTRL3_TMRB3CLK_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3EN */ + CTIMER_CTRL3_TMRB3EN_DIS = 0, /*!< DIS : Counter/Timer B3 Disable. */ + CTIMER_CTRL3_TMRB3EN_EN = 1, /*!< EN : Counter/Timer B3 Enable. */ +} CTIMER_CTRL3_TMRB3EN_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3PE [13..13] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3PE */ + CTIMER_CTRL3_TMRA3PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value + TMRA3POL. */ + CTIMER_CTRL3_TMRA3PE_EN = 1, /*!< EN : Enable counter/timer A3 to generate a signal on TMRPINA. */ +} CTIMER_CTRL3_TMRA3PE_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3POL */ + CTIMER_CTRL3_TMRA3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the + timer output. */ + CTIMER_CTRL3_TMRA3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of + the timer output. */ +} CTIMER_CTRL3_TMRA3POL_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3CLR */ + CTIMER_CTRL3_TMRA3CLR_RUN = 0, /*!< RUN : Allow counter/timer A3 to run */ + CTIMER_CTRL3_TMRA3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A3 at 0x0000. */ +} CTIMER_CTRL3_TMRA3CLR_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3IE1 */ + CTIMER_CTRL3_TMRA3IE1_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL3_TMRA3IE1_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL3_TMRA3IE1_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3IE0 */ + CTIMER_CTRL3_TMRA3IE0_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL3_TMRA3IE0_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL3_TMRA3IE0_Enum; + +/* ============================================== CTIMER CTRL3 TMRA3FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3FN */ + CTIMER_CTRL3_TMRA3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A3, stop. */ + CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A3, restart. */ + CTIMER_CTRL3_TMRA3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert, + count to CMPR1A3, deassert, stop. */ + CTIMER_CTRL3_TMRA3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A3, assert, count + to CMPR1A3, deassert, restart. */ + CTIMER_CTRL3_TMRA3FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ +} CTIMER_CTRL3_TMRA3FN_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3CLK */ + CTIMER_CTRL3_TMRA3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is HFRC / 4 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL3_TMRA3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL3_TMRA3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL3_TMRA3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL3_TMRA3CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */ + CTIMER_CTRL3_TMRA3CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream from CORE Buck. */ +} CTIMER_CTRL3_TMRA3CLK_Enum; + +/* ============================================== CTIMER CTRL3 TMRA3EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3EN */ + CTIMER_CTRL3_TMRA3EN_DIS = 0, /*!< DIS : Counter/Timer A3 Disable. */ + CTIMER_CTRL3_TMRA3EN_EN = 1, /*!< EN : Counter/Timer A3 Enable. */ +} CTIMER_CTRL3_TMRA3EN_Enum; + +/* ========================================================= STCFG ========================================================= */ +/* ============================================= CTIMER STCFG FREEZE [31..31] ============================================== */ +typedef enum { /*!< CTIMER_STCFG_FREEZE */ + CTIMER_STCFG_FREEZE_THAW = 0, /*!< THAW : Let the COUNTER register run on its input clock. */ + CTIMER_STCFG_FREEZE_FREEZE = 1, /*!< FREEZE : Stop the COUNTER register for loading. */ +} CTIMER_STCFG_FREEZE_Enum; + +/* ============================================== CTIMER STCFG CLEAR [30..30] ============================================== */ +typedef enum { /*!< CTIMER_STCFG_CLEAR */ + CTIMER_STCFG_CLEAR_RUN = 0, /*!< RUN : Let the COUNTER register run on its input clock. */ + CTIMER_STCFG_CLEAR_CLEAR = 1, /*!< CLEAR : Stop the COUNTER register for loading. */ +} CTIMER_STCFG_CLEAR_Enum; + +/* ========================================== CTIMER STCFG COMPARE_H_EN [15..15] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_H_EN */ + CTIMER_STCFG_COMPARE_H_EN_DISABLE = 0, /*!< DISABLE : Compare H disabled. */ + CTIMER_STCFG_COMPARE_H_EN_ENABLE = 1, /*!< ENABLE : Compare H enabled. */ +} CTIMER_STCFG_COMPARE_H_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_G_EN [14..14] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_G_EN */ + CTIMER_STCFG_COMPARE_G_EN_DISABLE = 0, /*!< DISABLE : Compare G disabled. */ + CTIMER_STCFG_COMPARE_G_EN_ENABLE = 1, /*!< ENABLE : Compare G enabled. */ +} CTIMER_STCFG_COMPARE_G_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_F_EN [13..13] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_F_EN */ + CTIMER_STCFG_COMPARE_F_EN_DISABLE = 0, /*!< DISABLE : Compare F disabled. */ + CTIMER_STCFG_COMPARE_F_EN_ENABLE = 1, /*!< ENABLE : Compare F enabled. */ +} CTIMER_STCFG_COMPARE_F_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_E_EN [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_E_EN */ + CTIMER_STCFG_COMPARE_E_EN_DISABLE = 0, /*!< DISABLE : Compare E disabled. */ + CTIMER_STCFG_COMPARE_E_EN_ENABLE = 1, /*!< ENABLE : Compare E enabled. */ +} CTIMER_STCFG_COMPARE_E_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_D_EN [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_D_EN */ + CTIMER_STCFG_COMPARE_D_EN_DISABLE = 0, /*!< DISABLE : Compare D disabled. */ + CTIMER_STCFG_COMPARE_D_EN_ENABLE = 1, /*!< ENABLE : Compare D enabled. */ +} CTIMER_STCFG_COMPARE_D_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_C_EN [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_C_EN */ + CTIMER_STCFG_COMPARE_C_EN_DISABLE = 0, /*!< DISABLE : Compare C disabled. */ + CTIMER_STCFG_COMPARE_C_EN_ENABLE = 1, /*!< ENABLE : Compare C enabled. */ +} CTIMER_STCFG_COMPARE_C_EN_Enum; + +/* =========================================== CTIMER STCFG COMPARE_B_EN [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_B_EN */ + CTIMER_STCFG_COMPARE_B_EN_DISABLE = 0, /*!< DISABLE : Compare B disabled. */ + CTIMER_STCFG_COMPARE_B_EN_ENABLE = 1, /*!< ENABLE : Compare B enabled. */ +} CTIMER_STCFG_COMPARE_B_EN_Enum; + +/* =========================================== CTIMER STCFG COMPARE_A_EN [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_A_EN */ + CTIMER_STCFG_COMPARE_A_EN_DISABLE = 0, /*!< DISABLE : Compare A disabled. */ + CTIMER_STCFG_COMPARE_A_EN_ENABLE = 1, /*!< ENABLE : Compare A enabled. */ +} CTIMER_STCFG_COMPARE_A_EN_Enum; + +/* ============================================== CTIMER STCFG CLKSEL [0..3] =============================================== */ +typedef enum { /*!< CTIMER_STCFG_CLKSEL */ + CTIMER_STCFG_CLKSEL_NOCLK = 0, /*!< NOCLK : No clock enabled. */ + CTIMER_STCFG_CLKSEL_HFRC_DIV16 = 1, /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider. */ + CTIMER_STCFG_CLKSEL_HFRC_DIV256 = 2, /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV1 = 3, /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV2 = 4, /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV32 = 5, /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_LFRC_DIV1 = 6, /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated). */ + CTIMER_STCFG_CLKSEL_CTIMER0A = 7, /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock + source. */ + CTIMER_STCFG_CLKSEL_CTIMER0B = 8, /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together) + as a prescaler for the clock source. */ +} CTIMER_STCFG_CLKSEL_Enum; + +/* ========================================================= STTMR ========================================================= */ +/* ==================================================== CAPTURE_CONTROL ==================================================== */ +/* ======================================== CTIMER CAPTURE_CONTROL CAPTURE_D [3..3] ======================================== */ +typedef enum { /*!< CTIMER_CAPTURE_CONTROL_CAPTURE_D */ + CTIMER_CAPTURE_CONTROL_CAPTURE_D_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURE_CONTROL_CAPTURE_D_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURE_CONTROL_CAPTURE_D_Enum; + +/* ======================================== CTIMER CAPTURE_CONTROL CAPTURE_C [2..2] ======================================== */ +typedef enum { /*!< CTIMER_CAPTURE_CONTROL_CAPTURE_C */ + CTIMER_CAPTURE_CONTROL_CAPTURE_C_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURE_CONTROL_CAPTURE_C_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURE_CONTROL_CAPTURE_C_Enum; + +/* ======================================== CTIMER CAPTURE_CONTROL CAPTURE_B [1..1] ======================================== */ +typedef enum { /*!< CTIMER_CAPTURE_CONTROL_CAPTURE_B */ + CTIMER_CAPTURE_CONTROL_CAPTURE_B_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURE_CONTROL_CAPTURE_B_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURE_CONTROL_CAPTURE_B_Enum; + +/* ======================================== CTIMER CAPTURE_CONTROL CAPTURE_A [0..0] ======================================== */ +typedef enum { /*!< CTIMER_CAPTURE_CONTROL_CAPTURE_A */ + CTIMER_CAPTURE_CONTROL_CAPTURE_A_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURE_CONTROL_CAPTURE_A_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURE_CONTROL_CAPTURE_A_Enum; + +/* ======================================================== SCMPR0 ========================================================= */ +/* ======================================================== SCMPR1 ========================================================= */ +/* ======================================================== SCMPR2 ========================================================= */ +/* ======================================================== SCMPR3 ========================================================= */ +/* ======================================================== SCMPR4 ========================================================= */ +/* ======================================================== SCMPR5 ========================================================= */ +/* ======================================================== SCMPR6 ========================================================= */ +/* ======================================================== SCMPR7 ========================================================= */ +/* ======================================================== SCAPT0 ========================================================= */ +/* ======================================================== SCAPT1 ========================================================= */ +/* ======================================================== SCAPT2 ========================================================= */ +/* ======================================================== SCAPT3 ========================================================= */ +/* ========================================================= SNVR0 ========================================================= */ +/* ========================================================= SNVR1 ========================================================= */ +/* ========================================================= SNVR2 ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= STMINTEN ======================================================== */ +/* =========================================== CTIMER STMINTEN CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTURED */ + CTIMER_STMINTEN_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTURED_Enum; + +/* =========================================== CTIMER STMINTEN CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREC */ + CTIMER_STMINTEN_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREC_Enum; + +/* =========================================== CTIMER STMINTEN CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREB */ + CTIMER_STMINTEN_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREB_Enum; + +/* ============================================ CTIMER STMINTEN CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREA */ + CTIMER_STMINTEN_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREA_Enum; + +/* ============================================ CTIMER STMINTEN OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_OVERFLOW */ + CTIMER_STMINTEN_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTEN_OVERFLOW_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREH */ + CTIMER_STMINTEN_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREH_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREG */ + CTIMER_STMINTEN_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREG_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREF */ + CTIMER_STMINTEN_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREF_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREE */ + CTIMER_STMINTEN_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREE_Enum; + +/* ============================================ CTIMER STMINTEN COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPARED */ + CTIMER_STMINTEN_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPARED_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREC */ + CTIMER_STMINTEN_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREC_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREB */ + CTIMER_STMINTEN_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREB_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREA */ + CTIMER_STMINTEN_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREA_Enum; + +/* ====================================================== STMINTSTAT ======================================================= */ +/* ========================================== CTIMER STMINTSTAT CAPTURED [12..12] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTURED */ + CTIMER_STMINTSTAT_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTSTAT CAPTUREC [11..11] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREC */ + CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTSTAT CAPTUREB [10..10] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREB */ + CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTSTAT CAPTUREA [9..9] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREA */ + CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTSTAT OVERFLOW [8..8] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_OVERFLOW */ + CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTSTAT_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREH [7..7] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREH */ + CTIMER_STMINTSTAT_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREG [6..6] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREG */ + CTIMER_STMINTSTAT_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREF [5..5] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREF */ + CTIMER_STMINTSTAT_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREE [4..4] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREE */ + CTIMER_STMINTSTAT_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPARED [3..3] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPARED */ + CTIMER_STMINTSTAT_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPARED_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREC [2..2] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREC */ + CTIMER_STMINTSTAT_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREB [1..1] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREB */ + CTIMER_STMINTSTAT_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREA [0..0] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREA */ + CTIMER_STMINTSTAT_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREA_Enum; + +/* ======================================================= STMINTCLR ======================================================= */ +/* ========================================== CTIMER STMINTCLR CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTURED */ + CTIMER_STMINTCLR_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTCLR CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREC */ + CTIMER_STMINTCLR_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTCLR CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREB */ + CTIMER_STMINTCLR_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTCLR CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREA */ + CTIMER_STMINTCLR_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTCLR OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_OVERFLOW */ + CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTCLR_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREH */ + CTIMER_STMINTCLR_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREG */ + CTIMER_STMINTCLR_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREF */ + CTIMER_STMINTCLR_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREE */ + CTIMER_STMINTCLR_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTCLR COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPARED */ + CTIMER_STMINTCLR_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPARED_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREC */ + CTIMER_STMINTCLR_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREB */ + CTIMER_STMINTCLR_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREA */ + CTIMER_STMINTCLR_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREA_Enum; + +/* ======================================================= STMINTSET ======================================================= */ +/* ========================================== CTIMER STMINTSET CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTURED */ + CTIMER_STMINTSET_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTSET CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREC */ + CTIMER_STMINTSET_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTSET CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREB */ + CTIMER_STMINTSET_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTSET CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREA */ + CTIMER_STMINTSET_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTSET OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_OVERFLOW */ + CTIMER_STMINTSET_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTSET_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREH */ + CTIMER_STMINTSET_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREG */ + CTIMER_STMINTSET_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREF */ + CTIMER_STMINTSET_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREE */ + CTIMER_STMINTSET_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTSET COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPARED */ + CTIMER_STMINTSET_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPARED_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREC */ + CTIMER_STMINTSET_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREB */ + CTIMER_STMINTSET_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREA */ + CTIMER_STMINTSET_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREA_Enum; + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PADREGA ======================================================== */ +/* =========================================== GPIO PADREGA PAD3FNCSEL [27..29] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3FNCSEL */ + GPIO_PADREGA_PAD3FNCSEL_UA0RTS = 0, /*!< UA0RTS : Configure as the UART0 RTS output */ + GPIO_PADREGA_PAD3FNCSEL_SLnCE = 1, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */ + GPIO_PADREGA_PAD3FNCSEL_M1nCE4 = 2, /*!< M1nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR1 */ + GPIO_PADREGA_PAD3FNCSEL_GPIO3 = 3, /*!< GPIO3 : Configure as GPIO3 */ + GPIO_PADREGA_PAD3FNCSEL_MxnCELB = 4, /*!< MxnCELB : Configure as the IOSLAVE SPI nCE loopback signal from + IOMSTRx */ + GPIO_PADREGA_PAD3FNCSEL_M2nCE0 = 5, /*!< M2nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR2 */ + GPIO_PADREGA_PAD3FNCSEL_TRIG1 = 6, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK = 7, /*!< I2S_WCLK : Configure as the I2S Word Clock input */ +} GPIO_PADREGA_PAD3FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD3STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3STRNG */ + GPIO_PADREGA_PAD3STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD3STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD3STRNG_Enum; + +/* ============================================ GPIO PADREGA PAD3INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3INPEN */ + GPIO_PADREGA_PAD3INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD3INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD3INPEN_Enum; + +/* ============================================ GPIO PADREGA PAD3PULL [24..24] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD3PULL */ + GPIO_PADREGA_PAD3PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD3PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD3PULL_Enum; + +/* =========================================== GPIO PADREGA PAD2FNCSEL [19..21] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2FNCSEL */ + GPIO_PADREGA_PAD2FNCSEL_SLWIR3 = 0, /*!< SLWIR3 : Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGA_PAD2FNCSEL_SLMOSI = 1, /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal */ + GPIO_PADREGA_PAD2FNCSEL_UART0RX = 2, /*!< UART0RX : Configure as the UART0 RX input */ + GPIO_PADREGA_PAD2FNCSEL_GPIO2 = 3, /*!< GPIO2 : Configure as GPIO2 */ + GPIO_PADREGA_PAD2FNCSEL_MxMOSILB = 4, /*!< MxMOSILB : Configure as the IOSLAVE SPI MOSI loopback signal + from IOMSTRx */ + GPIO_PADREGA_PAD2FNCSEL_M2MOSI = 5, /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal */ + GPIO_PADREGA_PAD2FNCSEL_MxWIR3LB = 6, /*!< MxWIR3LB : Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback + signal from IOMSTRx */ + GPIO_PADREGA_PAD2FNCSEL_M2WIR3 = 7, /*!< M2WIR3 : Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal */ +} GPIO_PADREGA_PAD2FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD2STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2STRNG */ + GPIO_PADREGA_PAD2STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD2STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD2STRNG_Enum; + +/* ============================================ GPIO PADREGA PAD2INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2INPEN */ + GPIO_PADREGA_PAD2INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD2INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD2INPEN_Enum; + +/* ============================================ GPIO PADREGA PAD2PULL [16..16] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD2PULL */ + GPIO_PADREGA_PAD2PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD2PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD2PULL_Enum; + +/* ============================================ GPIO PADREGA PAD1RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD1RSEL */ + GPIO_PADREGA_PAD1RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGA_PAD1RSEL_Enum; + +/* =========================================== GPIO PADREGA PAD1FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD1FNCSEL */ + GPIO_PADREGA_PAD1FNCSEL_SLSDA = 0, /*!< SLSDA : Configure as the IOSLAVE I2C SDA signal */ + GPIO_PADREGA_PAD1FNCSEL_SLMISO = 1, /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal */ + GPIO_PADREGA_PAD1FNCSEL_UART0TX = 2, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGA_PAD1FNCSEL_GPIO1 = 3, /*!< GPIO1 : Configure as GPIO1 */ + GPIO_PADREGA_PAD1FNCSEL_MxMISOLB = 4, /*!< MxMISOLB : Configure as the IOSLAVE SPI MISO loopback signal + from IOMSTRx */ + GPIO_PADREGA_PAD1FNCSEL_M2MISO = 5, /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal */ + GPIO_PADREGA_PAD1FNCSEL_MxSDALB = 6, /*!< MxSDALB : Configure as the IOSLAVE I2C SDA loopback signal from + IOMSTRx */ + GPIO_PADREGA_PAD1FNCSEL_M2SDA = 7, /*!< M2SDA : Configure as the IOMSTR2 I2C Serial data I/O signal */ +} GPIO_PADREGA_PAD1FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD1STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD1STRNG */ + GPIO_PADREGA_PAD1STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD1STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD1STRNG_Enum; + +/* ============================================= GPIO PADREGA PAD1INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD1INPEN */ + GPIO_PADREGA_PAD1INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD1INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD1INPEN_Enum; + +/* ============================================= GPIO PADREGA PAD1PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD1PULL */ + GPIO_PADREGA_PAD1PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD1PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD1PULL_Enum; + +/* ============================================= GPIO PADREGA PAD0RSEL [6..7] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD0RSEL */ + GPIO_PADREGA_PAD0RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGA_PAD0RSEL_Enum; + +/* ============================================ GPIO PADREGA PAD0FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0FNCSEL */ + GPIO_PADREGA_PAD0FNCSEL_SLSCL = 0, /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal */ + GPIO_PADREGA_PAD0FNCSEL_SLSCK = 1, /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal */ + GPIO_PADREGA_PAD0FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGA_PAD0FNCSEL_GPIO0 = 3, /*!< GPIO0 : Configure as GPIO0 */ + GPIO_PADREGA_PAD0FNCSEL_MxSCKLB = 4, /*!< MxSCKLB : Configure as the IOSLAVE SPI SCK loopback signal from + IOMSTRx */ + GPIO_PADREGA_PAD0FNCSEL_M2SCK = 5, /*!< M2SCK : Configure as the IOMSTR2 SPI SCK output */ + GPIO_PADREGA_PAD0FNCSEL_MxSCLLB = 6, /*!< MxSCLLB : Configure as the IOSLAVE I2C SCL loopback signal from + IOMSTRx */ + GPIO_PADREGA_PAD0FNCSEL_M2SCL = 7, /*!< M2SCL : Configure as the IOMSTR2 I2C SCL clock I/O signal */ +} GPIO_PADREGA_PAD0FNCSEL_Enum; + +/* ============================================= GPIO PADREGA PAD0STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0STRNG */ + GPIO_PADREGA_PAD0STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD0STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD0STRNG_Enum; + +/* ============================================= GPIO PADREGA PAD0INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0INPEN */ + GPIO_PADREGA_PAD0INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD0INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD0INPEN_Enum; + +/* ============================================= GPIO PADREGA PAD0PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD0PULL */ + GPIO_PADREGA_PAD0PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD0PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD0PULL_Enum; + +/* ======================================================== PADREGB ======================================================== */ +/* =========================================== GPIO PADREGB PAD7FNCSEL [27..29] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7FNCSEL */ + GPIO_PADREGB_PAD7FNCSEL_M0WIR3 = 0, /*!< M0WIR3 : Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGB_PAD7FNCSEL_M0MOSI = 1, /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal */ + GPIO_PADREGB_PAD7FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGB_PAD7FNCSEL_GPIO7 = 3, /*!< GPIO7 : Configure as GPIO7 */ + GPIO_PADREGB_PAD7FNCSEL_TRIG0 = 4, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGB_PAD7FNCSEL_UART0TX = 5, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGB_PAD7FNCSEL_SLWIR3LB = 6, /*!< SLWIR3LB : Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback + signal from IOSLAVE */ + GPIO_PADREGB_PAD7FNCSEL_M1nCE1 = 7, /*!< M1nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR1 */ +} GPIO_PADREGB_PAD7FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD7STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7STRNG */ + GPIO_PADREGB_PAD7STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD7STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD7STRNG_Enum; + +/* ============================================ GPIO PADREGB PAD7INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7INPEN */ + GPIO_PADREGB_PAD7INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD7INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD7INPEN_Enum; + +/* ============================================ GPIO PADREGB PAD7PULL [24..24] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD7PULL */ + GPIO_PADREGB_PAD7PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD7PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD7PULL_Enum; + +/* ============================================ GPIO PADREGB PAD6RSEL [22..23] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD6RSEL */ + GPIO_PADREGB_PAD6RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGB_PAD6RSEL_Enum; + +/* =========================================== GPIO PADREGB PAD6FNCSEL [19..21] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6FNCSEL */ + GPIO_PADREGB_PAD6FNCSEL_M0SDA = 0, /*!< M0SDA : Configure as the IOMSTR0 I2C SDA signal */ + GPIO_PADREGB_PAD6FNCSEL_M0MISO = 1, /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal */ + GPIO_PADREGB_PAD6FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGB_PAD6FNCSEL_GPIO6 = 3, /*!< GPIO6 : Configure as GPIO6 */ + GPIO_PADREGB_PAD6FNCSEL_SLMISOLB = 4, /*!< SLMISOLB : Configure as the IOMSTR0 SPI MISO loopback signal + from IOSLAVE */ + GPIO_PADREGB_PAD6FNCSEL_M1nCE0 = 5, /*!< M1nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR1 */ + GPIO_PADREGB_PAD6FNCSEL_SLSDALB = 6, /*!< SLSDALB : Configure as the IOMSTR0 I2C SDA loopback signal from + IOSLAVE */ + GPIO_PADREGB_PAD6FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the I2S Data output signal */ +} GPIO_PADREGB_PAD6FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD6STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6STRNG */ + GPIO_PADREGB_PAD6STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD6STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD6STRNG_Enum; + +/* ============================================ GPIO PADREGB PAD6INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6INPEN */ + GPIO_PADREGB_PAD6INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD6INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD6INPEN_Enum; + +/* ============================================ GPIO PADREGB PAD6PULL [16..16] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD6PULL */ + GPIO_PADREGB_PAD6PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD6PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD6PULL_Enum; + +/* ============================================ GPIO PADREGB PAD5RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD5RSEL */ + GPIO_PADREGB_PAD5RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGB_PAD5RSEL_Enum; + +/* =========================================== GPIO PADREGB PAD5FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD5FNCSEL */ + GPIO_PADREGB_PAD5FNCSEL_M0SCL = 0, /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal */ + GPIO_PADREGB_PAD5FNCSEL_M0SCK = 1, /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal */ + GPIO_PADREGB_PAD5FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS signal output */ + GPIO_PADREGB_PAD5FNCSEL_GPIO5 = 3, /*!< GPIO5 : Configure as GPIO5 */ + GPIO_PADREGB_PAD5FNCSEL_M0SCKLB = 4, /*!< M0SCKLB : Configure as the IOMSTR0 SPI SCK loopback signal from + IOSLAVE */ + GPIO_PADREGB_PAD5FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the External HFA input clock */ + GPIO_PADREGB_PAD5FNCSEL_M0SCLLB = 6, /*!< M0SCLLB : Configure as the IOMSTR0 I2C SCL loopback signal from + IOSLAVE */ + GPIO_PADREGB_PAD5FNCSEL_M1nCE2 = 7, /*!< M1nCE2 : Configure as the SPI Channel 2 nCE signal from IOMSTR1 */ +} GPIO_PADREGB_PAD5FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD5STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD5STRNG */ + GPIO_PADREGB_PAD5STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD5STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD5STRNG_Enum; + +/* ============================================= GPIO PADREGB PAD5INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD5INPEN */ + GPIO_PADREGB_PAD5INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD5INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD5INPEN_Enum; + +/* ============================================= GPIO PADREGB PAD5PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGB_PAD5PULL */ + GPIO_PADREGB_PAD5PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD5PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD5PULL_Enum; + +/* ============================================= GPIO PADREGB PAD4PWRDN [7..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4PWRDN */ + GPIO_PADREGB_PAD4PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGB_PAD4PWRDN_EN = 1, /*!< EN : Power switch enabled (switch to GND) */ +} GPIO_PADREGB_PAD4PWRDN_Enum; + +/* ============================================ GPIO PADREGB PAD4FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4FNCSEL */ + GPIO_PADREGB_PAD4FNCSEL_UA0CTS = 0, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGB_PAD4FNCSEL_SLINT = 1, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ + GPIO_PADREGB_PAD4FNCSEL_M0nCE5 = 2, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */ + GPIO_PADREGB_PAD4FNCSEL_GPIO4 = 3, /*!< GPIO4 : Configure as GPIO4 */ + GPIO_PADREGB_PAD4FNCSEL_SLINTGP = 4, /*!< SLINTGP : Configure as the IOSLAVE interrupt loopback signal */ + GPIO_PADREGB_PAD4FNCSEL_M2nCE5 = 5, /*!< M2nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR2 */ + GPIO_PADREGB_PAD4FNCSEL_CLKOUT = 6, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGB_PAD4FNCSEL_32khz_XT = 7, /*!< 32khz_XT : Configure as the 32kHz crystal output signal */ +} GPIO_PADREGB_PAD4FNCSEL_Enum; + +/* ============================================= GPIO PADREGB PAD4STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4STRNG */ + GPIO_PADREGB_PAD4STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD4STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD4STRNG_Enum; + +/* ============================================= GPIO PADREGB PAD4INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4INPEN */ + GPIO_PADREGB_PAD4INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD4INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD4INPEN_Enum; + +/* ============================================= GPIO PADREGB PAD4PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGB_PAD4PULL */ + GPIO_PADREGB_PAD4PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD4PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD4PULL_Enum; + +/* ======================================================== PADREGC ======================================================== */ +/* =========================================== GPIO PADREGC PAD11FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD11FNCSEL */ + GPIO_PADREGC_PAD11FNCSEL_ADCSE2 = 0, /*!< ADCSE2 : Configure as the analog input for ADC single ended + input 2 */ + GPIO_PADREGC_PAD11FNCSEL_M0nCE0 = 1, /*!< M0nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR0 */ + GPIO_PADREGC_PAD11FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGC_PAD11FNCSEL_GPIO11 = 3, /*!< GPIO11 : Configure as GPIO11 */ + GPIO_PADREGC_PAD11FNCSEL_M2nCE7 = 4, /*!< M2nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR2 */ + GPIO_PADREGC_PAD11FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGC_PAD11FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGC_PAD11FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as the PDM Data input signal */ +} GPIO_PADREGC_PAD11FNCSEL_Enum; + +/* =========================================== GPIO PADREGC PAD11STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11STRNG */ + GPIO_PADREGC_PAD11STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD11STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD11STRNG_Enum; + +/* =========================================== GPIO PADREGC PAD11INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11INPEN */ + GPIO_PADREGC_PAD11INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD11INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD11INPEN_Enum; + +/* ============================================ GPIO PADREGC PAD11PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11PULL */ + GPIO_PADREGC_PAD11PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD11PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD11PULL_Enum; + +/* =========================================== GPIO PADREGC PAD10FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD10FNCSEL */ + GPIO_PADREGC_PAD10FNCSEL_M1WIR3 = 0, /*!< M1WIR3 : Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGC_PAD10FNCSEL_M1MOSI = 1, /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal */ + GPIO_PADREGC_PAD10FNCSEL_M0nCE6 = 2, /*!< M0nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR0 */ + GPIO_PADREGC_PAD10FNCSEL_GPIO10 = 3, /*!< GPIO10 : Configure as GPIO10 */ + GPIO_PADREGC_PAD10FNCSEL_M2nCE6 = 4, /*!< M2nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR2 */ + GPIO_PADREGC_PAD10FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ + GPIO_PADREGC_PAD10FNCSEL_M4nCE4 = 6, /*!< M4nCE4 : Configure as the SPI channel 4 nCE signal from the + IOMSTR4 */ + GPIO_PADREGC_PAD10FNCSEL_SLWIR3LB = 7, /*!< SLWIR3LB : Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback + signal from IOSLAVE */ +} GPIO_PADREGC_PAD10FNCSEL_Enum; + +/* =========================================== GPIO PADREGC PAD10STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10STRNG */ + GPIO_PADREGC_PAD10STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD10STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD10STRNG_Enum; + +/* =========================================== GPIO PADREGC PAD10INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10INPEN */ + GPIO_PADREGC_PAD10INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD10INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD10INPEN_Enum; + +/* ============================================ GPIO PADREGC PAD10PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10PULL */ + GPIO_PADREGC_PAD10PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD10PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD10PULL_Enum; + +/* ============================================ GPIO PADREGC PAD9RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD9RSEL */ + GPIO_PADREGC_PAD9RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGC_PAD9RSEL_Enum; + +/* =========================================== GPIO PADREGC PAD9FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD9FNCSEL */ + GPIO_PADREGC_PAD9FNCSEL_M1SDA = 0, /*!< M1SDA : Configure as the IOMSTR1 I2C SDA signal */ + GPIO_PADREGC_PAD9FNCSEL_M1MISO = 1, /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal */ + GPIO_PADREGC_PAD9FNCSEL_M0nCE5 = 2, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */ + GPIO_PADREGC_PAD9FNCSEL_GPIO9 = 3, /*!< GPIO9 : Configure as GPIO9 */ + GPIO_PADREGC_PAD9FNCSEL_M4nCE5 = 4, /*!< M4nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR4 */ + GPIO_PADREGC_PAD9FNCSEL_SLMISOLB = 5, /*!< SLMISOLB : Configure as the IOMSTR1 SPI MISO loopback signal + from IOSLAVE */ + GPIO_PADREGC_PAD9FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as UART1 RX input signal */ + GPIO_PADREGC_PAD9FNCSEL_SLSDALB = 7, /*!< SLSDALB : Configure as the IOMSTR1 I2C SDA loopback signal from + IOSLAVE */ +} GPIO_PADREGC_PAD9FNCSEL_Enum; + +/* ============================================ GPIO PADREGC PAD9STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD9STRNG */ + GPIO_PADREGC_PAD9STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD9STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD9STRNG_Enum; + +/* ============================================= GPIO PADREGC PAD9INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD9INPEN */ + GPIO_PADREGC_PAD9INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD9INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD9INPEN_Enum; + +/* ============================================= GPIO PADREGC PAD9PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD9PULL */ + GPIO_PADREGC_PAD9PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD9PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD9PULL_Enum; + +/* ============================================= GPIO PADREGC PAD8RSEL [6..7] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD8RSEL */ + GPIO_PADREGC_PAD8RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGC_PAD8RSEL_Enum; + +/* ============================================ GPIO PADREGC PAD8FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8FNCSEL */ + GPIO_PADREGC_PAD8FNCSEL_M1SCL = 0, /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal */ + GPIO_PADREGC_PAD8FNCSEL_M1SCK = 1, /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal */ + GPIO_PADREGC_PAD8FNCSEL_M0nCE4 = 2, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */ + GPIO_PADREGC_PAD8FNCSEL_GPIO8 = 3, /*!< GPIO8 : Configure as GPIO8 */ + GPIO_PADREGC_PAD8FNCSEL_M2nCE4 = 4, /*!< M2nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR2 */ + GPIO_PADREGC_PAD8FNCSEL_M1SCKLB = 5, /*!< M1SCKLB : Configure as the IOMSTR1 SPI SCK loopback signal from + IOSLAVE */ + GPIO_PADREGC_PAD8FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGC_PAD8FNCSEL_M1SCLLB = 7, /*!< M1SCLLB : Configure as the IOMSTR1 I2C SCL loopback signal from + IOSLAVE */ +} GPIO_PADREGC_PAD8FNCSEL_Enum; + +/* ============================================= GPIO PADREGC PAD8STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8STRNG */ + GPIO_PADREGC_PAD8STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD8STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD8STRNG_Enum; + +/* ============================================= GPIO PADREGC PAD8INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8INPEN */ + GPIO_PADREGC_PAD8INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD8INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD8INPEN_Enum; + +/* ============================================= GPIO PADREGC PAD8PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD8PULL */ + GPIO_PADREGC_PAD8PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD8PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD8PULL_Enum; + +/* ======================================================== PADREGD ======================================================== */ +/* =========================================== GPIO PADREGD PAD15FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD15FNCSEL */ + GPIO_PADREGD_PAD15FNCSEL_ADCD1N = 0, /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input + signal */ + GPIO_PADREGD_PAD15FNCSEL_M1nCE3 = 1, /*!< M1nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR1 */ + GPIO_PADREGD_PAD15FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX signal */ + GPIO_PADREGD_PAD15FNCSEL_GPIO15 = 3, /*!< GPIO15 : Configure as GPIO15 */ + GPIO_PADREGD_PAD15FNCSEL_M2nCE2 = 4, /*!< M2nCE2 : Configure as the SPI Channel 2 nCE signal from IOMSTR2 */ + GPIO_PADREGD_PAD15FNCSEL_EXTXT = 5, /*!< EXTXT : Configure as the external XTAL oscillator input */ + GPIO_PADREGD_PAD15FNCSEL_SWDIO = 6, /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal */ + GPIO_PADREGD_PAD15FNCSEL_SWO = 7, /*!< SWO : Configure as an SWO (Serial Wire Trace output) */ +} GPIO_PADREGD_PAD15FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD15STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15STRNG */ + GPIO_PADREGD_PAD15STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD15STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD15STRNG_Enum; + +/* =========================================== GPIO PADREGD PAD15INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15INPEN */ + GPIO_PADREGD_PAD15INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD15INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD15INPEN_Enum; + +/* ============================================ GPIO PADREGD PAD15PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15PULL */ + GPIO_PADREGD_PAD15PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD15PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD15PULL_Enum; + +/* =========================================== GPIO PADREGD PAD14FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD14FNCSEL */ + GPIO_PADREGD_PAD14FNCSEL_ADCD1P = 0, /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input + signal */ + GPIO_PADREGD_PAD14FNCSEL_M1nCE2 = 1, /*!< M1nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR1 */ + GPIO_PADREGD_PAD14FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGD_PAD14FNCSEL_GPIO14 = 3, /*!< GPIO14 : Configure as GPIO14 */ + GPIO_PADREGD_PAD14FNCSEL_M2nCE1 = 4, /*!< M2nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR2 */ + GPIO_PADREGD_PAD14FNCSEL_EXTHFS = 5, /*!< EXTHFS : Configure as the External HFRC oscillator input select */ + GPIO_PADREGD_PAD14FNCSEL_SWDCK = 6, /*!< SWDCK : Configure as the alternate input for the SWDCK input + signal */ + GPIO_PADREGD_PAD14FNCSEL_32khz_XT = 7, /*!< 32khz_XT : Configure as the 32kHz crystal output signal */ +} GPIO_PADREGD_PAD14FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD14STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14STRNG */ + GPIO_PADREGD_PAD14STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD14STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD14STRNG_Enum; + +/* =========================================== GPIO PADREGD PAD14INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14INPEN */ + GPIO_PADREGD_PAD14INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD14INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD14INPEN_Enum; + +/* ============================================ GPIO PADREGD PAD14PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14PULL */ + GPIO_PADREGD_PAD14PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD14PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD14PULL_Enum; + +/* =========================================== GPIO PADREGD PAD13FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD13FNCSEL */ + GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8 = 0, /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single + Ended input 8 analog input signal. Determination of the + D0P vs SE8 usage is done when the particular channel is + selected within the ADC module */ + GPIO_PADREGD_PAD13FNCSEL_M1nCE1 = 1, /*!< M1nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR1 */ + GPIO_PADREGD_PAD13FNCSEL_TCTB0 = 2, /*!< TCTB0 : Configure as the input/output signal from CTIMER B0 */ + GPIO_PADREGD_PAD13FNCSEL_GPIO13 = 3, /*!< GPIO13 : Configure as GPIO13 */ + GPIO_PADREGD_PAD13FNCSEL_M2nCE3 = 4, /*!< M2nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR2 */ + GPIO_PADREGD_PAD13FNCSEL_EXTHFB = 5, /*!< EXTHFB : Configure as the external HFRC oscillator input */ + GPIO_PADREGD_PAD13FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS signal output */ + GPIO_PADREGD_PAD13FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGD_PAD13FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD13STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD13STRNG */ + GPIO_PADREGD_PAD13STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD13STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD13STRNG_Enum; + +/* ============================================ GPIO PADREGD PAD13INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD13INPEN */ + GPIO_PADREGD_PAD13INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD13INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD13INPEN_Enum; + +/* ============================================= GPIO PADREGD PAD13PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD13PULL */ + GPIO_PADREGD_PAD13PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD13PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD13PULL_Enum; + +/* ============================================ GPIO PADREGD PAD12FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD12FNCSEL */ + GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9 = 0, /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single + Ended input 9 analog input signal. Determination of the + D0N vs SE9 usage is done when the particular channel is + selected within the ADC module */ + GPIO_PADREGD_PAD12FNCSEL_M1nCE0 = 1, /*!< M1nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR1 */ + GPIO_PADREGD_PAD12FNCSEL_TCTA0 = 2, /*!< TCTA0 : Configure as the input/output signal from CTIMER A0 */ + GPIO_PADREGD_PAD12FNCSEL_GPIO12 = 3, /*!< GPIO12 : Configure as GPIO12 */ + GPIO_PADREGD_PAD12FNCSEL_CLKOUT = 4, /*!< CLKOUT : Configure as CLKOUT signal */ + GPIO_PADREGD_PAD12FNCSEL_PDM_CLK = 5, /*!< PDM_CLK : Configure as the PDM CLK output signal */ + GPIO_PADREGD_PAD12FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGD_PAD12FNCSEL_UART1TX = 7, /*!< UART1TX : Configure as the UART1 TX output signal */ +} GPIO_PADREGD_PAD12FNCSEL_Enum; + +/* ============================================ GPIO PADREGD PAD12STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12STRNG */ + GPIO_PADREGD_PAD12STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD12STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD12STRNG_Enum; + +/* ============================================ GPIO PADREGD PAD12INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12INPEN */ + GPIO_PADREGD_PAD12INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD12INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD12INPEN_Enum; + +/* ============================================= GPIO PADREGD PAD12PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12PULL */ + GPIO_PADREGD_PAD12PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD12PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD12PULL_Enum; + +/* ======================================================== PADREGE ======================================================== */ +/* =========================================== GPIO PADREGE PAD19FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD19FNCSEL */ + GPIO_PADREGE_PAD19FNCSEL_CMPRF0 = 0, /*!< CMPRF0 : Configure as the analog comparator reference 0 signal */ + GPIO_PADREGE_PAD19FNCSEL_M0nCE3 = 1, /*!< M0nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR0 */ + GPIO_PADREGE_PAD19FNCSEL_TCTB1 = 2, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGE_PAD19FNCSEL_GPIO19 = 3, /*!< GPIO19 : Configure as GPIO19 */ + GPIO_PADREGE_PAD19FNCSEL_TCTA1 = 4, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGE_PAD19FNCSEL_ANATEST1 = 5, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ + GPIO_PADREGE_PAD19FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGE_PAD19FNCSEL_I2S_BCLK = 7, /*!< I2S_BCLK : Configure as the I2S Byte clock input signal */ +} GPIO_PADREGE_PAD19FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD19STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19STRNG */ + GPIO_PADREGE_PAD19STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD19STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD19STRNG_Enum; + +/* =========================================== GPIO PADREGE PAD19INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19INPEN */ + GPIO_PADREGE_PAD19INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD19INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD19INPEN_Enum; + +/* ============================================ GPIO PADREGE PAD19PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19PULL */ + GPIO_PADREGE_PAD19PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD19PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD19PULL_Enum; + +/* =========================================== GPIO PADREGE PAD18FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD18FNCSEL */ + GPIO_PADREGE_PAD18FNCSEL_CMPIN1 = 0, /*!< CMPIN1 : Configure as the analog comparator input 1 signal */ + GPIO_PADREGE_PAD18FNCSEL_M0nCE2 = 1, /*!< M0nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR0 */ + GPIO_PADREGE_PAD18FNCSEL_TCTA1 = 2, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGE_PAD18FNCSEL_GPIO18 = 3, /*!< GPIO18 : Configure as GPIO18 */ + GPIO_PADREGE_PAD18FNCSEL_M4nCE1 = 4, /*!< M4nCE1 : Configure as the SPI nCE channel 1 from IOMSTR4 */ + GPIO_PADREGE_PAD18FNCSEL_ANATEST2 = 5, /*!< ANATEST2 : Configure as ANATEST2 I/O signal */ + GPIO_PADREGE_PAD18FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGE_PAD18FNCSEL_32khz_XT = 7, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */ +} GPIO_PADREGE_PAD18FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD18STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18STRNG */ + GPIO_PADREGE_PAD18STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD18STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD18STRNG_Enum; + +/* =========================================== GPIO PADREGE PAD18INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18INPEN */ + GPIO_PADREGE_PAD18INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD18INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD18INPEN_Enum; + +/* ============================================ GPIO PADREGE PAD18PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18PULL */ + GPIO_PADREGE_PAD18PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD18PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD18PULL_Enum; + +/* =========================================== GPIO PADREGE PAD17FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD17FNCSEL */ + GPIO_PADREGE_PAD17FNCSEL_CMPRF1 = 0, /*!< CMPRF1 : Configure as the analog comparator reference signal + 1 input signal */ + GPIO_PADREGE_PAD17FNCSEL_M0nCE1 = 1, /*!< M0nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR0 */ + GPIO_PADREGE_PAD17FNCSEL_TRIG1 = 2, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGE_PAD17FNCSEL_GPIO17 = 3, /*!< GPIO17 : Configure as GPIO17 */ + GPIO_PADREGE_PAD17FNCSEL_M4nCE3 = 4, /*!< M4nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR4 */ + GPIO_PADREGE_PAD17FNCSEL_EXTLF = 5, /*!< EXTLF : Configure as external LFRC oscillator input */ + GPIO_PADREGE_PAD17FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGE_PAD17FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGE_PAD17FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD17STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD17STRNG */ + GPIO_PADREGE_PAD17STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD17STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD17STRNG_Enum; + +/* ============================================ GPIO PADREGE PAD17INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD17INPEN */ + GPIO_PADREGE_PAD17INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD17INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD17INPEN_Enum; + +/* ============================================= GPIO PADREGE PAD17PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD17PULL */ + GPIO_PADREGE_PAD17PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD17PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD17PULL_Enum; + +/* ============================================ GPIO PADREGE PAD16FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD16FNCSEL */ + GPIO_PADREGE_PAD16FNCSEL_ADCSE0 = 0, /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input + signal */ + GPIO_PADREGE_PAD16FNCSEL_M0nCE4 = 1, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */ + GPIO_PADREGE_PAD16FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGE_PAD16FNCSEL_GPIO16 = 3, /*!< GPIO16 : Configure as GPIO16 */ + GPIO_PADREGE_PAD16FNCSEL_M2nCE3 = 4, /*!< M2nCE3 : Configure as SPI channel 3 nCE for IOMSTR2 */ + GPIO_PADREGE_PAD16FNCSEL_CMPIN0 = 5, /*!< CMPIN0 : Configure as comparator input 0 signal */ + GPIO_PADREGE_PAD16FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGE_PAD16FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGE_PAD16FNCSEL_Enum; + +/* ============================================ GPIO PADREGE PAD16STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16STRNG */ + GPIO_PADREGE_PAD16STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD16STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD16STRNG_Enum; + +/* ============================================ GPIO PADREGE PAD16INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16INPEN */ + GPIO_PADREGE_PAD16INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD16INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD16INPEN_Enum; + +/* ============================================= GPIO PADREGE PAD16PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16PULL */ + GPIO_PADREGE_PAD16PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD16PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD16PULL_Enum; + +/* ======================================================== PADREGF ======================================================== */ +/* =========================================== GPIO PADREGF PAD23FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD23FNCSEL */ + GPIO_PADREGF_PAD23FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX signal */ + GPIO_PADREGF_PAD23FNCSEL_M0nCE0 = 1, /*!< M0nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR0 */ + GPIO_PADREGF_PAD23FNCSEL_TCTB3 = 2, /*!< TCTB3 : Configure as the input/output signal from CTIMER B3 */ + GPIO_PADREGF_PAD23FNCSEL_GPIO23 = 3, /*!< GPIO23 : Configure as GPIO23 */ + GPIO_PADREGF_PAD23FNCSEL_PDM_DATA = 4, /*!< PDM_DATA : Configure as PDM Data input to the PDM module */ + GPIO_PADREGF_PAD23FNCSEL_CMPOUT = 5, /*!< CMPOUT : Configure as voltage comparitor output */ + GPIO_PADREGF_PAD23FNCSEL_TCTB1 = 6, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGF_PAD23FNCSEL_UNDEF7 = 7, /*!< UNDEF7 : Undefined/should not be used */ +} GPIO_PADREGF_PAD23FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD23STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23STRNG */ + GPIO_PADREGF_PAD23STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD23STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD23STRNG_Enum; + +/* =========================================== GPIO PADREGF PAD23INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23INPEN */ + GPIO_PADREGF_PAD23INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD23INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD23INPEN_Enum; + +/* ============================================ GPIO PADREGF PAD23PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23PULL */ + GPIO_PADREGF_PAD23PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD23PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD23PULL_Enum; + +/* =========================================== GPIO PADREGF PAD22PWRUP [23..23] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22PWRUP */ + GPIO_PADREGF_PAD22PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGF_PAD22PWRUP_EN = 1, /*!< EN : Power switch enabled */ +} GPIO_PADREGF_PAD22PWRUP_Enum; + +/* =========================================== GPIO PADREGF PAD22FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD22FNCSEL */ + GPIO_PADREGF_PAD22FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX signal */ + GPIO_PADREGF_PAD22FNCSEL_M1nCE7 = 1, /*!< M1nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR1 */ + GPIO_PADREGF_PAD22FNCSEL_TCTA3 = 2, /*!< TCTA3 : Configure as the input/output signal from CTIMER A3 */ + GPIO_PADREGF_PAD22FNCSEL_GPIO22 = 3, /*!< GPIO22 : Configure as GPIO22 */ + GPIO_PADREGF_PAD22FNCSEL_PDM_CLK = 4, /*!< PDM_CLK : Configure as the PDM CLK output */ + GPIO_PADREGF_PAD22FNCSEL_UNDEF5 = 5, /*!< UNDEF5 : Undefined/should not be used */ + GPIO_PADREGF_PAD22FNCSEL_TCTB1 = 6, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGF_PAD22FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGF_PAD22FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD22STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22STRNG */ + GPIO_PADREGF_PAD22STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD22STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD22STRNG_Enum; + +/* =========================================== GPIO PADREGF PAD22INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22INPEN */ + GPIO_PADREGF_PAD22INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD22INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD22INPEN_Enum; + +/* ============================================ GPIO PADREGF PAD22PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22PULL */ + GPIO_PADREGF_PAD22PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD22PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD22PULL_Enum; + +/* =========================================== GPIO PADREGF PAD21FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD21FNCSEL */ + GPIO_PADREGF_PAD21FNCSEL_SWDIO = 0, /*!< SWDIO : Configure as the serial wire debug data signal */ + GPIO_PADREGF_PAD21FNCSEL_M1nCE6 = 1, /*!< M1nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR1 */ + GPIO_PADREGF_PAD21FNCSEL_TCTB2 = 2, /*!< TCTB2 : Configure as the input/output signal from CTIMER B2 */ + GPIO_PADREGF_PAD21FNCSEL_GPIO21 = 3, /*!< GPIO21 : Configure as GPIO21 */ + GPIO_PADREGF_PAD21FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGF_PAD21FNCSEL_UART1RX = 5, /*!< UART1RX : Configure as UART1 RX input signal */ + GPIO_PADREGF_PAD21FNCSEL_UNDEF6 = 6, /*!< UNDEF6 : Undefined/should not be used */ + GPIO_PADREGF_PAD21FNCSEL_UNDEF7 = 7, /*!< UNDEF7 : Undefined/should not be used */ +} GPIO_PADREGF_PAD21FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD21STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD21STRNG */ + GPIO_PADREGF_PAD21STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD21STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD21STRNG_Enum; + +/* ============================================ GPIO PADREGF PAD21INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD21INPEN */ + GPIO_PADREGF_PAD21INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD21INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD21INPEN_Enum; + +/* ============================================= GPIO PADREGF PAD21PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD21PULL */ + GPIO_PADREGF_PAD21PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD21PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD21PULL_Enum; + +/* ============================================ GPIO PADREGF PAD20FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD20FNCSEL */ + GPIO_PADREGF_PAD20FNCSEL_SWDCK = 0, /*!< SWDCK : Configure as the serial wire debug clock signal */ + GPIO_PADREGF_PAD20FNCSEL_M1nCE5 = 1, /*!< M1nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR1 */ + GPIO_PADREGF_PAD20FNCSEL_TCTA2 = 2, /*!< TCTA2 : Configure as the input/output signal from CTIMER A2 */ + GPIO_PADREGF_PAD20FNCSEL_GPIO20 = 3, /*!< GPIO20 : Configure as GPIO20 */ + GPIO_PADREGF_PAD20FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGF_PAD20FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGF_PAD20FNCSEL_UNDEF6 = 6, /*!< UNDEF6 : Undefined/should not be used */ + GPIO_PADREGF_PAD20FNCSEL_UNDEF7 = 7, /*!< UNDEF7 : Undefined/should not be used */ +} GPIO_PADREGF_PAD20FNCSEL_Enum; + +/* ============================================ GPIO PADREGF PAD20STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20STRNG */ + GPIO_PADREGF_PAD20STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD20STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD20STRNG_Enum; + +/* ============================================ GPIO PADREGF PAD20INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20INPEN */ + GPIO_PADREGF_PAD20INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD20INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD20INPEN_Enum; + +/* ============================================= GPIO PADREGF PAD20PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20PULL */ + GPIO_PADREGF_PAD20PULL_DIS = 0, /*!< DIS : Pulldown disabled */ + GPIO_PADREGF_PAD20PULL_EN = 1, /*!< EN : Pulldown enabled */ +} GPIO_PADREGF_PAD20PULL_Enum; + +/* ======================================================== PADREGG ======================================================== */ +/* ============================================ GPIO PADREGG PAD27RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27RSEL */ + GPIO_PADREGG_PAD27RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGG_PAD27RSEL_Enum; + +/* =========================================== GPIO PADREGG PAD27FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD27FNCSEL */ + GPIO_PADREGG_PAD27FNCSEL_EXTHF = 0, /*!< EXTHF : Configure as the external HFRC oscillator input */ + GPIO_PADREGG_PAD27FNCSEL_M1nCE4 = 1, /*!< M1nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR1 */ + GPIO_PADREGG_PAD27FNCSEL_TCTA1 = 2, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGG_PAD27FNCSEL_GPIO27 = 3, /*!< GPIO27 : Configure as GPIO27 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCL = 4, /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCK = 5, /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCKLB = 6, /*!< M2SCKLB : Configure as IOMSTR2 SPI SCK loopback signal from + IOSLAVE */ + GPIO_PADREGG_PAD27FNCSEL_M2SCLLB = 7, /*!< M2SCLLB : Configure as IOMSTR2 I2C SCL loopback signal from + IOSLAVE */ +} GPIO_PADREGG_PAD27FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD27STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27STRNG */ + GPIO_PADREGG_PAD27STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD27STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD27STRNG_Enum; + +/* =========================================== GPIO PADREGG PAD27INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27INPEN */ + GPIO_PADREGG_PAD27INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD27INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD27INPEN_Enum; + +/* ============================================ GPIO PADREGG PAD27PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27PULL */ + GPIO_PADREGG_PAD27PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD27PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD27PULL_Enum; + +/* =========================================== GPIO PADREGG PAD26FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD26FNCSEL */ + GPIO_PADREGG_PAD26FNCSEL_EXTLF = 0, /*!< EXTLF : Configure as the external LFRC oscillator input */ + GPIO_PADREGG_PAD26FNCSEL_M0nCE3 = 1, /*!< M0nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR0 */ + GPIO_PADREGG_PAD26FNCSEL_TCTB0 = 2, /*!< TCTB0 : Configure as the input/output signal from CTIMER B0 */ + GPIO_PADREGG_PAD26FNCSEL_GPIO26 = 3, /*!< GPIO26 : Configure as GPIO26 */ + GPIO_PADREGG_PAD26FNCSEL_M2nCE0 = 4, /*!< M2nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR2 */ + GPIO_PADREGG_PAD26FNCSEL_TCTA1 = 5, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGG_PAD26FNCSEL_M5nCE1 = 6, /*!< M5nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR5 */ + GPIO_PADREGG_PAD26FNCSEL_M3nCE0 = 7, /*!< M3nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR3 */ +} GPIO_PADREGG_PAD26FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD26STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26STRNG */ + GPIO_PADREGG_PAD26STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD26STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD26STRNG_Enum; + +/* =========================================== GPIO PADREGG PAD26INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26INPEN */ + GPIO_PADREGG_PAD26INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD26INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD26INPEN_Enum; + +/* ============================================ GPIO PADREGG PAD26PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26PULL */ + GPIO_PADREGG_PAD26PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD26PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD26PULL_Enum; + +/* ============================================ GPIO PADREGG PAD25RSEL [14..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD25RSEL */ + GPIO_PADREGG_PAD25RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGG_PAD25RSEL_Enum; + +/* =========================================== GPIO PADREGG PAD25FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD25FNCSEL */ + GPIO_PADREGG_PAD25FNCSEL_EXTXT = 0, /*!< EXTXT : Configure as the external XTAL oscillator input */ + GPIO_PADREGG_PAD25FNCSEL_M0nCE2 = 1, /*!< M0nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR0 */ + GPIO_PADREGG_PAD25FNCSEL_TCTA0 = 2, /*!< TCTA0 : Configure as the input/output signal from CTIMER A0 */ + GPIO_PADREGG_PAD25FNCSEL_GPIO25 = 3, /*!< GPIO25 : Configure as GPIO25 */ + GPIO_PADREGG_PAD25FNCSEL_M2SDA = 4, /*!< M2SDA : Configure as the IOMSTR2 I2C Serial data I/O signal */ + GPIO_PADREGG_PAD25FNCSEL_M2MISO = 5, /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal */ + GPIO_PADREGG_PAD25FNCSEL_SLMISOLB = 6, /*!< SLMISOLB : Configure as the IOMSTR0 SPI MISO loopback signal + from IOSLAVE */ + GPIO_PADREGG_PAD25FNCSEL_SLSDALB = 7, /*!< SLSDALB : Configure as the IOMSTR0 I2C SDA loopback signal from + IOSLAVE */ +} GPIO_PADREGG_PAD25FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD25STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD25STRNG */ + GPIO_PADREGG_PAD25STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD25STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD25STRNG_Enum; + +/* ============================================ GPIO PADREGG PAD25INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD25INPEN */ + GPIO_PADREGG_PAD25INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD25INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD25INPEN_Enum; + +/* ============================================= GPIO PADREGG PAD25PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD25PULL */ + GPIO_PADREGG_PAD25PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD25PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD25PULL_Enum; + +/* ============================================ GPIO PADREGG PAD24FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD24FNCSEL */ + GPIO_PADREGG_PAD24FNCSEL_M2nCE1 = 0, /*!< M2nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR2 */ + GPIO_PADREGG_PAD24FNCSEL_M0nCE1 = 1, /*!< M0nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR0 */ + GPIO_PADREGG_PAD24FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGG_PAD24FNCSEL_GPIO24 = 3, /*!< GPIO24 : Configure as GPIO24 */ + GPIO_PADREGG_PAD24FNCSEL_M5nCE0 = 4, /*!< M5nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR5 */ + GPIO_PADREGG_PAD24FNCSEL_TCTA1 = 5, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGG_PAD24FNCSEL_I2S_BCLK = 6, /*!< I2S_BCLK : Configure as the I2S Byte clock input signal */ + GPIO_PADREGG_PAD24FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGG_PAD24FNCSEL_Enum; + +/* ============================================ GPIO PADREGG PAD24STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24STRNG */ + GPIO_PADREGG_PAD24STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD24STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD24STRNG_Enum; + +/* ============================================ GPIO PADREGG PAD24INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24INPEN */ + GPIO_PADREGG_PAD24INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD24INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD24INPEN_Enum; + +/* ============================================= GPIO PADREGG PAD24PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24PULL */ + GPIO_PADREGG_PAD24PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD24PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD24PULL_Enum; + +/* ======================================================== PADREGH ======================================================== */ +/* =========================================== GPIO PADREGH PAD31FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD31FNCSEL */ + GPIO_PADREGH_PAD31FNCSEL_ADCSE3 = 0, /*!< ADCSE3 : Configure as the analog input for ADC single ended + input 3 */ + GPIO_PADREGH_PAD31FNCSEL_M0nCE4 = 1, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */ + GPIO_PADREGH_PAD31FNCSEL_TCTA3 = 2, /*!< TCTA3 : Configure as the input/output signal from CTIMER A3 */ + GPIO_PADREGH_PAD31FNCSEL_GPIO31 = 3, /*!< GPIO31 : Configure as GPIO31 */ + GPIO_PADREGH_PAD31FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGH_PAD31FNCSEL_TCTB1 = 5, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGH_PAD31FNCSEL_UNDEF6 = 6, /*!< UNDEF6 : Undefined/should not be used */ + GPIO_PADREGH_PAD31FNCSEL_UNDEF7 = 7, /*!< UNDEF7 : Undefined/should not be used */ +} GPIO_PADREGH_PAD31FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD31STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31STRNG */ + GPIO_PADREGH_PAD31STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD31STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD31STRNG_Enum; + +/* =========================================== GPIO PADREGH PAD31INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31INPEN */ + GPIO_PADREGH_PAD31INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD31INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD31INPEN_Enum; + +/* ============================================ GPIO PADREGH PAD31PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31PULL */ + GPIO_PADREGH_PAD31PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD31PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD31PULL_Enum; + +/* =========================================== GPIO PADREGH PAD30FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD30FNCSEL */ + GPIO_PADREGH_PAD30FNCSEL_UNDEF0 = 0, /*!< UNDEF0 : Undefined/should not be used */ + GPIO_PADREGH_PAD30FNCSEL_M1nCE7 = 1, /*!< M1nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR1 */ + GPIO_PADREGH_PAD30FNCSEL_TCTB2 = 2, /*!< TCTB2 : Configure as the input/output signal from CTIMER B2 */ + GPIO_PADREGH_PAD30FNCSEL_GPIO30 = 3, /*!< GPIO30 : Configure as GPIO30 */ + GPIO_PADREGH_PAD30FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGH_PAD30FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as UART1 RTS output signal */ + GPIO_PADREGH_PAD30FNCSEL_UNDEF6 = 6, /*!< UNDEF6 : Undefined/should not be used */ + GPIO_PADREGH_PAD30FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the I2S Data output signal */ +} GPIO_PADREGH_PAD30FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD30STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30STRNG */ + GPIO_PADREGH_PAD30STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD30STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD30STRNG_Enum; + +/* =========================================== GPIO PADREGH PAD30INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30INPEN */ + GPIO_PADREGH_PAD30INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD30INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD30INPEN_Enum; + +/* ============================================ GPIO PADREGH PAD30PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30PULL */ + GPIO_PADREGH_PAD30PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD30PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD30PULL_Enum; + +/* =========================================== GPIO PADREGH PAD29FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD29FNCSEL */ + GPIO_PADREGH_PAD29FNCSEL_ADCSE1 = 0, /*!< ADCSE1 : Configure as the analog input for ADC single ended + input 1 */ + GPIO_PADREGH_PAD29FNCSEL_M1nCE6 = 1, /*!< M1nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR1 */ + GPIO_PADREGH_PAD29FNCSEL_TCTA2 = 2, /*!< TCTA2 : Configure as the input/output signal from CTIMER A2 */ + GPIO_PADREGH_PAD29FNCSEL_GPIO29 = 3, /*!< GPIO29 : Configure as GPIO29 */ + GPIO_PADREGH_PAD29FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS signal */ + GPIO_PADREGH_PAD29FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS signal */ + GPIO_PADREGH_PAD29FNCSEL_M4nCE0 = 6, /*!< M4nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR4 */ + GPIO_PADREGH_PAD29FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as PDM DATA input */ +} GPIO_PADREGH_PAD29FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD29STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD29STRNG */ + GPIO_PADREGH_PAD29STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD29STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD29STRNG_Enum; + +/* ============================================ GPIO PADREGH PAD29INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD29INPEN */ + GPIO_PADREGH_PAD29INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD29INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD29INPEN_Enum; + +/* ============================================= GPIO PADREGH PAD29PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD29PULL */ + GPIO_PADREGH_PAD29PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD29PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD29PULL_Enum; + +/* ============================================ GPIO PADREGH PAD28FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD28FNCSEL */ + GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK = 0, /*!< I2S_WCLK : Configure as the I2S Word Clock input */ + GPIO_PADREGH_PAD28FNCSEL_M1nCE5 = 1, /*!< M1nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR1 */ + GPIO_PADREGH_PAD28FNCSEL_TCTB1 = 2, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGH_PAD28FNCSEL_GPIO28 = 3, /*!< GPIO28 : Configure as GPIO28 */ + GPIO_PADREGH_PAD28FNCSEL_M2WIR3 = 4, /*!< M2WIR3 : Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGH_PAD28FNCSEL_M2MOSI = 5, /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal */ + GPIO_PADREGH_PAD28FNCSEL_M5nCE3 = 6, /*!< M5nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR5 */ + GPIO_PADREGH_PAD28FNCSEL_SLWIR3LB = 7, /*!< SLWIR3LB : Configure as the IOMSTR2 SPI 3-wire MOSI/MISO loopback + signal from IOSLAVE */ +} GPIO_PADREGH_PAD28FNCSEL_Enum; + +/* ============================================ GPIO PADREGH PAD28STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28STRNG */ + GPIO_PADREGH_PAD28STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD28STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD28STRNG_Enum; + +/* ============================================ GPIO PADREGH PAD28INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28INPEN */ + GPIO_PADREGH_PAD28INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD28INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD28INPEN_Enum; + +/* ============================================= GPIO PADREGH PAD28PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28PULL */ + GPIO_PADREGH_PAD28PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD28PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD28PULL_Enum; + +/* ======================================================== PADREGI ======================================================== */ +/* =========================================== GPIO PADREGI PAD35FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD35FNCSEL */ + GPIO_PADREGI_PAD35FNCSEL_ADCSE7 = 0, /*!< ADCSE7 : Configure as the analog input for ADC single ended + input 7 */ + GPIO_PADREGI_PAD35FNCSEL_M1nCE0 = 1, /*!< M1nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR1 */ + GPIO_PADREGI_PAD35FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX signal */ + GPIO_PADREGI_PAD35FNCSEL_GPIO35 = 3, /*!< GPIO35 : Configure as GPIO35 */ + GPIO_PADREGI_PAD35FNCSEL_M4nCE6 = 4, /*!< M4nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR4 */ + GPIO_PADREGI_PAD35FNCSEL_TCTA1 = 5, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGI_PAD35FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS output */ + GPIO_PADREGI_PAD35FNCSEL_M3nCE2 = 7, /*!< M3nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR3 */ +} GPIO_PADREGI_PAD35FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD35STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35STRNG */ + GPIO_PADREGI_PAD35STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD35STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD35STRNG_Enum; + +/* =========================================== GPIO PADREGI PAD35INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35INPEN */ + GPIO_PADREGI_PAD35INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD35INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD35INPEN_Enum; + +/* ============================================ GPIO PADREGI PAD35PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35PULL */ + GPIO_PADREGI_PAD35PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD35PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD35PULL_Enum; + +/* =========================================== GPIO PADREGI PAD34FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD34FNCSEL */ + GPIO_PADREGI_PAD34FNCSEL_ADCSE6 = 0, /*!< ADCSE6 : Configure as the analog input for ADC single ended + input 6 */ + GPIO_PADREGI_PAD34FNCSEL_M0nCE7 = 1, /*!< M0nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR0 */ + GPIO_PADREGI_PAD34FNCSEL_M2nCE3 = 2, /*!< M2nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR2 */ + GPIO_PADREGI_PAD34FNCSEL_GPIO34 = 3, /*!< GPIO34 : Configure as GPIO34 */ + GPIO_PADREGI_PAD34FNCSEL_CMPRF2 = 4, /*!< CMPRF2 : Configure as the analog comparator reference 2 signal */ + GPIO_PADREGI_PAD34FNCSEL_M3nCE1 = 5, /*!< M3nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR3 */ + GPIO_PADREGI_PAD34FNCSEL_M4nCE0 = 6, /*!< M4nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR4 */ + GPIO_PADREGI_PAD34FNCSEL_M5nCE2 = 7, /*!< M5nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR5 */ +} GPIO_PADREGI_PAD34FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD34STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34STRNG */ + GPIO_PADREGI_PAD34STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD34STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD34STRNG_Enum; + +/* =========================================== GPIO PADREGI PAD34INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34INPEN */ + GPIO_PADREGI_PAD34INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD34INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD34INPEN_Enum; + +/* ============================================ GPIO PADREGI PAD34PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34PULL */ + GPIO_PADREGI_PAD34PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD34PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD34PULL_Enum; + +/* =========================================== GPIO PADREGI PAD33FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD33FNCSEL */ + GPIO_PADREGI_PAD33FNCSEL_ADCSE5 = 0, /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input + signal */ + GPIO_PADREGI_PAD33FNCSEL_M0nCE6 = 1, /*!< M0nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR0 */ + GPIO_PADREGI_PAD33FNCSEL_32khz_XT = 2, /*!< 32khz_XT : Configure as the 32kHz crystal output signal */ + GPIO_PADREGI_PAD33FNCSEL_GPIO33 = 3, /*!< GPIO33 : Configure as GPIO33 */ + GPIO_PADREGI_PAD33FNCSEL_UNDEF4 = 4, /*!< UNDEF4 : Undefined/should not be used */ + GPIO_PADREGI_PAD33FNCSEL_M3nCE7 = 5, /*!< M3nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR3 */ + GPIO_PADREGI_PAD33FNCSEL_TCTB1 = 6, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGI_PAD33FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGI_PAD33FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD33STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD33STRNG */ + GPIO_PADREGI_PAD33STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD33STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD33STRNG_Enum; + +/* ============================================ GPIO PADREGI PAD33INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD33INPEN */ + GPIO_PADREGI_PAD33INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD33INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD33INPEN_Enum; + +/* ============================================= GPIO PADREGI PAD33PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD33PULL */ + GPIO_PADREGI_PAD33PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD33PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD33PULL_Enum; + +/* ============================================ GPIO PADREGI PAD32FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD32FNCSEL */ + GPIO_PADREGI_PAD32FNCSEL_ADCSE4 = 0, /*!< ADCSE4 : Configure as the analog input for ADC single ended + input 4 */ + GPIO_PADREGI_PAD32FNCSEL_M0nCE5 = 1, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */ + GPIO_PADREGI_PAD32FNCSEL_TCTB3 = 2, /*!< TCTB3 : Configure as the input/output signal from CTIMER B3 */ + GPIO_PADREGI_PAD32FNCSEL_GPIO32 = 3, /*!< GPIO32 : Configure as GPIO32 */ + GPIO_PADREGI_PAD32FNCSEL_UNDEF4 = 4, /*!< UNDEF4 : Undefined/should not be used */ + GPIO_PADREGI_PAD32FNCSEL_TCTB1 = 5, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGI_PAD32FNCSEL_UNDEF6 = 6, /*!< UNDEF6 : Undefined/should not be used */ + GPIO_PADREGI_PAD32FNCSEL_UNDEF7 = 7, /*!< UNDEF7 : Undefined/should not be used */ +} GPIO_PADREGI_PAD32FNCSEL_Enum; + +/* ============================================ GPIO PADREGI PAD32STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32STRNG */ + GPIO_PADREGI_PAD32STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD32STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD32STRNG_Enum; + +/* ============================================ GPIO PADREGI PAD32INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32INPEN */ + GPIO_PADREGI_PAD32INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD32INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD32INPEN_Enum; + +/* ============================================= GPIO PADREGI PAD32PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32PULL */ + GPIO_PADREGI_PAD32PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD32PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD32PULL_Enum; + +/* ======================================================== PADREGJ ======================================================== */ +/* ============================================ GPIO PADREGJ PAD39RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39RSEL */ + GPIO_PADREGJ_PAD39RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGJ_PAD39RSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD39FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD39FNCSEL */ + GPIO_PADREGJ_PAD39FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX Signal */ + GPIO_PADREGJ_PAD39FNCSEL_UART1TX = 1, /*!< UART1TX : Configure as the UART1 TX signal */ + GPIO_PADREGJ_PAD39FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGJ_PAD39FNCSEL_GPIO39 = 3, /*!< GPIO39 : Configure as GPIO39 */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCL = 4, /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCK = 5, /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCKLB = 6, /*!< M4SCKLB : Configure as the IOMSTR4 SPI SCK loopback signal from + IOSLAVE */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCLLB = 7, /*!< M4SCLLB : Configure as the IOMSTR4 I2C SCL loopback signal from + IOSLAVE */ +} GPIO_PADREGJ_PAD39FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD39STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39STRNG */ + GPIO_PADREGJ_PAD39STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD39STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD39STRNG_Enum; + +/* =========================================== GPIO PADREGJ PAD39INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39INPEN */ + GPIO_PADREGJ_PAD39INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD39INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD39INPEN_Enum; + +/* ============================================ GPIO PADREGJ PAD39PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39PULL */ + GPIO_PADREGJ_PAD39PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD39PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD39PULL_Enum; + +/* =========================================== GPIO PADREGJ PAD38FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD38FNCSEL */ + GPIO_PADREGJ_PAD38FNCSEL_TRIG3 = 0, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */ + GPIO_PADREGJ_PAD38FNCSEL_M1nCE3 = 1, /*!< M1nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR1 */ + GPIO_PADREGJ_PAD38FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS signal */ + GPIO_PADREGJ_PAD38FNCSEL_GPIO38 = 3, /*!< GPIO38 : Configure as GPIO38 */ + GPIO_PADREGJ_PAD38FNCSEL_M3WIR3 = 4, /*!< M3WIR3 : Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGJ_PAD38FNCSEL_M3MOSI = 5, /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal */ + GPIO_PADREGJ_PAD38FNCSEL_M4nCE7 = 6, /*!< M4nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR4 */ + GPIO_PADREGJ_PAD38FNCSEL_SLWIR3LB = 7, /*!< SLWIR3LB : Configure as the IOMSTR3 SPI 3-wire MOSI/MISO loopback + signal from IOSLAVE */ +} GPIO_PADREGJ_PAD38FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD38STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38STRNG */ + GPIO_PADREGJ_PAD38STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD38STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD38STRNG_Enum; + +/* =========================================== GPIO PADREGJ PAD38INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38INPEN */ + GPIO_PADREGJ_PAD38INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD38INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD38INPEN_Enum; + +/* ============================================ GPIO PADREGJ PAD38PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38PULL */ + GPIO_PADREGJ_PAD38PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD38PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD38PULL_Enum; + +/* =========================================== GPIO PADREGJ PAD37FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD37FNCSEL */ + GPIO_PADREGJ_PAD37FNCSEL_TRIG2 = 0, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */ + GPIO_PADREGJ_PAD37FNCSEL_M1nCE2 = 1, /*!< M1nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR1 */ + GPIO_PADREGJ_PAD37FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS signal */ + GPIO_PADREGJ_PAD37FNCSEL_GPIO37 = 3, /*!< GPIO37 : Configure as GPIO37 */ + GPIO_PADREGJ_PAD37FNCSEL_M3nCE4 = 4, /*!< M3nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR3 */ + GPIO_PADREGJ_PAD37FNCSEL_M4nCE1 = 5, /*!< M4nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR4 */ + GPIO_PADREGJ_PAD37FNCSEL_PDM_CLK = 6, /*!< PDM_CLK : Configure as the PDM CLK output signal */ + GPIO_PADREGJ_PAD37FNCSEL_TCTA1 = 7, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ +} GPIO_PADREGJ_PAD37FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD37STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD37STRNG */ + GPIO_PADREGJ_PAD37STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD37STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD37STRNG_Enum; + +/* ============================================ GPIO PADREGJ PAD37INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD37INPEN */ + GPIO_PADREGJ_PAD37INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD37INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD37INPEN_Enum; + +/* ============================================= GPIO PADREGJ PAD37PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD37PULL */ + GPIO_PADREGJ_PAD37PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD37PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD37PULL_Enum; + +/* ============================================ GPIO PADREGJ PAD36FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD36FNCSEL */ + GPIO_PADREGJ_PAD36FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGJ_PAD36FNCSEL_M1nCE1 = 1, /*!< M1nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR1 */ + GPIO_PADREGJ_PAD36FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX signal */ + GPIO_PADREGJ_PAD36FNCSEL_GPIO36 = 3, /*!< GPIO36 : Configure as GPIO36 */ + GPIO_PADREGJ_PAD36FNCSEL_32khz_XT = 4, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGJ_PAD36FNCSEL_M2nCE0 = 5, /*!< M2nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR2 */ + GPIO_PADREGJ_PAD36FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS signal */ + GPIO_PADREGJ_PAD36FNCSEL_M3nCE3 = 7, /*!< M3nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR3 */ +} GPIO_PADREGJ_PAD36FNCSEL_Enum; + +/* ============================================ GPIO PADREGJ PAD36STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36STRNG */ + GPIO_PADREGJ_PAD36STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD36STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD36STRNG_Enum; + +/* ============================================ GPIO PADREGJ PAD36INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36INPEN */ + GPIO_PADREGJ_PAD36INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD36INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD36INPEN_Enum; + +/* ============================================= GPIO PADREGJ PAD36PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36PULL */ + GPIO_PADREGJ_PAD36PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD36PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD36PULL_Enum; + +/* ======================================================== PADREGK ======================================================== */ +/* ============================================ GPIO PADREGK PAD43RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43RSEL */ + GPIO_PADREGK_PAD43RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD43RSEL_Enum; + +/* =========================================== GPIO PADREGK PAD43FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD43FNCSEL */ + GPIO_PADREGK_PAD43FNCSEL_M2nCE4 = 0, /*!< M2nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR2 */ + GPIO_PADREGK_PAD43FNCSEL_M0nCE1 = 1, /*!< M0nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR0 */ + GPIO_PADREGK_PAD43FNCSEL_TCTB0 = 2, /*!< TCTB0 : Configure as the input/output signal from CTIMER B0 */ + GPIO_PADREGK_PAD43FNCSEL_GPIO43 = 3, /*!< GPIO43 : Configure as GPIO43 */ + GPIO_PADREGK_PAD43FNCSEL_M3SDA = 4, /*!< M3SDA : Configure as the IOMSTR3 I2C SDA signal */ + GPIO_PADREGK_PAD43FNCSEL_M3MISO = 5, /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal */ + GPIO_PADREGK_PAD43FNCSEL_SLMISOLB = 6, /*!< SLMISOLB : Configure as the IOMSTR3 SPI MISO loopback signal + from IOSLAVE */ + GPIO_PADREGK_PAD43FNCSEL_SLSDALB = 7, /*!< SLSDALB : Configure as the IOMSTR3 I2C SDA loopback signal from + IOSLAVE */ +} GPIO_PADREGK_PAD43FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD43STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43STRNG */ + GPIO_PADREGK_PAD43STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD43STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD43STRNG_Enum; + +/* =========================================== GPIO PADREGK PAD43INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43INPEN */ + GPIO_PADREGK_PAD43INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD43INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD43INPEN_Enum; + +/* ============================================ GPIO PADREGK PAD43PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43PULL */ + GPIO_PADREGK_PAD43PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD43PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD43PULL_Enum; + +/* ============================================ GPIO PADREGK PAD42RSEL [22..23] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42RSEL */ + GPIO_PADREGK_PAD42RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD42RSEL_Enum; + +/* =========================================== GPIO PADREGK PAD42FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD42FNCSEL */ + GPIO_PADREGK_PAD42FNCSEL_M2nCE2 = 0, /*!< M2nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR2 */ + GPIO_PADREGK_PAD42FNCSEL_M0nCE0 = 1, /*!< M0nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR0 */ + GPIO_PADREGK_PAD42FNCSEL_TCTA0 = 2, /*!< TCTA0 : Configure as the input/output signal from CTIMER A0 */ + GPIO_PADREGK_PAD42FNCSEL_GPIO42 = 3, /*!< GPIO42 : Configure as GPIO42 */ + GPIO_PADREGK_PAD42FNCSEL_M3SCL = 4, /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal */ + GPIO_PADREGK_PAD42FNCSEL_M3SCK = 5, /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output */ + GPIO_PADREGK_PAD42FNCSEL_M3SCKLB = 6, /*!< M3SCKLB : Configure as the IOMSTR3 SPI clock loopback to the + IOSLAVE device */ + GPIO_PADREGK_PAD42FNCSEL_M3SCLLB = 7, /*!< M3SCLLB : Configure as the IOMSTR3 I2C clock loopback to the + IOSLAVE device */ +} GPIO_PADREGK_PAD42FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD42STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42STRNG */ + GPIO_PADREGK_PAD42STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD42STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD42STRNG_Enum; + +/* =========================================== GPIO PADREGK PAD42INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42INPEN */ + GPIO_PADREGK_PAD42INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD42INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD42INPEN_Enum; + +/* ============================================ GPIO PADREGK PAD42PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42PULL */ + GPIO_PADREGK_PAD42PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD42PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD42PULL_Enum; + +/* =========================================== GPIO PADREGK PAD41PWRUP [15..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD41PWRUP */ + GPIO_PADREGK_PAD41PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGK_PAD41PWRUP_EN = 1, /*!< EN : Power switch enabled (VDD switch) */ +} GPIO_PADREGK_PAD41PWRUP_Enum; + +/* =========================================== GPIO PADREGK PAD41FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD41FNCSEL */ + GPIO_PADREGK_PAD41FNCSEL_M2nCE1 = 0, /*!< M2nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR2 */ + GPIO_PADREGK_PAD41FNCSEL_CLKOUT = 1, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGK_PAD41FNCSEL_SWO = 2, /*!< SWO : Configure as the serial wire debug SWO signal */ + GPIO_PADREGK_PAD41FNCSEL_GPIO41 = 3, /*!< GPIO41 : Configure as GPIO41 */ + GPIO_PADREGK_PAD41FNCSEL_M3nCE5 = 4, /*!< M3nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR3 */ + GPIO_PADREGK_PAD41FNCSEL_M5nCE7 = 5, /*!< M5nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR5 */ + GPIO_PADREGK_PAD41FNCSEL_M4nCE2 = 6, /*!< M4nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR4 */ + GPIO_PADREGK_PAD41FNCSEL_UA0RTS = 7, /*!< UA0RTS : Configure as the UART0 RTS output */ +} GPIO_PADREGK_PAD41FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD41STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD41STRNG */ + GPIO_PADREGK_PAD41STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD41STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD41STRNG_Enum; + +/* ============================================ GPIO PADREGK PAD41INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD41INPEN */ + GPIO_PADREGK_PAD41INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD41INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD41INPEN_Enum; + +/* ============================================= GPIO PADREGK PAD41PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD41PULL */ + GPIO_PADREGK_PAD41PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD41PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD41PULL_Enum; + +/* ============================================= GPIO PADREGK PAD40RSEL [6..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40RSEL */ + GPIO_PADREGK_PAD40RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD40RSEL_Enum; + +/* ============================================ GPIO PADREGK PAD40FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD40FNCSEL */ + GPIO_PADREGK_PAD40FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGK_PAD40FNCSEL_UART1RX = 1, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGK_PAD40FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGK_PAD40FNCSEL_GPIO40 = 3, /*!< GPIO40 : Configure as GPIO40 */ + GPIO_PADREGK_PAD40FNCSEL_M4SDA = 4, /*!< M4SDA : Configure as the IOMSTR4 I2C serial data I/O signal */ + GPIO_PADREGK_PAD40FNCSEL_M4MISO = 5, /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal */ + GPIO_PADREGK_PAD40FNCSEL_SLMISOLB = 6, /*!< SLMISOLB : Configure as the IOMSTR4 SPI MISO loopback signal + from IOSLAVE */ + GPIO_PADREGK_PAD40FNCSEL_SLSDALB = 7, /*!< SLSDALB : Configure as the IOMSTR4 I2C SDA loopback signal from + IOSLAVE */ +} GPIO_PADREGK_PAD40FNCSEL_Enum; + +/* ============================================ GPIO PADREGK PAD40STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40STRNG */ + GPIO_PADREGK_PAD40STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD40STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD40STRNG_Enum; + +/* ============================================ GPIO PADREGK PAD40INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40INPEN */ + GPIO_PADREGK_PAD40INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD40INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD40INPEN_Enum; + +/* ============================================= GPIO PADREGK PAD40PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40PULL */ + GPIO_PADREGK_PAD40PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD40PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD40PULL_Enum; + +/* ======================================================== PADREGL ======================================================== */ +/* =========================================== GPIO PADREGL PAD47FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD47FNCSEL */ + GPIO_PADREGL_PAD47FNCSEL_M2nCE5 = 0, /*!< M2nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR2 */ + GPIO_PADREGL_PAD47FNCSEL_M0nCE5 = 1, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */ + GPIO_PADREGL_PAD47FNCSEL_TCTB2 = 2, /*!< TCTB2 : Configure as the input/output signal from CTIMER B2 */ + GPIO_PADREGL_PAD47FNCSEL_GPIO47 = 3, /*!< GPIO47 : Configure as GPIO47 */ + GPIO_PADREGL_PAD47FNCSEL_M5WIR3 = 4, /*!< M5WIR3 : Configure as the IOMSTR5 SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGL_PAD47FNCSEL_M5MOSI = 5, /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal */ + GPIO_PADREGL_PAD47FNCSEL_M4nCE5 = 6, /*!< M4nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR4 */ + GPIO_PADREGL_PAD47FNCSEL_SLWIR3LB = 7, /*!< SLWIR3LB : Configure as the IOMSTR5 SPI 3-wire MOSI/MISO loopback + signal from IOSLAVE */ +} GPIO_PADREGL_PAD47FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD47STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47STRNG */ + GPIO_PADREGL_PAD47STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD47STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD47STRNG_Enum; + +/* =========================================== GPIO PADREGL PAD47INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47INPEN */ + GPIO_PADREGL_PAD47INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD47INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD47INPEN_Enum; + +/* ============================================ GPIO PADREGL PAD47PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47PULL */ + GPIO_PADREGL_PAD47PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD47PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD47PULL_Enum; + +/* =========================================== GPIO PADREGL PAD46FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD46FNCSEL */ + GPIO_PADREGL_PAD46FNCSEL_32khz_XT = 0, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGL_PAD46FNCSEL_M0nCE4 = 1, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */ + GPIO_PADREGL_PAD46FNCSEL_TCTA2 = 2, /*!< TCTA2 : Configure as the input/output signal from CTIMER A2 */ + GPIO_PADREGL_PAD46FNCSEL_GPIO46 = 3, /*!< GPIO46 : Configure as GPIO46 */ + GPIO_PADREGL_PAD46FNCSEL_TCTA1 = 4, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGL_PAD46FNCSEL_M5nCE4 = 5, /*!< M5nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR5 */ + GPIO_PADREGL_PAD46FNCSEL_M4nCE4 = 6, /*!< M4nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR4 */ + GPIO_PADREGL_PAD46FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ +} GPIO_PADREGL_PAD46FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD46STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46STRNG */ + GPIO_PADREGL_PAD46STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD46STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD46STRNG_Enum; + +/* =========================================== GPIO PADREGL PAD46INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46INPEN */ + GPIO_PADREGL_PAD46INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD46INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD46INPEN_Enum; + +/* ============================================ GPIO PADREGL PAD46PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46PULL */ + GPIO_PADREGL_PAD46PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD46PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD46PULL_Enum; + +/* =========================================== GPIO PADREGL PAD45FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD45FNCSEL */ + GPIO_PADREGL_PAD45FNCSEL_UA1CTS = 0, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGL_PAD45FNCSEL_M0nCE3 = 1, /*!< M0nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR0 */ + GPIO_PADREGL_PAD45FNCSEL_TCTB1 = 2, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */ + GPIO_PADREGL_PAD45FNCSEL_GPIO45 = 3, /*!< GPIO45 : Configure as GPIO45 */ + GPIO_PADREGL_PAD45FNCSEL_M4nCE3 = 4, /*!< M4nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR4 */ + GPIO_PADREGL_PAD45FNCSEL_M3nCE6 = 5, /*!< M3nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR3 */ + GPIO_PADREGL_PAD45FNCSEL_M5nCE5 = 6, /*!< M5nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR5 */ + GPIO_PADREGL_PAD45FNCSEL_TCTA1 = 7, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ +} GPIO_PADREGL_PAD45FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD45STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD45STRNG */ + GPIO_PADREGL_PAD45STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD45STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD45STRNG_Enum; + +/* ============================================ GPIO PADREGL PAD45INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD45INPEN */ + GPIO_PADREGL_PAD45INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD45INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD45INPEN_Enum; + +/* ============================================= GPIO PADREGL PAD45PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD45PULL */ + GPIO_PADREGL_PAD45PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD45PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD45PULL_Enum; + +/* ============================================ GPIO PADREGL PAD44FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD44FNCSEL */ + GPIO_PADREGL_PAD44FNCSEL_UA1RTS = 0, /*!< UA1RTS : Configure as the UART1 RTS output signal */ + GPIO_PADREGL_PAD44FNCSEL_M0nCE2 = 1, /*!< M0nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR0 */ + GPIO_PADREGL_PAD44FNCSEL_TCTA1 = 2, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */ + GPIO_PADREGL_PAD44FNCSEL_GPIO44 = 3, /*!< GPIO44 : Configure as GPIO44 */ + GPIO_PADREGL_PAD44FNCSEL_M4WIR3 = 4, /*!< M4WIR3 : Configure as the IOMSTR4 SPI 3-wire MOSI/MISO signal */ + GPIO_PADREGL_PAD44FNCSEL_M4MOSI = 5, /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal */ + GPIO_PADREGL_PAD44FNCSEL_M5nCE6 = 6, /*!< M5nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR5 */ + GPIO_PADREGL_PAD44FNCSEL_SLWIR3LB = 7, /*!< SLWIR3LB : Configure as the IOMSTR4 SPI 3-wire MOSI/MISO loopback + signal from IOSLAVE */ +} GPIO_PADREGL_PAD44FNCSEL_Enum; + +/* ============================================ GPIO PADREGL PAD44STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44STRNG */ + GPIO_PADREGL_PAD44STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD44STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD44STRNG_Enum; + +/* ============================================ GPIO PADREGL PAD44INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44INPEN */ + GPIO_PADREGL_PAD44INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD44INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD44INPEN_Enum; + +/* ============================================= GPIO PADREGL PAD44PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44PULL */ + GPIO_PADREGL_PAD44PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD44PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD44PULL_Enum; + +/* ======================================================== PADREGM ======================================================== */ +/* ============================================ GPIO PADREGM PAD49RSEL [14..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD49RSEL */ + GPIO_PADREGM_PAD49RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGM_PAD49RSEL_Enum; + +/* =========================================== GPIO PADREGM PAD49FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGM_PAD49FNCSEL */ + GPIO_PADREGM_PAD49FNCSEL_M2nCE7 = 0, /*!< M2nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR2 */ + GPIO_PADREGM_PAD49FNCSEL_M0nCE7 = 1, /*!< M0nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR0 */ + GPIO_PADREGM_PAD49FNCSEL_TCTB3 = 2, /*!< TCTB3 : Configure as the input/output signal from CTIMER B3 */ + GPIO_PADREGM_PAD49FNCSEL_GPIO49 = 3, /*!< GPIO49 : Configure as GPIO49 */ + GPIO_PADREGM_PAD49FNCSEL_M5SDA = 4, /*!< M5SDA : Configure as the IOMSTR5 I2C serial data I/O signal */ + GPIO_PADREGM_PAD49FNCSEL_M5MISO = 5, /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal */ + GPIO_PADREGM_PAD49FNCSEL_SLMISOLB = 6, /*!< SLMISOLB : Configure as the IOMSTR5 SPI MISO loopback signal + from IOSLAVE */ + GPIO_PADREGM_PAD49FNCSEL_SLSDALB = 7, /*!< SLSDALB : Configure as the IOMSTR5 I2C SDA loopback signal from + IOSLAVE */ +} GPIO_PADREGM_PAD49FNCSEL_Enum; + +/* =========================================== GPIO PADREGM PAD49STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD49STRNG */ + GPIO_PADREGM_PAD49STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGM_PAD49STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGM_PAD49STRNG_Enum; + +/* ============================================ GPIO PADREGM PAD49INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD49INPEN */ + GPIO_PADREGM_PAD49INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGM_PAD49INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGM_PAD49INPEN_Enum; + +/* ============================================= GPIO PADREGM PAD49PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD49PULL */ + GPIO_PADREGM_PAD49PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGM_PAD49PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGM_PAD49PULL_Enum; + +/* ============================================= GPIO PADREGM PAD48RSEL [6..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48RSEL */ + GPIO_PADREGM_PAD48RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGM_PAD48RSEL_Enum; + +/* ============================================ GPIO PADREGM PAD48FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD48FNCSEL */ + GPIO_PADREGM_PAD48FNCSEL_M2nCE6 = 0, /*!< M2nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR2 */ + GPIO_PADREGM_PAD48FNCSEL_M0nCE6 = 1, /*!< M0nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR0 */ + GPIO_PADREGM_PAD48FNCSEL_TCTA3 = 2, /*!< TCTA3 : Configure as the input/output signal from CTIMER A3 */ + GPIO_PADREGM_PAD48FNCSEL_GPIO48 = 3, /*!< GPIO48 : Configure as GPIO48 */ + GPIO_PADREGM_PAD48FNCSEL_M5SCL = 4, /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal */ + GPIO_PADREGM_PAD48FNCSEL_M5SCK = 5, /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output */ + GPIO_PADREGM_PAD48FNCSEL_M5SCKLB = 6, /*!< M5SCKLB : Configure as the IOMSTR5 SPI clock loopback to the + IOSLAVE device */ + GPIO_PADREGM_PAD48FNCSEL_M5SCLLB = 7, /*!< M5SCLLB : Configure as the IOMSTR5 I2C clock loopback to the + IOSLAVE device */ +} GPIO_PADREGM_PAD48FNCSEL_Enum; + +/* ============================================ GPIO PADREGM PAD48STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48STRNG */ + GPIO_PADREGM_PAD48STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGM_PAD48STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGM_PAD48STRNG_Enum; + +/* ============================================ GPIO PADREGM PAD48INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48INPEN */ + GPIO_PADREGM_PAD48INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGM_PAD48INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGM_PAD48INPEN_Enum; + +/* ============================================= GPIO PADREGM PAD48PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48PULL */ + GPIO_PADREGM_PAD48PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGM_PAD48PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGM_PAD48PULL_Enum; + +/* ========================================================= CFGA ========================================================== */ +/* ============================================= GPIO CFGA GPIO7INTD [31..31] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO7INTD */ + GPIO_CFGA_GPIO7INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO7INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO7INTD_Enum; + +/* ============================================ GPIO CFGA GPIO7OUTCFG [29..30] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO7OUTCFG */ + GPIO_CFGA_GPIO7OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO7OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO7OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO7OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO7OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO7INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO7INCFG */ + GPIO_CFGA_GPIO7INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO7INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO7INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO6INTD [27..27] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO6INTD */ + GPIO_CFGA_GPIO6INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO6INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO6INTD_Enum; + +/* ============================================ GPIO CFGA GPIO6OUTCFG [25..26] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO6OUTCFG */ + GPIO_CFGA_GPIO6OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO6OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO6OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO6OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO6OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO6INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO6INCFG */ + GPIO_CFGA_GPIO6INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO6INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO6INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO5INTD [23..23] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO5INTD */ + GPIO_CFGA_GPIO5INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO5INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO5INTD_Enum; + +/* ============================================ GPIO CFGA GPIO5OUTCFG [21..22] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO5OUTCFG */ + GPIO_CFGA_GPIO5OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO5OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO5OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO5OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO5OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO5INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO5INCFG */ + GPIO_CFGA_GPIO5INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO5INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO5INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO4INTD [19..19] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO4INTD */ + GPIO_CFGA_GPIO4INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO4INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO4INTD_Enum; + +/* ============================================ GPIO CFGA GPIO4OUTCFG [17..18] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO4OUTCFG */ + GPIO_CFGA_GPIO4OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO4OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO4OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO4OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO4OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO4INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO4INCFG */ + GPIO_CFGA_GPIO4INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO4INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO4INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO3INTD [15..15] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO3INTD */ + GPIO_CFGA_GPIO3INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO3INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO3INTD_Enum; + +/* ============================================ GPIO CFGA GPIO3OUTCFG [13..14] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO3OUTCFG */ + GPIO_CFGA_GPIO3OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO3OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO3OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO3OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO3OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO3INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO3INCFG */ + GPIO_CFGA_GPIO3INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO3INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO3INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO2INTD [11..11] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO2INTD */ + GPIO_CFGA_GPIO2INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO2INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO2INTD_Enum; + +/* ============================================= GPIO CFGA GPIO2OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO2OUTCFG */ + GPIO_CFGA_GPIO2OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO2OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO2OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO2OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO2OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO2INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO2INCFG */ + GPIO_CFGA_GPIO2INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO2INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO2INCFG_Enum; + +/* ============================================== GPIO CFGA GPIO1INTD [7..7] =============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1INTD */ + GPIO_CFGA_GPIO1INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO1INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO1INTD_Enum; + +/* ============================================= GPIO CFGA GPIO1OUTCFG [5..6] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1OUTCFG */ + GPIO_CFGA_GPIO1OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO1OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO1OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO1OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO1OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO1INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1INCFG */ + GPIO_CFGA_GPIO1INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO1INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO1INCFG_Enum; + +/* ============================================== GPIO CFGA GPIO0INTD [3..3] =============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0INTD */ + GPIO_CFGA_GPIO0INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGA_GPIO0INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGA_GPIO0INTD_Enum; + +/* ============================================= GPIO CFGA GPIO0OUTCFG [1..2] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0OUTCFG */ + GPIO_CFGA_GPIO0OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGA_GPIO0OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGA_GPIO0OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGA_GPIO0OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGA_GPIO0OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO0INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0INCFG */ + GPIO_CFGA_GPIO0INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO0INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGA_GPIO0INCFG_Enum; + +/* ========================================================= CFGB ========================================================== */ +/* ============================================= GPIO CFGB GPIO15INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO15INTD */ + GPIO_CFGB_GPIO15INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO15INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO15INTD_Enum; + +/* ============================================ GPIO CFGB GPIO15OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO15OUTCFG */ + GPIO_CFGB_GPIO15OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO15OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO15OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO15OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO15OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO15INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO15INCFG */ + GPIO_CFGB_GPIO15INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO15INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO15INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO14INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO14INTD */ + GPIO_CFGB_GPIO14INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO14INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO14INTD_Enum; + +/* ============================================ GPIO CFGB GPIO14OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO14OUTCFG */ + GPIO_CFGB_GPIO14OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO14OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO14OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO14OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO14OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO14INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO14INCFG */ + GPIO_CFGB_GPIO14INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO14INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO14INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO13INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO13INTD */ + GPIO_CFGB_GPIO13INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO13INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO13INTD_Enum; + +/* ============================================ GPIO CFGB GPIO13OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO13OUTCFG */ + GPIO_CFGB_GPIO13OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO13OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO13OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO13OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO13OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO13INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO13INCFG */ + GPIO_CFGB_GPIO13INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO13INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO13INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO12INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO12INTD */ + GPIO_CFGB_GPIO12INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO12INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO12INTD_Enum; + +/* ============================================ GPIO CFGB GPIO12OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO12OUTCFG */ + GPIO_CFGB_GPIO12OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO12OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO12OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO12OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO12OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO12INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO12INCFG */ + GPIO_CFGB_GPIO12INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO12INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO12INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO11INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO11INTD */ + GPIO_CFGB_GPIO11INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO11INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO11INTD_Enum; + +/* ============================================ GPIO CFGB GPIO11OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO11OUTCFG */ + GPIO_CFGB_GPIO11OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO11OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO11OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO11OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO11OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO11INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO11INCFG */ + GPIO_CFGB_GPIO11INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO11INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO11INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO10INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO10INTD */ + GPIO_CFGB_GPIO10INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO10INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO10INTD_Enum; + +/* ============================================ GPIO CFGB GPIO10OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO10OUTCFG */ + GPIO_CFGB_GPIO10OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO10OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO10OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO10OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO10OUTCFG_Enum; + +/* ============================================= GPIO CFGB GPIO10INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO10INCFG */ + GPIO_CFGB_GPIO10INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO10INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO10INCFG_Enum; + +/* ============================================== GPIO CFGB GPIO9INTD [7..7] =============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9INTD */ + GPIO_CFGB_GPIO9INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO9INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO9INTD_Enum; + +/* ============================================= GPIO CFGB GPIO9OUTCFG [5..6] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9OUTCFG */ + GPIO_CFGB_GPIO9OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO9OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO9OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO9OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO9OUTCFG_Enum; + +/* ============================================== GPIO CFGB GPIO9INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9INCFG */ + GPIO_CFGB_GPIO9INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO9INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO9INCFG_Enum; + +/* ============================================== GPIO CFGB GPIO8INTD [3..3] =============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8INTD */ + GPIO_CFGB_GPIO8INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGB_GPIO8INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGB_GPIO8INTD_Enum; + +/* ============================================= GPIO CFGB GPIO8OUTCFG [1..2] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8OUTCFG */ + GPIO_CFGB_GPIO8OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGB_GPIO8OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGB_GPIO8OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGB_GPIO8OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGB_GPIO8OUTCFG_Enum; + +/* ============================================== GPIO CFGB GPIO8INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8INCFG */ + GPIO_CFGB_GPIO8INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO8INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGB_GPIO8INCFG_Enum; + +/* ========================================================= CFGC ========================================================== */ +/* ============================================= GPIO CFGC GPIO23INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO23INTD */ + GPIO_CFGC_GPIO23INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO23INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO23INTD_Enum; + +/* ============================================ GPIO CFGC GPIO23OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO23OUTCFG */ + GPIO_CFGC_GPIO23OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO23OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO23OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO23OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO23OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO23INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO23INCFG */ + GPIO_CFGC_GPIO23INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO23INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO23INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO22INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO22INTD */ + GPIO_CFGC_GPIO22INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO22INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO22INTD_Enum; + +/* ============================================ GPIO CFGC GPIO22OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO22OUTCFG */ + GPIO_CFGC_GPIO22OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO22OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO22OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO22OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO22OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO22INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO22INCFG */ + GPIO_CFGC_GPIO22INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO22INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO22INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO21INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO21INTD */ + GPIO_CFGC_GPIO21INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO21INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO21INTD_Enum; + +/* ============================================ GPIO CFGC GPIO21OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO21OUTCFG */ + GPIO_CFGC_GPIO21OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO21OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO21OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO21OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO21OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO21INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO21INCFG */ + GPIO_CFGC_GPIO21INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO21INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO21INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO20INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO20INTD */ + GPIO_CFGC_GPIO20INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO20INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO20INTD_Enum; + +/* ============================================ GPIO CFGC GPIO20OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO20OUTCFG */ + GPIO_CFGC_GPIO20OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO20OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO20OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO20OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO20OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO20INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO20INCFG */ + GPIO_CFGC_GPIO20INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO20INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO20INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO19INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO19INTD */ + GPIO_CFGC_GPIO19INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO19INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO19INTD_Enum; + +/* ============================================ GPIO CFGC GPIO19OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO19OUTCFG */ + GPIO_CFGC_GPIO19OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO19OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO19OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO19OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO19OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO19INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO19INCFG */ + GPIO_CFGC_GPIO19INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO19INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO19INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO18INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO18INTD */ + GPIO_CFGC_GPIO18INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO18INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO18INTD_Enum; + +/* ============================================ GPIO CFGC GPIO18OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO18OUTCFG */ + GPIO_CFGC_GPIO18OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO18OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO18OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO18OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO18OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO18INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO18INCFG */ + GPIO_CFGC_GPIO18INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO18INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO18INCFG_Enum; + +/* ============================================== GPIO CFGC GPIO17INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO17INTD */ + GPIO_CFGC_GPIO17INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO17INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO17INTD_Enum; + +/* ============================================= GPIO CFGC GPIO17OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO17OUTCFG */ + GPIO_CFGC_GPIO17OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO17OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO17OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO17OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO17OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO17INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO17INCFG */ + GPIO_CFGC_GPIO17INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO17INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO17INCFG_Enum; + +/* ============================================== GPIO CFGC GPIO16INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO16INTD */ + GPIO_CFGC_GPIO16INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGC_GPIO16INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGC_GPIO16INTD_Enum; + +/* ============================================= GPIO CFGC GPIO16OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO16OUTCFG */ + GPIO_CFGC_GPIO16OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGC_GPIO16OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGC_GPIO16OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGC_GPIO16OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGC_GPIO16OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO16INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO16INCFG */ + GPIO_CFGC_GPIO16INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO16INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGC_GPIO16INCFG_Enum; + +/* ========================================================= CFGD ========================================================== */ +/* ============================================= GPIO CFGD GPIO31INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO31INTD */ + GPIO_CFGD_GPIO31INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO31INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO31INTD_Enum; + +/* ============================================ GPIO CFGD GPIO31OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO31OUTCFG */ + GPIO_CFGD_GPIO31OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO31OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO31OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO31OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO31OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO31INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO31INCFG */ + GPIO_CFGD_GPIO31INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO31INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO31INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO30INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO30INTD */ + GPIO_CFGD_GPIO30INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO30INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO30INTD_Enum; + +/* ============================================ GPIO CFGD GPIO30OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO30OUTCFG */ + GPIO_CFGD_GPIO30OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO30OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO30OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO30OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO30OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO30INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO30INCFG */ + GPIO_CFGD_GPIO30INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO30INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO30INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO29INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO29INTD */ + GPIO_CFGD_GPIO29INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO29INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO29INTD_Enum; + +/* ============================================ GPIO CFGD GPIO29OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO29OUTCFG */ + GPIO_CFGD_GPIO29OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO29OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO29OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO29OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO29OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO29INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO29INCFG */ + GPIO_CFGD_GPIO29INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO29INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO29INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO28INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO28INTD */ + GPIO_CFGD_GPIO28INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO28INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO28INTD_Enum; + +/* ============================================ GPIO CFGD GPIO28OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO28OUTCFG */ + GPIO_CFGD_GPIO28OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO28OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO28OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO28OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO28OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO28INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO28INCFG */ + GPIO_CFGD_GPIO28INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO28INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO28INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO27INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO27INTD */ + GPIO_CFGD_GPIO27INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO27INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO27INTD_Enum; + +/* ============================================ GPIO CFGD GPIO27OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO27OUTCFG */ + GPIO_CFGD_GPIO27OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO27OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO27OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO27OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO27OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO27INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO27INCFG */ + GPIO_CFGD_GPIO27INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO27INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO27INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO26INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO26INTD */ + GPIO_CFGD_GPIO26INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO26INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO26INTD_Enum; + +/* ============================================ GPIO CFGD GPIO26OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO26OUTCFG */ + GPIO_CFGD_GPIO26OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO26OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO26OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO26OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO26OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO26INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO26INCFG */ + GPIO_CFGD_GPIO26INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO26INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO26INCFG_Enum; + +/* ============================================== GPIO CFGD GPIO25INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO25INTD */ + GPIO_CFGD_GPIO25INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO25INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO25INTD_Enum; + +/* ============================================= GPIO CFGD GPIO25OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO25OUTCFG */ + GPIO_CFGD_GPIO25OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO25OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO25OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO25OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO25OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO25INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO25INCFG */ + GPIO_CFGD_GPIO25INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO25INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO25INCFG_Enum; + +/* ============================================== GPIO CFGD GPIO24INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO24INTD */ + GPIO_CFGD_GPIO24INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGD_GPIO24INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGD_GPIO24INTD_Enum; + +/* ============================================= GPIO CFGD GPIO24OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO24OUTCFG */ + GPIO_CFGD_GPIO24OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGD_GPIO24OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGD_GPIO24OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGD_GPIO24OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGD_GPIO24OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO24INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO24INCFG */ + GPIO_CFGD_GPIO24INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO24INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGD_GPIO24INCFG_Enum; + +/* ========================================================= CFGE ========================================================== */ +/* ============================================= GPIO CFGE GPIO39INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO39INTD */ + GPIO_CFGE_GPIO39INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO39INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO39INTD_Enum; + +/* ============================================ GPIO CFGE GPIO39OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO39OUTCFG */ + GPIO_CFGE_GPIO39OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO39OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO39OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO39OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO39OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO39INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO39INCFG */ + GPIO_CFGE_GPIO39INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO39INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO39INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO38INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO38INTD */ + GPIO_CFGE_GPIO38INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO38INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO38INTD_Enum; + +/* ============================================ GPIO CFGE GPIO38OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO38OUTCFG */ + GPIO_CFGE_GPIO38OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO38OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO38OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO38OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO38OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO38INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO38INCFG */ + GPIO_CFGE_GPIO38INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO38INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO38INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO37INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO37INTD */ + GPIO_CFGE_GPIO37INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO37INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO37INTD_Enum; + +/* ============================================ GPIO CFGE GPIO37OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO37OUTCFG */ + GPIO_CFGE_GPIO37OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO37OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO37OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO37OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO37OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO37INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO37INCFG */ + GPIO_CFGE_GPIO37INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO37INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO37INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO36INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO36INTD */ + GPIO_CFGE_GPIO36INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO36INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO36INTD_Enum; + +/* ============================================ GPIO CFGE GPIO36OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO36OUTCFG */ + GPIO_CFGE_GPIO36OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO36OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO36OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO36OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO36OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO36INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO36INCFG */ + GPIO_CFGE_GPIO36INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO36INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO36INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO35INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO35INTD */ + GPIO_CFGE_GPIO35INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO35INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO35INTD_Enum; + +/* ============================================ GPIO CFGE GPIO35OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO35OUTCFG */ + GPIO_CFGE_GPIO35OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO35OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO35OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO35OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO35OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO35INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO35INCFG */ + GPIO_CFGE_GPIO35INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO35INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO35INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO34INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO34INTD */ + GPIO_CFGE_GPIO34INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO34INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO34INTD_Enum; + +/* ============================================ GPIO CFGE GPIO34OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO34OUTCFG */ + GPIO_CFGE_GPIO34OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO34OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO34OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO34OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO34OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO34INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO34INCFG */ + GPIO_CFGE_GPIO34INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO34INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO34INCFG_Enum; + +/* ============================================== GPIO CFGE GPIO33INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO33INTD */ + GPIO_CFGE_GPIO33INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO33INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO33INTD_Enum; + +/* ============================================= GPIO CFGE GPIO33OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO33OUTCFG */ + GPIO_CFGE_GPIO33OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO33OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO33OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO33OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO33OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO33INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO33INCFG */ + GPIO_CFGE_GPIO33INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO33INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO33INCFG_Enum; + +/* ============================================== GPIO CFGE GPIO32INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO32INTD */ + GPIO_CFGE_GPIO32INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGE_GPIO32INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGE_GPIO32INTD_Enum; + +/* ============================================= GPIO CFGE GPIO32OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO32OUTCFG */ + GPIO_CFGE_GPIO32OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGE_GPIO32OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGE_GPIO32OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGE_GPIO32OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGE_GPIO32OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO32INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO32INCFG */ + GPIO_CFGE_GPIO32INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO32INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGE_GPIO32INCFG_Enum; + +/* ========================================================= CFGF ========================================================== */ +/* ============================================= GPIO CFGF GPIO47INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO47INTD */ + GPIO_CFGF_GPIO47INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO47INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO47INTD_Enum; + +/* ============================================ GPIO CFGF GPIO47OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO47OUTCFG */ + GPIO_CFGF_GPIO47OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO47OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO47OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO47OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO47OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO47INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO47INCFG */ + GPIO_CFGF_GPIO47INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO47INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO47INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO46INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO46INTD */ + GPIO_CFGF_GPIO46INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO46INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO46INTD_Enum; + +/* ============================================ GPIO CFGF GPIO46OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO46OUTCFG */ + GPIO_CFGF_GPIO46OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO46OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO46OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO46OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO46OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO46INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO46INCFG */ + GPIO_CFGF_GPIO46INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO46INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO46INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO45INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO45INTD */ + GPIO_CFGF_GPIO45INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO45INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO45INTD_Enum; + +/* ============================================ GPIO CFGF GPIO45OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO45OUTCFG */ + GPIO_CFGF_GPIO45OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO45OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO45OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO45OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO45OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO45INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO45INCFG */ + GPIO_CFGF_GPIO45INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO45INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO45INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO44INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO44INTD */ + GPIO_CFGF_GPIO44INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO44INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO44INTD_Enum; + +/* ============================================ GPIO CFGF GPIO44OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO44OUTCFG */ + GPIO_CFGF_GPIO44OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO44OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO44OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO44OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO44OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO44INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO44INCFG */ + GPIO_CFGF_GPIO44INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO44INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO44INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO43INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO43INTD */ + GPIO_CFGF_GPIO43INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO43INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO43INTD_Enum; + +/* ============================================ GPIO CFGF GPIO43OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO43OUTCFG */ + GPIO_CFGF_GPIO43OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO43OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO43OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO43OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO43OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO43INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO43INCFG */ + GPIO_CFGF_GPIO43INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO43INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO43INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO42INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO42INTD */ + GPIO_CFGF_GPIO42INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO42INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO42INTD_Enum; + +/* ============================================ GPIO CFGF GPIO42OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO42OUTCFG */ + GPIO_CFGF_GPIO42OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO42OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO42OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO42OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO42OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO42INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO42INCFG */ + GPIO_CFGF_GPIO42INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO42INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO42INCFG_Enum; + +/* ============================================== GPIO CFGF GPIO41INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO41INTD */ + GPIO_CFGF_GPIO41INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO41INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO41INTD_Enum; + +/* ============================================= GPIO CFGF GPIO41OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO41OUTCFG */ + GPIO_CFGF_GPIO41OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO41OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO41OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO41OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO41OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO41INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO41INCFG */ + GPIO_CFGF_GPIO41INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO41INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO41INCFG_Enum; + +/* ============================================== GPIO CFGF GPIO40INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO40INTD */ + GPIO_CFGF_GPIO40INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGF_GPIO40INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGF_GPIO40INTD_Enum; + +/* ============================================= GPIO CFGF GPIO40OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO40OUTCFG */ + GPIO_CFGF_GPIO40OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGF_GPIO40OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGF_GPIO40OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGF_GPIO40OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGF_GPIO40OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO40INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO40INCFG */ + GPIO_CFGF_GPIO40INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO40INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGF_GPIO40INCFG_Enum; + +/* ========================================================= CFGG ========================================================== */ +/* ============================================== GPIO CFGG GPIO49INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO49INTD */ + GPIO_CFGG_GPIO49INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGG_GPIO49INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGG_GPIO49INTD_Enum; + +/* ============================================= GPIO CFGG GPIO49OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGG_GPIO49OUTCFG */ + GPIO_CFGG_GPIO49OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGG_GPIO49OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGG_GPIO49OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGG_GPIO49OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGG_GPIO49OUTCFG_Enum; + +/* ============================================= GPIO CFGG GPIO49INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO49INCFG */ + GPIO_CFGG_GPIO49INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGG_GPIO49INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGG_GPIO49INCFG_Enum; + +/* ============================================== GPIO CFGG GPIO48INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO48INTD */ + GPIO_CFGG_GPIO48INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */ + GPIO_CFGG_GPIO48INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */ +} GPIO_CFGG_GPIO48INTD_Enum; + +/* ============================================= GPIO CFGG GPIO48OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGG_GPIO48OUTCFG */ + GPIO_CFGG_GPIO48OUTCFG_DIS = 0, /*!< DIS : Output disabled */ + GPIO_CFGG_GPIO48OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */ + GPIO_CFGG_GPIO48OUTCFG_OD = 2, /*!< OD : Output is open drain */ + GPIO_CFGG_GPIO48OUTCFG_TS = 3, /*!< TS : Output is tri-state */ +} GPIO_CFGG_GPIO48OUTCFG_Enum; + +/* ============================================= GPIO CFGG GPIO48INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO48INCFG */ + GPIO_CFGG_GPIO48INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGG_GPIO48INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */ +} GPIO_CFGG_GPIO48INCFG_Enum; + +/* ======================================================== PADKEY ========================================================= */ +/* ============================================== GPIO PADKEY PADKEY [0..31] =============================================== */ +typedef enum { /*!< GPIO_PADKEY_PADKEY */ + GPIO_PADKEY_PADKEY_Key = 115, /*!< Key : Key */ +} GPIO_PADKEY_PADKEY_Enum; + +/* ========================================================== RDA ========================================================== */ +/* ========================================================== RDB ========================================================== */ +/* ========================================================== WTA ========================================================== */ +/* ========================================================== WTB ========================================================== */ +/* ========================================================= WTSA ========================================================== */ +/* ========================================================= WTSB ========================================================== */ +/* ========================================================= WTCA ========================================================== */ +/* ========================================================= WTCB ========================================================== */ +/* ========================================================== ENA ========================================================== */ +/* ========================================================== ENB ========================================================== */ +/* ========================================================= ENSA ========================================================== */ +/* ========================================================= ENSB ========================================================== */ +/* ========================================================= ENCA ========================================================== */ +/* ========================================================= ENCB ========================================================== */ +/* ======================================================== STMRCAP ======================================================== */ +/* ============================================= GPIO STMRCAP STPOL3 [30..30] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL3 */ + GPIO_STMRCAP_STPOL3_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL3_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL3_Enum; + +/* ============================================= GPIO STMRCAP STPOL2 [22..22] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL2 */ + GPIO_STMRCAP_STPOL2_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL2_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL2_Enum; + +/* ============================================= GPIO STMRCAP STPOL1 [14..14] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL1 */ + GPIO_STMRCAP_STPOL1_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL1_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL1_Enum; + +/* ============================================== GPIO STMRCAP STPOL0 [6..6] =============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL0 */ + GPIO_STMRCAP_STPOL0_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL0_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL0_Enum; + +/* ======================================================== IOM0IRQ ======================================================== */ +/* ======================================================== IOM1IRQ ======================================================== */ +/* ======================================================== IOM2IRQ ======================================================== */ +/* ======================================================== IOM3IRQ ======================================================== */ +/* ======================================================== IOM4IRQ ======================================================== */ +/* ======================================================== IOM5IRQ ======================================================== */ +/* ======================================================= LOOPBACK ======================================================== */ +/* ============================================= GPIO LOOPBACK LOOPBACK [0..2] ============================================= */ +typedef enum { /*!< GPIO_LOOPBACK_LOOPBACK */ + GPIO_LOOPBACK_LOOPBACK_LOOP0 = 0, /*!< LOOP0 : Loop IOM0 to IOS */ + GPIO_LOOPBACK_LOOPBACK_LOOP1 = 1, /*!< LOOP1 : Loop IOM1 to IOS */ + GPIO_LOOPBACK_LOOPBACK_LOOP2 = 2, /*!< LOOP2 : Loop IOM2 to IOS */ + GPIO_LOOPBACK_LOOPBACK_LOOP3 = 3, /*!< LOOP3 : Loop IOM3 to IOS */ + GPIO_LOOPBACK_LOOPBACK_LOOP4 = 4, /*!< LOOP4 : Loop IOM4 to IOS */ + GPIO_LOOPBACK_LOOPBACK_LOOP5 = 5, /*!< LOOP5 : Loop IOM5 to IOS */ + GPIO_LOOPBACK_LOOPBACK_LOOPNONE = 6, /*!< LOOPNONE : No loopback connections */ +} GPIO_LOOPBACK_LOOPBACK_Enum; + +/* ======================================================== GPIOOBS ======================================================== */ +/* ====================================================== ALTPADCFGA ======================================================= */ +/* =========================================== GPIO ALTPADCFGA PAD3_SR [28..28] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD3_SR */ + GPIO_ALTPADCFGA_PAD3_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD3_SR_Enum; + +/* =========================================== GPIO ALTPADCFGA PAD2_SR [20..20] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD2_SR */ + GPIO_ALTPADCFGA_PAD2_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD2_SR_Enum; + +/* =========================================== GPIO ALTPADCFGA PAD1_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD1_SR */ + GPIO_ALTPADCFGA_PAD1_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD1_SR_Enum; + +/* ============================================ GPIO ALTPADCFGA PAD0_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD0_SR */ + GPIO_ALTPADCFGA_PAD0_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD0_SR_Enum; + +/* ====================================================== ALTPADCFGB ======================================================= */ +/* =========================================== GPIO ALTPADCFGB PAD7_SR [28..28] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD7_SR */ + GPIO_ALTPADCFGB_PAD7_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD7_SR_Enum; + +/* =========================================== GPIO ALTPADCFGB PAD6_SR [20..20] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD6_SR */ + GPIO_ALTPADCFGB_PAD6_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD6_SR_Enum; + +/* =========================================== GPIO ALTPADCFGB PAD5_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD5_SR */ + GPIO_ALTPADCFGB_PAD5_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD5_SR_Enum; + +/* ============================================ GPIO ALTPADCFGB PAD4_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD4_SR */ + GPIO_ALTPADCFGB_PAD4_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD4_SR_Enum; + +/* ====================================================== ALTPADCFGC ======================================================= */ +/* =========================================== GPIO ALTPADCFGC PAD11_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD11_SR */ + GPIO_ALTPADCFGC_PAD11_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD11_SR_Enum; + +/* =========================================== GPIO ALTPADCFGC PAD10_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD10_SR */ + GPIO_ALTPADCFGC_PAD10_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD10_SR_Enum; + +/* =========================================== GPIO ALTPADCFGC PAD9_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD9_SR */ + GPIO_ALTPADCFGC_PAD9_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD9_SR_Enum; + +/* ============================================ GPIO ALTPADCFGC PAD8_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD8_SR */ + GPIO_ALTPADCFGC_PAD8_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD8_SR_Enum; + +/* ====================================================== ALTPADCFGD ======================================================= */ +/* =========================================== GPIO ALTPADCFGD PAD15_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD15_SR */ + GPIO_ALTPADCFGD_PAD15_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD15_SR_Enum; + +/* =========================================== GPIO ALTPADCFGD PAD14_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD14_SR */ + GPIO_ALTPADCFGD_PAD14_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD14_SR_Enum; + +/* =========================================== GPIO ALTPADCFGD PAD13_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD13_SR */ + GPIO_ALTPADCFGD_PAD13_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD13_SR_Enum; + +/* ============================================ GPIO ALTPADCFGD PAD12_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD12_SR */ + GPIO_ALTPADCFGD_PAD12_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD12_SR_Enum; + +/* ====================================================== ALTPADCFGE ======================================================= */ +/* =========================================== GPIO ALTPADCFGE PAD19_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD19_SR */ + GPIO_ALTPADCFGE_PAD19_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD19_SR_Enum; + +/* =========================================== GPIO ALTPADCFGE PAD18_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD18_SR */ + GPIO_ALTPADCFGE_PAD18_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD18_SR_Enum; + +/* =========================================== GPIO ALTPADCFGE PAD17_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD17_SR */ + GPIO_ALTPADCFGE_PAD17_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD17_SR_Enum; + +/* ============================================ GPIO ALTPADCFGE PAD16_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD16_SR */ + GPIO_ALTPADCFGE_PAD16_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD16_SR_Enum; + +/* ====================================================== ALTPADCFGF ======================================================= */ +/* =========================================== GPIO ALTPADCFGF PAD23_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD23_SR */ + GPIO_ALTPADCFGF_PAD23_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD23_SR_Enum; + +/* =========================================== GPIO ALTPADCFGF PAD22_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD22_SR */ + GPIO_ALTPADCFGF_PAD22_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD22_SR_Enum; + +/* =========================================== GPIO ALTPADCFGF PAD21_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD21_SR */ + GPIO_ALTPADCFGF_PAD21_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD21_SR_Enum; + +/* ============================================ GPIO ALTPADCFGF PAD20_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD20_SR */ + GPIO_ALTPADCFGF_PAD20_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD20_SR_Enum; + +/* ====================================================== ALTPADCFGG ======================================================= */ +/* =========================================== GPIO ALTPADCFGG PAD27_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD27_SR */ + GPIO_ALTPADCFGG_PAD27_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD27_SR_Enum; + +/* =========================================== GPIO ALTPADCFGG PAD26_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD26_SR */ + GPIO_ALTPADCFGG_PAD26_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD26_SR_Enum; + +/* =========================================== GPIO ALTPADCFGG PAD25_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD25_SR */ + GPIO_ALTPADCFGG_PAD25_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD25_SR_Enum; + +/* ============================================ GPIO ALTPADCFGG PAD24_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD24_SR */ + GPIO_ALTPADCFGG_PAD24_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD24_SR_Enum; + +/* ====================================================== ALTPADCFGH ======================================================= */ +/* =========================================== GPIO ALTPADCFGH PAD31_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD31_SR */ + GPIO_ALTPADCFGH_PAD31_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD31_SR_Enum; + +/* =========================================== GPIO ALTPADCFGH PAD30_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD30_SR */ + GPIO_ALTPADCFGH_PAD30_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD30_SR_Enum; + +/* =========================================== GPIO ALTPADCFGH PAD29_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD29_SR */ + GPIO_ALTPADCFGH_PAD29_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD29_SR_Enum; + +/* ============================================ GPIO ALTPADCFGH PAD28_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD28_SR */ + GPIO_ALTPADCFGH_PAD28_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD28_SR_Enum; + +/* ====================================================== ALTPADCFGI ======================================================= */ +/* =========================================== GPIO ALTPADCFGI PAD35_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD35_SR */ + GPIO_ALTPADCFGI_PAD35_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD35_SR_Enum; + +/* =========================================== GPIO ALTPADCFGI PAD34_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD34_SR */ + GPIO_ALTPADCFGI_PAD34_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD34_SR_Enum; + +/* =========================================== GPIO ALTPADCFGI PAD33_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD33_SR */ + GPIO_ALTPADCFGI_PAD33_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD33_SR_Enum; + +/* ============================================ GPIO ALTPADCFGI PAD32_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD32_SR */ + GPIO_ALTPADCFGI_PAD32_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD32_SR_Enum; + +/* ====================================================== ALTPADCFGJ ======================================================= */ +/* =========================================== GPIO ALTPADCFGJ PAD39_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD39_SR */ + GPIO_ALTPADCFGJ_PAD39_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD39_SR_Enum; + +/* =========================================== GPIO ALTPADCFGJ PAD38_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD38_SR */ + GPIO_ALTPADCFGJ_PAD38_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD38_SR_Enum; + +/* =========================================== GPIO ALTPADCFGJ PAD37_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD37_SR */ + GPIO_ALTPADCFGJ_PAD37_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD37_SR_Enum; + +/* ============================================ GPIO ALTPADCFGJ PAD36_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD36_SR */ + GPIO_ALTPADCFGJ_PAD36_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD36_SR_Enum; + +/* ====================================================== ALTPADCFGK ======================================================= */ +/* =========================================== GPIO ALTPADCFGK PAD43_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD43_SR */ + GPIO_ALTPADCFGK_PAD43_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD43_SR_Enum; + +/* =========================================== GPIO ALTPADCFGK PAD42_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD42_SR */ + GPIO_ALTPADCFGK_PAD42_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD42_SR_Enum; + +/* =========================================== GPIO ALTPADCFGK PAD41_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD41_SR */ + GPIO_ALTPADCFGK_PAD41_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD41_SR_Enum; + +/* ============================================ GPIO ALTPADCFGK PAD40_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD40_SR */ + GPIO_ALTPADCFGK_PAD40_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD40_SR_Enum; + +/* ====================================================== ALTPADCFGL ======================================================= */ +/* =========================================== GPIO ALTPADCFGL PAD47_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD47_SR */ + GPIO_ALTPADCFGL_PAD47_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD47_SR_Enum; + +/* =========================================== GPIO ALTPADCFGL PAD46_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD46_SR */ + GPIO_ALTPADCFGL_PAD46_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD46_SR_Enum; + +/* =========================================== GPIO ALTPADCFGL PAD45_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD45_SR */ + GPIO_ALTPADCFGL_PAD45_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD45_SR_Enum; + +/* ============================================ GPIO ALTPADCFGL PAD44_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD44_SR */ + GPIO_ALTPADCFGL_PAD44_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD44_SR_Enum; + +/* ====================================================== ALTPADCFGM ======================================================= */ +/* =========================================== GPIO ALTPADCFGM PAD49_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGM_PAD49_SR */ + GPIO_ALTPADCFGM_PAD49_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGM_PAD49_SR_Enum; + +/* ============================================ GPIO ALTPADCFGM PAD48_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGM_PAD48_SR */ + GPIO_ALTPADCFGM_PAD48_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGM_PAD48_SR_Enum; + +/* ======================================================== INT0EN ========================================================= */ +/* ======================================================= INT0STAT ======================================================== */ +/* ======================================================== INT0CLR ======================================================== */ +/* ======================================================== INT0SET ======================================================== */ +/* ======================================================== INT1EN ========================================================= */ +/* ======================================================= INT1STAT ======================================================== */ +/* ======================================================== INT1CLR ======================================================== */ +/* ======================================================== INT1SET ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ IOMSTR0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== TLNGTH ========================================================= */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ======================================================== CLKCFG ========================================================= */ +/* ============================================= IOMSTR0 CLKCFG DIVEN [12..12] ============================================= */ +typedef enum { /*!< IOMSTR0_CLKCFG_DIVEN */ + IOMSTR0_CLKCFG_DIVEN_DIS = 0, /*!< DIS : Disable TOTPER division. */ + IOMSTR0_CLKCFG_DIVEN_EN = 1, /*!< EN : Enable TOTPER division. */ +} IOMSTR0_CLKCFG_DIVEN_Enum; + +/* ============================================= IOMSTR0 CLKCFG DIV3 [11..11] ============================================== */ +typedef enum { /*!< IOMSTR0_CLKCFG_DIV3 */ + IOMSTR0_CLKCFG_DIV3_DIS = 0, /*!< DIS : Select divide by 1. */ + IOMSTR0_CLKCFG_DIV3_EN = 1, /*!< EN : Select divide by 3. */ +} IOMSTR0_CLKCFG_DIV3_Enum; + +/* ============================================== IOMSTR0 CLKCFG FSEL [8..10] ============================================== */ +typedef enum { /*!< IOMSTR0_CLKCFG_FSEL */ + IOMSTR0_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should + be used whenever the IOMSTR is not active. */ + IOMSTR0_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ + IOMSTR0_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ + IOMSTR0_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ + IOMSTR0_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ + IOMSTR0_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ + IOMSTR0_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ + IOMSTR0_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ +} IOMSTR0_CLKCFG_FSEL_Enum; + +/* ========================================================== CMD ========================================================== */ +/* ======================================================== CMDRPT ========================================================= */ +/* ======================================================== STATUS ========================================================= */ +/* ============================================= IOMSTR0 STATUS IDLEST [2..2] ============================================== */ +typedef enum { /*!< IOMSTR0_STATUS_IDLEST */ + IOMSTR0_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ +} IOMSTR0_STATUS_IDLEST_Enum; + +/* ============================================= IOMSTR0 STATUS CMDACT [1..1] ============================================== */ +typedef enum { /*!< IOMSTR0_STATUS_CMDACT */ + IOMSTR0_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. */ +} IOMSTR0_STATUS_CMDACT_Enum; + +/* =============================================== IOMSTR0 STATUS ERR [0..0] =============================================== */ +typedef enum { /*!< IOMSTR0_STATUS_ERR */ + IOMSTR0_STATUS_ERR_ERROR = 1, /*!< ERROR : An error has been indicated by the IOM. */ +} IOMSTR0_STATUS_ERR_Enum; + +/* ========================================================== CFG ========================================================== */ +/* ============================================== IOMSTR0 CFG IFCEN [31..31] =============================================== */ +typedef enum { /*!< IOMSTR0_CFG_IFCEN */ + IOMSTR0_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IO Master. */ + IOMSTR0_CFG_IFCEN_EN = 1, /*!< EN : Enable the IO Master. */ +} IOMSTR0_CFG_IFCEN_Enum; + +/* ============================================= IOMSTR0 CFG RDFCPOL [14..14] ============================================== */ +typedef enum { /*!< IOMSTR0_CFG_RDFCPOL */ + IOMSTR0_CFG_RDFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high creates flow control. */ + IOMSTR0_CFG_RDFCPOL_LOW = 1, /*!< LOW : Flow control signal low creates flow control. */ +} IOMSTR0_CFG_RDFCPOL_Enum; + +/* ============================================= IOMSTR0 CFG WTFCPOL [13..13] ============================================== */ +typedef enum { /*!< IOMSTR0_CFG_WTFCPOL */ + IOMSTR0_CFG_WTFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high creates flow control. */ + IOMSTR0_CFG_WTFCPOL_LOW = 1, /*!< LOW : Flow control signal low creates flow control. */ +} IOMSTR0_CFG_WTFCPOL_Enum; + +/* ============================================= IOMSTR0 CFG WTFCIRQ [12..12] ============================================== */ +typedef enum { /*!< IOMSTR0_CFG_WTFCIRQ */ + IOMSTR0_CFG_WTFCIRQ_MISO = 0, /*!< MISO : MISO is used as the write mode flow control signal. */ + IOMSTR0_CFG_WTFCIRQ_IRQ = 1, /*!< IRQ : IRQ is used as the write mode flow control signal. */ +} IOMSTR0_CFG_WTFCIRQ_Enum; + +/* ============================================= IOMSTR0 CFG MOSIINV [10..10] ============================================== */ +typedef enum { /*!< IOMSTR0_CFG_MOSIINV */ + IOMSTR0_CFG_MOSIINV_NORMAL = 0, /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode. */ + IOMSTR0_CFG_MOSIINV_INVERT = 1, /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode. */ +} IOMSTR0_CFG_MOSIINV_Enum; + +/* ================================================ IOMSTR0 CFG RDFC [9..9] ================================================ */ +typedef enum { /*!< IOMSTR0_CFG_RDFC */ + IOMSTR0_CFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ + IOMSTR0_CFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ +} IOMSTR0_CFG_RDFC_Enum; + +/* ================================================ IOMSTR0 CFG WTFC [8..8] ================================================ */ +typedef enum { /*!< IOMSTR0_CFG_WTFC */ + IOMSTR0_CFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ + IOMSTR0_CFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ +} IOMSTR0_CFG_WTFC_Enum; + +/* ============================================== IOMSTR0 CFG STARTRD [4..5] =============================================== */ +typedef enum { /*!< IOMSTR0_CFG_STARTRD */ + IOMSTR0_CFG_STARTRD_PRERD0 = 0, /*!< PRERD0 : 0 read delay cycles. */ + IOMSTR0_CFG_STARTRD_PRERD1 = 1, /*!< PRERD1 : 1 read delay cycles. */ + IOMSTR0_CFG_STARTRD_PRERD2 = 2, /*!< PRERD2 : 2 read delay cycles. */ + IOMSTR0_CFG_STARTRD_PRERD3 = 3, /*!< PRERD3 : 3 read delay cycles. */ +} IOMSTR0_CFG_STARTRD_Enum; + +/* ============================================== IOMSTR0 CFG FULLDUP [3..3] =============================================== */ +typedef enum { /*!< IOMSTR0_CFG_FULLDUP */ + IOMSTR0_CFG_FULLDUP_NORMAL = 0, /*!< NORMAL : 128 byte FIFO in half duplex mode. */ + IOMSTR0_CFG_FULLDUP_FULLDUP = 1, /*!< FULLDUP : 64 byte FIFO in full duplex mode. */ +} IOMSTR0_CFG_FULLDUP_Enum; + +/* ================================================ IOMSTR0 CFG SPHA [2..2] ================================================ */ +typedef enum { /*!< IOMSTR0_CFG_SPHA */ + IOMSTR0_CFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge. */ + IOMSTR0_CFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock + edge. */ +} IOMSTR0_CFG_SPHA_Enum; + +/* ================================================ IOMSTR0 CFG SPOL [1..1] ================================================ */ +typedef enum { /*!< IOMSTR0_CFG_SPOL */ + IOMSTR0_CFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The base value of the clock is 0. */ + IOMSTR0_CFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The base value of the clock is 1. */ +} IOMSTR0_CFG_SPOL_Enum; + +/* =============================================== IOMSTR0 CFG IFCSEL [0..0] =============================================== */ +typedef enum { /*!< IOMSTR0_CFG_IFCSEL */ + IOMSTR0_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the I/O Master. */ + IOMSTR0_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the I/O Master. */ +} IOMSTR0_CFG_IFCSEL_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOCFG ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ========================================================= FUPD ========================================================== */ +/* ======================================================== FIFOCTR ======================================================== */ +/* ======================================================== FIFOINC ======================================================== */ +/* ========================================================== CFG ========================================================== */ +/* ============================================== IOSLAVE CFG IFCEN [31..31] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_IFCEN */ + IOSLAVE_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IOSLAVE */ + IOSLAVE_CFG_IFCEN_EN = 1, /*!< EN : Enable the IOSLAVE */ +} IOSLAVE_CFG_IFCEN_Enum; + +/* ============================================== IOSLAVE CFG STARTRD [4..4] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_STARTRD */ + IOSLAVE_CFG_STARTRD_LATE = 0, /*!< LATE : Initiate I/O RAM read late in each transferred byte. */ + IOSLAVE_CFG_STARTRD_EARLY = 1, /*!< EARLY : Initiate I/O RAM read early in each transferred byte. */ +} IOSLAVE_CFG_STARTRD_Enum; + +/* ================================================ IOSLAVE CFG LSB [2..2] ================================================= */ +typedef enum { /*!< IOSLAVE_CFG_LSB */ + IOSLAVE_CFG_LSB_MSB_FIRST = 0, /*!< MSB_FIRST : Data is assumed to be sent and received with MSB + first. */ + IOSLAVE_CFG_LSB_LSB_FIRST = 1, /*!< LSB_FIRST : Data is assumed to be sent and received with LSB + first. */ +} IOSLAVE_CFG_LSB_Enum; + +/* ================================================ IOSLAVE CFG SPOL [1..1] ================================================ */ +typedef enum { /*!< IOSLAVE_CFG_SPOL */ + IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0, /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3. */ + IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1, /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2. */ +} IOSLAVE_CFG_SPOL_Enum; + +/* =============================================== IOSLAVE CFG IFCSEL [0..0] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_IFCSEL */ + IOSLAVE_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the IO Slave. */ + IOSLAVE_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the IO Slave. */ +} IOSLAVE_CFG_IFCSEL_Enum; + +/* ========================================================= PRENC ========================================================= */ +/* ======================================================= IOINTCTL ======================================================== */ +/* ======================================================== GENADD ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ====================================================== REGACCINTEN ====================================================== */ +/* ===================================================== REGACCINTSTAT ===================================================== */ +/* ===================================================== REGACCINTCLR ====================================================== */ +/* ===================================================== REGACCINTSET ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CHIP_INFO ======================================================= */ +/* =========================================== MCUCTRL CHIP_INFO PARTNUM [0..31] =========================================== */ +typedef enum { /*!< MCUCTRL_CHIP_INFO_PARTNUM */ + MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 = 50331648,/*!< APOLLO2 : Apollo2 part number is 0x03XXXXXX. */ + MCUCTRL_CHIP_INFO_PARTNUM_APOLLO = 16777216,/*!< APOLLO : Apollo part number is 0x01XXXXXX. */ + MCUCTRL_CHIP_INFO_PARTNUM_PN_M = -16777216,/*!< PN_M : Mask for the PN field. */ +} MCUCTRL_CHIP_INFO_PARTNUM_Enum; + +/* ======================================================== CHIPID0 ======================================================== */ +/* ============================================= MCUCTRL CHIPID0 VALUE [0..31] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPID0_VALUE */ + MCUCTRL_CHIPID0_VALUE_APOLLO2 = 0, /*!< APOLLO2 : Apollo2 CHIPID0. The lower 32-bits of the 64-bit CHIPID + value, which is unique for each part. */ +} MCUCTRL_CHIPID0_VALUE_Enum; + +/* ======================================================== CHIPID1 ======================================================== */ +/* ============================================= MCUCTRL CHIPID1 VALUE [0..31] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPID1_VALUE */ + MCUCTRL_CHIPID1_VALUE_APOLLO2 = 0, /*!< APOLLO2 : Apollo2 CHIPID1. The upper 32-bits of the 64-bit CHIPID + value, which is unique for each part. */ +} MCUCTRL_CHIPID1_VALUE_Enum; + +/* ======================================================== CHIPREV ======================================================== */ +/* ============================================= MCUCTRL CHIPREV REVMAJ [4..7] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPREV_REVMAJ */ + MCUCTRL_CHIPREV_REVMAJ_B = 2, /*!< B : Apollo2 revision B */ + MCUCTRL_CHIPREV_REVMAJ_A = 1, /*!< A : Apollo2 revision A */ +} MCUCTRL_CHIPREV_REVMAJ_Enum; + +/* ============================================= MCUCTRL CHIPREV REVMIN [0..3] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPREV_REVMIN */ + MCUCTRL_CHIPREV_REVMIN_REV0 = 0, /*!< REV0 : Apollo2 minor revision value. Succeeding minor revisions + will increment from this value. */ + MCUCTRL_CHIPREV_REVMIN_REV2 = 2, /*!< REV2 : Apollo2 minor revision value. */ +} MCUCTRL_CHIPREV_REVMIN_Enum; + +/* ======================================================= VENDORID ======================================================== */ +/* ============================================ MCUCTRL VENDORID VALUE [0..31] ============================================= */ +typedef enum { /*!< MCUCTRL_VENDORID_VALUE */ + MCUCTRL_VENDORID_VALUE_AMBIQ = 1095582289,/*!< AMBIQ : Ambiq Vendor ID */ +} MCUCTRL_VENDORID_VALUE_Enum; + +/* ======================================================= DEBUGGER ======================================================== */ +/* ========================================================= BUCK ========================================================== */ +/* ============================================ MCUCTRL BUCK MEMBUCKPWD [4..4] ============================================= */ +typedef enum { /*!< MCUCTRL_BUCK_MEMBUCKPWD */ + MCUCTRL_BUCK_MEMBUCKPWD_EN = 0, /*!< EN : Memory Buck Enable. */ +} MCUCTRL_BUCK_MEMBUCKPWD_Enum; + +/* ============================================ MCUCTRL BUCK COREBUCKPWD [2..2] ============================================ */ +typedef enum { /*!< MCUCTRL_BUCK_COREBUCKPWD */ + MCUCTRL_BUCK_COREBUCKPWD_EN = 0, /*!< EN : Core Buck enable. */ +} MCUCTRL_BUCK_COREBUCKPWD_Enum; + +/* ============================================== MCUCTRL BUCK BUCKSWE [0..0] ============================================== */ +typedef enum { /*!< MCUCTRL_BUCK_BUCKSWE */ + MCUCTRL_BUCK_BUCKSWE_OVERRIDE_DIS = 0, /*!< OVERRIDE_DIS : BUCK Software Override Disable. */ + MCUCTRL_BUCK_BUCKSWE_OVERRIDE_EN = 1, /*!< OVERRIDE_EN : BUCK Software Override Enable. */ +} MCUCTRL_BUCK_BUCKSWE_Enum; + +/* ========================================================= BUCK3 ========================================================= */ +/* ======================================================== LDOREG1 ======================================================== */ +/* ======================================================== LDOREG3 ======================================================== */ +/* ====================================================== BODPORCTRL ======================================================= */ +/* ======================================== MCUCTRL BODPORCTRL BODEXTREFSEL [3..3] ========================================= */ +typedef enum { /*!< MCUCTRL_BODPORCTRL_BODEXTREFSEL */ + MCUCTRL_BODPORCTRL_BODEXTREFSEL_SELECT = 1, /*!< SELECT : BOD external reference select. */ +} MCUCTRL_BODPORCTRL_BODEXTREFSEL_Enum; + +/* ======================================== MCUCTRL BODPORCTRL PDREXTREFSEL [2..2] ========================================= */ +typedef enum { /*!< MCUCTRL_BODPORCTRL_PDREXTREFSEL */ + MCUCTRL_BODPORCTRL_PDREXTREFSEL_SELECT = 1, /*!< SELECT : PDR external reference select. */ +} MCUCTRL_BODPORCTRL_PDREXTREFSEL_Enum; + +/* =========================================== MCUCTRL BODPORCTRL PWDBOD [1..1] ============================================ */ +typedef enum { /*!< MCUCTRL_BODPORCTRL_PWDBOD */ + MCUCTRL_BODPORCTRL_PWDBOD_PWR_DN = 1, /*!< PWR_DN : BOD power down. */ +} MCUCTRL_BODPORCTRL_PWDBOD_Enum; + +/* =========================================== MCUCTRL BODPORCTRL PWDPDR [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_BODPORCTRL_PWDPDR */ + MCUCTRL_BODPORCTRL_PWDPDR_PWR_DN = 1, /*!< PWR_DN : PDR power down */ +} MCUCTRL_BODPORCTRL_PWDPDR_Enum; + +/* ======================================================= ADCPWRDLY ======================================================= */ +/* ======================================================== ADCCAL ========================================================= */ +/* ========================================== MCUCTRL ADCCAL ADCCALIBRATED [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_ADCCAL_ADCCALIBRATED */ + MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE = 0, /*!< FALSE : ADC is not calibrated */ + MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE = 1, /*!< TRUE : ADC is calibrated */ +} MCUCTRL_ADCCAL_ADCCALIBRATED_Enum; + +/* =========================================== MCUCTRL ADCCAL CALONPWRUP [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_ADCCAL_CALONPWRUP */ + MCUCTRL_ADCCAL_CALONPWRUP_DIS = 0, /*!< DIS : Disable automatic calibration on initial power up */ + MCUCTRL_ADCCAL_CALONPWRUP_EN = 1, /*!< EN : Enable automatic calibration on initial power up */ +} MCUCTRL_ADCCAL_CALONPWRUP_Enum; + +/* ====================================================== ADCBATTLOAD ====================================================== */ +/* ========================================== MCUCTRL ADCBATTLOAD BATTLOAD [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD */ + MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS = 0, /*!< DIS : Battery load is disconnected */ + MCUCTRL_ADCBATTLOAD_BATTLOAD_EN = 1, /*!< EN : Battery load is enabled */ +} MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum; + +/* ======================================================= BUCKTRIM ======================================================== */ +/* ====================================================== XTALGENCTRL ====================================================== */ +/* ========================================== MCUCTRL XTALGENCTRL ACWARMUP [0..1] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALGENCTRL_ACWARMUP */ + MCUCTRL_XTALGENCTRL_ACWARMUP_1SEC = 0, /*!< 1SEC : Warmup period of 1-2 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_2SEC = 1, /*!< 2SEC : Warmup period of 2-4 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_4SEC = 2, /*!< 4SEC : Warmup period of 4-8 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_8SEC = 3, /*!< 8SEC : Warmup period of 8-16 seconds */ +} MCUCTRL_XTALGENCTRL_ACWARMUP_Enum; + +/* ===================================================== BOOTLOADERLOW ===================================================== */ +/* ========================================== MCUCTRL BOOTLOADERLOW VALUE [0..0] =========================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADERLOW_VALUE */ + MCUCTRL_BOOTLOADERLOW_VALUE_ADDR0 = 1, /*!< ADDR0 : Bootloader code at 0x00000000. */ +} MCUCTRL_BOOTLOADERLOW_VALUE_Enum; + +/* ====================================================== SHADOWVALID ====================================================== */ +/* ========================================= MCUCTRL SHADOWVALID BL_DSLEEP [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_BL_DSLEEP */ + MCUCTRL_SHADOWVALID_BL_DSLEEP_DEEPSLEEP = 1, /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image + loaded */ +} MCUCTRL_SHADOWVALID_BL_DSLEEP_Enum; + +/* =========================================== MCUCTRL SHADOWVALID VALID [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_VALID */ + MCUCTRL_SHADOWVALID_VALID_VALID = 1, /*!< VALID : Flash information space contains valid data. */ +} MCUCTRL_SHADOWVALID_VALID_Enum; + +/* ==================================================== ICODEFAULTADDR ===================================================== */ +/* ==================================================== DCODEFAULTADDR ===================================================== */ +/* ===================================================== SYSFAULTADDR ====================================================== */ +/* ====================================================== FAULTSTATUS ====================================================== */ +/* ============================================ MCUCTRL FAULTSTATUS SYS [2..2] ============================================= */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_SYS */ + MCUCTRL_FAULTSTATUS_SYS_NOFAULT = 0, /*!< NOFAULT : No bus fault has been detected. */ + MCUCTRL_FAULTSTATUS_SYS_FAULT = 1, /*!< FAULT : Bus fault detected. */ +} MCUCTRL_FAULTSTATUS_SYS_Enum; + +/* =========================================== MCUCTRL FAULTSTATUS DCODE [1..1] ============================================ */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_DCODE */ + MCUCTRL_FAULTSTATUS_DCODE_NOFAULT = 0, /*!< NOFAULT : No DCODE fault has been detected. */ + MCUCTRL_FAULTSTATUS_DCODE_FAULT = 1, /*!< FAULT : DCODE fault detected. */ +} MCUCTRL_FAULTSTATUS_DCODE_Enum; + +/* =========================================== MCUCTRL FAULTSTATUS ICODE [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_ICODE */ + MCUCTRL_FAULTSTATUS_ICODE_NOFAULT = 0, /*!< NOFAULT : No ICODE fault has been detected. */ + MCUCTRL_FAULTSTATUS_ICODE_FAULT = 1, /*!< FAULT : ICODE fault detected. */ +} MCUCTRL_FAULTSTATUS_ICODE_Enum; + +/* ==================================================== FAULTCAPTUREEN ===================================================== */ +/* ========================================= MCUCTRL FAULTCAPTUREEN ENABLE [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_FAULTCAPTUREEN_ENABLE */ + MCUCTRL_FAULTCAPTUREEN_ENABLE_DIS = 0, /*!< DIS : Disable fault capture. */ + MCUCTRL_FAULTCAPTUREEN_ENABLE_EN = 1, /*!< EN : Enable fault capture. */ +} MCUCTRL_FAULTCAPTUREEN_ENABLE_Enum; + +/* ========================================================= DBGR1 ========================================================= */ +/* ========================================================= DBGR2 ========================================================= */ +/* ======================================================= PMUENABLE ======================================================= */ +/* ============================================ MCUCTRL PMUENABLE ENABLE [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_PMUENABLE_ENABLE */ + MCUCTRL_PMUENABLE_ENABLE_DIS = 0, /*!< DIS : Disable MCU power management. */ + MCUCTRL_PMUENABLE_ENABLE_EN = 1, /*!< EN : Enable MCU power management. */ +} MCUCTRL_PMUENABLE_ENABLE_Enum; + +/* ======================================================= TPIUCTRL ======================================================== */ +/* ============================================ MCUCTRL TPIUCTRL CLKSEL [8..10] ============================================ */ +typedef enum { /*!< MCUCTRL_TPIUCTRL_CLKSEL */ + MCUCTRL_TPIUCTRL_CLKSEL_LOW_PWR = 0, /*!< LOW_PWR : Low power state. */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_2 = 1, /*!< HFRC_DIV_2 : Selects HFRC divided by 2 as the source TPIU clk */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_8 = 2, /*!< HFRC_DIV_8 : Selects HFRC divided by 8 as the source TPIU clk */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_16 = 3, /*!< HFRC_DIV_16 : Selects HFRC divided by 16 as the source TPIU + clk */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_32 = 4, /*!< HFRC_DIV_32 : Selects HFRC divided by 32 as the source TPIU + clk */ +} MCUCTRL_TPIUCTRL_CLKSEL_Enum; + +/* ============================================ MCUCTRL TPIUCTRL ENABLE [0..0] ============================================= */ +typedef enum { /*!< MCUCTRL_TPIUCTRL_ENABLE */ + MCUCTRL_TPIUCTRL_ENABLE_DIS = 0, /*!< DIS : Disable the TPIU. */ + MCUCTRL_TPIUCTRL_ENABLE_EN = 1, /*!< EN : Enable the TPIU. */ +} MCUCTRL_TPIUCTRL_ENABLE_Enum; + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCFG ========================================================== */ +/* =============================================== PDM PCFG LRSWAP [31..31] ================================================ */ +typedef enum { /*!< PDM_PCFG_LRSWAP */ + PDM_PCFG_LRSWAP_EN = 1, /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT). */ + PDM_PCFG_LRSWAP_NOSWAP = 0, /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT). */ +} PDM_PCFG_LRSWAP_Enum; + +/* ============================================== PDM PCFG PGARIGHT [27..30] =============================================== */ +typedef enum { /*!< PDM_PCFG_PGARIGHT */ + PDM_PCFG_PGARIGHT_M15DB = 15, /*!< M15DB : -1.5 db gain. */ + PDM_PCFG_PGARIGHT_M300DB = 14, /*!< M300DB : -3.0 db gain. */ + PDM_PCFG_PGARIGHT_M45DB = 13, /*!< M45DB : -4.5 db gain. */ + PDM_PCFG_PGARIGHT_M60DB = 12, /*!< M60DB : -6.0 db gain. */ + PDM_PCFG_PGARIGHT_M75DB = 11, /*!< M75DB : -7.5 db gain. */ + PDM_PCFG_PGARIGHT_M90DB = 10, /*!< M90DB : -9.0 db gain. */ + PDM_PCFG_PGARIGHT_M105DB = 9, /*!< M105DB : -10.5 db gain. */ + PDM_PCFG_PGARIGHT_M120DB = 8, /*!< M120DB : -12.0 db gain. */ + PDM_PCFG_PGARIGHT_P105DB = 7, /*!< P105DB : 10.5 db gain. */ + PDM_PCFG_PGARIGHT_P90DB = 6, /*!< P90DB : 9.0 db gain. */ + PDM_PCFG_PGARIGHT_P75DB = 5, /*!< P75DB : 7.5 db gain. */ + PDM_PCFG_PGARIGHT_P60DB = 4, /*!< P60DB : 6.0 db gain. */ + PDM_PCFG_PGARIGHT_P45DB = 3, /*!< P45DB : 4.5 db gain. */ + PDM_PCFG_PGARIGHT_P30DB = 2, /*!< P30DB : 3.0 db gain. */ + PDM_PCFG_PGARIGHT_P15DB = 1, /*!< P15DB : 1.5 db gain. */ + PDM_PCFG_PGARIGHT_0DB = 0, /*!< 0DB : 0.0 db gain. */ +} PDM_PCFG_PGARIGHT_Enum; + +/* =============================================== PDM PCFG PGALEFT [23..26] =============================================== */ +typedef enum { /*!< PDM_PCFG_PGALEFT */ + PDM_PCFG_PGALEFT_M15DB = 15, /*!< M15DB : -1.5 db gain. */ + PDM_PCFG_PGALEFT_M300DB = 14, /*!< M300DB : -3.0 db gain. */ + PDM_PCFG_PGALEFT_M45DB = 13, /*!< M45DB : -4.5 db gain. */ + PDM_PCFG_PGALEFT_M60DB = 12, /*!< M60DB : -6.0 db gain. */ + PDM_PCFG_PGALEFT_M75DB = 11, /*!< M75DB : -7.5 db gain. */ + PDM_PCFG_PGALEFT_M90DB = 10, /*!< M90DB : -9.0 db gain. */ + PDM_PCFG_PGALEFT_M105DB = 9, /*!< M105DB : -10.5 db gain. */ + PDM_PCFG_PGALEFT_M120DB = 8, /*!< M120DB : -12.0 db gain. */ + PDM_PCFG_PGALEFT_P105DB = 7, /*!< P105DB : 10.5 db gain. */ + PDM_PCFG_PGALEFT_P90DB = 6, /*!< P90DB : 9.0 db gain. */ + PDM_PCFG_PGALEFT_P75DB = 5, /*!< P75DB : 7.5 db gain. */ + PDM_PCFG_PGALEFT_P60DB = 4, /*!< P60DB : 6.0 db gain. */ + PDM_PCFG_PGALEFT_P45DB = 3, /*!< P45DB : 4.5 db gain. */ + PDM_PCFG_PGALEFT_P30DB = 2, /*!< P30DB : 3.0 db gain. */ + PDM_PCFG_PGALEFT_P15DB = 1, /*!< P15DB : 1.5 db gain. */ + PDM_PCFG_PGALEFT_0DB = 0, /*!< 0DB : 0.0 db gain. */ +} PDM_PCFG_PGALEFT_Enum; + +/* =============================================== PDM PCFG MCLKDIV [17..18] =============================================== */ +typedef enum { /*!< PDM_PCFG_MCLKDIV */ + PDM_PCFG_MCLKDIV_MCKDIV4 = 3, /*!< MCKDIV4 : Divide input clock by 4 */ + PDM_PCFG_MCLKDIV_MCKDIV3 = 2, /*!< MCKDIV3 : Divide input clock by 3 */ + PDM_PCFG_MCLKDIV_MCKDIV2 = 1, /*!< MCKDIV2 : Divide input clock by 2 */ + PDM_PCFG_MCLKDIV_MCKDIV1 = 0, /*!< MCKDIV1 : Divide input clock by 1 */ +} PDM_PCFG_MCLKDIV_Enum; + +/* ================================================ PDM PCFG ADCHPD [9..9] ================================================= */ +typedef enum { /*!< PDM_PCFG_ADCHPD */ + PDM_PCFG_ADCHPD_EN = 0, /*!< EN : Enable high pass filter. */ + PDM_PCFG_ADCHPD_DIS = 1, /*!< DIS : Disable high pass filter. */ +} PDM_PCFG_ADCHPD_Enum; + +/* =============================================== PDM PCFG SOFTMUTE [1..1] ================================================ */ +typedef enum { /*!< PDM_PCFG_SOFTMUTE */ + PDM_PCFG_SOFTMUTE_EN = 1, /*!< EN : Enable Soft Mute. */ + PDM_PCFG_SOFTMUTE_DIS = 0, /*!< DIS : Disable Soft Mute. */ +} PDM_PCFG_SOFTMUTE_Enum; + +/* ================================================ PDM PCFG PDMCORE [0..0] ================================================ */ +typedef enum { /*!< PDM_PCFG_PDMCORE */ + PDM_PCFG_PDMCORE_EN = 1, /*!< EN : Enable Data Streaming. */ + PDM_PCFG_PDMCORE_DIS = 0, /*!< DIS : Disable Data Streaming. */ +} PDM_PCFG_PDMCORE_Enum; + +/* ========================================================= VCFG ========================================================== */ +/* =============================================== PDM VCFG IOCLKEN [31..31] =============================================== */ +typedef enum { /*!< PDM_VCFG_IOCLKEN */ + PDM_VCFG_IOCLKEN_DIS = 0, /*!< DIS : Disable FIFO read. */ + PDM_VCFG_IOCLKEN_EN = 1, /*!< EN : Enable FIFO read. */ +} PDM_VCFG_IOCLKEN_Enum; + +/* ================================================ PDM VCFG RSTB [30..30] ================================================= */ +typedef enum { /*!< PDM_VCFG_RSTB */ + PDM_VCFG_RSTB_RESET = 0, /*!< RESET : Reset the core. */ + PDM_VCFG_RSTB_NORM = 1, /*!< NORM : Enable the core. */ +} PDM_VCFG_RSTB_Enum; + +/* ============================================== PDM VCFG PDMCLKSEL [27..29] ============================================== */ +typedef enum { /*!< PDM_VCFG_PDMCLKSEL */ + PDM_VCFG_PDMCLKSEL_DISABLE = 0, /*!< DISABLE : Static value. */ + PDM_VCFG_PDMCLKSEL_12MHz = 1, /*!< 12MHz : PDM clock is 12 MHz. */ + PDM_VCFG_PDMCLKSEL_6MHz = 2, /*!< 6MHz : PDM clock is 6 MHz. */ + PDM_VCFG_PDMCLKSEL_3MHz = 3, /*!< 3MHz : PDM clock is 3 MHz. */ + PDM_VCFG_PDMCLKSEL_1_5MHz = 4, /*!< 1_5MHz : PDM clock is 1.5 MHz. */ + PDM_VCFG_PDMCLKSEL_750KHz = 5, /*!< 750KHz : PDM clock is 750 KHz. */ + PDM_VCFG_PDMCLKSEL_375KHz = 6, /*!< 375KHz : PDM clock is 375 KHz. */ + PDM_VCFG_PDMCLKSEL_187KHz = 7, /*!< 187KHz : PDM clock is 187.5 KHz. */ +} PDM_VCFG_PDMCLKSEL_Enum; + +/* =============================================== PDM VCFG PDMCLK [26..26] ================================================ */ +typedef enum { /*!< PDM_VCFG_PDMCLK */ + PDM_VCFG_PDMCLK_DIS = 0, /*!< DIS : Disable serial clock. */ + PDM_VCFG_PDMCLK_EN = 1, /*!< EN : Enable serial clock. */ +} PDM_VCFG_PDMCLK_Enum; + +/* =============================================== PDM VCFG I2SMODE [20..20] =============================================== */ +typedef enum { /*!< PDM_VCFG_I2SMODE */ + PDM_VCFG_I2SMODE_DIS = 0, /*!< DIS : Disable I2S interface. */ + PDM_VCFG_I2SMODE_EN = 1, /*!< EN : Enable I2S interface. */ +} PDM_VCFG_I2SMODE_Enum; + +/* =============================================== PDM VCFG BCLKINV [19..19] =============================================== */ +typedef enum { /*!< PDM_VCFG_BCLKINV */ + PDM_VCFG_BCLKINV_INV = 0, /*!< INV : BCLK inverted. */ + PDM_VCFG_BCLKINV_NORM = 1, /*!< NORM : BCLK not inverted. */ +} PDM_VCFG_BCLKINV_Enum; + +/* ============================================== PDM VCFG DMICKDEL [17..17] =============================================== */ +typedef enum { /*!< PDM_VCFG_DMICKDEL */ + PDM_VCFG_DMICKDEL_0CYC = 0, /*!< 0CYC : No delay. */ + PDM_VCFG_DMICKDEL_1CYC = 1, /*!< 1CYC : 1 cycle delay. */ +} PDM_VCFG_DMICKDEL_Enum; + +/* ================================================ PDM VCFG SELAP [16..16] ================================================ */ +typedef enum { /*!< PDM_VCFG_SELAP */ + PDM_VCFG_SELAP_I2S = 1, /*!< I2S : Clock source from I2S BCLK. */ + PDM_VCFG_SELAP_INTERNAL = 0, /*!< INTERNAL : Clock source from internal clock generator. */ +} PDM_VCFG_SELAP_Enum; + +/* ================================================ PDM VCFG PCMPACK [8..8] ================================================ */ +typedef enum { /*!< PDM_VCFG_PCMPACK */ + PDM_VCFG_PCMPACK_DIS = 0, /*!< DIS : Disable PCM packing. */ + PDM_VCFG_PCMPACK_EN = 1, /*!< EN : Enable PCM packing. */ +} PDM_VCFG_PCMPACK_Enum; + +/* ================================================= PDM VCFG CHSET [3..4] ================================================= */ +typedef enum { /*!< PDM_VCFG_CHSET */ + PDM_VCFG_CHSET_DIS = 0, /*!< DIS : Channel disabled. */ + PDM_VCFG_CHSET_LEFT = 1, /*!< LEFT : Mono left channel. */ + PDM_VCFG_CHSET_RIGHT = 2, /*!< RIGHT : Mono right channel. */ + PDM_VCFG_CHSET_STEREO = 3, /*!< STEREO : Stereo channels. */ +} PDM_VCFG_CHSET_Enum; + +/* ========================================================== FR =========================================================== */ +/* ========================================================== FRD ========================================================== */ +/* ========================================================= FLUSH ========================================================= */ +/* ========================================================= FTHR ========================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SUPPLYSRC ======================================================= */ +/* ===================================== PWRCTRL SUPPLYSRC SWITCH_LDO_IN_SLEEP [2..2] ====================================== */ +typedef enum { /*!< PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP */ + PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN = 1, /*!< EN : Automatically switch from CORE BUCK to CORE LDO when CPU + is in DEEP SLEEP */ +} PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_Enum; + +/* ========================================== PWRCTRL SUPPLYSRC COREBUCKEN [1..1] ========================================== */ +typedef enum { /*!< PWRCTRL_SUPPLYSRC_COREBUCKEN */ + PWRCTRL_SUPPLYSRC_COREBUCKEN_EN = 1, /*!< EN : Enable the Core Buck for the low-voltage power domain. */ +} PWRCTRL_SUPPLYSRC_COREBUCKEN_Enum; + +/* ========================================== PWRCTRL SUPPLYSRC MEMBUCKEN [0..0] =========================================== */ +typedef enum { /*!< PWRCTRL_SUPPLYSRC_MEMBUCKEN */ + PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN = 1, /*!< EN : Enable the Memory Buck as the supply for flash and SRAM. */ +} PWRCTRL_SUPPLYSRC_MEMBUCKEN_Enum; + +/* ====================================================== POWERSTATUS ====================================================== */ +/* ========================================= PWRCTRL POWERSTATUS COREBUCKON [1..1] ========================================= */ +typedef enum { /*!< PWRCTRL_POWERSTATUS_COREBUCKON */ + PWRCTRL_POWERSTATUS_COREBUCKON_LDO = 0, /*!< LDO : Indicates the the LDO is supplying the Core low-voltage. */ + PWRCTRL_POWERSTATUS_COREBUCKON_BUCK = 1, /*!< BUCK : Indicates the the Buck is supplying the Core low-voltage. */ +} PWRCTRL_POWERSTATUS_COREBUCKON_Enum; + +/* ========================================= PWRCTRL POWERSTATUS MEMBUCKON [0..0] ========================================== */ +typedef enum { /*!< PWRCTRL_POWERSTATUS_MEMBUCKON */ + PWRCTRL_POWERSTATUS_MEMBUCKON_LDO = 0, /*!< LDO : Indicates the LDO is supplying the memory power domain. */ + PWRCTRL_POWERSTATUS_MEMBUCKON_BUCK = 1, /*!< BUCK : Indicates the Buck is supplying the memory power domain. */ +} PWRCTRL_POWERSTATUS_MEMBUCKON_Enum; + +/* ======================================================= DEVICEEN ======================================================== */ +/* =========================================== PWRCTRL DEVICEEN PWRPDM [10..10] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVICEEN_PWRPDM */ + PWRCTRL_DEVICEEN_PWRPDM_EN = 1, /*!< EN : Enable PDM */ + PWRCTRL_DEVICEEN_PWRPDM_DIS = 0, /*!< DIS : Disables PDM */ +} PWRCTRL_DEVICEEN_PWRPDM_Enum; + +/* ============================================ PWRCTRL DEVICEEN PWRADC [9..9] ============================================= */ +typedef enum { /*!< PWRCTRL_DEVICEEN_PWRADC */ + PWRCTRL_DEVICEEN_PWRADC_EN = 1, /*!< EN : Enable ADC */ + PWRCTRL_DEVICEEN_PWRADC_DIS = 0, /*!< DIS : Disables ADC */ +} PWRCTRL_DEVICEEN_PWRADC_Enum; + +/* =========================================== PWRCTRL DEVICEEN PWRUART1 [8..8] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVICEEN_PWRUART1 */ + PWRCTRL_DEVICEEN_PWRUART1_EN = 1, /*!< EN : Enable UART 1 */ + PWRCTRL_DEVICEEN_PWRUART1_DIS = 0, /*!< DIS : Disables UART 1 */ +} PWRCTRL_DEVICEEN_PWRUART1_Enum; + +/* =========================================== PWRCTRL DEVICEEN PWRUART0 [7..7] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVICEEN_PWRUART0 */ + PWRCTRL_DEVICEEN_PWRUART0_EN = 1, /*!< EN : Enable UART 0 */ + PWRCTRL_DEVICEEN_PWRUART0_DIS = 0, /*!< DIS : Disables UART 0 */ +} PWRCTRL_DEVICEEN_PWRUART0_Enum; + +/* ========================================== PWRCTRL DEVICEEN IO_MASTER5 [6..6] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_MASTER5 */ + PWRCTRL_DEVICEEN_IO_MASTER5_EN = 1, /*!< EN : Enable IO MASTER 5 */ + PWRCTRL_DEVICEEN_IO_MASTER5_DIS = 0, /*!< DIS : Disables IO MASTER 5 */ +} PWRCTRL_DEVICEEN_IO_MASTER5_Enum; + +/* ========================================== PWRCTRL DEVICEEN IO_MASTER4 [5..5] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_MASTER4 */ + PWRCTRL_DEVICEEN_IO_MASTER4_EN = 1, /*!< EN : Enable IO MASTER 4 */ + PWRCTRL_DEVICEEN_IO_MASTER4_DIS = 0, /*!< DIS : Disables IO MASTER 4 */ +} PWRCTRL_DEVICEEN_IO_MASTER4_Enum; + +/* ========================================== PWRCTRL DEVICEEN IO_MASTER3 [4..4] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_MASTER3 */ + PWRCTRL_DEVICEEN_IO_MASTER3_EN = 1, /*!< EN : Enable IO MASTER 3 */ + PWRCTRL_DEVICEEN_IO_MASTER3_DIS = 0, /*!< DIS : Disables IO MASTER 3 */ +} PWRCTRL_DEVICEEN_IO_MASTER3_Enum; + +/* ========================================== PWRCTRL DEVICEEN IO_MASTER2 [3..3] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_MASTER2 */ + PWRCTRL_DEVICEEN_IO_MASTER2_EN = 1, /*!< EN : Enable IO MASTER 2 */ + PWRCTRL_DEVICEEN_IO_MASTER2_DIS = 0, /*!< DIS : Disables IO MASTER 2 */ +} PWRCTRL_DEVICEEN_IO_MASTER2_Enum; + +/* ========================================== PWRCTRL DEVICEEN IO_MASTER1 [2..2] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_MASTER1 */ + PWRCTRL_DEVICEEN_IO_MASTER1_EN = 1, /*!< EN : Enable IO MASTER 1 */ + PWRCTRL_DEVICEEN_IO_MASTER1_DIS = 0, /*!< DIS : Disables IO MASTER 1 */ +} PWRCTRL_DEVICEEN_IO_MASTER1_Enum; + +/* ========================================== PWRCTRL DEVICEEN IO_MASTER0 [1..1] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_MASTER0 */ + PWRCTRL_DEVICEEN_IO_MASTER0_EN = 1, /*!< EN : Enable IO MASTER 0 */ + PWRCTRL_DEVICEEN_IO_MASTER0_DIS = 0, /*!< DIS : Disables IO MASTER 0 */ +} PWRCTRL_DEVICEEN_IO_MASTER0_Enum; + +/* =========================================== PWRCTRL DEVICEEN IO_SLAVE [0..0] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVICEEN_IO_SLAVE */ + PWRCTRL_DEVICEEN_IO_SLAVE_EN = 1, /*!< EN : Enable IO SLAVE */ + PWRCTRL_DEVICEEN_IO_SLAVE_DIS = 0, /*!< DIS : Disables IO SLAVE */ +} PWRCTRL_DEVICEEN_IO_SLAVE_Enum; + +/* ==================================================== SRAMPWDINSLEEP ===================================================== */ +/* ===================================== PWRCTRL SRAMPWDINSLEEP CACHE_PWD_SLP [31..31] ===================================== */ +typedef enum { /*!< PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP */ + PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_EN = 1, /*!< EN : CACHE BANKS POWER DOWN in CORE SLEEP */ + PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_DIS = 0, /*!< DIS : CACHE BANKS STAYS in Retention in CORE SLEEP */ +} PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_Enum; + +/* =================================== PWRCTRL SRAMPWDINSLEEP SRAMSLEEPPOWERDOWN [0..10] =================================== */ +typedef enum { /*!< PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_NONE = 0,/*!< NONE : All banks retained */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM0 = 1,/*!< GROUP0_SRAM0 : 0KB-8KB SRAM */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM1 = 2,/*!< GROUP0_SRAM1 : 8KB-16KB SRAM */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM2 = 4,/*!< GROUP0_SRAM2 : 16KB-24KB SRAM */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM3 = 8,/*!< GROUP0_SRAM3 : 24KB-32KB SRAM */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP1 = 16,/*!< GROUP1 : 32KB-64KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP2 = 32,/*!< GROUP2 : 64KB-96KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP3 = 64,/*!< GROUP3 : 96KB-128KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP4 = 128,/*!< GROUP4 : 128KB-160KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP5 = 256,/*!< GROUP5 : 160KB-192KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP6 = 512,/*!< GROUP6 : 192KB-224KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP7 = 1024,/*!< GROUP7 : 224KB-256KB SRAMs */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM16K = 3,/*!< SRAM16K : Do not Retain lower 16KB */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM32K = 15,/*!< SRAM32K : Do not Retain lower 32KB */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM64K = 31,/*!< SRAM64K : Do not Retain lower 64KB */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM128K = 127,/*!< SRAM128K : Do not Retain lower 128KB */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER8K = 2046,/*!< ALLBUTLOWER8K : All banks but lower 8k powered down. */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER16K = 2044,/*!< ALLBUTLOWER16K : All banks but lower 16k powered down. */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER24K = 2040,/*!< ALLBUTLOWER24K : All banks but lower 24k powered down. */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER32K = 2032,/*!< ALLBUTLOWER32K : All banks but lower 32k powered down. */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER64K = 2016,/*!< ALLBUTLOWER64K : All banks but lower 64k powered down. */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER128K = 1920,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down. */ + PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALL = 2047,/*!< ALL : All banks powered down. */ +} PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_Enum; + +/* ========================================================= MEMEN ========================================================= */ +/* ============================================ PWRCTRL MEMEN CACHEB2 [31..31] ============================================= */ +typedef enum { /*!< PWRCTRL_MEMEN_CACHEB2 */ + PWRCTRL_MEMEN_CACHEB2_EN = 1, /*!< EN : Enable CACHE BANK 2 */ + PWRCTRL_MEMEN_CACHEB2_DIS = 0, /*!< DIS : Disable CACHE BANK 2 */ +} PWRCTRL_MEMEN_CACHEB2_Enum; + +/* ============================================ PWRCTRL MEMEN CACHEB0 [29..29] ============================================= */ +typedef enum { /*!< PWRCTRL_MEMEN_CACHEB0 */ + PWRCTRL_MEMEN_CACHEB0_EN = 1, /*!< EN : Enable CACHE BANK 0 */ + PWRCTRL_MEMEN_CACHEB0_DIS = 0, /*!< DIS : Disable CACHE BANK 0 */ +} PWRCTRL_MEMEN_CACHEB0_Enum; + +/* ============================================= PWRCTRL MEMEN FLASH1 [12..12] ============================================= */ +typedef enum { /*!< PWRCTRL_MEMEN_FLASH1 */ + PWRCTRL_MEMEN_FLASH1_EN = 1, /*!< EN : Enable FLASH1 */ + PWRCTRL_MEMEN_FLASH1_DIS = 0, /*!< DIS : Disables FLASH1 */ +} PWRCTRL_MEMEN_FLASH1_Enum; + +/* ============================================= PWRCTRL MEMEN FLASH0 [11..11] ============================================= */ +typedef enum { /*!< PWRCTRL_MEMEN_FLASH0 */ + PWRCTRL_MEMEN_FLASH0_EN = 1, /*!< EN : Enable FLASH 0 */ + PWRCTRL_MEMEN_FLASH0_DIS = 0, /*!< DIS : Disables FLASH 0 */ +} PWRCTRL_MEMEN_FLASH0_Enum; + +/* ============================================= PWRCTRL MEMEN SRAMEN [0..10] ============================================== */ +typedef enum { /*!< PWRCTRL_MEMEN_SRAMEN */ + PWRCTRL_MEMEN_SRAMEN_NONE = 0, /*!< NONE : All banks disabled */ + PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 = 1, /*!< GROUP0_SRAM0 : 0KB-8KB SRAM */ + PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 = 2, /*!< GROUP0_SRAM1 : 8KB-16KB SRAM */ + PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2 = 4, /*!< GROUP0_SRAM2 : 16KB-24KB SRAM */ + PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM3 = 8, /*!< GROUP0_SRAM3 : 24KB-32KB SRAM */ + PWRCTRL_MEMEN_SRAMEN_GROUP1 = 16, /*!< GROUP1 : 32KB-64KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_GROUP2 = 32, /*!< GROUP2 : 64KB-96KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_GROUP3 = 64, /*!< GROUP3 : 96KB-128KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_GROUP4 = 128, /*!< GROUP4 : 128KB-160KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_GROUP5 = 256, /*!< GROUP5 : 160KB-192KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_GROUP6 = 512, /*!< GROUP6 : 192KB-224KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_GROUP7 = 1024, /*!< GROUP7 : 224KB-256KB SRAMs */ + PWRCTRL_MEMEN_SRAMEN_SRAM16K = 3, /*!< SRAM16K : ENABLE lower 16KB */ + PWRCTRL_MEMEN_SRAMEN_SRAM32K = 15, /*!< SRAM32K : ENABLE lower 32KB */ + PWRCTRL_MEMEN_SRAMEN_SRAM64K = 31, /*!< SRAM64K : ENABLE lower 64KB */ + PWRCTRL_MEMEN_SRAMEN_SRAM128K = 127, /*!< SRAM128K : ENABLE lower 128KB */ + PWRCTRL_MEMEN_SRAMEN_SRAM256K = 2047, /*!< SRAM256K : ENABLE lower 256KB */ +} PWRCTRL_MEMEN_SRAMEN_Enum; + +/* ====================================================== PWRONSTATUS ====================================================== */ +/* ======================================================= SRAMCTRL ======================================================== */ +/* ====================================== PWRCTRL SRAMCTRL SRAM_MASTER_CLKGATE [2..2] ====================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE */ + PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN = 1, /*!< EN : Enable Master SRAM Clock Gate */ + PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_DIS = 0, /*!< DIS : Disables Master SRAM Clock Gating */ +} PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_Enum; + +/* ========================================= PWRCTRL SRAMCTRL SRAM_CLKGATE [1..1] ========================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAM_CLKGATE */ + PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN = 1, /*!< EN : Enable Individual SRAM Clock Gating */ + PWRCTRL_SRAMCTRL_SRAM_CLKGATE_DIS = 0, /*!< DIS : Disables Individual SRAM Clock Gating */ +} PWRCTRL_SRAMCTRL_SRAM_CLKGATE_Enum; + +/* ======================================= PWRCTRL SRAMCTRL SRAM_LIGHT_SLEEP [0..0] ======================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP */ + PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_EN = 1, /*!< EN : Enable LIGHT SLEEP for SRAMs */ + PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS = 0, /*!< DIS : Disables LIGHT SLEEP for SRAMs */ +} PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_Enum; + +/* ======================================================= ADCSTATUS ======================================================= */ +/* ======================================================== MISCOPT ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ========================================================= SWPOI ========================================================= */ +/* ============================================= RSTGEN SWPOI SWPOIKEY [0..7] ============================================== */ +typedef enum { /*!< RSTGEN_SWPOI_SWPOIKEY */ + RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27, /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset. */ +} RSTGEN_SWPOI_SWPOIKEY_Enum; + +/* ========================================================= SWPOR ========================================================= */ +/* ============================================= RSTGEN SWPOR SWPORKEY [0..7] ============================================== */ +typedef enum { /*!< RSTGEN_SWPOR_SWPORKEY */ + RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212, /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset. */ +} RSTGEN_SWPOR_SWPORKEY_Enum; + +/* ========================================================= STAT ========================================================== */ +/* ======================================================== CLRSTAT ======================================================== */ +/* ======================================================= TPIU_RST ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLOW ========================================================= */ +/* ========================================================= CTRUP ========================================================= */ +/* =============================================== RTC CTRUP CTERR [31..31] ================================================ */ +typedef enum { /*!< RTC_CTRUP_CTERR */ + RTC_CTRUP_CTERR_NOERR = 0, /*!< NOERR : No read error occurred */ + RTC_CTRUP_CTERR_RDERR = 1, /*!< RDERR : Read error occurred */ +} RTC_CTRUP_CTERR_Enum; + +/* ================================================ RTC CTRUP CEB [28..28] ================================================= */ +typedef enum { /*!< RTC_CTRUP_CEB */ + RTC_CTRUP_CEB_DIS = 0, /*!< DIS : Disable the Century bit from changing */ + RTC_CTRUP_CEB_EN = 1, /*!< EN : Enable the Century bit to change */ +} RTC_CTRUP_CEB_Enum; + +/* ================================================= RTC CTRUP CB [27..27] ================================================= */ +typedef enum { /*!< RTC_CTRUP_CB */ + RTC_CTRUP_CB_2000 = 0, /*!< 2000 : Century is 2000s */ + RTC_CTRUP_CB_1900_2100 = 1, /*!< 1900_2100 : Century is 1900s/2100s */ +} RTC_CTRUP_CB_Enum; + +/* ======================================================== ALMLOW ========================================================= */ +/* ========================================================= ALMUP ========================================================= */ +/* ======================================================== RTCCTL ========================================================= */ +/* =============================================== RTC RTCCTL HR1224 [5..5] ================================================ */ +typedef enum { /*!< RTC_RTCCTL_HR1224 */ + RTC_RTCCTL_HR1224_24HR = 0, /*!< 24HR : Hours in 24 hour mode */ + RTC_RTCCTL_HR1224_12HR = 1, /*!< 12HR : Hours in 12 hour mode */ +} RTC_RTCCTL_HR1224_Enum; + +/* ================================================ RTC RTCCTL RSTOP [4..4] ================================================ */ +typedef enum { /*!< RTC_RTCCTL_RSTOP */ + RTC_RTCCTL_RSTOP_RUN = 0, /*!< RUN : Allow the RTC input clock to run */ + RTC_RTCCTL_RSTOP_STOP = 1, /*!< STOP : Stop the RTC input clock */ +} RTC_RTCCTL_RSTOP_Enum; + +/* ================================================= RTC RTCCTL RPT [1..3] ================================================= */ +typedef enum { /*!< RTC_RTCCTL_RPT */ + RTC_RTCCTL_RPT_DIS = 0, /*!< DIS : Alarm interrupt disabled */ + RTC_RTCCTL_RPT_YEAR = 1, /*!< YEAR : Interrupt every year */ + RTC_RTCCTL_RPT_MONTH = 2, /*!< MONTH : Interrupt every month */ + RTC_RTCCTL_RPT_WEEK = 3, /*!< WEEK : Interrupt every week */ + RTC_RTCCTL_RPT_DAY = 4, /*!< DAY : Interrupt every day */ + RTC_RTCCTL_RPT_HR = 5, /*!< HR : Interrupt every hour */ + RTC_RTCCTL_RPT_MIN = 6, /*!< MIN : Interrupt every minute */ + RTC_RTCCTL_RPT_SEC = 7, /*!< SEC : Interrupt every second/10th/100th */ +} RTC_RTCCTL_RPT_Enum; + +/* ================================================ RTC RTCCTL WRTC [0..0] ================================================= */ +typedef enum { /*!< RTC_RTCCTL_WRTC */ + RTC_RTCCTL_WRTC_DIS = 0, /*!< DIS : Counter writes are disabled */ + RTC_RTCCTL_WRTC_EN = 1, /*!< EN : Counter writes are enabled */ +} RTC_RTCCTL_WRTC_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DR =========================================================== */ +/* =============================================== UART0 DR OEDATA [11..11] ================================================ */ +typedef enum { /*!< UART0_DR_OEDATA */ + UART0_DR_OEDATA_NOERR = 0, /*!< NOERR : No error on UART OEDATA, overrun error indicator. */ + UART0_DR_OEDATA_ERR = 1, /*!< ERR : Error on UART OEDATA, overrun error indicator. */ +} UART0_DR_OEDATA_Enum; + +/* =============================================== UART0 DR BEDATA [10..10] ================================================ */ +typedef enum { /*!< UART0_DR_BEDATA */ + UART0_DR_BEDATA_NOERR = 0, /*!< NOERR : No error on UART BEDATA, break error indicator. */ + UART0_DR_BEDATA_ERR = 1, /*!< ERR : Error on UART BEDATA, break error indicator. */ +} UART0_DR_BEDATA_Enum; + +/* ================================================ UART0 DR PEDATA [9..9] ================================================= */ +typedef enum { /*!< UART0_DR_PEDATA */ + UART0_DR_PEDATA_NOERR = 0, /*!< NOERR : No error on UART PEDATA, parity error indicator. */ + UART0_DR_PEDATA_ERR = 1, /*!< ERR : Error on UART PEDATA, parity error indicator. */ +} UART0_DR_PEDATA_Enum; + +/* ================================================ UART0 DR FEDATA [8..8] ================================================= */ +typedef enum { /*!< UART0_DR_FEDATA */ + UART0_DR_FEDATA_NOERR = 0, /*!< NOERR : No error on UART FEDATA, framing error indicator. */ + UART0_DR_FEDATA_ERR = 1, /*!< ERR : Error on UART FEDATA, framing error indicator. */ +} UART0_DR_FEDATA_Enum; + +/* ========================================================== RSR ========================================================== */ +/* ================================================ UART0 RSR OESTAT [3..3] ================================================ */ +typedef enum { /*!< UART0_RSR_OESTAT */ + UART0_RSR_OESTAT_NOERR = 0, /*!< NOERR : No error on UART OESTAT, overrun error indicator. */ + UART0_RSR_OESTAT_ERR = 1, /*!< ERR : Error on UART OESTAT, overrun error indicator. */ +} UART0_RSR_OESTAT_Enum; + +/* ================================================ UART0 RSR BESTAT [2..2] ================================================ */ +typedef enum { /*!< UART0_RSR_BESTAT */ + UART0_RSR_BESTAT_NOERR = 0, /*!< NOERR : No error on UART BESTAT, break error indicator. */ + UART0_RSR_BESTAT_ERR = 1, /*!< ERR : Error on UART BESTAT, break error indicator. */ +} UART0_RSR_BESTAT_Enum; + +/* ================================================ UART0 RSR PESTAT [1..1] ================================================ */ +typedef enum { /*!< UART0_RSR_PESTAT */ + UART0_RSR_PESTAT_NOERR = 0, /*!< NOERR : No error on UART PESTAT, parity error indicator. */ + UART0_RSR_PESTAT_ERR = 1, /*!< ERR : Error on UART PESTAT, parity error indicator. */ +} UART0_RSR_PESTAT_Enum; + +/* ================================================ UART0 RSR FESTAT [0..0] ================================================ */ +typedef enum { /*!< UART0_RSR_FESTAT */ + UART0_RSR_FESTAT_NOERR = 0, /*!< NOERR : No error on UART FESTAT, framing error indicator. */ + UART0_RSR_FESTAT_ERR = 1, /*!< ERR : Error on UART FESTAT, framing error indicator. */ +} UART0_RSR_FESTAT_Enum; + +/* ========================================================== FR =========================================================== */ +/* ================================================= UART0 FR TXFE [7..7] ================================================== */ +typedef enum { /*!< UART0_FR_TXFE */ + UART0_FR_TXFE_XMTFIFO_EMPTY = 1, /*!< XMTFIFO_EMPTY : Transmit fifo is empty. */ +} UART0_FR_TXFE_Enum; + +/* ================================================= UART0 FR RXFF [6..6] ================================================== */ +typedef enum { /*!< UART0_FR_RXFF */ + UART0_FR_RXFF_RCVFIFO_FULL = 1, /*!< RCVFIFO_FULL : Receive fifo is full. */ +} UART0_FR_RXFF_Enum; + +/* ================================================= UART0 FR TXFF [5..5] ================================================== */ +typedef enum { /*!< UART0_FR_TXFF */ + UART0_FR_TXFF_XMTFIFO_FULL = 1, /*!< XMTFIFO_FULL : Transmit fifo is full. */ +} UART0_FR_TXFF_Enum; + +/* ================================================= UART0 FR RXFE [4..4] ================================================== */ +typedef enum { /*!< UART0_FR_RXFE */ + UART0_FR_RXFE_RCVFIFO_EMPTY = 1, /*!< RCVFIFO_EMPTY : Receive fifo is empty. */ +} UART0_FR_RXFE_Enum; + +/* ================================================= UART0 FR BUSY [3..3] ================================================== */ +typedef enum { /*!< UART0_FR_BUSY */ + UART0_FR_BUSY_BUSY = 1, /*!< BUSY : UART busy indicator. */ +} UART0_FR_BUSY_Enum; + +/* ================================================== UART0 FR DCD [2..2] ================================================== */ +typedef enum { /*!< UART0_FR_DCD */ + UART0_FR_DCD_DETECTED = 1, /*!< DETECTED : Data carrier detect detected. */ +} UART0_FR_DCD_Enum; + +/* ================================================== UART0 FR DSR [1..1] ================================================== */ +typedef enum { /*!< UART0_FR_DSR */ + UART0_FR_DSR_READY = 1, /*!< READY : Data set ready. */ +} UART0_FR_DSR_Enum; + +/* ================================================== UART0 FR CTS [0..0] ================================================== */ +typedef enum { /*!< UART0_FR_CTS */ + UART0_FR_CTS_CLEARTOSEND = 1, /*!< CLEARTOSEND : Clear to send is indicated. */ +} UART0_FR_CTS_Enum; + +/* ========================================================= ILPR ========================================================== */ +/* ========================================================= IBRD ========================================================== */ +/* ========================================================= FBRD ========================================================== */ +/* ========================================================= LCRH ========================================================== */ +/* ========================================================== CR =========================================================== */ +/* ================================================ UART0 CR CLKSEL [4..6] ================================================= */ +typedef enum { /*!< UART0_CR_CLKSEL */ + UART0_CR_CLKSEL_NOCLK = 0, /*!< NOCLK : No UART clock. This is the low power default. */ + UART0_CR_CLKSEL_24MHZ = 1, /*!< 24MHZ : 24 MHz clock. */ + UART0_CR_CLKSEL_12MHZ = 2, /*!< 12MHZ : 12 MHz clock. */ + UART0_CR_CLKSEL_6MHZ = 3, /*!< 6MHZ : 6 MHz clock. */ + UART0_CR_CLKSEL_3MHZ = 4, /*!< 3MHZ : 3 MHz clock. */ +} UART0_CR_CLKSEL_Enum; + +/* ========================================================= IFLS ========================================================== */ +/* ========================================================== IER ========================================================== */ +/* ========================================================== IES ========================================================== */ +/* ========================================================== MIS ========================================================== */ +/* ========================================================== IEC ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* =============================================== VCOMP CFG LVLSEL [16..19] =============================================== */ +typedef enum { /*!< VCOMP_CFG_LVLSEL */ + VCOMP_CFG_LVLSEL_0P58V = 0, /*!< 0P58V : Set Reference input to 0.58 Volts. */ + VCOMP_CFG_LVLSEL_0P77V = 1, /*!< 0P77V : Set Reference input to 0.77 Volts. */ + VCOMP_CFG_LVLSEL_0P97V = 2, /*!< 0P97V : Set Reference input to 0.97 Volts. */ + VCOMP_CFG_LVLSEL_1P16V = 3, /*!< 1P16V : Set Reference input to 1.16 Volts. */ + VCOMP_CFG_LVLSEL_1P35V = 4, /*!< 1P35V : Set Reference input to 1.35 Volts. */ + VCOMP_CFG_LVLSEL_1P55V = 5, /*!< 1P55V : Set Reference input to 1.55 Volts. */ + VCOMP_CFG_LVLSEL_1P74V = 6, /*!< 1P74V : Set Reference input to 1.74 Volts. */ + VCOMP_CFG_LVLSEL_1P93V = 7, /*!< 1P93V : Set Reference input to 1.93 Volts. */ + VCOMP_CFG_LVLSEL_2P13V = 8, /*!< 2P13V : Set Reference input to 2.13 Volts. */ + VCOMP_CFG_LVLSEL_2P32V = 9, /*!< 2P32V : Set Reference input to 2.32 Volts. */ + VCOMP_CFG_LVLSEL_2P51V = 10, /*!< 2P51V : Set Reference input to 2.51 Volts. */ + VCOMP_CFG_LVLSEL_2P71V = 11, /*!< 2P71V : Set Reference input to 2.71 Volts. */ + VCOMP_CFG_LVLSEL_2P90V = 12, /*!< 2P90V : Set Reference input to 2.90 Volts. */ + VCOMP_CFG_LVLSEL_3P09V = 13, /*!< 3P09V : Set Reference input to 3.09 Volts. */ + VCOMP_CFG_LVLSEL_3P29V = 14, /*!< 3P29V : Set Reference input to 3.29 Volts. */ + VCOMP_CFG_LVLSEL_3P48V = 15, /*!< 3P48V : Set Reference input to 3.48 Volts. */ +} VCOMP_CFG_LVLSEL_Enum; + +/* ================================================= VCOMP CFG NSEL [8..9] ================================================= */ +typedef enum { /*!< VCOMP_CFG_NSEL */ + VCOMP_CFG_NSEL_VREFEXT1 = 0, /*!< VREFEXT1 : Use external reference 1 for reference input. */ + VCOMP_CFG_NSEL_VREFEXT2 = 1, /*!< VREFEXT2 : Use external reference 2 for reference input. */ + VCOMP_CFG_NSEL_VREFEXT3 = 2, /*!< VREFEXT3 : Use external reference 3 for reference input. */ + VCOMP_CFG_NSEL_DAC = 3, /*!< DAC : Use DAC output selected by LVLSEL for reference input. */ +} VCOMP_CFG_NSEL_Enum; + +/* ================================================= VCOMP CFG PSEL [0..1] ================================================= */ +typedef enum { /*!< VCOMP_CFG_PSEL */ + VCOMP_CFG_PSEL_VDDADJ = 0, /*!< VDDADJ : Use VDDADJ for the positive input. */ + VCOMP_CFG_PSEL_VTEMP = 1, /*!< VTEMP : Use the temperature sensor output for the positive input. + Note: If this channel is selected for PSEL, the bandap + circuit required for temperature comparisons will automatically + turn on. The bandgap circuit requires 11us to stabalize. */ + VCOMP_CFG_PSEL_VEXT1 = 2, /*!< VEXT1 : Use external voltage 0 for positive input. */ + VCOMP_CFG_PSEL_VEXT2 = 3, /*!< VEXT2 : Use external voltage 1 for positive input. */ +} VCOMP_CFG_PSEL_Enum; + +/* ========================================================= STAT ========================================================== */ +/* =============================================== VCOMP STAT PWDSTAT [1..1] =============================================== */ +typedef enum { /*!< VCOMP_STAT_PWDSTAT */ + VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : The voltage comparator is powered down. */ +} VCOMP_STAT_PWDSTAT_Enum; + +/* =============================================== VCOMP STAT CMPOUT [0..0] ================================================ */ +typedef enum { /*!< VCOMP_STAT_CMPOUT */ + VCOMP_STAT_CMPOUT_VOUT_LOW = 0, /*!< VOUT_LOW : The negative input of the comparator is greater than + the positive input. */ + VCOMP_STAT_CMPOUT_VOUT_HIGH = 1, /*!< VOUT_HIGH : The positive input of the comparator is greater + than the negative input. */ +} VCOMP_STAT_CMPOUT_Enum; + +/* ======================================================== PWDKEY ========================================================= */ +/* ============================================== VCOMP PWDKEY PWDKEY [0..31] ============================================== */ +typedef enum { /*!< VCOMP_PWDKEY_PWDKEY */ + VCOMP_PWDKEY_PWDKEY_Key = 55, /*!< Key : Key */ +} VCOMP_PWDKEY_PWDKEY_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ================================================ WDT CFG CLKSEL [24..26] ================================================ */ +typedef enum { /*!< WDT_CFG_CLKSEL */ + WDT_CFG_CLKSEL_OFF = 0, /*!< OFF : Low Power Mode. */ + WDT_CFG_CLKSEL_128HZ = 1, /*!< 128HZ : 128 Hz LFRC clock. */ + WDT_CFG_CLKSEL_16HZ = 2, /*!< 16HZ : 16 Hz LFRC clock. */ + WDT_CFG_CLKSEL_1HZ = 3, /*!< 1HZ : 1 Hz LFRC clock. */ + WDT_CFG_CLKSEL_1_16HZ = 4, /*!< 1_16HZ : 1/16th Hz LFRC clock. */ +} WDT_CFG_CLKSEL_Enum; + +/* ========================================================= RSTRT ========================================================= */ +/* ================================================ WDT RSTRT RSTRT [0..7] ================================================= */ +typedef enum { /*!< WDT_RSTRT_RSTRT */ + WDT_RSTRT_RSTRT_KEYVALUE = 178, /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart + the WDT. */ +} WDT_RSTRT_RSTRT_Enum; + +/* ========================================================= LOCK ========================================================== */ +/* ================================================= WDT LOCK LOCK [0..7] ================================================== */ +typedef enum { /*!< WDT_LOCK_LOCK */ + WDT_LOCK_LOCK_KEYVALUE = 58, /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock + the WDT. */ +} WDT_LOCK_LOCK_Enum; + +/* ========================================================= COUNT ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + +/** @} */ /* End of group EnumValue_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* APOLLO2_H */ + + +/** @} */ /* End of group apollo2 */ + +/** @} */ /* End of group Ambiq Micro */ diff --git a/CMSIS/AmbiqMicro/Include/system_apollo2.h b/CMSIS/AmbiqMicro/Include/system_apollo2.h new file mode 100644 index 0000000..2b6d529 --- /dev/null +++ b/CMSIS/AmbiqMicro/Include/system_apollo2.h @@ -0,0 +1,66 @@ +//***************************************************************************** +// +//! @file system_apollo2.h +//! +//! @brief Ambiq Micro Apollo2 MCU specific functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef SYSTEM_APOLLO2_H +#define SYSTEM_APOLLO2_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void SystemInit (void); +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif // SYSTEM_APOLLO2_H + diff --git a/README.rst b/README.rst index 40eaa5c..9d9b109 100644 --- a/README.rst +++ b/README.rst @@ -30,6 +30,8 @@ Status +------------------------+--------------------------------+ | SOC | AmbiqSuite SDK Revision | +========================+================================+ +| Apollo2 | v2.5.1 | ++------------------------+--------------------------------+ | Apollo3 Blue | v3.1.1 | +------------------------+--------------------------------+ | Apollo3 Blue Plus | v3.1.1 | diff --git a/docs/apollo2/index.html b/docs/apollo2/index.html new file mode 100644 index 0000000..bd8745f --- /dev/null +++ b/docs/apollo2/index.html @@ -0,0 +1,95 @@ + + + + + + +AmbiqSuite User Guide: AmbiqSuite Apollo2 Device Register Overview + + + + + + + +
+
+ + + + + + + +
+
Apollo2 Register Documentation +
+
+
+ + + + +
+ + +
+
+
Select a Peripheral to View its Register Documentation.
+
+ +
+ +
+
+ + + + + +
 ARM Peripherals    +
 ITMIntegrated Trace Module
 TPIUTrace Port Interface Unit
 NVICNested Vectored Interrupt Controller
 SYSCTRLSystem Control
 SYSTICKSystem Timer
+
+
+ +
+ +
+
+ + + + + + + + + + + + + + + + +
 Apollo2 Peripherals + +
 ADCAnalog Digital Converter Control
 CACHECTRLCache Control
 CLKGENClock Generator
 CTIMERCounter/Timer
 GPIOGeneral Purpose IO
 IOMSTRSPI/I2C I/O Master
 IOSLAVESPI/I2C I/O Slave
 MCUCTRLMCU Miscellaneous Control Logic
 PDMPulse Density Modulation Input (DMEMS Microphone)
 PWRCTRLPower Control
 RSTGENMCU Reset Generator
 RTCReal Time Clock
 UARTSerial UART
 VCOMPVoltage Comparator
 WDTWatchdog Timer
+
+
+ +
+ + + + diff --git a/docs/apollo2/pages/adc_regs.html b/docs/apollo2/pages/adc_regs.html new file mode 100644 index 0000000..2885585 --- /dev/null +++ b/docs/apollo2/pages/adc_regs.html @@ -0,0 +1,3695 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
ADC - Analog Digital Converter Control
+
+
+ + +
+
+
+

ADC Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CFG - Configuration Register +
+   + 0x00000004: + +   + STAT - ADC Power Status +
+   + 0x00000008: + +   + SWT - Software trigger +
+   + 0x0000000C: + +   + SL0CFG - Slot 0 Configuration Register +
+   + 0x00000010: + +   + SL1CFG - Slot 1 Configuration Register +
+   + 0x00000014: + +   + SL2CFG - Slot 2 Configuration Register +
+   + 0x00000018: + +   + SL3CFG - Slot 3 Configuration Register +
+   + 0x0000001C: + +   + SL4CFG - Slot 4 Configuration Register +
+   + 0x00000020: + +   + SL5CFG - Slot 5 Configuration Register +
+   + 0x00000024: + +   + SL6CFG - Slot 6 Configuration Register +
+   + 0x00000028: + +   + SL7CFG - Slot 7 Configuration Register +
+   + 0x0000002C: + +   + WULIM - Window Comparator Upper Limits Register +
+   + 0x00000030: + +   + WLLIM - Window Comparator Lower Limits Register +
+   + 0x00000038: + +   + FIFO - FIFO Data and Valid Count Register +
+   + 0x00000200: + +   + INTEN - ADC Interrupt registers: Enable +
+   + 0x00000204: + +   + INTSTAT - ADC Interrupt registers: Status +
+   + 0x00000208: + +   + INTCLR - ADC Interrupt registers: Clear +
+   + 0x0000020C: + +   + INTSET - ADC Interrupt registers: Set +
+
+
+ +
+
+

CFG - Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010000 +
+

Description:

+

The ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions, the trigger polarity, the trigger select, the reference voltage select, the low power mode, the operating mode (single scan per trigger vs. repeating mode) and ADC enable.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CLKSEL +
0x0		RSVD +
0x0		TRIGPOL +
0x0		TRIGSEL +
0x0		RSVD +
0x0		REFSEL +
0x0		RSVD +
0x0		CKMODE +
0x0		LPMODE +
0x0		RPTEN +
0x0		RSVD +
0x0		ADCEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:26RSVDRORESERVED.

+
25:24CLKSELRWSelect the source and frequency for the ADC clock. All values not enumerated below are undefined.

+ OFF = 0x0 - Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing.
+ HFRC = 0x1 - HFRC Core Clock Frequency
+ HFRC_DIV2 = 0x2 - HFRC Core Clock / 2
23:20RSVDRORESERVED.

+
19TRIGPOLRWThis bit selects the ADC trigger polarity for external off chip triggers.

+ RISING_EDGE = 0x0 - Trigger on rising edge.
+ FALLING_EDGE = 0x1 - Trigger on falling edge.
18:16TRIGSELRWSelect the ADC trigger source.

+ EXT0 = 0x0 - Off chip External Trigger0 (ADC_ET0)
+ EXT1 = 0x1 - Off chip External Trigger1 (ADC_ET1)
+ EXT2 = 0x2 - Off chip External Trigger2 (ADC_ET2)
+ EXT3 = 0x3 - Off chip External Trigger3 (ADC_ET3)
+ VCOMP = 0x4 - Voltage Comparator Output
+ SWT = 0x7 - Software Trigger
15:10RSVDRORESERVED.

+
9:8REFSELRWSelect the ADC reference voltage.

+ INT2P0 = 0x0 - Internal 2.0V Bandgap Reference Voltage
+ INT1P5 = 0x1 - Internal 1.5V Bandgap Reference Voltage
+ EXT2P0 = 0x2 - Off Chip 2.0V Reference
+ EXT1P5 = 0x3 - Off Chip 1.5V Reference
7:5RSVDRORESERVED.

+
4CKMODERWClock mode register

+ LPCKMODE = 0x0 - Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC.
+ LLCKMODE = 0x1 - Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0.
3LPMODERWSelect power mode to enter between active scans.

+ MODE0 = 0x0 - Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection.
+ MODE1 = 0x1 - Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode.
2RPTENRWThis bit enables Repeating Scan Mode.

+ SINGLE_SCAN = 0x0 - In Single Scan Mode, the ADC will complete a single scan upon each trigger event.
+ REPEATING_SCAN = 0x1 - In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared.
1RSVDRORESERVED.

+
0ADCENRWThis bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.

+ DIS = 0x0 - Disable the ADC module.
+ EN = 0x1 - Enable the ADC module.
+
+
+
+ +
+
+

STAT - ADC Power Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010004 +
+

Description:

+

This register indicates the basic power status for the ADC. For detailed power status, see the power control power status register. ADC power mode 0 indicates the ADC is in it's full power state and is ready to process scans. ADC Power mode 1 indicates the ADC enabled and in a low power state.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PWDSTAT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0PWDSTATROIndicates the power-status of the ADC.

+ ON = 0x0 - Powered on.
+ POWERED_DOWN = 0x1 - ADC Low Power Mode 1.
+
+
+
+ +
+
+

SWT - Software trigger

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010008 +
+

Description:

+

This register enables initiating an ADC scan through software.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SWT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED.

+
7:0SWTRWWriting 0x37 to this register generates a software trigger.

+ GEN_SW_TRIGGER = 0x37 - Writing this value generates a software trigger.
+
+
+
+ +
+
+

SL0CFG - Slot 0 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5001000C +
+

Description:

+

Slot 0 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL0 +
0x0		RSVD +
0x0		PRMODE0 +
0x0		RSVD +
0x0		CHSEL0 +
0x0		RSVD +
0x0		WCEN0 +
0x0		SLEN0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL0RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE0RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL0RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN0RWThis bit enables the window compare function for slot 0.

+ WCEN = 0x1 - Enable the window compare for slot 0.
0SLEN0RWThis bit enables slot 0 for ADC conversions.

+ SLEN = 0x1 - Enable slot 0 for ADC conversions.
+
+
+
+ +
+
+

SL1CFG - Slot 1 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010010 +
+

Description:

+

Slot 1 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL1 +
0x0		RSVD +
0x0		PRMODE1 +
0x0		RSVD +
0x0		CHSEL1 +
0x0		RSVD +
0x0		WCEN1 +
0x0		SLEN1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL1RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE1RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL1RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN1RWThis bit enables the window compare function for slot 1.

+ WCEN = 0x1 - Enable the window compare for slot 1.
0SLEN1RWThis bit enables slot 1 for ADC conversions.

+ SLEN = 0x1 - Enable slot 1 for ADC conversions.
+
+
+
+ +
+
+

SL2CFG - Slot 2 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010014 +
+

Description:

+

Slot 2 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL2 +
0x0		RSVD +
0x0		PRMODE2 +
0x0		RSVD +
0x0		CHSEL2 +
0x0		RSVD +
0x0		WCEN2 +
0x0		SLEN2 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL2RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE2RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL2RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN2RWThis bit enables the window compare function for slot 2.

+ WCEN = 0x1 - Enable the window compare for slot 2.
0SLEN2RWThis bit enables slot 2 for ADC conversions.

+ SLEN = 0x1 - Enable slot 2 for ADC conversions.
+
+
+
+ +
+
+

SL3CFG - Slot 3 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010018 +
+

Description:

+

Slot 3 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL3 +
0x0		RSVD +
0x0		PRMODE3 +
0x0		RSVD +
0x0		CHSEL3 +
0x0		RSVD +
0x0		WCEN3 +
0x0		SLEN3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL3RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE3RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL3RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN3RWThis bit enables the window compare function for slot 3.

+ WCEN = 0x1 - Enable the window compare for slot 3.
0SLEN3RWThis bit enables slot 3 for ADC conversions.

+ SLEN = 0x1 - Enable slot 3 for ADC conversions.
+
+
+
+ +
+
+

SL4CFG - Slot 4 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5001001C +
+

Description:

+

Slot 4 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL4 +
0x0		RSVD +
0x0		PRMODE4 +
0x0		RSVD +
0x0		CHSEL4 +
0x0		RSVD +
0x0		WCEN4 +
0x0		SLEN4 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL4RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE4RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL4RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN4RWThis bit enables the window compare function for slot 4.

+ WCEN = 0x1 - Enable the window compare for slot 4.
0SLEN4RWThis bit enables slot 4 for ADC conversions.

+ SLEN = 0x1 - Enable slot 4 for ADC conversions.
+
+
+
+ +
+
+

SL5CFG - Slot 5 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010020 +
+

Description:

+

Slot 5 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL5 +
0x0		RSVD +
0x0		PRMODE5 +
0x0		RSVD +
0x0		CHSEL5 +
0x0		RSVD +
0x0		WCEN5 +
0x0		SLEN5 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL5RWSelect number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE5RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL5RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN5RWThis bit enables the window compare function for slot 5.

+ WCEN = 0x1 - Enable the window compare for slot 5.
0SLEN5RWThis bit enables slot 5 for ADC conversions.

+ SLEN = 0x1 - Enable slot 5 for ADC conversions.
+
+
+
+ +
+
+

SL6CFG - Slot 6 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010024 +
+

Description:

+

Slot 6 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL6 +
0x0		RSVD +
0x0		PRMODE6 +
0x0		RSVD +
0x0		CHSEL6 +
0x0		RSVD +
0x0		WCEN6 +
0x0		SLEN6 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL6RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE6RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL6RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN6RWThis bit enables the window compare function for slot 6.

+ WCEN = 0x1 - Enable the window compare for slot 6.
0SLEN6RWThis bit enables slot 6 for ADC conversions.

+ SLEN = 0x1 - Enable slot 6 for ADC conversions.
+
+
+
+ +
+
+

SL7CFG - Slot 7 Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010028 +
+

Description:

+

Slot 7 Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADSEL7 +
0x0		RSVD +
0x0		PRMODE7 +
0x0		RSVD +
0x0		CHSEL7 +
0x0		RSVD +
0x0		WCEN7 +
0x0		SLEN7 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26:24ADSEL7RWSelect the number of measurements to average in the accumulate divide module for this slot.

+ AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
+ AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
+ AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
+ AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
+ AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
+ AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
+ AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
+ AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18RSVDRORESERVED.

+
17:16PRMODE7RWSet the Precision Mode For Slot.

+ P14B = 0x0 - 14-bit precision mode
+ P12B = 0x1 - 12-bit precision mode
+ P10B = 0x2 - 10-bit precision mode
+ P8B = 0x3 - 8-bit precision mode
15:12RSVDRORESERVED.

+
11:8CHSEL7RWSelect one of the 14 channel inputs for this slot.

+ SE0 = 0x0 - single ended external GPIO connection to pad16.
+ SE1 = 0x1 - single ended external GPIO connection to pad29.
+ SE2 = 0x2 - single ended external GPIO connection to pad11.
+ SE3 = 0x3 - single ended external GPIO connection to pad31.
+ SE4 = 0x4 - single ended external GPIO connection to pad32.
+ SE5 = 0x5 - single ended external GPIO connection to pad33.
+ SE6 = 0x6 - single ended external GPIO connection to pad34.
+ SE7 = 0x7 - single ended external GPIO connection to pad35.
+ SE8 = 0x8 - single ended external GPIO connection to pad13.
+ SE9 = 0x9 - single ended external GPIO connection to pad12.
+ DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
+ DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
+ TEMP = 0xC - internal temperature sensor.
+ BATT = 0xD - internal voltage divide-by-3 connection.
+ VSS = 0xE - Input VSS
7:2RSVDRORESERVED.

+
1WCEN7RWThis bit enables the window compare function for slot 7.

+ WCEN = 0x1 - Enable the window compare for slot 7.
0SLEN7RWThis bit enables slot 7 for ADC conversions.

+ SLEN = 0x1 - Enable slot 7 for ADC conversions.
+
+
+
+ +
+
+

WULIM - Window Comparator Upper Limits Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5001002C +
+

Description:

+

Window Comparator Upper Limits Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ULIM +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDRORESERVED.

+
19:0ULIMRWSets the upper limit for the wondow comparator.

+
+
+
+
+ +
+
+

WLLIM - Window Comparator Lower Limits Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010030 +
+

Description:

+

Window Comparator Lower Limits Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		LLIM +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDRORESERVED.

+
19:0LLIMRWSets the lower limit for the wondow comparator.

+
+
+
+
+ +
+
+

FIFO - FIFO Data and Valid Count Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010038 +
+

Description:

+

The ADC FIFO Register contains the slot number and fifo data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO and decrease the COUNT by 1 if the COUNT is greater than zero.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SLOTNUM +
0x0		COUNT +
0x0		DATA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31RSVDRORESERVED.

+
30:28SLOTNUMROSlot number associated with this FIFO data.

+
27:20COUNTRONumber of valid entries in the ADC FIFO.

+
19:0DATAROOldest data in the FIFO.

+
+
+
+
+ +
+
+

INTEN - ADC Interrupt registers: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WCINC +
0x0		WCEXC +
0x0		FIFOOVR2 +
0x0		FIFOOVR1 +
0x0		SCNCMP +
0x0		CNVCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED.

+
5WCINCRWWindow comparator voltage incursion interrupt.

+ WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4WCEXCRWWindow comparator voltage excursion interrupt.

+ WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3FIFOOVR2RWFIFO 100 percent full interrupt.

+ FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2FIFOOVR1RWFIFO 75 percent full interrupt.

+ FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1SCNCMPRWADC scan complete interrupt.

+ SCNCMPINT = 0x1 - ADC scan complete interrupt.
0CNVCMPRWADC conversion complete interrupt.

+ CNVCMPINT = 0x1 - ADC conversion complete interrupt.
+
+
+
+ +
+
+

INTSTAT - ADC Interrupt registers: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WCINC +
0x0		WCEXC +
0x0		FIFOOVR2 +
0x0		FIFOOVR1 +
0x0		SCNCMP +
0x0		CNVCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED.

+
5WCINCRWWindow comparator voltage incursion interrupt.

+ WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4WCEXCRWWindow comparator voltage excursion interrupt.

+ WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3FIFOOVR2RWFIFO 100 percent full interrupt.

+ FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2FIFOOVR1RWFIFO 75 percent full interrupt.

+ FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1SCNCMPRWADC scan complete interrupt.

+ SCNCMPINT = 0x1 - ADC scan complete interrupt.
0CNVCMPRWADC conversion complete interrupt.

+ CNVCMPINT = 0x1 - ADC conversion complete interrupt.
+
+
+
+ +
+
+

INTCLR - ADC Interrupt registers: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50010208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WCINC +
0x0		WCEXC +
0x0		FIFOOVR2 +
0x0		FIFOOVR1 +
0x0		SCNCMP +
0x0		CNVCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED.

+
5WCINCRWWindow comparator voltage incursion interrupt.

+ WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4WCEXCRWWindow comparator voltage excursion interrupt.

+ WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3FIFOOVR2RWFIFO 100 percent full interrupt.

+ FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2FIFOOVR1RWFIFO 75 percent full interrupt.

+ FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1SCNCMPRWADC scan complete interrupt.

+ SCNCMPINT = 0x1 - ADC scan complete interrupt.
0CNVCMPRWADC conversion complete interrupt.

+ CNVCMPINT = 0x1 - ADC conversion complete interrupt.
+
+
+
+ +
+
+

INTSET - ADC Interrupt registers: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5001020C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WCINC +
0x0		WCEXC +
0x0		FIFOOVR2 +
0x0		FIFOOVR1 +
0x0		SCNCMP +
0x0		CNVCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED.

+
5WCINCRWWindow comparator voltage incursion interrupt.

+ WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4WCEXCRWWindow comparator voltage excursion interrupt.

+ WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3FIFOOVR2RWFIFO 100 percent full interrupt.

+ FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2FIFOOVR1RWFIFO 75 percent full interrupt.

+ FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1SCNCMPRWADC scan complete interrupt.

+ SCNCMPINT = 0x1 - ADC scan complete interrupt.
0CNVCMPRWADC conversion complete interrupt.

+ CNVCMPINT = 0x1 - ADC conversion complete interrupt.
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/cachectrl_regs.html b/docs/apollo2/pages/cachectrl_regs.html new file mode 100644 index 0000000..5fde4e3 --- /dev/null +++ b/docs/apollo2/pages/cachectrl_regs.html @@ -0,0 +1,2513 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
CACHECTRL - Flash Cache Controller
+
+
+ + +
+
+
+

CACHECTRL Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CACHECFG - Flash Cache Control Register +
+   + 0x00000004: + +   + FLASHCFG - Flash Control Register +
+   + 0x00000008: + +   + CTRL - Cache Control +
+   + 0x00000010: + +   + NCR0START - Flash Cache Noncachable Region 0 Start Address. +
+   + 0x00000014: + +   + NCR0END - Flash Cache Noncachable Region 0 End +
+   + 0x00000018: + +   + NCR1START - Flash Cache Noncachable Region 1 Start +
+   + 0x0000001C: + +   + NCR1END - Flash Cache Noncachable Region 1 End +
+   + 0x00000030: + +   + CACHEMODE - Flash Cache Mode Register. Used to trim performance/power. +
+   + 0x00000040: + +   + DMON0 - Data Cache Total Accesses +
+   + 0x00000044: + +   + DMON1 - Data Cache Tag Lookups +
+   + 0x00000048: + +   + DMON2 - Data Cache Hits +
+   + 0x0000004C: + +   + DMON3 - Data Cache Line Hits +
+   + 0x00000050: + +   + IMON0 - Instruction Cache Total Accesses +
+   + 0x00000054: + +   + IMON1 - Instruction Cache Tag Lookups +
+   + 0x00000058: + +   + IMON2 - Instruction Cache Hits +
+   + 0x0000005C: + +   + IMON3 - Instruction Cache Line Hits +
+
+
+ +
+
+

CACHECFG - Flash Cache Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018000 +
+

Description:

+

Flash Cache Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ENABLE_MONITOR +
0x0		RSVD +
0x0		DATA_CLKGATE +
0x1		SMDLY +
0x6		DLY +
0x6		CACHE_LS +
0x1		CACHE_CLKGATE +
0x1		DCACHE_ENABLE +
0x0		ICACHE_ENABLE +
0x0		SERIAL +
0x0		CONFIG +
0x5		ENABLE_NC1 +
0x0		ENABLE_NC0 +
0x0		LRU +
0x0		ENABLE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:25RSVDROThis bitfield is reserved for future use.

+
24ENABLE_MONITORRWEnable Cache Monitoring Stats. Only enable this for debug/performance analysis since it will consume additional power. See IMON/DMON registers for data.

+
23:21RSVDROThis bitfield is reserved for future use.

+
20DATA_CLKGATERWEnable clock gating of entire cache data array subsystem. This should be enabled for normal operation.

+
19:16SMDLYRWUnused. Should be left at default value.

+
15:12DLYRWUnused. Should be left at default value.

+
11CACHE_LSRWEnable LS (light sleep) of cache RAMs. This should not be enabled for normal operation. When this bit is set, the cache's RAMS will be put into light sleep mode while inactive. NOTE: if the cache is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.

+
10CACHE_CLKGATERWEnable clock gating of individual cache RAMs. This bit should be enabled for normal operation for lowest power consumption.

+
9DCACHE_ENABLERWEnable Flash Data Caching. When set to 1, all instruction accesses to flash will be cached.

+
8ICACHE_ENABLERWEnable Flash Instruction Caching. When set to 1, all instruction accesses to flash will be cached.

+
7SERIALRWBitfield should always be programmed to 0.

+
6:4CONFIGRWSets the cache configuration. Only a single configuration of 0x5 is valid.

+ W2_128B_512E = 0x5 - Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active)
3ENABLE_NC1RWEnable Non-cacheable region 1. See the NCR1 registers to set the region boundaries and size.

+
2ENABLE_NC0RWEnable Non-cacheable region 0. See the NCR0 registers to set the region boundaries and size.

+
1LRURWSets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM and is recommended.

+
0ENABLERWEnables the main flash cache controller logic and enables power to the cache RAMs. Instruction and Data caching need to be enabled independently using the ICACHE_ENABLE and DCACHE_ENABLE bits.

+
+
+
+
+ +
+
+

FLASHCFG - Flash Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018004 +
+

Description:

+

Flash Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RD_WAIT +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDROThis bitfield is reserved for future use.

+
2:0RD_WAITRWSets read waitstates for flash accesses (in clock cycles). This should be left at the default value for normal flash operation.

+
+
+
+
+ +
+
+

CTRL - Cache Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018008 +
+

Description:

+

Cache Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FLASH1_SLM_ENABLE +
0x0		FLASH1_SLM_DISABLE +
0x0		FLASH1_SLM_STATUS +
0x0		RSVD +
0x0		FLASH0_SLM_ENABLE +
0x0		FLASH0_SLM_DISABLE +
0x0		FLASH0_SLM_STATUS +
0x0		RSVD +
0x0		CACHE_READY +
0x0		RESET_STAT +
0x0		INVALIDATE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDROThis bitfield is reserved for future use.

+
10FLASH1_SLM_ENABLEWOEnable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.

+
9FLASH1_SLM_DISABLEWODisable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.

+
8FLASH1_SLM_STATUSROFlash Sleep Mode Status. When 1, flash instance 1 is asleep.

+
7RSVDROThis bitfield is reserved for future use.

+
6FLASH0_SLM_ENABLEWOEnable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.

+
5FLASH0_SLM_DISABLEWODisable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.

+
4FLASH0_SLM_STATUSROFlash Sleep Mode Status. When 1, flash instance 0 is asleep.

+
3RSVDROThis bitfield is reserved for future use.

+
2CACHE_READYROCache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation.

+
1RESET_STATWOWriting a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield.

+ CLEAR = 0x1 - Clear Cache Stats
0INVALIDATEWOWriting a 1 to this bitfield invalidates the flash cache contents.

+ GO = 0x1 - Initiate a programming operation to flash info.
+
+
+
+ +
+
+

NCR0START - Flash Cache Noncachable Region 0 Start Address.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018010 +
+

Description:

+

Flash Cache Noncachable Region 0 Start Address.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADDR +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDROThis bitfield is reserved for future use.

+
19:4ADDRRWStart address for non-cacheable region 0. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).

+
3:0RSVDROThis bitfield is reserved for future use.

+
+
+
+
+ +
+
+

NCR0END - Flash Cache Noncachable Region 0 End

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018014 +
+

Description:

+

Flash Cache Noncachable Region 0 End

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADDR +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDROThis bitfield is reserved for future use.

+
19:4ADDRRWEnd address for non-cacheable region 0. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).

+
3:0RSVDROThis bitfield is reserved for future use.

+
+
+
+
+ +
+
+

NCR1START - Flash Cache Noncachable Region 1 Start

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018018 +
+

Description:

+

Flash Cache Noncachable Region 1 Start

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADDR +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDROThis bitfield is reserved for future use.

+
19:4ADDRRWStart address for non-cacheable region 1. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).

+
3:0RSVDROThis bitfield is reserved for future use.

+
+
+
+
+ +
+
+

NCR1END - Flash Cache Noncachable Region 1 End

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001801C +
+

Description:

+

Flash Cache Noncachable Region 1 End

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADDR +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDROThis bitfield is reserved for future use.

+
19:4ADDRRWEnd address for non-cacheable region 1. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).

+
3:0RSVDROThis bitfield is reserved for future use.

+
+
+
+
+ +
+
+

CACHEMODE - Flash Cache Mode Register. Used to trim performance/power.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018030 +
+

Description:

+

Flash Cache Mode Register. Used to trim performance/power.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		THROTTLE6 +
0x0		THROTTLE5 +
0x0		THROTTLE4 +
0x0		THROTTLE3 +
0x0		THROTTLE2 +
0x0		THROTTLE1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDROThis bitfield is reserved for future use.

+
5THROTTLE6RWDisallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value should be left at zero for optimal performance.

+
4THROTTLE5RWDisallow Data RAM reads (from line hits) during lookup read ops. Value should be left at zero for optimal performance.

+
3THROTTLE4RWDisallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should be left at zero for optimal performance.

+
2THROTTLE3RWDisallow cache data RAM writes on data RAM read cycles. Value should be left at zero for optimal performance.

+
1THROTTLE2RWDisallow cache data RAM writes on tag RAM read cycles. Value should be left at zero for optimal performance.

+
0THROTTLE1RWDisallow cache data RAM writes on tag RAM fill cycles. Value should be left at zero for optimal performance.

+
+
+
+
+ +
+
+

DMON0 - Data Cache Total Accesses

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018040 +
+

Description:

+

Data Cache Total Accesses

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
DACCESS_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0DACCESS_COUNTROTotal accesses to data cache

+
+
+
+
+ +
+
+

DMON1 - Data Cache Tag Lookups

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018044 +
+

Description:

+

Data Cache Tag Lookups

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
DLOOKUP_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0DLOOKUP_COUNTROTotal tag lookups from data cache

+
+
+
+
+ +
+
+

DMON2 - Data Cache Hits

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018048 +
+

Description:

+

Data Cache Hits

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
DHIT_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0DHIT_COUNTROCache hits from lookup operations

+
+
+
+
+ +
+
+

DMON3 - Data Cache Line Hits

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001804C +
+

Description:

+

Data Cache Line Hits

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
DLINE_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0DLINE_COUNTROCache hits from line cache

+
+
+
+
+ +
+
+

IMON0 - Instruction Cache Total Accesses

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018050 +
+

Description:

+

Instruction Cache Total Accesses

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
IACCESS_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0IACCESS_COUNTROTotal accesses to Instruction cache

+
+
+
+
+ +
+
+

IMON1 - Instruction Cache Tag Lookups

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018054 +
+

Description:

+

Instruction Cache Tag Lookups

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ILOOKUP_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ILOOKUP_COUNTROTotal tag lookups from Instruction cache

+
+
+
+
+ +
+
+

IMON2 - Instruction Cache Hits

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40018058 +
+

Description:

+

Instruction Cache Hits

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
IHIT_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0IHIT_COUNTROCache hits from lookup operations

+
+
+
+
+ +
+
+

IMON3 - Instruction Cache Line Hits

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001805C +
+

Description:

+

Instruction Cache Line Hits

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ILINE_COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ILINE_COUNTROCache hits from line cache

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/clkgen_regs.html b/docs/apollo2/pages/clkgen_regs.html new file mode 100644 index 0000000..45de877 --- /dev/null +++ b/docs/apollo2/pages/clkgen_regs.html @@ -0,0 +1,2737 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
CLKGEN - Clock Generator
+
+
+ + +
+
+
+

CLKGEN Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CALXT - XT Oscillator Control +
+   + 0x00000004: + +   + CALRC - RC Oscillator Control +
+   + 0x00000008: + +   + ACALCTR - Autocalibration Counter +
+   + 0x0000000C: + +   + OCTRL - Oscillator Control +
+   + 0x00000010: + +   + CLKOUT - CLKOUT Frequency Select +
+   + 0x00000014: + +   + CLKKEY - Key Register for Clock Control Register +
+   + 0x00000018: + +   + CCTRL - HFRC Clock Control +
+   + 0x0000001C: + +   + STATUS - Clock Generator Status +
+   + 0x00000020: + +   + HFADJ - HFRC Adjustment +
+   + 0x00000028: + +   + CLOCKEN - Clock Enable Status +
+   + 0x0000002C: + +   + CLOCKEN2 - Clock Enable Status +
+   + 0x00000030: + +   + CLOCKEN3 - Clock Enable Status +
+   + 0x00000034: + +   + UARTEN - UART Enable +
+   + 0x00000100: + +   + INTEN - CLKGEN Interrupt Register: Enable +
+   + 0x00000104: + +   + INTSTAT - CLKGEN Interrupt Register: Status +
+   + 0x00000108: + +   + INTCLR - CLKGEN Interrupt Register: Clear +
+   + 0x0000010C: + +   + INTSET - CLKGEN Interrupt Register: Set +
+
+
+ +
+
+

CALXT - XT Oscillator Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004000 +
+

Description:

+

XT Oscillator Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CALXT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED

+
10:0CALXTRWXT Oscillator calibration value

+
+
+
+
+ +
+
+

CALRC - RC Oscillator Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004004 +
+

Description:

+

RC Oscillator Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CALRC +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0CALRCRWLFRC Oscillator calibration value

+
+
+
+
+ +
+
+

ACALCTR - Autocalibration Counter

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004008 +
+

Description:

+

Autocalibration Counter

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ACALCTR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED

+
23:0ACALCTRROAutocalibration Counter result.

+
+
+
+
+ +
+
+

OCTRL - Oscillator Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000400C +
+

Description:

+

Oscillator Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ACAL +
0x0		OSEL +
0x0		FOS +
0x0		RSVD +
0x0		STOPRC +
0x0		STOPXT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED

+
10:8ACALRWAutocalibration control

+ DIS = 0x0 - Disable Autocalibration
+ 1024SEC = 0x2 - Autocalibrate every 1024 seconds
+ 512SEC = 0x3 - Autocalibrate every 512 seconds
+ XTFREQ = 0x6 - Frequency measurement using XT
+ EXTFREQ = 0x7 - Frequency measurement using external clock
7OSELRWSelects the RTC oscillator (1 => LFRC, 0 => XT)

+ RTC_XT = 0x0 - RTC uses the XT
+ RTC_LFRC = 0x1 - RTC uses the LFRC
6FOSRWOscillator switch on failure function

+ DIS = 0x0 - Disable the oscillator switch on failure function
+ EN = 0x1 - Enable the oscillator switch on failure function
5:2RSVDRORESERVED

+
1STOPRCRWStop the LFRC Oscillator to the RTC

+ EN = 0x0 - Enable the LFRC Oscillator to drive the RTC
+ STOP = 0x1 - Stop the LFRC Oscillator when driving the RTC
0STOPXTRWStop the XT Oscillator to the RTC

+ EN = 0x0 - Enable the XT Oscillator to drive the RTC
+ STOP = 0x1 - Stop the XT Oscillator when driving the RTC
+
+
+
+ +
+
+

CLKOUT - CLKOUT Frequency Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004010 +
+

Description:

+

CLKOUT Frequency Select

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CKEN +
0x0		RSVD +
0x0		CKSEL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED

+
7CKENRWEnable the CLKOUT signal

+ DIS = 0x0 - Disable CLKOUT
+ EN = 0x1 - Enable CLKOUT
6RSVDRORESERVED

+
5:0CKSELRWCLKOUT signal select. Note that HIGH_DRIVE should be selected if any high frequencies (such as from HFRC) are selected for CLKOUT.

+ LFRC = 0x0 - LFRC
+ XT_DIV2 = 0x1 - XT / 2
+ XT_DIV4 = 0x2 - XT / 4
+ XT_DIV8 = 0x3 - XT / 8
+ XT_DIV16 = 0x4 - XT / 16
+ XT_DIV32 = 0x5 - XT / 32
+ RTC_1Hz = 0x10 - 1 Hz as selected in RTC
+ XT_DIV2M = 0x16 - XT / 2^21
+ XT = 0x17 - XT
+ CG_100Hz = 0x18 - 100 Hz as selected in CLKGEN
+ HFRC = 0x19 - HFRC
+ HFRC_DIV4 = 0x1A - HFRC / 4
+ HFRC_DIV8 = 0x1B - HFRC / 8
+ HFRC_DIV16 = 0x1C - HFRC / 16
+ HFRC_DIV64 = 0x1D - HFRC / 64
+ HFRC_DIV128 = 0x1E - HFRC / 128
+ HFRC_DIV256 = 0x1F - HFRC / 256
+ HFRC_DIV512 = 0x20 - HFRC / 512
+ FLASH_CLK = 0x22 - Flash Clock
+ LFRC_DIV2 = 0x23 - LFRC / 2
+ LFRC_DIV32 = 0x24 - LFRC / 32
+ LFRC_DIV512 = 0x25 - LFRC / 512
+ LFRC_DIV32K = 0x26 - LFRC / 32768
+ XT_DIV256 = 0x27 - XT / 256
+ XT_DIV8K = 0x28 - XT / 8192
+ XT_DIV64K = 0x29 - XT / 2^16
+ ULFRC_DIV16 = 0x2A - Uncal LFRC / 16
+ ULFRC_DIV128 = 0x2B - Uncal LFRC / 128
+ ULFRC_1Hz = 0x2C - Uncal LFRC / 1024
+ ULFRC_DIV4K = 0x2D - Uncal LFRC / 4096
+ ULFRC_DIV1M = 0x2E - Uncal LFRC / 2^20
+ HFRC_DIV64K = 0x2F - HFRC / 2^16
+ HFRC_DIV16M = 0x30 - HFRC / 2^24
+ LFRC_DIV2M = 0x31 - LFRC / 2^20
+ HFRCNE = 0x32 - HFRC (not autoenabled)
+ HFRCNE_DIV8 = 0x33 - HFRC / 8 (not autoenabled)
+ XTNE = 0x35 - XT (not autoenabled)
+ XTNE_DIV16 = 0x36 - XT / 16 (not autoenabled)
+ LFRCNE_DIV32 = 0x37 - LFRC / 32 (not autoenabled)
+ LFRCNE = 0x39 - LFRC (not autoenabled) - Default for undefined values
+
+
+
+ +
+
+

CLKKEY - Key Register for Clock Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004014 +
+

Description:

+

Key Register for Clock Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CLKKEY +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CLKKEYRWKey register value.

+ Key = 0x47 - Key
+
+
+
+ +
+
+

CCTRL - HFRC Clock Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004018 +
+

Description:

+

HFRC Clock Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CORESEL +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED

+
0CORESELRWCore Clock divisor

+ HFRC = 0x0 - Core Clock is HFRC
+ HFRC_DIV2 = 0x1 - Core Clock is HFRC / 2
+
+
+
+ +
+
+

STATUS - Clock Generator Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000401C +
+

Description:

+

Clock Generator Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OSCF +
0x0		OMODE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED

+
1OSCFROXT Oscillator is enabled but not oscillating

+
0OMODEROCurrent RTC oscillator (1 => LFRC, 0 => XT)

+
+
+
+
+ +
+
+

HFADJ - HFRC Adjustment

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004020 +
+

Description:

+

HFRC Adjustment

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		HFADJ_GAIN +
0x1		HFWARMUP +
0x0		HFXTADJ +
0x5b8		RSVD +
0x0		HFADJCK +
0x0		HFADJEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED

+
23:21HFADJ_GAINRWGain control for HFRC adjustment

+ Gain_of_1 = 0x0 - HF Adjust with Gain of 1
+ Gain_of_1_in_2 = 0x1 - HF Adjust with Gain of 0.5
+ Gain_of_1_in_4 = 0x2 - HF Adjust with Gain of 0.25
+ Gain_of_1_in_8 = 0x3 - HF Adjust with Gain of 0.125
+ Gain_of_1_in_16 = 0x4 - HF Adjust with Gain of 0.0625
+ Gain_of_1_in_32 = 0x5 - HF Adjust with Gain of 0.03125
20HFWARMUPRWXT warmup period for HFRC adjustment

+ 1SEC = 0x0 - Autoadjust XT warmup period = 1-2 seconds
+ 2SEC = 0x1 - Autoadjust XT warmup period = 2-4 seconds
19:8HFXTADJRWTarget HFRC adjustment value.

+
7:4RSVDRORESERVED

+
3:1HFADJCKRWRepeat period for HFRC adjustment

+ 4SEC = 0x0 - Autoadjust repeat period = 4 seconds
+ 16SEC = 0x1 - Autoadjust repeat period = 16 seconds
+ 32SEC = 0x2 - Autoadjust repeat period = 32 seconds
+ 64SEC = 0x3 - Autoadjust repeat period = 64 seconds
+ 128SEC = 0x4 - Autoadjust repeat period = 128 seconds
+ 256SEC = 0x5 - Autoadjust repeat period = 256 seconds
+ 512SEC = 0x6 - Autoadjust repeat period = 512 seconds
+ 1024SEC = 0x7 - Autoadjust repeat period = 1024 seconds
0HFADJENRWHFRC adjustment control

+ DIS = 0x0 - Disable the HFRC adjustment
+ EN = 0x1 - Enable the HFRC adjustment
+
+
+
+ +
+
+

CLOCKEN - Clock Enable Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004028 +
+

Description:

+

Clock Enable Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CLOCKEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CLOCKENROClock enable status

+ ADC_CLKEN = 0x1 - Clock enable for the ADC.
+ CTIMER_CLKEN = 0x2 - Clock enable for the CTIMER.
+ CTIMER0A_CLKEN = 0x4 - Clock enable for the CTIMER0A.
+ CTIMER0B_CLKEN = 0x8 - Clock enable for the CTIMER0B.
+ CTIMER1A_CLKEN = 0x10 - Clock enable for the CTIMER1A.
+ CTIMER1B_CLKEN = 0x20 - Clock enable for the CTIMER1B.
+ CTIMER2A_CLKEN = 0x40 - Clock enable for the CTIMER2A.
+ CTIMER2B_CLKEN = 0x80 - Clock enable for the CTIMER2B.
+ CTIMER3A_CLKEN = 0x100 - Clock enable for the CTIMER3A.
+ CTIMER3B_CLKEN = 0x200 - Clock enable for the CTIMER3B.
+ IOMSTR0_CLKEN = 0x400 - Clock enable for the IO Master 0.
+ IOMSTR1_CLKEN = 0x800 - Clock enable for the IO Master 1.
+ IOMSTR2_CLKEN = 0x1000 - Clock enable for the IO Master 2.
+ IOMSTR3_CLKEN = 0x2000 - Clock enable for the IO Master 3.
+ IOMSTR4_CLKEN = 0x4000 - Clock enable for the IO Master 4.
+ IOMSTR5_CLKEN = 0x8000 - Clock enable for the IO Master 5.
+ IOMSTRIFC0_CLKEN = 0x10000 - Clock enable for the IO Master IFC0.
+ IOMSTRIFC1_CLKEN = 0x20000 - Clock enable for the IO Master IFC1.
+ IOMSTRIFC2_CLKEN = 0x40000 - Clock enable for the IO Master IFC2.
+ IOMSTRIFC3_CLKEN = 0x80000 - Clock enable for the IO Master IFC3.
+ IOMSTRIFC4_CLKEN = 0x100000 - Clock enable for the IO Master IFC4.
+ IOMSTRIFC5_CLKEN = 0x200000 - Clock enable for the IO Master IFC5.
+ IOSLAVE_CLKEN = 0x400000 - Clock enable for the IO Slave.
+ PDM_CLKEN = 0x800000 - Clock enable for the PDM.
+ PDMIFC_CLKEN = 0x1000000 - Clock enable for the PDM IFC.
+ RSTGEN_CLKEN = 0x2000000 - Clock enable for the RSTGEN.
+ SRAM_WIPE_CLKEN = 0x4000000 - Clock enable for the SRAM_WIPE.
+ STIMER_CLKEN = 0x8000000 - Clock enable for the STIMER.
+ STIMER_CNT_CLKEN = 0x10000000 - Clock enable for the STIMER_CNT.
+ TPIU_CLKEN = 0x20000000 - Clock enable for the TPIU.
+ UART0_HCLK_CLKEN = 0x40000000 - Clock enable for the UART0_HCLK.
+ UART0HF_CLKEN = 0x80000000 - Clock enable for the UART0HF.
+
+
+
+ +
+
+

CLOCKEN2 - Clock Enable Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000402C +
+

Description:

+

Clock Enable Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CLOCKEN2 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CLOCKEN2ROClock enable status 2

+ UART1_HCLK_CLKEN = 0x1 - Clock enable for the UART1_HCLK.
+ UART1HF_CLKEN = 0x2 - Clock enable for the UART1HF.
+ WDT_CLKEN = 0x4 - Clock enable for the WDT.
+ XT_32KHz_EN = 0x40000000 - Clock enable for the XT_32KHz.
+ FRCHFRC = 0x80000000 - Force HFRC On Status.
+
+
+
+ +
+
+

CLOCKEN3 - Clock Enable Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004030 +
+

Description:

+

Clock Enable Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CLOCKEN3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CLOCKEN3ROClock enable status 3

+ periph_all_xtal_en = 0x1000000 - At least 1 peripherial is requesting for XTAL Clock
+ periph_all_hfrc_en = 0x2000000 - At least 1 peripherial is requesting for HFRC Clock
+ HFADJEN = 0x4000000 - HFRC Adjust Enable Status
+ HFRC_en_out = 0x8000000 - HFRC is enabled during adjustment status
+ RTC_SOURCE = 0x10000000 - Selects the RTC oscillator (0 => LFRC, 1 => XT)
+ XTAL_EN = 0x20000000 - XT is enabled Status
+ HFRC_EN = 0x40000000 - HFRC is enabled Status
+ FLASHCLK_EN = 0x80000000 - Flash Clock is enabled Status
+
+
+
+ +
+
+

UARTEN - UART Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004034 +
+

Description:

+

UART Enable

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		UART1EN +
0x0		RSVD +
0x0		UART0EN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9:8UART1ENRWUART1 system clock control

+ DIS = 0x0 - Disable the UART1 system clock
+ EN = 0x1 - Enable the UART1 system clock
+ REDUCE_FREQ = 0x2 - Run UART_Hclk at the same frequency as UART_hfclk
+ EN_POWER_SAV = 0x3 - Enable UART_hclk to reduce to UART_hfclk at low power mode
7:2RSVDRORESERVED

+
1:0UART0ENRWUART0 system clock control

+ DIS = 0x0 - Disable the UART0 system clock
+ EN = 0x1 - Enable the UART0 system clock
+ REDUCE_FREQ = 0x2 - Run UART_Hclk at the same frequency as UART_hfclk
+ EN_POWER_SAV = 0x3 - Enable UART_hclk to reduce to UART_hfclk at low power mode
+
+
+
+ +
+
+

INTEN - CLKGEN Interrupt Register: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004100 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ +
+
+

INTSTAT - CLKGEN Interrupt Register: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004104 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ +
+
+

INTCLR - CLKGEN Interrupt Register: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004108 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ +
+
+

INTSET - CLKGEN Interrupt Register: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000410C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/ctimer_regs.html b/docs/apollo2/pages/ctimer_regs.html new file mode 100644 index 0000000..993c98a --- /dev/null +++ b/docs/apollo2/pages/ctimer_regs.html @@ -0,0 +1,7907 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
CTIMER - Counter/Timer
+
+
+ + +
+
+
+

CTIMER Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + TMR0 - Counter/Timer Register +
+   + 0x00000004: + +   + CMPRA0 - Counter/Timer A0 Compare Registers +
+   + 0x00000008: + +   + CMPRB0 - Counter/Timer B0 Compare Registers +
+   + 0x0000000C: + +   + CTRL0 - Counter/Timer Control +
+   + 0x00000010: + +   + TMR1 - Counter/Timer Register +
+   + 0x00000014: + +   + CMPRA1 - Counter/Timer A1 Compare Registers +
+   + 0x00000018: + +   + CMPRB1 - Counter/Timer B1 Compare Registers +
+   + 0x0000001C: + +   + CTRL1 - Counter/Timer Control +
+   + 0x00000020: + +   + TMR2 - Counter/Timer Register +
+   + 0x00000024: + +   + CMPRA2 - Counter/Timer A2 Compare Registers +
+   + 0x00000028: + +   + CMPRB2 - Counter/Timer B2 Compare Registers +
+   + 0x0000002C: + +   + CTRL2 - Counter/Timer Control +
+   + 0x00000030: + +   + TMR3 - Counter/Timer Register +
+   + 0x00000034: + +   + CMPRA3 - Counter/Timer A3 Compare Registers +
+   + 0x00000038: + +   + CMPRB3 - Counter/Timer B3 Compare Registers +
+   + 0x0000003C: + +   + CTRL3 - Counter/Timer Control +
+   + 0x00000100: + +   + STCFG - Configuration Register +
+   + 0x00000104: + +   + STTMR - System Timer Count Register (Real Time Counter) +
+   + 0x00000108: + +   + CAPTURE_CONTROL - Capture Control Register +
+   + 0x00000110: + +   + SCMPR0 - Compare Register A +
+   + 0x00000114: + +   + SCMPR1 - Compare Register B +
+   + 0x00000118: + +   + SCMPR2 - Compare Register C +
+   + 0x0000011C: + +   + SCMPR3 - Compare Register D +
+   + 0x00000120: + +   + SCMPR4 - Compare Register E +
+   + 0x00000124: + +   + SCMPR5 - Compare Register F +
+   + 0x00000128: + +   + SCMPR6 - Compare Register G +
+   + 0x0000012C: + +   + SCMPR7 - Compare Register H +
+   + 0x000001E0: + +   + SCAPT0 - Capture Register A +
+   + 0x000001E4: + +   + SCAPT1 - Capture Register B +
+   + 0x000001E8: + +   + SCAPT2 - Capture Register C +
+   + 0x000001EC: + +   + SCAPT3 - Capture Register D +
+   + 0x000001F0: + +   + SNVR0 - System Timer NVRAM_A Register +
+   + 0x000001F4: + +   + SNVR1 - System Timer NVRAM_B Register +
+   + 0x000001F8: + +   + SNVR2 - System Timer NVRAM_C Register +
+   + 0x00000200: + +   + INTEN - Counter/Timer Interrupts: Enable +
+   + 0x00000204: + +   + INTSTAT - Counter/Timer Interrupts: Status +
+   + 0x00000208: + +   + INTCLR - Counter/Timer Interrupts: Clear +
+   + 0x0000020C: + +   + INTSET - Counter/Timer Interrupts: Set +
+   + 0x00000300: + +   + STMINTEN - STIMER Interrupt registers: Enable +
+   + 0x00000304: + +   + STMINTSTAT - STIMER Interrupt registers: Status +
+   + 0x00000308: + +   + STMINTCLR - STIMER Interrupt registers: Clear +
+   + 0x0000030C: + +   + STMINTSET - STIMER Interrupt registers: Set +
+
+
+ +
+
+

TMR0 - Counter/Timer Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008000 +
+

Description:

+

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTTMRB0 +
0x0		CTTMRA0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CTTMRB0ROCounter/Timer B0.

+
15:0CTTMRA0ROCounter/Timer A0.

+
+
+
+
+ +
+
+

CMPRA0 - Counter/Timer A0 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008004 +
+

Description:

+

Compare limits for timer half A.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1A0 +
0x0		CMPR0A0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1A0RWCounter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.

+
15:0CMPR0A0RWCounter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.

+
+
+
+
+ +
+
+

CMPRB0 - Counter/Timer B0 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008008 +
+

Description:

+

Compare limits for timer half B.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1B0 +
0x0		CMPR0B0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1B0RWCounter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.

+
15:0CMPR0B0RWCounter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.

+
+
+
+
+ +
+
+

CTRL0 - Counter/Timer Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000800C +
+

Description:

+

Control bit fields for both halves of timer 0.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTLINK0 +
0x0		RSVD +
0x0		TMRB0PE +
0x0		TMRB0POL +
0x0		TMRB0CLR +
0x0		TMRB0IE1 +
0x0		TMRB0IE0 +
0x0		TMRB0FN +
0x0		TMRB0CLK +
0x0		TMRB0EN +
0x0		RSVD +
0x0		TMRA0PE +
0x0		TMRA0POL +
0x0		TMRA0CLR +
0x0		TMRA0IE1 +
0x0		TMRA0IE0 +
0x0		TMRA0FN +
0x0		TMRA0CLK +
0x0		TMRA0EN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CTLINK0RWCounter/Timer A0/B0 Link bit.

+ TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default).
+ 32BIT_TIMER = 0x1 - Link A0/B0 timers into a single 32-bit timer.
30RSVDRORESERVED

+
29TMRB0PERWCounter/Timer B0 Output Enable bit.

+ DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB0POL.
+ EN = 0x1 - Enable counter/timer B0 to generate a signal on TMRPINB.
28TMRB0POLRWCounter/Timer B0 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINB0 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINB0 pin is the inverse of the timer output.
27TMRB0CLRRWCounter/Timer B0 Clear bit.

+ RUN = 0x0 - Allow counter/timer B0 to run
+ CLEAR = 0x1 - Holds counter/timer B0 at 0x0000.
26TMRB0IE1RWCounter/Timer B0 Interrupt Enable bit for COMPR1.

+ DIS = 0x0 - Disable counter/timer B0 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer B0 to generate an interrupt based on COMPR1.
25TMRB0IE0RWCounter/Timer B0 Interrupt Enable bit for COMPR0.

+ DIS = 0x0 - Disable counter/timer B0 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer B0 to generate an interrupt based on COMPR0
24:22TMRB0FNRWCounter/Timer B0 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B0, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17TMRB0CLKRWCounter/Timer B0 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINB.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKB = 0x10 - Clock source is buck converter stream from CORE Buck.
16TMRB0ENRWCounter/Timer B0 Enable bit.

+ DIS = 0x0 - Counter/Timer B0 Disable.
+ EN = 0x1 - Counter/Timer B0 Enable.
15:14RSVDRORESERVED

+
13TMRA0PERWCounter/Timer A0 Output Enable bit.

+ DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA0POL.
+ EN = 0x1 - Enable counter/timer A0 to generate a signal on TMRPINA.
12TMRA0POLRWCounter/Timer A0 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINA0 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINA0 pin is the inverse of the timer output.
11TMRA0CLRRWCounter/Timer A0 Clear bit.

+ RUN = 0x0 - Allow counter/timer A0 to run
+ CLEAR = 0x1 - Holds counter/timer A0 at 0x0000.
10TMRA0IE1RWCounter/Timer A0 Interrupt Enable bit based on COMPR1.

+ DIS = 0x0 - Disable counter/timer A0 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer A0 to generate an interrupt based on COMPR1.
9TMRA0IE0RWCounter/Timer A0 Interrupt Enable bit based on COMPR0.

+ DIS = 0x0 - Disable counter/timer A0 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer A0 to generate an interrupt based on COMPR0.
8:6TMRA0FNRWCounter/Timer A0 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A0, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1TMRA0CLKRWCounter/Timer A0 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINA.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK_DIV4 = 0xF - Clock source is HCLK / 4.
+ BUCKA = 0x10 - Clock source is buck converter stream from MEM Buck.
0TMRA0ENRWCounter/Timer A0 Enable bit.

+ DIS = 0x0 - Counter/Timer A0 Disable.
+ EN = 0x1 - Counter/Timer A0 Enable.
+
+
+
+ +
+
+

TMR1 - Counter/Timer Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008010 +
+

Description:

+

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTTMRB1 +
0x0		CTTMRA1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CTTMRB1ROCounter/Timer B1.

+
15:0CTTMRA1ROCounter/Timer A1.

+
+
+
+
+ +
+
+

CMPRA1 - Counter/Timer A1 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008014 +
+

Description:

+

This register holds the compare limits for timer half A.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1A1 +
0x0		CMPR0A1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1A1RWCounter/Timer A1 Compare Register 1.

+
15:0CMPR0A1RWCounter/Timer A1 Compare Register 0.

+
+
+
+
+ +
+
+

CMPRB1 - Counter/Timer B1 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008018 +
+

Description:

+

This register holds the compare limits for timer half B.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1B1 +
0x0		CMPR0B1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1B1RWCounter/Timer B1 Compare Register 1.

+
15:0CMPR0B1RWCounter/Timer B1 Compare Register 0.

+
+
+
+
+ +
+
+

CTRL1 - Counter/Timer Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000801C +
+

Description:

+

Control bit fields for both halves of timer 0.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTLINK1 +
0x0		RSVD +
0x0		TMRB1PE +
0x0		TMRB1POL +
0x0		TMRB1CLR +
0x0		TMRB1IE1 +
0x0		TMRB1IE0 +
0x0		TMRB1FN +
0x0		TMRB1CLK +
0x0		TMRB1EN +
0x0		RSVD +
0x0		TMRA1PE +
0x0		TMRA1POL +
0x0		TMRA1CLR +
0x0		TMRA1IE1 +
0x0		TMRA1IE0 +
0x0		TMRA1FN +
0x0		TMRA1CLK +
0x0		TMRA1EN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CTLINK1RWCounter/Timer A1/B1 Link bit.

+ TWO_16BIT_TIMERS = 0x0 - Use A1/B1 timers as two independent 16-bit timers (default).
+ 32BIT_TIMER = 0x1 - Link A1/B1 timers into a single 32-bit timer.
30RSVDRORESERVED

+
29TMRB1PERWCounter/Timer B1 Output Enable bit.

+ DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB1POL.
+ EN = 0x1 - Enable counter/timer B1 to generate a signal on TMRPINB.
28TMRB1POLRWCounter/Timer B1 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINB1 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINB1 pin is the inverse of the timer output.
27TMRB1CLRRWCounter/Timer B1 Clear bit.

+ RUN = 0x0 - Allow counter/timer B1 to run
+ CLEAR = 0x1 - Holds counter/timer B1 at 0x0000.
26TMRB1IE1RWCounter/Timer B1 Interrupt Enable bit for COMPR1.

+ DIS = 0x0 - Disable counter/timer B1 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer B1 to generate an interrupt based on COMPR1.
25TMRB1IE0RWCounter/Timer B1 Interrupt Enable bit for COMPR0.

+ DIS = 0x0 - Disable counter/timer B1 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer B1 to generate an interrupt based on COMPR0
24:22TMRB1FNRWCounter/Timer B1 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B1, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17TMRB1CLKRWCounter/Timer B1 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINB.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKB = 0x10 - Clock source is buck converter stream from CORE Buck.
16TMRB1ENRWCounter/Timer B1 Enable bit.

+ DIS = 0x0 - Counter/Timer B1 Disable.
+ EN = 0x1 - Counter/Timer B1 Enable.
15:14RSVDRORESERVED

+
13TMRA1PERWCounter/Timer A1 Output Enable bit.

+ DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA1POL.
+ EN = 0x1 - Enable counter/timer A1 to generate a signal on TMRPINA.
12TMRA1POLRWCounter/Timer A1 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINA1 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINA1 pin is the inverse of the timer output.
11TMRA1CLRRWCounter/Timer A1 Clear bit.

+ RUN = 0x0 - Allow counter/timer A1 to run
+ CLEAR = 0x1 - Holds counter/timer A1 at 0x0000.
10TMRA1IE1RWCounter/Timer A1 Interrupt Enable bit based on COMPR1.

+ DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR1.
9TMRA1IE0RWCounter/Timer A1 Interrupt Enable bit based on COMPR0.

+ DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR0.
8:6TMRA1FNRWCounter/Timer A1 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A1, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1TMRA1CLKRWCounter/Timer A1 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINA.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKA = 0x10 - Clock source is buck converter stream from MEM Buck.
0TMRA1ENRWCounter/Timer A1 Enable bit.

+ DIS = 0x0 - Counter/Timer A1 Disable.
+ EN = 0x1 - Counter/Timer A1 Enable.
+
+
+
+ +
+
+

TMR2 - Counter/Timer Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008020 +
+

Description:

+

Counter/Timer Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTTMRB2 +
0x0		CTTMRA2 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CTTMRB2ROCounter/Timer B2.

+
15:0CTTMRA2ROCounter/Timer A2.

+
+
+
+
+ +
+
+

CMPRA2 - Counter/Timer A2 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008024 +
+

Description:

+

This register holds the compare limits for timer half A.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1A2 +
0x0		CMPR0A2 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1A2RWCounter/Timer A2 Compare Register 1.

+
15:0CMPR0A2RWCounter/Timer A2 Compare Register 0.

+
+
+
+
+ +
+
+

CMPRB2 - Counter/Timer B2 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008028 +
+

Description:

+

This register holds the compare limits for timer half B.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1B2 +
0x0		CMPR0B2 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1B2RWCounter/Timer B2 Compare Register 1.

+
15:0CMPR0B2RWCounter/Timer B2 Compare Register 0.

+
+
+
+
+ +
+
+

CTRL2 - Counter/Timer Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000802C +
+

Description:

+

This register holds the control bit fields for both halves of timer 2.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTLINK2 +
0x0		RSVD +
0x0		TMRB2PE +
0x0		TMRB2POL +
0x0		TMRB2CLR +
0x0		TMRB2IE1 +
0x0		TMRB2IE0 +
0x0		TMRB2FN +
0x0		TMRB2CLK +
0x0		TMRB2EN +
0x0		RSVD +
0x0		TMRA2PE +
0x0		TMRA2POL +
0x0		TMRA2CLR +
0x0		TMRA2IE1 +
0x0		TMRA2IE0 +
0x0		TMRA2FN +
0x0		TMRA2CLK +
0x0		TMRA2EN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CTLINK2RWCounter/Timer A2/B2 Link bit.

+ TWO_16BIT_TIMERS = 0x0 - Use A2/B2 timers as two independent 16-bit timers (default).
+ 32BIT_TIMER = 0x1 - Link A2/B2 timers into a single 32-bit timer.
30RSVDRORESERVED

+
29TMRB2PERWCounter/Timer B2 Output Enable bit.

+ DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB2POL.
+ EN = 0x1 - Enable counter/timer B2 to generate a signal on TMRPINB.
28TMRB2POLRWCounter/Timer B2 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINB2 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINB2 pin is the inverse of the timer output.
27TMRB2CLRRWCounter/Timer B2 Clear bit.

+ RUN = 0x0 - Allow counter/timer B2 to run
+ CLEAR = 0x1 - Holds counter/timer B2 at 0x0000.
26TMRB2IE1RWCounter/Timer B2 Interrupt Enable bit for COMPR1.

+ DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COMPR1.
25TMRB2IE0RWCounter/Timer B2 Interrupt Enable bit for COMPR0.

+ DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COMPR0
24:22TMRB2FNRWCounter/Timer B2 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B2, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17TMRB2CLKRWCounter/Timer B2 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINB.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKA = 0x10 - Clock source is buck converter stream from MEM Buck.
16TMRB2ENRWCounter/Timer B2 Enable bit.

+ DIS = 0x0 - Counter/Timer B2 Disable.
+ EN = 0x1 - Counter/Timer B2 Enable.
15:14RSVDRORESERVED

+
13TMRA2PERWCounter/Timer A2 Output Enable bit.

+ DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA2POL.
+ EN = 0x1 - Enable counter/timer A2 to generate a signal on TMRPINA.
12TMRA2POLRWCounter/Timer A2 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINA2 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINA2 pin is the inverse of the timer output.
11TMRA2CLRRWCounter/Timer A2 Clear bit.

+ RUN = 0x0 - Allow counter/timer A2 to run
+ CLEAR = 0x1 - Holds counter/timer A2 at 0x0000.
10TMRA2IE1RWCounter/Timer A2 Interrupt Enable bit based on COMPR1.

+ DIS = 0x0 - Disable counter/timer A2 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer A2 to generate an interrupt based on COMPR1.
9TMRA2IE0RWCounter/Timer A2 Interrupt Enable bit based on COMPR0.

+ DIS = 0x0 - Disable counter/timer A2 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer A2 to generate an interrupt based on COMPR0.
8:6TMRA2FNRWCounter/Timer A2 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A2, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1TMRA2CLKRWCounter/Timer A2 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINA.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKB = 0x10 - Clock source is buck converter stream from CORE Buck.
0TMRA2ENRWCounter/Timer A2 Enable bit.

+ DIS = 0x0 - Counter/Timer A2 Disable.
+ EN = 0x1 - Counter/Timer A2 Enable.
+
+
+
+ +
+
+

TMR3 - Counter/Timer Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008030 +
+

Description:

+

Counter/Timer Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTTMRB3 +
0x0		CTTMRA3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CTTMRB3ROCounter/Timer B3.

+
15:0CTTMRA3ROCounter/Timer A3.

+
+
+
+
+ +
+
+

CMPRA3 - Counter/Timer A3 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008034 +
+

Description:

+

This register holds the compare limits for timer half A.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1A3 +
0x0		CMPR0A3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1A3RWCounter/Timer A3 Compare Register 1.

+
15:0CMPR0A3RWCounter/Timer A3 Compare Register 0.

+
+
+
+
+ +
+
+

CMPRB3 - Counter/Timer B3 Compare Registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008038 +
+

Description:

+

This register holds the compare limits for timer half B.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMPR1B3 +
0x0		CMPR0B3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16CMPR1B3RWCounter/Timer B3 Compare Register 1.

+
15:0CMPR0B3RWCounter/Timer B3 Compare Register 0.

+
+
+
+
+ +
+
+

CTRL3 - Counter/Timer Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000803C +
+

Description:

+

This register holds the control bit fields for both halves of timer 3.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTLINK3 +
0x0		RSVD +
0x0		TMRB3PE +
0x0		TMRB3POL +
0x0		TMRB3CLR +
0x0		TMRB3IE1 +
0x0		TMRB3IE0 +
0x0		TMRB3FN +
0x0		TMRB3CLK +
0x0		TMRB3EN +
0x0		ADCEN +
0x0		RSVD +
0x0		TMRA3PE +
0x0		TMRA3POL +
0x0		TMRA3CLR +
0x0		TMRA3IE1 +
0x0		TMRA3IE0 +
0x0		TMRA3FN +
0x0		TMRA3CLK +
0x0		TMRA3EN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CTLINK3RWCounter/Timer A3/B3 Link bit.

+ TWO_16BIT_TIMERS = 0x0 - Use A3/B3 timers as two independent 16-bit timers (default).
+ 32BIT_TIMER = 0x1 - Link A3/B3 timers into a single 32-bit timer.
30RSVDRORESERVED

+
29TMRB3PERWCounter/Timer B3 Output Enable bit.

+ DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB3POL.
+ EN = 0x1 - Enable counter/timer B3 to generate a signal on TMRPINB.
28TMRB3POLRWCounter/Timer B3 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINB3 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINB3 pin is the inverse of the timer output.
27TMRB3CLRRWCounter/Timer B3 Clear bit.

+ RUN = 0x0 - Allow counter/timer B3 to run
+ CLEAR = 0x1 - Holds counter/timer B3 at 0x0000.
26TMRB3IE1RWCounter/Timer B3 Interrupt Enable bit for COMPR1.

+ DIS = 0x0 - Disable counter/timer B3 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer B3 to generate an interrupt based on COMPR1.
25TMRB3IE0RWCounter/Timer B3 Interrupt Enable bit for COMPR0.

+ DIS = 0x0 - Disable counter/timer B3 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer B3 to generate an interrupt based on COMPR0
24:22TMRB3FNRWCounter/Timer B3 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B3, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17TMRB3CLKRWCounter/Timer B3 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINB.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKA = 0x10 - Clock source is buck converter stream from MEM Buck.
16TMRB3ENRWCounter/Timer B3 Enable bit.

+ DIS = 0x0 - Counter/Timer B3 Disable.
+ EN = 0x1 - Counter/Timer B3 Enable.
15ADCENRWSpecial Timer A3 enable for ADC function.

+
14RSVDRORESERVED

+
13TMRA3PERWCounter/Timer A3 Output Enable bit.

+ DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA3POL.
+ EN = 0x1 - Enable counter/timer A3 to generate a signal on TMRPINA.
12TMRA3POLRWCounter/Timer A3 output polarity.

+ NORMAL = 0x0 - The polarity of the TMRPINA3 pin is the same as the timer output.
+ INVERTED = 0x1 - The polarity of the TMRPINA3 pin is the inverse of the timer output.
11TMRA3CLRRWCounter/Timer A3 Clear bit.

+ RUN = 0x0 - Allow counter/timer A3 to run
+ CLEAR = 0x1 - Holds counter/timer A3 at 0x0000.
10TMRA3IE1RWCounter/Timer A3 Interrupt Enable bit based on COMPR1.

+ DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR1.
+ EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR1.
9TMRA3IE0RWCounter/Timer A3 Interrupt Enable bit based on COMPR0.

+ DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR0.
+ EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR0.
8:6TMRA3FNRWCounter/Timer A3 Function Select.

+ SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A3, stop.
+ REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.
+ PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop.
+ PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.
+ CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1TMRA3CLKRWCounter/Timer A3 Clock Select.

+ TMRPIN = 0x0 - Clock source is TMRPINA.
+ HFRC_DIV4 = 0x1 - Clock source is HFRC / 4
+ HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
+ HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
+ HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
+ HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
+ XT = 0x6 - Clock source is the XT (uncalibrated).
+ XT_DIV2 = 0x7 - Clock source is XT / 2
+ XT_DIV16 = 0x8 - Clock source is XT / 16
+ XT_DIV256 = 0x9 - Clock source is XT / 256
+ LFRC_DIV2 = 0xA - Clock source is LFRC / 2
+ LFRC_DIV32 = 0xB - Clock source is LFRC / 32
+ LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
+ LFRC = 0xD - Clock source is LFRC
+ RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
+ HCLK = 0xF - Clock source is HCLK.
+ BUCKB = 0x10 - Clock source is buck converter stream from CORE Buck.
0TMRA3ENRWCounter/Timer A3 Enable bit.

+ DIS = 0x0 - Counter/Timer A3 Disable.
+ EN = 0x1 - Counter/Timer A3 Enable.
+
+
+
+ +
+
+

STCFG - Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008100 +
+

Description:

+

The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
FREEZE +
0x1		CLEAR +
0x0		RSVD +
0x0		COMPARE_H_EN +
0x0		COMPARE_G_EN +
0x0		COMPARE_F_EN +
0x0		COMPARE_E_EN +
0x0		COMPARE_D_EN +
0x0		COMPARE_C_EN +
0x0		COMPARE_B_EN +
0x0		COMPARE_A_EN +
0x0		RSVD +
0x0		CLKSEL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31FREEZERWSet this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume.

+ THAW = 0x0 - Let the COUNTER register run on its input clock.
+ FREEZE = 0x1 - Stop the COUNTER register for loading.
30CLEARRWSet this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running.

+ RUN = 0x0 - Let the COUNTER register run on its input clock.
+ CLEAR = 0x1 - Stop the COUNTER register for loading.
29:16RSVDRORESERVED.

+
15COMPARE_H_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare H disabled.
+ ENABLE = 0x1 - Compare H enabled.
14COMPARE_G_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare G disabled.
+ ENABLE = 0x1 - Compare G enabled.
13COMPARE_F_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare F disabled.
+ ENABLE = 0x1 - Compare F enabled.
12COMPARE_E_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare E disabled.
+ ENABLE = 0x1 - Compare E enabled.
11COMPARE_D_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare D disabled.
+ ENABLE = 0x1 - Compare D enabled.
10COMPARE_C_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare C disabled.
+ ENABLE = 0x1 - Compare C enabled.
9COMPARE_B_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare B disabled.
+ ENABLE = 0x1 - Compare B enabled.
8COMPARE_A_ENRWSelects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.

+ DISABLE = 0x0 - Compare A disabled.
+ ENABLE = 0x1 - Compare A enabled.
7:4RSVDRORESERVED.

+
3:0CLKSELRWSelects an appropriate clock source and divider to use for the System Timer clock.

+ NOCLK = 0x0 - No clock enabled.
+ HFRC_DIV16 = 0x1 - 3MHz from the HFRC clock divider.
+ HFRC_DIV256 = 0x2 - 187.5KHz from the HFRC clock divider.
+ XTAL_DIV1 = 0x3 - 32768Hz from the crystal oscillator.
+ XTAL_DIV2 = 0x4 - 16384Hz from the crystal oscillator.
+ XTAL_DIV32 = 0x5 - 1024Hz from the crystal oscillator.
+ LFRC_DIV1 = 0x6 - Approximately 1KHz from the LFRC oscillator (uncalibrated).
+ CTIMER0A = 0x7 - Use CTIMER 0 section A as a prescaler for the clock source.
+ CTIMER0B = 0x8 - Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source.
+
+
+
+ +
+
+

STTMR - System Timer Count Register (Real Time Counter)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008104 +
+

Description:

+

The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is this counter value that is compared against the various compare registers. Writing to this register will ultimately set the COUNTER VALUE to the specified value. WARNING there is an asynchronous clock crossing on the read and write path which can add several STIMER clocks of uncertainty to reading or setting. Use the FREEZE bit in the DEBUG register to safely write to this register for diagnostic purposes.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROValue of the 32-bit counter as it ticks over.

+
+
+
+
+ +
+
+

CAPTURE_CONTROL - Capture Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008108 +
+

Description:

+

The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source, enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control individual capture registers atomically.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CAPTURE_D +
0x0		CAPTURE_C +
0x0		CAPTURE_B +
0x0		CAPTURE_A +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED.

+
3CAPTURE_DRWSelects whether capture is enabled for the specified capture register.

+ DISABLE = 0x0 - Capture function disabled.
+ ENABLE = 0x1 - Capture function enabled.
2CAPTURE_CRWSelects whether capture is enabled for the specified capture register.

+ DISABLE = 0x0 - Capture function disabled.
+ ENABLE = 0x1 - Capture function enabled.
1CAPTURE_BRWSelects whether capture is enabled for the specified capture register.

+ DISABLE = 0x0 - Capture function disabled.
+ ENABLE = 0x1 - Capture function enabled.
0CAPTURE_ARWSelects whether capture is enabled for the specified capture register.

+ DISABLE = 0x0 - Capture function disabled.
+ ENABLE = 0x1 - Capture function enabled.
+
+
+
+ +
+
+

SCMPR0 - Compare Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008110 +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR1 - Compare Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008114 +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR2 - Compare Register C

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008118 +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR3 - Compare Register D

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000811C +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR4 - Compare Register E

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008120 +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR5 - Compare Register F

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008124 +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR6 - Compare Register G

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008128 +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCMPR7 - Compare Register H

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000812C +
+

Description:

+

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWCompare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register.

+
+
+
+
+ +
+
+

SCAPT0 - Capture Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081E0 +
+

Description:

+

The STIMER capture Register A grabs the VALUE in the COUNTER register whenever capture condition (event) A is asserted. This register holds a time stamp for the event.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROWhenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

+
+
+
+
+ +
+
+

SCAPT1 - Capture Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081E4 +
+

Description:

+

The STIMER capture Register B grabs the VALUE in the COUNTER register whenever capture condition (event) B is asserted. This register holds a time stamp for the event.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROWhenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

+
+
+
+
+ +
+
+

SCAPT2 - Capture Register C

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081E8 +
+

Description:

+

The STIMER capture Register C grabs the VALUE in the COUNTER register whenever capture condition (event) C is asserted. This register holds a time stamp for the event.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROWhenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

+
+
+
+
+ +
+
+

SCAPT3 - Capture Register D

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081EC +
+

Description:

+

The STIMER capture Register D grabs the VALUE in the COUNTER register whenever capture condition (event) D is asserted. This register holds a time stamp for the event.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROWhenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

+
+
+
+
+ +
+
+

SNVR0 - System Timer NVRAM_A Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081F0 +
+

Description:

+

The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWValue of the 32-bit counter as it ticks over.

+
+
+
+
+ +
+
+

SNVR1 - System Timer NVRAM_B Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081F4 +
+

Description:

+

The NVRAM_B Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWValue of the 32-bit counter as it ticks over.

+
+
+
+
+ +
+
+

SNVR2 - System Timer NVRAM_C Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400081F8 +
+

Description:

+

The NVRAM_C Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWValue of the 32-bit counter as it ticks over.

+
+
+
+
+ +
+
+

INTEN - Counter/Timer Interrupts: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CTMRB3C1INT +
0x0		CTMRA3C1INT +
0x0		CTMRB2C1INT +
0x0		CTMRA2C1INT +
0x0		CTMRB1C1INT +
0x0		CTMRA1C1INT +
0x0		CTMRB0C1INT +
0x0		CTMRA0C1INT +
0x0		CTMRB3C0INT +
0x0		CTMRA3C0INT +
0x0		CTMRB2C0INT +
0x0		CTMRA2C0INT +
0x0		CTMRB1C0INT +
0x0		CTMRA1C0INT +
0x0		CTMRB0C0INT +
0x0		CTMRA0C0INT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15CTMRB3C1INTRWCounter/Timer B3 interrupt based on COMPR1.

+
14CTMRA3C1INTRWCounter/Timer A3 interrupt based on COMPR1.

+
13CTMRB2C1INTRWCounter/Timer B2 interrupt based on COMPR1.

+
12CTMRA2C1INTRWCounter/Timer A2 interrupt based on COMPR1.

+
11CTMRB1C1INTRWCounter/Timer B1 interrupt based on COMPR1.

+
10CTMRA1C1INTRWCounter/Timer A1 interrupt based on COMPR1.

+
9CTMRB0C1INTRWCounter/Timer B0 interrupt based on COMPR1.

+
8CTMRA0C1INTRWCounter/Timer A0 interrupt based on COMPR1.

+
7CTMRB3C0INTRWCounter/Timer B3 interrupt based on COMPR0.

+
6CTMRA3C0INTRWCounter/Timer A3 interrupt based on COMPR0.

+
5CTMRB2C0INTRWCounter/Timer B2 interrupt based on COMPR0.

+
4CTMRA2C0INTRWCounter/Timer A2 interrupt based on COMPR0.

+
3CTMRB1C0INTRWCounter/Timer B1 interrupt based on COMPR0.

+
2CTMRA1C0INTRWCounter/Timer A1 interrupt based on COMPR0.

+
1CTMRB0C0INTRWCounter/Timer B0 interrupt based on COMPR0.

+
0CTMRA0C0INTRWCounter/Timer A0 interrupt based on COMPR0.

+
+
+
+
+ +
+
+

INTSTAT - Counter/Timer Interrupts: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CTMRB3C1INT +
0x0		CTMRA3C1INT +
0x0		CTMRB2C1INT +
0x0		CTMRA2C1INT +
0x0		CTMRB1C1INT +
0x0		CTMRA1C1INT +
0x0		CTMRB0C1INT +
0x0		CTMRA0C1INT +
0x0		CTMRB3C0INT +
0x0		CTMRA3C0INT +
0x0		CTMRB2C0INT +
0x0		CTMRA2C0INT +
0x0		CTMRB1C0INT +
0x0		CTMRA1C0INT +
0x0		CTMRB0C0INT +
0x0		CTMRA0C0INT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15CTMRB3C1INTRWCounter/Timer B3 interrupt based on COMPR1.

+
14CTMRA3C1INTRWCounter/Timer A3 interrupt based on COMPR1.

+
13CTMRB2C1INTRWCounter/Timer B2 interrupt based on COMPR1.

+
12CTMRA2C1INTRWCounter/Timer A2 interrupt based on COMPR1.

+
11CTMRB1C1INTRWCounter/Timer B1 interrupt based on COMPR1.

+
10CTMRA1C1INTRWCounter/Timer A1 interrupt based on COMPR1.

+
9CTMRB0C1INTRWCounter/Timer B0 interrupt based on COMPR1.

+
8CTMRA0C1INTRWCounter/Timer A0 interrupt based on COMPR1.

+
7CTMRB3C0INTRWCounter/Timer B3 interrupt based on COMPR0.

+
6CTMRA3C0INTRWCounter/Timer A3 interrupt based on COMPR0.

+
5CTMRB2C0INTRWCounter/Timer B2 interrupt based on COMPR0.

+
4CTMRA2C0INTRWCounter/Timer A2 interrupt based on COMPR0.

+
3CTMRB1C0INTRWCounter/Timer B1 interrupt based on COMPR0.

+
2CTMRA1C0INTRWCounter/Timer A1 interrupt based on COMPR0.

+
1CTMRB0C0INTRWCounter/Timer B0 interrupt based on COMPR0.

+
0CTMRA0C0INTRWCounter/Timer A0 interrupt based on COMPR0.

+
+
+
+
+ +
+
+

INTCLR - Counter/Timer Interrupts: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CTMRB3C1INT +
0x0		CTMRA3C1INT +
0x0		CTMRB2C1INT +
0x0		CTMRA2C1INT +
0x0		CTMRB1C1INT +
0x0		CTMRA1C1INT +
0x0		CTMRB0C1INT +
0x0		CTMRA0C1INT +
0x0		CTMRB3C0INT +
0x0		CTMRA3C0INT +
0x0		CTMRB2C0INT +
0x0		CTMRA2C0INT +
0x0		CTMRB1C0INT +
0x0		CTMRA1C0INT +
0x0		CTMRB0C0INT +
0x0		CTMRA0C0INT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15CTMRB3C1INTRWCounter/Timer B3 interrupt based on COMPR1.

+
14CTMRA3C1INTRWCounter/Timer A3 interrupt based on COMPR1.

+
13CTMRB2C1INTRWCounter/Timer B2 interrupt based on COMPR1.

+
12CTMRA2C1INTRWCounter/Timer A2 interrupt based on COMPR1.

+
11CTMRB1C1INTRWCounter/Timer B1 interrupt based on COMPR1.

+
10CTMRA1C1INTRWCounter/Timer A1 interrupt based on COMPR1.

+
9CTMRB0C1INTRWCounter/Timer B0 interrupt based on COMPR1.

+
8CTMRA0C1INTRWCounter/Timer A0 interrupt based on COMPR1.

+
7CTMRB3C0INTRWCounter/Timer B3 interrupt based on COMPR0.

+
6CTMRA3C0INTRWCounter/Timer A3 interrupt based on COMPR0.

+
5CTMRB2C0INTRWCounter/Timer B2 interrupt based on COMPR0.

+
4CTMRA2C0INTRWCounter/Timer A2 interrupt based on COMPR0.

+
3CTMRB1C0INTRWCounter/Timer B1 interrupt based on COMPR0.

+
2CTMRA1C0INTRWCounter/Timer A1 interrupt based on COMPR0.

+
1CTMRB0C0INTRWCounter/Timer B0 interrupt based on COMPR0.

+
0CTMRA0C0INTRWCounter/Timer A0 interrupt based on COMPR0.

+
+
+
+
+ +
+
+

INTSET - Counter/Timer Interrupts: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000820C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CTMRB3C1INT +
0x0		CTMRA3C1INT +
0x0		CTMRB2C1INT +
0x0		CTMRA2C1INT +
0x0		CTMRB1C1INT +
0x0		CTMRA1C1INT +
0x0		CTMRB0C1INT +
0x0		CTMRA0C1INT +
0x0		CTMRB3C0INT +
0x0		CTMRA3C0INT +
0x0		CTMRB2C0INT +
0x0		CTMRA2C0INT +
0x0		CTMRB1C0INT +
0x0		CTMRA1C0INT +
0x0		CTMRB0C0INT +
0x0		CTMRA0C0INT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15CTMRB3C1INTRWCounter/Timer B3 interrupt based on COMPR1.

+
14CTMRA3C1INTRWCounter/Timer A3 interrupt based on COMPR1.

+
13CTMRB2C1INTRWCounter/Timer B2 interrupt based on COMPR1.

+
12CTMRA2C1INTRWCounter/Timer A2 interrupt based on COMPR1.

+
11CTMRB1C1INTRWCounter/Timer B1 interrupt based on COMPR1.

+
10CTMRA1C1INTRWCounter/Timer A1 interrupt based on COMPR1.

+
9CTMRB0C1INTRWCounter/Timer B0 interrupt based on COMPR1.

+
8CTMRA0C1INTRWCounter/Timer A0 interrupt based on COMPR1.

+
7CTMRB3C0INTRWCounter/Timer B3 interrupt based on COMPR0.

+
6CTMRA3C0INTRWCounter/Timer A3 interrupt based on COMPR0.

+
5CTMRB2C0INTRWCounter/Timer B2 interrupt based on COMPR0.

+
4CTMRA2C0INTRWCounter/Timer A2 interrupt based on COMPR0.

+
3CTMRB1C0INTRWCounter/Timer B1 interrupt based on COMPR0.

+
2CTMRA1C0INTRWCounter/Timer A1 interrupt based on COMPR0.

+
1CTMRB0C0INTRWCounter/Timer B0 interrupt based on COMPR0.

+
0CTMRA0C0INTRWCounter/Timer A0 interrupt based on COMPR0.

+
+
+
+
+ +
+
+

STMINTEN - STIMER Interrupt registers: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008300 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CAPTURED +
0x0		CAPTUREC +
0x0		CAPTUREB +
0x0		CAPTUREA +
0x0		OVERFLOW +
0x0		COMPAREH +
0x0		COMPAREG +
0x0		COMPAREF +
0x0		COMPAREE +
0x0		COMPARED +
0x0		COMPAREC +
0x0		COMPAREB +
0x0		COMPAREA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:13RSVDRORESERVED.

+
12CAPTUREDRWCAPTURE register D has grabbed the value in the counter

+ CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11CAPTURECRWCAPTURE register C has grabbed the value in the counter

+ CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10CAPTUREBRWCAPTURE register B has grabbed the value in the counter

+ CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9CAPTUREARWCAPTURE register A has grabbed the value in the counter

+ CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8OVERFLOWRWCOUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

+ OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7COMPAREHRWCOUNTER is greater than or equal to COMPARE register H.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6COMPAREGRWCOUNTER is greater than or equal to COMPARE register G.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5COMPAREFRWCOUNTER is greater than or equal to COMPARE register F.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4COMPAREERWCOUNTER is greater than or equal to COMPARE register E.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3COMPAREDRWCOUNTER is greater than or equal to COMPARE register D.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2COMPARECRWCOUNTER is greater than or equal to COMPARE register C.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1COMPAREBRWCOUNTER is greater than or equal to COMPARE register B.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0COMPAREARWCOUNTER is greater than or equal to COMPARE register A.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
+
+
+
+ +
+
+

STMINTSTAT - STIMER Interrupt registers: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008304 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CAPTURED +
0x0		CAPTUREC +
0x0		CAPTUREB +
0x0		CAPTUREA +
0x0		OVERFLOW +
0x0		COMPAREH +
0x0		COMPAREG +
0x0		COMPAREF +
0x0		COMPAREE +
0x0		COMPARED +
0x0		COMPAREC +
0x0		COMPAREB +
0x0		COMPAREA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:13RSVDRORESERVED.

+
12CAPTUREDRWCAPTURE register D has grabbed the value in the counter

+ CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11CAPTURECRWCAPTURE register C has grabbed the value in the counter

+ CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10CAPTUREBRWCAPTURE register B has grabbed the value in the counter

+ CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9CAPTUREARWCAPTURE register A has grabbed the value in the counter

+ CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8OVERFLOWRWCOUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

+ OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7COMPAREHRWCOUNTER is greater than or equal to COMPARE register H.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6COMPAREGRWCOUNTER is greater than or equal to COMPARE register G.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5COMPAREFRWCOUNTER is greater than or equal to COMPARE register F.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4COMPAREERWCOUNTER is greater than or equal to COMPARE register E.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3COMPAREDRWCOUNTER is greater than or equal to COMPARE register D.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2COMPARECRWCOUNTER is greater than or equal to COMPARE register C.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1COMPAREBRWCOUNTER is greater than or equal to COMPARE register B.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0COMPAREARWCOUNTER is greater than or equal to COMPARE register A.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
+
+
+
+ +
+
+

STMINTCLR - STIMER Interrupt registers: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40008308 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CAPTURED +
0x0		CAPTUREC +
0x0		CAPTUREB +
0x0		CAPTUREA +
0x0		OVERFLOW +
0x0		COMPAREH +
0x0		COMPAREG +
0x0		COMPAREF +
0x0		COMPAREE +
0x0		COMPARED +
0x0		COMPAREC +
0x0		COMPAREB +
0x0		COMPAREA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:13RSVDRORESERVED.

+
12CAPTUREDRWCAPTURE register D has grabbed the value in the counter

+ CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11CAPTURECRWCAPTURE register C has grabbed the value in the counter

+ CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10CAPTUREBRWCAPTURE register B has grabbed the value in the counter

+ CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9CAPTUREARWCAPTURE register A has grabbed the value in the counter

+ CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8OVERFLOWRWCOUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

+ OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7COMPAREHRWCOUNTER is greater than or equal to COMPARE register H.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6COMPAREGRWCOUNTER is greater than or equal to COMPARE register G.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5COMPAREFRWCOUNTER is greater than or equal to COMPARE register F.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4COMPAREERWCOUNTER is greater than or equal to COMPARE register E.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3COMPAREDRWCOUNTER is greater than or equal to COMPARE register D.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2COMPARECRWCOUNTER is greater than or equal to COMPARE register C.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1COMPAREBRWCOUNTER is greater than or equal to COMPARE register B.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0COMPAREARWCOUNTER is greater than or equal to COMPARE register A.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
+
+
+
+ +
+
+

STMINTSET - STIMER Interrupt registers: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000830C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CAPTURED +
0x0		CAPTUREC +
0x0		CAPTUREB +
0x0		CAPTUREA +
0x0		OVERFLOW +
0x0		COMPAREH +
0x0		COMPAREG +
0x0		COMPAREF +
0x0		COMPAREE +
0x0		COMPARED +
0x0		COMPAREC +
0x0		COMPAREB +
0x0		COMPAREA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:13RSVDRORESERVED.

+
12CAPTUREDRWCAPTURE register D has grabbed the value in the counter

+ CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11CAPTURECRWCAPTURE register C has grabbed the value in the counter

+ CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10CAPTUREBRWCAPTURE register B has grabbed the value in the counter

+ CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9CAPTUREARWCAPTURE register A has grabbed the value in the counter

+ CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8OVERFLOWRWCOUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

+ OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7COMPAREHRWCOUNTER is greater than or equal to COMPARE register H.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6COMPAREGRWCOUNTER is greater than or equal to COMPARE register G.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5COMPAREFRWCOUNTER is greater than or equal to COMPARE register F.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4COMPAREERWCOUNTER is greater than or equal to COMPARE register E.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3COMPAREDRWCOUNTER is greater than or equal to COMPARE register D.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2COMPARECRWCOUNTER is greater than or equal to COMPARE register C.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1COMPAREBRWCOUNTER is greater than or equal to COMPARE register B.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0COMPAREARWCOUNTER is greater than or equal to COMPARE register A.

+ COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/gpio_regs.html b/docs/apollo2/pages/gpio_regs.html new file mode 100644 index 0000000..ec6ecd5 --- /dev/null +++ b/docs/apollo2/pages/gpio_regs.html @@ -0,0 +1,17677 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
GPIO - General Purpose IO
+
+
+ + +
+
+
+

GPIO Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + PADREGA - Pad Configuration Register A +
+   + 0x00000004: + +   + PADREGB - Pad Configuration Register B +
+   + 0x00000008: + +   + PADREGC - Pad Configuration Register C +
+   + 0x0000000C: + +   + PADREGD - Pad Configuration Register D +
+   + 0x00000010: + +   + PADREGE - Pad Configuration Register E +
+   + 0x00000014: + +   + PADREGF - Pad Configuration Register F +
+   + 0x00000018: + +   + PADREGG - Pad Configuration Register G +
+   + 0x0000001C: + +   + PADREGH - Pad Configuration Register H +
+   + 0x00000020: + +   + PADREGI - Pad Configuration Register I +
+   + 0x00000024: + +   + PADREGJ - Pad Configuration Register J +
+   + 0x00000028: + +   + PADREGK - Pad Configuration Register K +
+   + 0x0000002C: + +   + PADREGL - Pad Configuration Register L +
+   + 0x00000030: + +   + PADREGM - Pad Configuration Register M +
+   + 0x00000040: + +   + CFGA - GPIO Configuration Register A +
+   + 0x00000044: + +   + CFGB - GPIO Configuration Register B +
+   + 0x00000048: + +   + CFGC - GPIO Configuration Register C +
+   + 0x0000004C: + +   + CFGD - GPIO Configuration Register D +
+   + 0x00000050: + +   + CFGE - GPIO Configuration Register E +
+   + 0x00000054: + +   + CFGF - GPIO Configuration Register F +
+   + 0x00000058: + +   + CFGG - GPIO Configuration Register G +
+   + 0x00000060: + +   + PADKEY - Key Register for all pad configuration registers +
+   + 0x00000080: + +   + RDA - GPIO Input Register A +
+   + 0x00000084: + +   + RDB - GPIO Input Register B +
+   + 0x00000088: + +   + WTA - GPIO Output Register A +
+   + 0x0000008C: + +   + WTB - GPIO Output Register B +
+   + 0x00000090: + +   + WTSA - GPIO Output Register A Set +
+   + 0x00000094: + +   + WTSB - GPIO Output Register B Set +
+   + 0x00000098: + +   + WTCA - GPIO Output Register A Clear +
+   + 0x0000009C: + +   + WTCB - GPIO Output Register B Clear +
+   + 0x000000A0: + +   + ENA - GPIO Enable Register A +
+   + 0x000000A4: + +   + ENB - GPIO Enable Register B +
+   + 0x000000A8: + +   + ENSA - GPIO Enable Register A Set +
+   + 0x000000AC: + +   + ENSB - GPIO Enable Register B Set +
+   + 0x000000B4: + +   + ENCA - GPIO Enable Register A Clear +
+   + 0x000000B8: + +   + ENCB - GPIO Enable Register B Clear +
+   + 0x000000BC: + +   + STMRCAP - STIMER Capture Control +
+   + 0x000000C0: + +   + IOM0IRQ - IOM0 Flow Control IRQ Select +
+   + 0x000000C4: + +   + IOM1IRQ - IOM1 Flow Control IRQ Select +
+   + 0x000000C8: + +   + IOM2IRQ - IOM2 Flow Control IRQ Select +
+   + 0x000000CC: + +   + IOM3IRQ - IOM3 Flow Control IRQ Select +
+   + 0x000000D0: + +   + IOM4IRQ - IOM4 Flow Control IRQ Select +
+   + 0x000000D4: + +   + IOM5IRQ - IOM5 Flow Control IRQ Select +
+   + 0x000000D8: + +   + LOOPBACK - IOM to IOS Loopback Control +
+   + 0x000000DC: + +   + GPIOOBS - GPIO Observation Mode Sample register +
+   + 0x000000E0: + +   + ALTPADCFGA - Alternate Pad Configuration reg0 (Pads 3,2,1,0) +
+   + 0x000000E4: + +   + ALTPADCFGB - Alternate Pad Configuration reg1 (Pads 7,6,5,4) +
+   + 0x000000E8: + +   + ALTPADCFGC - Alternate Pad Configuration reg2 (Pads 11,10,9,8) +
+   + 0x000000EC: + +   + ALTPADCFGD - Alternate Pad Configuration reg3 (Pads 15,14,13,12) +
+   + 0x000000F0: + +   + ALTPADCFGE - Alternate Pad Configuration reg4 (Pads 19,18,17,16) +
+   + 0x000000F4: + +   + ALTPADCFGF - Alternate Pad Configuration reg5 (Pads 23,22,21,20) +
+   + 0x000000F8: + +   + ALTPADCFGG - Alternate Pad Configuration reg6 (Pads 27,26,25,24) +
+   + 0x000000FC: + +   + ALTPADCFGH - Alternate Pad Configuration reg7 (Pads 31,30,29,28) +
+   + 0x00000100: + +   + ALTPADCFGI - Alternate Pad Configuration reg8 (Pads 35,34,33,32) +
+   + 0x00000104: + +   + ALTPADCFGJ - Alternate Pad Configuration reg9 (Pads 39,38,37,36) +
+   + 0x00000108: + +   + ALTPADCFGK - Alternate Pad Configuration reg10 (Pads 43,42,41,40) +
+   + 0x0000010C: + +   + ALTPADCFGL - Alternate Pad Configuration reg11 (Pads 47,46,45,44) +
+   + 0x00000110: + +   + ALTPADCFGM - Alternate Pad Configuration reg12 (Pads 49,48) +
+   + 0x00000200: + +   + INT0EN - GPIO Interrupt Registers 31-0: Enable +
+   + 0x00000204: + +   + INT0STAT - GPIO Interrupt Registers 31-0: Status +
+   + 0x00000208: + +   + INT0CLR - GPIO Interrupt Registers 31-0: Clear +
+   + 0x0000020C: + +   + INT0SET - GPIO Interrupt Registers 31-0: Set +
+   + 0x00000210: + +   + INT1EN - GPIO Interrupt Registers 49-32: Enable +
+   + 0x00000214: + +   + INT1STAT - GPIO Interrupt Registers 49-32: Status +
+   + 0x00000218: + +   + INT1CLR - GPIO Interrupt Registers 49-32: Clear +
+   + 0x0000021C: + +   + INT1SET - GPIO Interrupt Registers 49-32: Set +
+
+
+ +
+
+

PADREGA - Pad Configuration Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010000 +
+

Description:

+

This register controls the pad configuration controls for PAD3 through PAD0. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD3FNCSEL +
0x3		PAD3STRNG +
0x0		PAD3INPEN +
0x0		PAD3PULL +
0x0		RSVD +
0x0		PAD2FNCSEL +
0x3		PAD2STRNG +
0x0		PAD2INPEN +
0x0		PAD2PULL +
0x0		PAD1RSEL +
0x0		PAD1FNCSEL +
0x3		PAD1STRNG +
0x0		PAD1INPEN +
0x0		PAD1PULL +
0x0		PAD0RSEL +
0x0		PAD0FNCSEL +
0x3		PAD0STRNG +
0x0		PAD0INPEN +
0x0		PAD0PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD3FNCSELRWPad 3 function select

+ UA0RTS = 0x0 - Configure as the UART0 RTS output
+ SLnCE = 0x1 - Configure as the IOSLAVE SPI nCE signal
+ M1nCE4 = 0x2 - Configure as the SPI channel 4 nCE signal from IOMSTR1
+ GPIO3 = 0x3 - Configure as GPIO3
+ MxnCELB = 0x4 - Configure as the IOSLAVE SPI nCE loopback signal from IOMSTRx
+ M2nCE0 = 0x5 - Configure as the SPI channel 0 nCE signal from IOMSTR2
+ TRIG1 = 0x6 - Configure as the ADC Trigger 1 signal
+ I2S_WCLK = 0x7 - Configure as the I2S Word Clock input
26PAD3STRNGRWPad 3 drive strength.

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD3INPENRWPad 3 input enable.

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD3PULLRWPad 3 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD2FNCSELRWPad 2 function select

+ SLWIR3 = 0x0 - Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal
+ SLMOSI = 0x1 - Configure as the IOSLAVE SPI MOSI signal
+ UART0RX = 0x2 - Configure as the UART0 RX input
+ GPIO2 = 0x3 - Configure as GPIO2
+ MxMOSILB = 0x4 - Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTRx
+ M2MOSI = 0x5 - Configure as the IOMSTR2 SPI MOSI output signal
+ MxWIR3LB = 0x6 - Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTRx
+ M2WIR3 = 0x7 - Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal
18PAD2STRNGRWPad 2 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD2INPENRWPad 2 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD2PULLRWPad 2 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14PAD1RSELRWPad 1 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
13:11PAD1FNCSELRWPad 1 function select

+ SLSDA = 0x0 - Configure as the IOSLAVE I2C SDA signal
+ SLMISO = 0x1 - Configure as the IOSLAVE SPI MISO signal
+ UART0TX = 0x2 - Configure as the UART0 TX output signal
+ GPIO1 = 0x3 - Configure as GPIO1
+ MxMISOLB = 0x4 - Configure as the IOSLAVE SPI MISO loopback signal from IOMSTRx
+ M2MISO = 0x5 - Configure as the IOMSTR2 SPI MISO input signal
+ MxSDALB = 0x6 - Configure as the IOSLAVE I2C SDA loopback signal from IOMSTRx
+ M2SDA = 0x7 - Configure as the IOMSTR2 I2C Serial data I/O signal
10PAD1STRNGRWPad 1 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD1INPENRWPad 1 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD1PULLRWPad 1 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6PAD0RSELRWPad 0 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
5:3PAD0FNCSELRWPad 0 function select

+ SLSCL = 0x0 - Configure as the IOSLAVE I2C SCL signal
+ SLSCK = 0x1 - Configure as the IOSLAVE SPI SCK signal
+ CLKOUT = 0x2 - Configure as the CLKOUT signal
+ GPIO0 = 0x3 - Configure as GPIO0
+ MxSCKLB = 0x4 - Configure as the IOSLAVE SPI SCK loopback signal from IOMSTRx
+ M2SCK = 0x5 - Configure as the IOMSTR2 SPI SCK output
+ MxSCLLB = 0x6 - Configure as the IOSLAVE I2C SCL loopback signal from IOMSTRx
+ M2SCL = 0x7 - Configure as the IOMSTR2 I2C SCL clock I/O signal
2PAD0STRNGRWPad 0 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD0INPENRWPad 0 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD0PULLRWPad 0 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGB - Pad Configuration Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010004 +
+

Description:

+

This register controls the pad configuration controls for PAD7 through PAD4. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD7FNCSEL +
0x3		PAD7STRNG +
0x0		PAD7INPEN +
0x0		PAD7PULL +
0x0		PAD6RSEL +
0x0		PAD6FNCSEL +
0x3		PAD6STRNG +
0x0		PAD6INPEN +
0x0		PAD6PULL +
0x0		PAD5RSEL +
0x0		PAD5FNCSEL +
0x3		PAD5STRNG +
0x0		PAD5INPEN +
0x0		PAD5PULL +
0x0		PAD4PWRDN +
0x0		RSVD +
0x0		PAD4FNCSEL +
0x3		PAD4STRNG +
0x0		PAD4INPEN +
0x0		PAD4PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD7FNCSELRWPad 7 function select

+ M0WIR3 = 0x0 - Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal
+ M0MOSI = 0x1 - Configure as the IOMSTR0 SPI MOSI signal
+ CLKOUT = 0x2 - Configure as the CLKOUT signal
+ GPIO7 = 0x3 - Configure as GPIO7
+ TRIG0 = 0x4 - Configure as the ADC Trigger 0 signal
+ UART0TX = 0x5 - Configure as the UART0 TX output signal
+ SLWIR3LB = 0x6 - Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE
+ M1nCE1 = 0x7 - Configure as the SPI channel 1 nCE signal from IOMSTR1
26PAD7STRNGRWPad 7 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD7INPENRWPad 7 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD7PULLRWPad 7 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22PAD6RSELRWPad 6 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
21:19PAD6FNCSELRWPad 6 function select

+ M0SDA = 0x0 - Configure as the IOMSTR0 I2C SDA signal
+ M0MISO = 0x1 - Configure as the IOMSTR0 SPI MISO signal
+ UA0CTS = 0x2 - Configure as the UART0 CTS input signal
+ GPIO6 = 0x3 - Configure as GPIO6
+ SLMISOLB = 0x4 - Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE
+ M1nCE0 = 0x5 - Configure as the SPI channel 0 nCE signal from IOMSTR1
+ SLSDALB = 0x6 - Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE
+ I2S_DAT = 0x7 - Configure as the I2S Data output signal
18PAD6STRNGRWPad 6 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD6INPENRWPad 6 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD6PULLRWPad 6 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14PAD5RSELRWPad 5 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
13:11PAD5FNCSELRWPad 5 function select

+ M0SCL = 0x0 - Configure as the IOMSTR0 I2C SCL signal
+ M0SCK = 0x1 - Configure as the IOMSTR0 SPI SCK signal
+ UA0RTS = 0x2 - Configure as the UART0 RTS signal output
+ GPIO5 = 0x3 - Configure as GPIO5
+ M0SCKLB = 0x4 - Configure as the IOMSTR0 SPI SCK loopback signal from IOSLAVE
+ EXTHFA = 0x5 - Configure as the External HFA input clock
+ M0SCLLB = 0x6 - Configure as the IOMSTR0 I2C SCL loopback signal from IOSLAVE
+ M1nCE2 = 0x7 - Configure as the SPI Channel 2 nCE signal from IOMSTR1
10PAD5STRNGRWPad 5 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD5INPENRWPad 5 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD5PULLRWPad 5 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7PAD4PWRDNRWPad 4 VSS power switch enable

+ DIS = 0x0 - Power switch disabled
+ EN = 0x1 - Power switch enabled (switch to GND)
6RSVDRORESERVED

+
5:3PAD4FNCSELRWPad 4 function select

+ UA0CTS = 0x0 - Configure as the UART0 CTS input signal
+ SLINT = 0x1 - Configure as the IOSLAVE interrupt out signal
+ M0nCE5 = 0x2 - Configure as the SPI channel 5 nCE signal from IOMSTR0
+ GPIO4 = 0x3 - Configure as GPIO4
+ SLINTGP = 0x4 - Configure as the IOSLAVE interrupt loopback signal
+ M2nCE5 = 0x5 - Configure as the SPI channel 5 nCE signal from IOMSTR2
+ CLKOUT = 0x6 - Configure as the CLKOUT signal
+ 32khz_XT = 0x7 - Configure as the 32kHz crystal output signal
2PAD4STRNGRWPad 4 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD4INPENRWPad 4 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD4PULLRWPad 4 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGC - Pad Configuration Register C

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010008 +
+

Description:

+

This register controls the pad configuration controls for PAD11 through PAD8. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD11FNCSEL +
0x3		PAD11STRNG +
0x0		PAD11INPEN +
0x0		PAD11PULL +
0x0		RSVD +
0x0		PAD10FNCSEL +
0x3		PAD10STRNG +
0x0		PAD10INPEN +
0x0		PAD10PULL +
0x0		PAD9RSEL +
0x0		PAD9FNCSEL +
0x3		PAD9STRNG +
0x0		PAD9INPEN +
0x0		PAD9PULL +
0x0		PAD8RSEL +
0x0		PAD8FNCSEL +
0x3		PAD8STRNG +
0x0		PAD8INPEN +
0x0		PAD8PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD11FNCSELRWPad 11 function select

+ ADCSE2 = 0x0 - Configure as the analog input for ADC single ended input 2
+ M0nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR0
+ CLKOUT = 0x2 - Configure as the CLKOUT signal
+ GPIO11 = 0x3 - Configure as GPIO11
+ M2nCE7 = 0x4 - Configure as the SPI channel 7 nCE signal from IOMSTR2
+ UA1CTS = 0x5 - Configure as the UART1 CTS input signal
+ UART0RX = 0x6 - Configure as the UART0 RX input signal
+ PDM_DATA = 0x7 - Configure as the PDM Data input signal
26PAD11STRNGRWPad 11 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD11INPENRWPad 11 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD11PULLRWPad 11 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD10FNCSELRWPad 10 function select

+ M1WIR3 = 0x0 - Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal
+ M1MOSI = 0x1 - Configure as the IOMSTR1 SPI MOSI signal
+ M0nCE6 = 0x2 - Configure as the SPI channel 6 nCE signal from IOMSTR0
+ GPIO10 = 0x3 - Configure as GPIO10
+ M2nCE6 = 0x4 - Configure as the SPI channel 6 nCE signal from IOMSTR2
+ UA1RTS = 0x5 - Configure as the UART1 RTS output signal
+ M4nCE4 = 0x6 - Configure as the SPI channel 4 nCE signal from the IOMSTR4
+ SLWIR3LB = 0x7 - Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE
18PAD10STRNGRWPad 10 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD10INPENRWPad 10 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD10PULLRWPad 10 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14PAD9RSELRWPad 9 pullup resistor selection

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
13:11PAD9FNCSELRWPad 9 function select

+ M1SDA = 0x0 - Configure as the IOMSTR1 I2C SDA signal
+ M1MISO = 0x1 - Configure as the IOMSTR1 SPI MISO signal
+ M0nCE5 = 0x2 - Configure as the SPI channel 5 nCE signal from IOMSTR0
+ GPIO9 = 0x3 - Configure as GPIO9
+ M4nCE5 = 0x4 - Configure as the SPI channel 5 nCE signal from IOMSTR4
+ SLMISOLB = 0x5 - Configure as the IOMSTR1 SPI MISO loopback signal from IOSLAVE
+ UART1RX = 0x6 - Configure as UART1 RX input signal
+ SLSDALB = 0x7 - Configure as the IOMSTR1 I2C SDA loopback signal from IOSLAVE
10PAD9STRNGRWPad 9 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD9INPENRWPad 9 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD9PULLRWPad 9 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6PAD8RSELRWPad 8 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
5:3PAD8FNCSELRWPad 8 function select

+ M1SCL = 0x0 - Configure as the IOMSTR1 I2C SCL signal
+ M1SCK = 0x1 - Configure as the IOMSTR1 SPI SCK signal
+ M0nCE4 = 0x2 - Configure as the SPI channel 4 nCE signal from IOMSTR0
+ GPIO8 = 0x3 - Configure as GPIO8
+ M2nCE4 = 0x4 - Configure as the SPI channel 4 nCE signal from IOMSTR2
+ M1SCKLB = 0x5 - Configure as the IOMSTR1 SPI SCK loopback signal from IOSLAVE
+ UART1TX = 0x6 - Configure as the UART1 TX output signal
+ M1SCLLB = 0x7 - Configure as the IOMSTR1 I2C SCL loopback signal from IOSLAVE
2PAD8STRNGRWPad 8 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD8INPENRWPad 8 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD8PULLRWPad 8 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGD - Pad Configuration Register D

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001000C +
+

Description:

+

This register controls the pad configuration controls for PAD15 through PAD12. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD15FNCSEL +
0x3		PAD15STRNG +
0x0		PAD15INPEN +
0x0		PAD15PULL +
0x0		RSVD +
0x0		PAD14FNCSEL +
0x3		PAD14STRNG +
0x0		PAD14INPEN +
0x0		PAD14PULL +
0x0		RSVD +
0x0		PAD13FNCSEL +
0x3		PAD13STRNG +
0x0		PAD13INPEN +
0x0		PAD13PULL +
0x0		RSVD +
0x0		PAD12FNCSEL +
0x3		PAD12STRNG +
0x0		PAD12INPEN +
0x0		PAD12PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD15FNCSELRWPad 15 function select

+ ADCD1N = 0x0 - Configure as the analog ADC differential pair 1 N input signal
+ M1nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR1
+ UART1RX = 0x2 - Configure as the UART1 RX signal
+ GPIO15 = 0x3 - Configure as GPIO15
+ M2nCE2 = 0x4 - Configure as the SPI Channel 2 nCE signal from IOMSTR2
+ EXTXT = 0x5 - Configure as the external XTAL oscillator input
+ SWDIO = 0x6 - Configure as an alternate port for the SWDIO I/O signal
+ SWO = 0x7 - Configure as an SWO (Serial Wire Trace output)
26PAD15STRNGRWPad 15 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD15INPENRWPad 15 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD15PULLRWPad 15 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD14FNCSELRWPad 14 function select

+ ADCD1P = 0x0 - Configure as the analog ADC differential pair 1 P input signal
+ M1nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR1
+ UART1TX = 0x2 - Configure as the UART1 TX output signal
+ GPIO14 = 0x3 - Configure as GPIO14
+ M2nCE1 = 0x4 - Configure as the SPI channel 1 nCE signal from IOMSTR2
+ EXTHFS = 0x5 - Configure as the External HFRC oscillator input select
+ SWDCK = 0x6 - Configure as the alternate input for the SWDCK input signal
+ 32khz_XT = 0x7 - Configure as the 32kHz crystal output signal
18PAD14STRNGRWPad 14 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD14INPENRWPad 14 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD14PULLRWPad 14 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD13FNCSELRWPad 13 function select

+ ADCD0PSE8 = 0x0 - Configure as the ADC Differential pair 0 P, or Single Ended input 8 analog input signal. Determination of the D0P vs SE8 usage is done when the particular channel is selected within the ADC module
+ M1nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR1
+ TCTB0 = 0x2 - Configure as the input/output signal from CTIMER B0
+ GPIO13 = 0x3 - Configure as GPIO13
+ M2nCE3 = 0x4 - Configure as the SPI channel 3 nCE signal from IOMSTR2
+ EXTHFB = 0x5 - Configure as the external HFRC oscillator input
+ UA0RTS = 0x6 - Configure as the UART0 RTS signal output
+ UART1RX = 0x7 - Configure as the UART1 RX input signal
10PAD13STRNGRWPad 13 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD13INPENRWPad 13 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD13PULLRWPad 13 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD12FNCSELRWPad 12 function select

+ ADCD0NSE9 = 0x0 - Configure as the ADC Differential pair 0 N, or Single Ended input 9 analog input signal. Determination of the D0N vs SE9 usage is done when the particular channel is selected within the ADC module
+ M1nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR1
+ TCTA0 = 0x2 - Configure as the input/output signal from CTIMER A0
+ GPIO12 = 0x3 - Configure as GPIO12
+ CLKOUT = 0x4 - Configure as CLKOUT signal
+ PDM_CLK = 0x5 - Configure as the PDM CLK output signal
+ UA0CTS = 0x6 - Configure as the UART0 CTS input signal
+ UART1TX = 0x7 - Configure as the UART1 TX output signal
2PAD12STRNGRWPad 12 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD12INPENRWPad 12 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD12PULLRWPad 12 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGE - Pad Configuration Register E

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010010 +
+

Description:

+

This register controls the pad configuration controls for PAD19 through PAD16. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD19FNCSEL +
0x3		PAD19STRNG +
0x0		PAD19INPEN +
0x0		PAD19PULL +
0x0		RSVD +
0x0		PAD18FNCSEL +
0x3		PAD18STRNG +
0x0		PAD18INPEN +
0x0		PAD18PULL +
0x0		RSVD +
0x0		PAD17FNCSEL +
0x3		PAD17STRNG +
0x0		PAD17INPEN +
0x0		PAD17PULL +
0x0		RSVD +
0x0		PAD16FNCSEL +
0x3		PAD16STRNG +
0x0		PAD16INPEN +
0x0		PAD16PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD19FNCSELRWPad 19 function select

+ CMPRF0 = 0x0 - Configure as the analog comparator reference 0 signal
+ M0nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR0
+ TCTB1 = 0x2 - Configure as the input/output signal from CTIMER B1
+ GPIO19 = 0x3 - Configure as GPIO19
+ TCTA1 = 0x4 - Configure as the input/output signal from CTIMER A1
+ ANATEST1 = 0x5 - Configure as the ANATEST1 I/O signal
+ UART1RX = 0x6 - Configure as the UART1 RX input signal
+ I2S_BCLK = 0x7 - Configure as the I2S Byte clock input signal
26PAD19STRNGRWPad 19 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD19INPENRWPad 19 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD19PULLRWPad 19 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD18FNCSELRWPad 18 function select

+ CMPIN1 = 0x0 - Configure as the analog comparator input 1 signal
+ M0nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR0
+ TCTA1 = 0x2 - Configure as the input/output signal from CTIMER A1
+ GPIO18 = 0x3 - Configure as GPIO18
+ M4nCE1 = 0x4 - Configure as the SPI nCE channel 1 from IOMSTR4
+ ANATEST2 = 0x5 - Configure as ANATEST2 I/O signal
+ UART1TX = 0x6 - Configure as UART1 TX output signal
+ 32khz_XT = 0x7 - Configure as the 32kHz output clock from the crystal
18PAD18STRNGRWPad 18 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD18INPENRWPad 18 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD18PULLRWPad 18 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD17FNCSELRWPad 17 function select

+ CMPRF1 = 0x0 - Configure as the analog comparator reference signal 1 input signal
+ M0nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR0
+ TRIG1 = 0x2 - Configure as the ADC Trigger 1 signal
+ GPIO17 = 0x3 - Configure as GPIO17
+ M4nCE3 = 0x4 - Configure as the SPI channel 3 nCE signal from IOMSTR4
+ EXTLF = 0x5 - Configure as external LFRC oscillator input
+ UART0RX = 0x6 - Configure as UART0 RX input signal
+ UA1CTS = 0x7 - Configure as UART1 CTS input signal
10PAD17STRNGRWPad 17 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD17INPENRWPad 17 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD17PULLRWPad 17 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD16FNCSELRWPad 16 function select

+ ADCSE0 = 0x0 - Configure as the analog ADC single ended port 0 input signal
+ M0nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR0
+ TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal
+ GPIO16 = 0x3 - Configure as GPIO16
+ M2nCE3 = 0x4 - Configure as SPI channel 3 nCE for IOMSTR2
+ CMPIN0 = 0x5 - Configure as comparator input 0 signal
+ UART0TX = 0x6 - Configure as UART0 TX output signal
+ UA1RTS = 0x7 - Configure as UART1 RTS output signal
2PAD16STRNGRWPad 16 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD16INPENRWPad 16 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD16PULLRWPad 16 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGF - Pad Configuration Register F

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010014 +
+

Description:

+

This register controls the pad configuration controls for PAD23 through PAD20. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD23FNCSEL +
0x3		PAD23STRNG +
0x0		PAD23INPEN +
0x0		PAD23PULL +
0x0		PAD22PWRUP +
0x0		RSVD +
0x0		PAD22FNCSEL +
0x3		PAD22STRNG +
0x0		PAD22INPEN +
0x0		PAD22PULL +
0x0		RSVD +
0x0		PAD21FNCSEL +
0x0		PAD21STRNG +
0x0		PAD21INPEN +
0x1		PAD21PULL +
0x0		RSVD +
0x0		PAD20FNCSEL +
0x0		PAD20STRNG +
0x0		PAD20INPEN +
0x1		PAD20PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD23FNCSELRWPad 23 function select

+ UART0RX = 0x0 - Configure as the UART0 RX signal
+ M0nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR0
+ TCTB3 = 0x2 - Configure as the input/output signal from CTIMER B3
+ GPIO23 = 0x3 - Configure as GPIO23
+ PDM_DATA = 0x4 - Configure as PDM Data input to the PDM module
+ CMPOUT = 0x5 - Configure as voltage comparitor output
+ TCTB1 = 0x6 - Configure as the input/output signal from CTIMER B1
+ UNDEF7 = 0x7 - Undefined/should not be used
26PAD23STRNGRWPad 23 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD23INPENRWPad 23 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD23PULLRWPad 23 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23PAD22PWRUPRWPad 22 upper power switch enable

+ DIS = 0x0 - Power switch disabled
+ EN = 0x1 - Power switch enabled
22RSVDRORESERVED

+
21:19PAD22FNCSELRWPad 22 function select

+ UART0TX = 0x0 - Configure as the UART0 TX signal
+ M1nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR1
+ TCTA3 = 0x2 - Configure as the input/output signal from CTIMER A3
+ GPIO22 = 0x3 - Configure as GPIO22
+ PDM_CLK = 0x4 - Configure as the PDM CLK output
+ UNDEF5 = 0x5 - Undefined/should not be used
+ TCTB1 = 0x6 - Configure as the input/output signal from CTIMER B1
+ SWO = 0x7 - Configure as the serial trace data output signal
18PAD22STRNGRWPad 22 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD22INPENRWPad 22 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD22PULLRWPad 22 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD21FNCSELRWPad 21 function select

+ SWDIO = 0x0 - Configure as the serial wire debug data signal
+ M1nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR1
+ TCTB2 = 0x2 - Configure as the input/output signal from CTIMER B2
+ GPIO21 = 0x3 - Configure as GPIO21
+ UART0RX = 0x4 - Configure as UART0 RX input signal
+ UART1RX = 0x5 - Configure as UART1 RX input signal
+ UNDEF6 = 0x6 - Undefined/should not be used
+ UNDEF7 = 0x7 - Undefined/should not be used
10PAD21STRNGRWPad 21 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD21INPENRWPad 21 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD21PULLRWPad 21 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD20FNCSELRWPad 20 function select

+ SWDCK = 0x0 - Configure as the serial wire debug clock signal
+ M1nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR1
+ TCTA2 = 0x2 - Configure as the input/output signal from CTIMER A2
+ GPIO20 = 0x3 - Configure as GPIO20
+ UART0TX = 0x4 - Configure as UART0 TX output signal
+ UART1TX = 0x5 - Configure as UART1 TX output signal
+ UNDEF6 = 0x6 - Undefined/should not be used
+ UNDEF7 = 0x7 - Undefined/should not be used
2PAD20STRNGRWPad 20 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD20INPENRWPad 20 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD20PULLRWPad 20 pulldown enable

+ DIS = 0x0 - Pulldown disabled
+ EN = 0x1 - Pulldown enabled
+
+
+
+ +
+
+

PADREGG - Pad Configuration Register G

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010018 +
+

Description:

+

This register controls the pad configuration controls for PAD27 through PAD24. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PAD27RSEL +
0x0		PAD27FNCSEL +
0x3		PAD27STRNG +
0x0		PAD27INPEN +
0x0		PAD27PULL +
0x0		RSVD +
0x0		PAD26FNCSEL +
0x3		PAD26STRNG +
0x0		PAD26INPEN +
0x0		PAD26PULL +
0x0		PAD25RSEL +
0x0		PAD25FNCSEL +
0x3		PAD25STRNG +
0x0		PAD25INPEN +
0x0		PAD25PULL +
0x0		RSVD +
0x0		PAD24FNCSEL +
0x3		PAD24STRNG +
0x0		PAD24INPEN +
0x0		PAD24PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30PAD27RSELRWPad 27 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
29:27PAD27FNCSELRWPad 27 function select

+ EXTHF = 0x0 - Configure as the external HFRC oscillator input
+ M1nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR1
+ TCTA1 = 0x2 - Configure as the input/output signal from CTIMER A1
+ GPIO27 = 0x3 - Configure as GPIO27
+ M2SCL = 0x4 - Configure as I2C clock I/O signal from IOMSTR2
+ M2SCK = 0x5 - Configure as SPI clock output signal from IOMSTR2
+ M2SCKLB = 0x6 - Configure as IOMSTR2 SPI SCK loopback signal from IOSLAVE
+ M2SCLLB = 0x7 - Configure as IOMSTR2 I2C SCL loopback signal from IOSLAVE
26PAD27STRNGRWPad 27 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD27INPENRWPad 27 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD27PULLRWPad 27 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD26FNCSELRWPad 26 function select

+ EXTLF = 0x0 - Configure as the external LFRC oscillator input
+ M0nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR0
+ TCTB0 = 0x2 - Configure as the input/output signal from CTIMER B0
+ GPIO26 = 0x3 - Configure as GPIO26
+ M2nCE0 = 0x4 - Configure as the SPI channel 0 nCE signal from IOMSTR2
+ TCTA1 = 0x5 - Configure as the input/output signal from CTIMER A1
+ M5nCE1 = 0x6 - Configure as the SPI channel 1 nCE signal from IOMSTR5
+ M3nCE0 = 0x7 - Configure as the SPI channel 0 nCE signal from IOMSTR3
18PAD26STRNGRWPad 26 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD26INPENRWPad 26 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD26PULLRWPad 26 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14PAD25RSELRWPad 25 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
13:11PAD25FNCSELRWPad 25 function select

+ EXTXT = 0x0 - Configure as the external XTAL oscillator input
+ M0nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR0
+ TCTA0 = 0x2 - Configure as the input/output signal from CTIMER A0
+ GPIO25 = 0x3 - Configure as GPIO25
+ M2SDA = 0x4 - Configure as the IOMSTR2 I2C Serial data I/O signal
+ M2MISO = 0x5 - Configure as the IOMSTR2 SPI MISO input signal
+ SLMISOLB = 0x6 - Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE
+ SLSDALB = 0x7 - Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE
10PAD25STRNGRWPad 25 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD25INPENRWPad 25 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD25PULLRWPad 25 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD24FNCSELRWPad 24 function select

+ M2nCE1 = 0x0 - Configure as the SPI channel 1 nCE signal from IOMSTR2
+ M0nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR0
+ CLKOUT = 0x2 - Configure as the CLKOUT signal
+ GPIO24 = 0x3 - Configure as GPIO24
+ M5nCE0 = 0x4 - Configure as the SPI channel 0 nCE signal from IOMSTR5
+ TCTA1 = 0x5 - Configure as the input/output signal from CTIMER A1
+ I2S_BCLK = 0x6 - Configure as the I2S Byte clock input signal
+ SWO = 0x7 - Configure as the serial trace data output signal
2PAD24STRNGRWPad 24 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD24INPENRWPad 24 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD24PULLRWPad 24 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGH - Pad Configuration Register H

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001001C +
+

Description:

+

This register controls the pad configuration controls for PAD31 through PAD28. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD31FNCSEL +
0x3		PAD31STRNG +
0x0		PAD31INPEN +
0x0		PAD31PULL +
0x0		RSVD +
0x0		PAD30FNCSEL +
0x3		PAD30STRNG +
0x0		PAD30INPEN +
0x0		PAD30PULL +
0x0		RSVD +
0x0		PAD29FNCSEL +
0x3		PAD29STRNG +
0x0		PAD29INPEN +
0x0		PAD29PULL +
0x0		RSVD +
0x0		PAD28FNCSEL +
0x3		PAD28STRNG +
0x0		PAD28INPEN +
0x0		PAD28PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD31FNCSELRWPad 31 function select

+ ADCSE3 = 0x0 - Configure as the analog input for ADC single ended input 3
+ M0nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR0
+ TCTA3 = 0x2 - Configure as the input/output signal from CTIMER A3
+ GPIO31 = 0x3 - Configure as GPIO31
+ UART0RX = 0x4 - Configure as the UART0 RX input signal
+ TCTB1 = 0x5 - Configure as the input/output signal from CTIMER B1
+ UNDEF6 = 0x6 - Undefined/should not be used
+ UNDEF7 = 0x7 - Undefined/should not be used
26PAD31STRNGRWPad 31 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD31INPENRWPad 31 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD31PULLRWPad 31 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD30FNCSELRWPad 30 function select

+ UNDEF0 = 0x0 - Undefined/should not be used
+ M1nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR1
+ TCTB2 = 0x2 - Configure as the input/output signal from CTIMER B2
+ GPIO30 = 0x3 - Configure as GPIO30
+ UART0TX = 0x4 - Configure as UART0 TX output signal
+ UA1RTS = 0x5 - Configure as UART1 RTS output signal
+ UNDEF6 = 0x6 - Undefined/should not be used
+ I2S_DAT = 0x7 - Configure as the I2S Data output signal
18PAD30STRNGRWPad 30 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD30INPENRWPad 30 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD30PULLRWPad 30 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD29FNCSELRWPad 29 function select

+ ADCSE1 = 0x0 - Configure as the analog input for ADC single ended input 1
+ M1nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR1
+ TCTA2 = 0x2 - Configure as the input/output signal from CTIMER A2
+ GPIO29 = 0x3 - Configure as GPIO29
+ UA0CTS = 0x4 - Configure as the UART0 CTS signal
+ UA1CTS = 0x5 - Configure as the UART1 CTS signal
+ M4nCE0 = 0x6 - Configure as the SPI channel 0 nCE signal from IOMSTR4
+ PDM_DATA = 0x7 - Configure as PDM DATA input
10PAD29STRNGRWPad 29 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD29INPENRWPad 29 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD29PULLRWPad 29 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD28FNCSELRWPad 28 function select

+ I2S_WCLK = 0x0 - Configure as the I2S Word Clock input
+ M1nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR1
+ TCTB1 = 0x2 - Configure as the input/output signal from CTIMER B1
+ GPIO28 = 0x3 - Configure as GPIO28
+ M2WIR3 = 0x4 - Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal
+ M2MOSI = 0x5 - Configure as the IOMSTR2 SPI MOSI output signal
+ M5nCE3 = 0x6 - Configure as the SPI channel 3 nCE signal from IOMSTR5
+ SLWIR3LB = 0x7 - Configure as the IOMSTR2 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE
2PAD28STRNGRWPad 28 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD28INPENRWPad 28 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD28PULLRWPad 28 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGI - Pad Configuration Register I

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010020 +
+

Description:

+

This register controls the pad configuration controls for PAD35 through PAD32. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD35FNCSEL +
0x3		PAD35STRNG +
0x0		PAD35INPEN +
0x0		PAD35PULL +
0x0		RSVD +
0x0		PAD34FNCSEL +
0x3		PAD34STRNG +
0x0		PAD34INPEN +
0x0		PAD34PULL +
0x0		RSVD +
0x0		PAD33FNCSEL +
0x3		PAD33STRNG +
0x0		PAD33INPEN +
0x0		PAD33PULL +
0x0		RSVD +
0x0		PAD32FNCSEL +
0x3		PAD32STRNG +
0x0		PAD32INPEN +
0x0		PAD32PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD35FNCSELRWPad 35 function select

+ ADCSE7 = 0x0 - Configure as the analog input for ADC single ended input 7
+ M1nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR1
+ UART1TX = 0x2 - Configure as the UART1 TX signal
+ GPIO35 = 0x3 - Configure as GPIO35
+ M4nCE6 = 0x4 - Configure as the SPI channel 6 nCE signal from IOMSTR4
+ TCTA1 = 0x5 - Configure as the input/output signal from CTIMER A1
+ UA0RTS = 0x6 - Configure as the UART0 RTS output
+ M3nCE2 = 0x7 - Configure as the SPI channel 2 nCE signal from IOMSTR3
26PAD35STRNGRWPad 35 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD35INPENRWPad 35 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD35PULLRWPad 35 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD34FNCSELRWPad 34 function select

+ ADCSE6 = 0x0 - Configure as the analog input for ADC single ended input 6
+ M0nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR0
+ M2nCE3 = 0x2 - Configure as the SPI channel 3 nCE signal from IOMSTR2
+ GPIO34 = 0x3 - Configure as GPIO34
+ CMPRF2 = 0x4 - Configure as the analog comparator reference 2 signal
+ M3nCE1 = 0x5 - Configure as the SPI channel 1 nCE signal from IOMSTR3
+ M4nCE0 = 0x6 - Configure as the SPI channel 0 nCE signal from IOMSTR4
+ M5nCE2 = 0x7 - Configure as the SPI channel 2 nCE signal from IOMSTR5
18PAD34STRNGRWPad 34 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD34INPENRWPad 34 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD34PULLRWPad 34 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD33FNCSELRWPad 33 function select

+ ADCSE5 = 0x0 - Configure as the analog ADC single ended port 5 input signal
+ M0nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR0
+ 32khz_XT = 0x2 - Configure as the 32kHz crystal output signal
+ GPIO33 = 0x3 - Configure as GPIO33
+ UNDEF4 = 0x4 - Undefined/should not be used
+ M3nCE7 = 0x5 - Configure as the SPI channel 7 nCE signal from IOMSTR3
+ TCTB1 = 0x6 - Configure as the input/output signal from CTIMER B1
+ SWO = 0x7 - Configure as the serial trace data output signal
10PAD33STRNGRWPad 33 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD33INPENRWPad 33 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD33PULLRWPad 33 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD32FNCSELRWPad 32 function select

+ ADCSE4 = 0x0 - Configure as the analog input for ADC single ended input 4
+ M0nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR0
+ TCTB3 = 0x2 - Configure as the input/output signal from CTIMER B3
+ GPIO32 = 0x3 - Configure as GPIO32
+ UNDEF4 = 0x4 - Undefined/should not be used
+ TCTB1 = 0x5 - Configure as the input/output signal from CTIMER B1
+ UNDEF6 = 0x6 - Undefined/should not be used
+ UNDEF7 = 0x7 - Undefined/should not be used
2PAD32STRNGRWPad 32 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD32INPENRWPad 32 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD32PULLRWPad 32 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGJ - Pad Configuration Register J

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010024 +
+

Description:

+

This register controls the pad configuration controls for PAD39 through PAD36. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PAD39RSEL +
0x0		PAD39FNCSEL +
0x3		PAD39STRNG +
0x0		PAD39INPEN +
0x0		PAD39PULL +
0x0		RSVD +
0x0		PAD38FNCSEL +
0x3		PAD38STRNG +
0x0		PAD38INPEN +
0x0		PAD38PULL +
0x0		RSVD +
0x0		PAD37FNCSEL +
0x3		PAD37STRNG +
0x0		PAD37INPEN +
0x0		PAD37PULL +
0x0		RSVD +
0x0		PAD36FNCSEL +
0x3		PAD36STRNG +
0x0		PAD36INPEN +
0x0		PAD36PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30PAD39RSELRWPad 39 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
29:27PAD39FNCSELRWPad 39 function select

+ UART0TX = 0x0 - Configure as the UART0 TX Signal
+ UART1TX = 0x1 - Configure as the UART1 TX signal
+ CLKOUT = 0x2 - Configure as the CLKOUT signal
+ GPIO39 = 0x3 - Configure as GPIO39
+ M4SCL = 0x4 - Configure as the IOMSTR4 I2C SCL signal
+ M4SCK = 0x5 - Configure as the IOMSTR4 SPI SCK signal
+ M4SCKLB = 0x6 - Configure as the IOMSTR4 SPI SCK loopback signal from IOSLAVE
+ M4SCLLB = 0x7 - Configure as the IOMSTR4 I2C SCL loopback signal from IOSLAVE
26PAD39STRNGRWPad 39 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD39INPENRWPad 39 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD39PULLRWPad 39 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD38FNCSELRWPad 38 function select

+ TRIG3 = 0x0 - Configure as the ADC Trigger 3 signal
+ M1nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR1
+ UA0CTS = 0x2 - Configure as the UART0 CTS signal
+ GPIO38 = 0x3 - Configure as GPIO38
+ M3WIR3 = 0x4 - Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal
+ M3MOSI = 0x5 - Configure as the IOMSTR3 SPI MOSI output signal
+ M4nCE7 = 0x6 - Configure as the SPI channel 7 nCE signal from IOMSTR4
+ SLWIR3LB = 0x7 - Configure as the IOMSTR3 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE
18PAD38STRNGRWPad 38 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD38INPENRWPad 38 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD38PULLRWPad 38 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD37FNCSELRWPad 37 function select

+ TRIG2 = 0x0 - Configure as the ADC Trigger 2 signal
+ M1nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR1
+ UA0RTS = 0x2 - Configure as the UART0 RTS signal
+ GPIO37 = 0x3 - Configure as GPIO37
+ M3nCE4 = 0x4 - Configure as the SPI channel 4 nCE signal from IOMSTR3
+ M4nCE1 = 0x5 - Configure as the SPI channel 1 nCE signal from IOMSTR4
+ PDM_CLK = 0x6 - Configure as the PDM CLK output signal
+ TCTA1 = 0x7 - Configure as the input/output signal from CTIMER A1
10PAD37STRNGRWPad 37 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD37INPENRWPad 37 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD37PULLRWPad 37 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD36FNCSELRWPad 36 function select

+ TRIG1 = 0x0 - Configure as the ADC Trigger 1 signal
+ M1nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR1
+ UART1RX = 0x2 - Configure as the UART1 RX signal
+ GPIO36 = 0x3 - Configure as GPIO36
+ 32khz_XT = 0x4 - Configure as the 32kHz output clock from the crystal
+ M2nCE0 = 0x5 - Configure as the SPI channel 0 nCE signal from IOMSTR2
+ UA0CTS = 0x6 - Configure as the UART0 CTS signal
+ M3nCE3 = 0x7 - Configure as the SPI channel 3 nCE signal from IOMSTR3
2PAD36STRNGRWPad 36 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD36INPENRWPad 36 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD36PULLRWPad 36 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGK - Pad Configuration Register K

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010028 +
+

Description:

+

This register controls the pad configuration controls for PAD43 through PAD40. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PAD43RSEL +
0x0		PAD43FNCSEL +
0x3		PAD43STRNG +
0x0		PAD43INPEN +
0x0		PAD43PULL +
0x0		PAD42RSEL +
0x0		PAD42FNCSEL +
0x3		PAD42STRNG +
0x0		PAD42INPEN +
0x0		PAD42PULL +
0x0		PAD41PWRUP +
0x0		RSVD +
0x0		PAD41FNCSEL +
0x3		PAD41STRNG +
0x0		PAD41INPEN +
0x0		PAD41PULL +
0x0		PAD40RSEL +
0x0		PAD40FNCSEL +
0x3		PAD40STRNG +
0x0		PAD40INPEN +
0x0		PAD40PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30PAD43RSELRWPad 43 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
29:27PAD43FNCSELRWPad 43 function select

+ M2nCE4 = 0x0 - Configure as the SPI channel 4 nCE signal from IOMSTR2
+ M0nCE1 = 0x1 - Configure as the SPI channel 1 nCE signal from IOMSTR0
+ TCTB0 = 0x2 - Configure as the input/output signal from CTIMER B0
+ GPIO43 = 0x3 - Configure as GPIO43
+ M3SDA = 0x4 - Configure as the IOMSTR3 I2C SDA signal
+ M3MISO = 0x5 - Configure as the IOMSTR3 SPI MISO signal
+ SLMISOLB = 0x6 - Configure as the IOMSTR3 SPI MISO loopback signal from IOSLAVE
+ SLSDALB = 0x7 - Configure as the IOMSTR3 I2C SDA loopback signal from IOSLAVE
26PAD43STRNGRWPad 43 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD43INPENRWPad 43 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD43PULLRWPad 43 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22PAD42RSELRWPad 42 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
21:19PAD42FNCSELRWPad 42 function select

+ M2nCE2 = 0x0 - Configure as the SPI channel 2 nCE signal from IOMSTR2
+ M0nCE0 = 0x1 - Configure as the SPI channel 0 nCE signal from IOMSTR0
+ TCTA0 = 0x2 - Configure as the input/output signal from CTIMER A0
+ GPIO42 = 0x3 - Configure as GPIO42
+ M3SCL = 0x4 - Configure as the IOMSTR3 I2C SCL clock I/O signal
+ M3SCK = 0x5 - Configure as the IOMSTR3 SPI SCK output
+ M3SCKLB = 0x6 - Configure as the IOMSTR3 SPI clock loopback to the IOSLAVE device
+ M3SCLLB = 0x7 - Configure as the IOMSTR3 I2C clock loopback to the IOSLAVE device
18PAD42STRNGRWPad 42 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD42INPENRWPad 42 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD42PULLRWPad 42 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15PAD41PWRUPRWPad 41 upper power switch enable

+ DIS = 0x0 - Power switch disabled
+ EN = 0x1 - Power switch enabled (VDD switch)
14RSVDRORESERVED

+
13:11PAD41FNCSELRWPad 41 function select

+ M2nCE1 = 0x0 - Configure as the SPI channel 1 nCE signal from IOMSTR2
+ CLKOUT = 0x1 - Configure as the CLKOUT signal
+ SWO = 0x2 - Configure as the serial wire debug SWO signal
+ GPIO41 = 0x3 - Configure as GPIO41
+ M3nCE5 = 0x4 - Configure as the SPI channel 5 nCE signal from IOMSTR3
+ M5nCE7 = 0x5 - Configure as the SPI channel 7 nCE signal from IOMSTR5
+ M4nCE2 = 0x6 - Configure as the SPI channel 2 nCE signal from IOMSTR4
+ UA0RTS = 0x7 - Configure as the UART0 RTS output
10PAD41STRNGRWPad 41 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD41INPENRWPad 41 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD41PULLRWPad 41 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6PAD40RSELRWPad 40 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
5:3PAD40FNCSELRWPad 40 function select

+ UART0RX = 0x0 - Configure as the UART0 RX input signal
+ UART1RX = 0x1 - Configure as the UART1 RX input signal
+ TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal
+ GPIO40 = 0x3 - Configure as GPIO40
+ M4SDA = 0x4 - Configure as the IOMSTR4 I2C serial data I/O signal
+ M4MISO = 0x5 - Configure as the IOMSTR4 SPI MISO input signal
+ SLMISOLB = 0x6 - Configure as the IOMSTR4 SPI MISO loopback signal from IOSLAVE
+ SLSDALB = 0x7 - Configure as the IOMSTR4 I2C SDA loopback signal from IOSLAVE
2PAD40STRNGRWPad 40 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD40INPENRWPad 40 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD40PULLRWPad 40 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGL - Pad Configuration Register L

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001002C +
+

Description:

+

This register controls the pad configuration controls for PAD47 through PAD44. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD47FNCSEL +
0x3		PAD47STRNG +
0x0		PAD47INPEN +
0x0		PAD47PULL +
0x0		RSVD +
0x0		PAD46FNCSEL +
0x3		PAD46STRNG +
0x0		PAD46INPEN +
0x0		PAD46PULL +
0x0		RSVD +
0x0		PAD45FNCSEL +
0x3		PAD45STRNG +
0x0		PAD45INPEN +
0x0		PAD45PULL +
0x0		RSVD +
0x0		PAD44FNCSEL +
0x3		PAD44STRNG +
0x0		PAD44INPEN +
0x0		PAD44PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:27PAD47FNCSELRWPad 47 function select

+ M2nCE5 = 0x0 - Configure as the SPI channel 5 nCE signal from IOMSTR2
+ M0nCE5 = 0x1 - Configure as the SPI channel 5 nCE signal from IOMSTR0
+ TCTB2 = 0x2 - Configure as the input/output signal from CTIMER B2
+ GPIO47 = 0x3 - Configure as GPIO47
+ M5WIR3 = 0x4 - Configure as the IOMSTR5 SPI 3-wire MOSI/MISO signal
+ M5MOSI = 0x5 - Configure as the IOMSTR5 SPI MOSI output signal
+ M4nCE5 = 0x6 - Configure as the SPI channel 5 nCE signal from IOMSTR4
+ SLWIR3LB = 0x7 - Configure as the IOMSTR5 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE
26PAD47STRNGRWPad 47 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
25PAD47INPENRWPad 47 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
24PAD47PULLRWPad 47 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
23:22RSVDRORESERVED

+
21:19PAD46FNCSELRWPad 46 function select

+ 32khz_XT = 0x0 - Configure as the 32kHz output clock from the crystal
+ M0nCE4 = 0x1 - Configure as the SPI channel 4 nCE signal from IOMSTR0
+ TCTA2 = 0x2 - Configure as the input/output signal from CTIMER A2
+ GPIO46 = 0x3 - Configure as GPIO46
+ TCTA1 = 0x4 - Configure as the input/output signal from CTIMER A1
+ M5nCE4 = 0x5 - Configure as the SPI channel 4 nCE signal from IOMSTR5
+ M4nCE4 = 0x6 - Configure as the SPI channel 4 nCE signal from IOMSTR4
+ SWO = 0x7 - Configure as the serial wire debug SWO signal
18PAD46STRNGRWPad 46 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
17PAD46INPENRWPad 46 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
16PAD46PULLRWPad 46 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
15:14RSVDRORESERVED

+
13:11PAD45FNCSELRWPad 45 function select

+ UA1CTS = 0x0 - Configure as the UART1 CTS input signal
+ M0nCE3 = 0x1 - Configure as the SPI channel 3 nCE signal from IOMSTR0
+ TCTB1 = 0x2 - Configure as the input/output signal from CTIMER B1
+ GPIO45 = 0x3 - Configure as GPIO45
+ M4nCE3 = 0x4 - Configure as the SPI channel 3 nCE signal from IOMSTR4
+ M3nCE6 = 0x5 - Configure as the SPI channel 6 nCE signal from IOMSTR3
+ M5nCE5 = 0x6 - Configure as the SPI channel 5 nCE signal from IOMSTR5
+ TCTA1 = 0x7 - Configure as the input/output signal from CTIMER A1
10PAD45STRNGRWPad 45 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD45INPENRWPad 45 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD45PULLRWPad 45 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6RSVDRORESERVED

+
5:3PAD44FNCSELRWPad 44 function select

+ UA1RTS = 0x0 - Configure as the UART1 RTS output signal
+ M0nCE2 = 0x1 - Configure as the SPI channel 2 nCE signal from IOMSTR0
+ TCTA1 = 0x2 - Configure as the input/output signal from CTIMER A1
+ GPIO44 = 0x3 - Configure as GPIO44
+ M4WIR3 = 0x4 - Configure as the IOMSTR4 SPI 3-wire MOSI/MISO signal
+ M4MOSI = 0x5 - Configure as the IOMSTR4 SPI MOSI signal
+ M5nCE6 = 0x6 - Configure as the SPI channel 6 nCE signal from IOMSTR5
+ SLWIR3LB = 0x7 - Configure as the IOMSTR4 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE
2PAD44STRNGRWPad 44 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD44INPENRWPad 44 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD44PULLRWPad 44 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

PADREGM - Pad Configuration Register M

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010030 +
+

Description:

+

This register controls the pad configuration controls for PAD49 through PAD48. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD49RSEL +
0x0		PAD49FNCSEL +
0x3		PAD49STRNG +
0x0		PAD49INPEN +
0x0		PAD49PULL +
0x0		PAD48RSEL +
0x0		PAD48FNCSEL +
0x3		PAD48STRNG +
0x0		PAD48INPEN +
0x0		PAD48PULL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15:14PAD49RSELRWPad 49 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
13:11PAD49FNCSELRWPad 49 function select

+ M2nCE7 = 0x0 - Configure as the SPI channel 7 nCE signal from IOMSTR2
+ M0nCE7 = 0x1 - Configure as the SPI channel 7 nCE signal from IOMSTR0
+ TCTB3 = 0x2 - Configure as the input/output signal from CTIMER B3
+ GPIO49 = 0x3 - Configure as GPIO49
+ M5SDA = 0x4 - Configure as the IOMSTR5 I2C serial data I/O signal
+ M5MISO = 0x5 - Configure as the IOMSTR5 SPI MISO input signal
+ SLMISOLB = 0x6 - Configure as the IOMSTR5 SPI MISO loopback signal from IOSLAVE
+ SLSDALB = 0x7 - Configure as the IOMSTR5 I2C SDA loopback signal from IOSLAVE
10PAD49STRNGRWPad 49 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
9PAD49INPENRWPad 49 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
8PAD49PULLRWPad 49 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
7:6PAD48RSELRWPad 48 pullup resistor selection.

+ PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
+ PULL6K = 0x1 - Pullup is ~6 KOhms
+ PULL12K = 0x2 - Pullup is ~12 KOhms
+ PULL24K = 0x3 - Pullup is ~24 KOhms
5:3PAD48FNCSELRWPad 48 function select

+ M2nCE6 = 0x0 - Configure as the SPI channel 6 nCE signal from IOMSTR2
+ M0nCE6 = 0x1 - Configure as the SPI channel 6 nCE signal from IOMSTR0
+ TCTA3 = 0x2 - Configure as the input/output signal from CTIMER A3
+ GPIO48 = 0x3 - Configure as GPIO48
+ M5SCL = 0x4 - Configure as the IOMSTR5 I2C SCL clock I/O signal
+ M5SCK = 0x5 - Configure as the IOMSTR5 SPI SCK output
+ M5SCKLB = 0x6 - Configure as the IOMSTR5 SPI clock loopback to the IOSLAVE device
+ M5SCLLB = 0x7 - Configure as the IOMSTR5 I2C clock loopback to the IOSLAVE device
2PAD48STRNGRWPad 48 drive strength

+ LOW = 0x0 - Low drive strength
+ HIGH = 0x1 - High drive strength
1PAD48INPENRWPad 48 input enable

+ DIS = 0x0 - Pad input disabled
+ EN = 0x1 - Pad input enabled
0PAD48PULLRWPad 48 pullup enable

+ DIS = 0x0 - Pullup disabled
+ EN = 0x1 - Pullup enabled
+
+
+
+ +
+
+

CFGA - GPIO Configuration Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010040 +
+

Description:

+

GPIO configuration controls for GPIO[7:0]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO7INTD +
0x0		GPIO7OUTCFG +
0x0		GPIO7INCFG +
0x0		GPIO6INTD +
0x0		GPIO6OUTCFG +
0x0		GPIO6INCFG +
0x0		GPIO5INTD +
0x0		GPIO5OUTCFG +
0x0		GPIO5INCFG +
0x0		GPIO4INTD +
0x0		GPIO4OUTCFG +
0x0		GPIO4INCFG +
0x0		GPIO3INTD +
0x0		GPIO3OUTCFG +
0x0		GPIO3INCFG +
0x0		GPIO2INTD +
0x0		GPIO2OUTCFG +
0x0		GPIO2INCFG +
0x0		GPIO1INTD +
0x0		GPIO1OUTCFG +
0x0		GPIO1INCFG +
0x0		GPIO0INTD +
0x0		GPIO0OUTCFG +
0x0		GPIO0INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO7INTDRWGPIO7 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
30:29GPIO7OUTCFGRWGPIO7 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
28GPIO7INCFGRWGPIO7 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
27GPIO6INTDRWGPIO6 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
26:25GPIO6OUTCFGRWGPIO6 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
24GPIO6INCFGRWGPIO6 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
23GPIO5INTDRWGPIO5 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
22:21GPIO5OUTCFGRWGPIO5 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
20GPIO5INCFGRWGPIO5 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
19GPIO4INTDRWGPIO4 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
18:17GPIO4OUTCFGRWGPIO4 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
16GPIO4INCFGRWGPIO4 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
15GPIO3INTDRWGPIO3 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
14:13GPIO3OUTCFGRWGPIO3 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
12GPIO3INCFGRWGPIO3 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
11GPIO2INTDRWGPIO2 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
10:9GPIO2OUTCFGRWGPIO2 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
8GPIO2INCFGRWGPIO2 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
7GPIO1INTDRWGPIO1 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO1OUTCFGRWGPIO1 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO1INCFGRWGPIO1 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO0INTDRWGPIO0 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO0OUTCFGRWGPIO0 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO0INCFGRWGPIO0 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

CFGB - GPIO Configuration Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010044 +
+

Description:

+

GPIO configuration controls for GPIO[15:8]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO15INTD +
0x0		GPIO15OUTCFG +
0x0		GPIO15INCFG +
0x0		GPIO14INTD +
0x0		GPIO14OUTCFG +
0x0		GPIO14INCFG +
0x0		GPIO13INTD +
0x0		GPIO13OUTCFG +
0x0		GPIO13INCFG +
0x0		GPIO12INTD +
0x0		GPIO12OUTCFG +
0x0		GPIO12INCFG +
0x0		GPIO11INTD +
0x0		GPIO11OUTCFG +
0x0		GPIO11INCFG +
0x0		GPIO10INTD +
0x0		GPIO10OUTCFG +
0x0		GPIO10INCFG +
0x0		GPIO9INTD +
0x0		GPIO9OUTCFG +
0x0		GPIO9INCFG +
0x0		GPIO8INTD +
0x0		GPIO8OUTCFG +
0x0		GPIO8INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO15INTDRWGPIO15 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
30:29GPIO15OUTCFGRWGPIO15 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
28GPIO15INCFGRWGPIO15 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
27GPIO14INTDRWGPIO14 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
26:25GPIO14OUTCFGRWGPIO14 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
24GPIO14INCFGRWGPIO14 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
23GPIO13INTDRWGPIO13 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
22:21GPIO13OUTCFGRWGPIO13 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
20GPIO13INCFGRWGPIO13 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
19GPIO12INTDRWGPIO12 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
18:17GPIO12OUTCFGRWGPIO12 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
16GPIO12INCFGRWGPIO12 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
15GPIO11INTDRWGPIO11 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
14:13GPIO11OUTCFGRWGPIO11 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
12GPIO11INCFGRWGPIO11 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
11GPIO10INTDRWGPIO10 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
10:9GPIO10OUTCFGRWGPIO10 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
8GPIO10INCFGRWGPIO10 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
7GPIO9INTDRWGPIO9 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO9OUTCFGRWGPIO9 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO9INCFGRWGPIO9 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO8INTDRWGPIO8 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO8OUTCFGRWGPIO8 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO8INCFGRWGPIO8 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

CFGC - GPIO Configuration Register C

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010048 +
+

Description:

+

GPIO configuration controls for GPIO[23:16]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO23INTD +
0x0		GPIO23OUTCFG +
0x0		GPIO23INCFG +
0x0		GPIO22INTD +
0x0		GPIO22OUTCFG +
0x0		GPIO22INCFG +
0x0		GPIO21INTD +
0x0		GPIO21OUTCFG +
0x0		GPIO21INCFG +
0x1		GPIO20INTD +
0x0		GPIO20OUTCFG +
0x0		GPIO20INCFG +
0x1		GPIO19INTD +
0x0		GPIO19OUTCFG +
0x0		GPIO19INCFG +
0x0		GPIO18INTD +
0x0		GPIO18OUTCFG +
0x0		GPIO18INCFG +
0x0		GPIO17INTD +
0x0		GPIO17OUTCFG +
0x0		GPIO17INCFG +
0x0		GPIO16INTD +
0x0		GPIO16OUTCFG +
0x0		GPIO16INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO23INTDRWGPIO23 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
30:29GPIO23OUTCFGRWGPIO23 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
28GPIO23INCFGRWGPIO23 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
27GPIO22INTDRWGPIO22 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
26:25GPIO22OUTCFGRWGPIO22 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
24GPIO22INCFGRWGPIO22 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
23GPIO21INTDRWGPIO21 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
22:21GPIO21OUTCFGRWGPIO21 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
20GPIO21INCFGRWGPIO21 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
19GPIO20INTDRWGPIO20 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
18:17GPIO20OUTCFGRWGPIO20 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
16GPIO20INCFGRWGPIO20 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
15GPIO19INTDRWGPIO19 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
14:13GPIO19OUTCFGRWGPIO19 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
12GPIO19INCFGRWGPIO19 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
11GPIO18INTDRWGPIO18 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
10:9GPIO18OUTCFGRWGPIO18 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
8GPIO18INCFGRWGPIO18 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
7GPIO17INTDRWGPIO17 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO17OUTCFGRWGPIO17 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO17INCFGRWGPIO17 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO16INTDRWGPIO16 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO16OUTCFGRWGPIO16 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO16INCFGRWGPIO16 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

CFGD - GPIO Configuration Register D

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001004C +
+

Description:

+

GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO31INTD +
0x0		GPIO31OUTCFG +
0x0		GPIO31INCFG +
0x0		GPIO30INTD +
0x0		GPIO30OUTCFG +
0x0		GPIO30INCFG +
0x0		GPIO29INTD +
0x0		GPIO29OUTCFG +
0x0		GPIO29INCFG +
0x0		GPIO28INTD +
0x0		GPIO28OUTCFG +
0x0		GPIO28INCFG +
0x0		GPIO27INTD +
0x0		GPIO27OUTCFG +
0x0		GPIO27INCFG +
0x0		GPIO26INTD +
0x0		GPIO26OUTCFG +
0x0		GPIO26INCFG +
0x0		GPIO25INTD +
0x0		GPIO25OUTCFG +
0x0		GPIO25INCFG +
0x0		GPIO24INTD +
0x0		GPIO24OUTCFG +
0x0		GPIO24INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO31INTDRWGPIO31 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
30:29GPIO31OUTCFGRWGPIO31 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
28GPIO31INCFGRWGPIO31 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
27GPIO30INTDRWGPIO30 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
26:25GPIO30OUTCFGRWGPIO30 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
24GPIO30INCFGRWGPIO30 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
23GPIO29INTDRWGPIO29 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
22:21GPIO29OUTCFGRWGPIO29 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
20GPIO29INCFGRWGPIO29 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
19GPIO28INTDRWGPIO28 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
18:17GPIO28OUTCFGRWGPIO28 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
16GPIO28INCFGRWGPIO28 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
15GPIO27INTDRWGPIO27 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
14:13GPIO27OUTCFGRWGPIO27 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
12GPIO27INCFGRWGPIO27 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
11GPIO26INTDRWGPIO26 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
10:9GPIO26OUTCFGRWGPIO26 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
8GPIO26INCFGRWGPIO26 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
7GPIO25INTDRWGPIO25 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO25OUTCFGRWGPIO25 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO25INCFGRWGPIO25 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO24INTDRWGPIO24 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO24OUTCFGRWGPIO24 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO24INCFGRWGPIO24 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

CFGE - GPIO Configuration Register E

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010050 +
+

Description:

+

GPIO configuration controls for GPIO[39:32]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO39INTD +
0x0		GPIO39OUTCFG +
0x0		GPIO39INCFG +
0x0		GPIO38INTD +
0x0		GPIO38OUTCFG +
0x0		GPIO38INCFG +
0x0		GPIO37INTD +
0x0		GPIO37OUTCFG +
0x0		GPIO37INCFG +
0x0		GPIO36INTD +
0x0		GPIO36OUTCFG +
0x0		GPIO36INCFG +
0x0		GPIO35INTD +
0x0		GPIO35OUTCFG +
0x0		GPIO35INCFG +
0x0		GPIO34INTD +
0x0		GPIO34OUTCFG +
0x0		GPIO34INCFG +
0x0		GPIO33INTD +
0x0		GPIO33OUTCFG +
0x0		GPIO33INCFG +
0x0		GPIO32INTD +
0x0		GPIO32OUTCFG +
0x0		GPIO32INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO39INTDRWGPIO39 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
30:29GPIO39OUTCFGRWGPIO39 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
28GPIO39INCFGRWGPIO39 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
27GPIO38INTDRWGPIO38 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
26:25GPIO38OUTCFGRWGPIO38 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
24GPIO38INCFGRWGPIO38 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
23GPIO37INTDRWGPIO37 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
22:21GPIO37OUTCFGRWGPIO37 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
20GPIO37INCFGRWGPIO37 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
19GPIO36INTDRWGPIO36 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
18:17GPIO36OUTCFGRWGPIO36 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
16GPIO36INCFGRWGPIO36 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
15GPIO35INTDRWGPIO35 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
14:13GPIO35OUTCFGRWGPIO35 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
12GPIO35INCFGRWGPIO35 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
11GPIO34INTDRWGPIO34 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
10:9GPIO34OUTCFGRWGPIO34 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
8GPIO34INCFGRWGPIO34 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
7GPIO33INTDRWGPIO33 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO33OUTCFGRWGPIO33 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO33INCFGRWGPIO33 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO32INTDRWGPIO32 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO32OUTCFGRWGPIO32 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO32INCFGRWGPIO32 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

CFGF - GPIO Configuration Register F

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010054 +
+

Description:

+

GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO47INTD +
0x0		GPIO47OUTCFG +
0x0		GPIO47INCFG +
0x0		GPIO46INTD +
0x0		GPIO46OUTCFG +
0x0		GPIO46INCFG +
0x0		GPIO45INTD +
0x0		GPIO45OUTCFG +
0x0		GPIO45INCFG +
0x0		GPIO44INTD +
0x0		GPIO44OUTCFG +
0x0		GPIO44INCFG +
0x0		GPIO43INTD +
0x0		GPIO43OUTCFG +
0x0		GPIO43INCFG +
0x0		GPIO42INTD +
0x0		GPIO42OUTCFG +
0x0		GPIO42INCFG +
0x0		GPIO41INTD +
0x0		GPIO41OUTCFG +
0x0		GPIO41INCFG +
0x0		GPIO40INTD +
0x0		GPIO40OUTCFG +
0x0		GPIO40INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO47INTDRWGPIO47 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
30:29GPIO47OUTCFGRWGPIO47 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
28GPIO47INCFGRWGPIO47 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
27GPIO46INTDRWGPIO46 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
26:25GPIO46OUTCFGRWGPIO46 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
24GPIO46INCFGRWGPIO46 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
23GPIO45INTDRWGPIO45 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
22:21GPIO45OUTCFGRWGPIO45 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
20GPIO45INCFGRWGPIO45 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
19GPIO44INTDRWGPIO44 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
18:17GPIO44OUTCFGRWGPIO44 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
16GPIO44INCFGRWGPIO44 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
15GPIO43INTDRWGPIO43 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
14:13GPIO43OUTCFGRWGPIO43 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
12GPIO43INCFGRWGPIO43 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
11GPIO42INTDRWGPIO42 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
10:9GPIO42OUTCFGRWGPIO42 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
8GPIO42INCFGRWGPIO42 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
7GPIO41INTDRWGPIO41 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO41OUTCFGRWGPIO41 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO41INCFGRWGPIO41 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO40INTDRWGPIO40 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO40OUTCFGRWGPIO40 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO40INCFGRWGPIO40 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

CFGG - GPIO Configuration Register G

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010058 +
+

Description:

+

GPIO configuration controls for GPIO[49:48]. Writes to this register must be unlocked by the PADKEY register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		GPIO49INTD +
0x0		GPIO49OUTCFG +
0x0		GPIO49INCFG +
0x0		GPIO48INTD +
0x0		GPIO48OUTCFG +
0x0		GPIO48INCFG +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED

+
7GPIO49INTDRWGPIO49 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
6:5GPIO49OUTCFGRWGPIO49 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
4GPIO49INCFGRWGPIO49 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
3GPIO48INTDRWGPIO48 interrupt direction.

+ INTLH = 0x0 - Interrupt on low to high GPIO transition
+ INTHL = 0x1 - Interrupt on high to low GPIO transition
2:1GPIO48OUTCFGRWGPIO48 output configuration.

+ DIS = 0x0 - Output disabled
+ PUSHPULL = 0x1 - Output is push-pull
+ OD = 0x2 - Output is open drain
+ TS = 0x3 - Output is tri-state
0GPIO48INCFGRWGPIO48 input enable.

+ READ = 0x0 - Read the GPIO pin data
+ RDZERO = 0x1 - Readback will always be zero
+
+
+
+ +
+
+

PADKEY - Key Register for all pad configuration registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010060 +
+

Description:

+

Key Register for all pad configuration registers

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PADKEY +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PADKEYRWKey register value.

+ Key = 0x73 - Key
+
+
+
+ +
+
+

RDA - GPIO Input Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010080 +
+

Description:

+

GPIO Input Register A

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RDA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0RDAROGPIO31-0 read data.

+
+
+
+
+ +
+
+

RDB - GPIO Input Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010084 +
+

Description:

+

GPIO Input Register B

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RDB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0RDBROGPIO49-32 read data.

+
+
+
+
+ +
+
+

WTA - GPIO Output Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010088 +
+

Description:

+

GPIO Output Register A

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
WTA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0WTARWGPIO31-0 write data.

+
+
+
+
+ +
+
+

WTB - GPIO Output Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001008C +
+

Description:

+

GPIO Output Register B

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WTB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0WTBRWGPIO49-32 write data.

+
+
+
+
+ +
+
+

WTSA - GPIO Output Register A Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010090 +
+

Description:

+

GPIO Output Register A Set

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
WTSA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0WTSAWOSet the GPIO31-0 write data.

+
+
+
+
+ +
+
+

WTSB - GPIO Output Register B Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010094 +
+

Description:

+

GPIO Output Register B Set

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WTSB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0WTSBWOSet the GPIO49-32 write data.

+
+
+
+
+ +
+
+

WTCA - GPIO Output Register A Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010098 +
+

Description:

+

GPIO Output Register A Clear

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
WTCA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0WTCAWOClear the GPIO31-0 write data.

+
+
+
+
+ +
+
+

WTCB - GPIO Output Register B Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001009C +
+

Description:

+

GPIO Output Register B Clear

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WTCB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0WTCBWOClear the GPIO49-32 write data.

+
+
+
+
+ +
+
+

ENA - GPIO Enable Register A

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100A0 +
+

Description:

+

GPIO Enable Register A

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ENA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ENARWGPIO31-0 output enables

+
+
+
+
+ +
+
+

ENB - GPIO Enable Register B

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100A4 +
+

Description:

+

GPIO Enable Register B

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ENB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0ENBRWGPIO49-32 output enables

+
+
+
+
+ +
+
+

ENSA - GPIO Enable Register A Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100A8 +
+

Description:

+

GPIO Enable Register A Set

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ENSA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ENSARWSet the GPIO31-0 output enables

+
+
+
+
+ +
+
+

ENSB - GPIO Enable Register B Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100AC +
+

Description:

+

GPIO Enable Register B Set

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ENSB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0ENSBRWSet the GPIO49-32 output enables

+
+
+
+
+ +
+
+

ENCA - GPIO Enable Register A Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100B4 +
+

Description:

+

GPIO Enable Register A Clear

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ENCA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ENCARWClear the GPIO31-0 output enables

+
+
+
+
+ +
+
+

ENCB - GPIO Enable Register B Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100B8 +
+

Description:

+

GPIO Enable Register B Clear

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ENCB +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17:0ENCBRWClear the GPIO49-32 output enables

+
+
+
+
+ +
+
+

STMRCAP - STIMER Capture Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100BC +
+

Description:

+

STIMER Capture trigger select and enable.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		STPOL3 +
0x0		STSEL3 +
0x3f		RSVD +
0x0		STPOL2 +
0x0		STSEL2 +
0x3f		RSVD +
0x0		STPOL1 +
0x0		STSEL1 +
0x3f		RSVD +
0x0		STPOL0 +
0x0		STSEL0 +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31RSVDRORESERVED

+
30STPOL3RWSTIMER Capture 3 Polarity.

+ CAPLH = 0x0 - Capture on low to high GPIO transition
+ CAPHL = 0x1 - Capture on high to low GPIO transition
29:24STSEL3RWSTIMER Capture 3 Select.

+
23RSVDRORESERVED

+
22STPOL2RWSTIMER Capture 2 Polarity.

+ CAPLH = 0x0 - Capture on low to high GPIO transition
+ CAPHL = 0x1 - Capture on high to low GPIO transition
21:16STSEL2RWSTIMER Capture 2 Select.

+
15RSVDRORESERVED

+
14STPOL1RWSTIMER Capture 1 Polarity.

+ CAPLH = 0x0 - Capture on low to high GPIO transition
+ CAPHL = 0x1 - Capture on high to low GPIO transition
13:8STSEL1RWSTIMER Capture 1 Select.

+
7RSVDRORESERVED

+
6STPOL0RWSTIMER Capture 0 Polarity.

+ CAPLH = 0x0 - Capture on low to high GPIO transition
+ CAPHL = 0x1 - Capture on high to low GPIO transition
5:0STSEL0RWSTIMER Capture 0 Select.

+
+
+
+
+ +
+
+

IOM0IRQ - IOM0 Flow Control IRQ Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100C0 +
+

Description:

+

IOMSTR0 IRQ select for flow control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOM0IRQ +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5:0IOM0IRQRWIOMSTR0 IRQ pad select.

+
+
+
+
+ +
+
+

IOM1IRQ - IOM1 Flow Control IRQ Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100C4 +
+

Description:

+

IOMSTR1 IRQ select for flow control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOM1IRQ +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5:0IOM1IRQRWIOMSTR1 IRQ pad select.

+
+
+
+
+ +
+
+

IOM2IRQ - IOM2 Flow Control IRQ Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100C8 +
+

Description:

+

IOMSTR2 IRQ select for flow control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOM2IRQ +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5:0IOM2IRQRWIOMSTR2 IRQ pad select.

+
+
+
+
+ +
+
+

IOM3IRQ - IOM3 Flow Control IRQ Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100CC +
+

Description:

+

IOMSTR3 IRQ select for flow control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOM3IRQ +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5:0IOM3IRQRWIOMSTR3 IRQ pad select.

+
+
+
+
+ +
+
+

IOM4IRQ - IOM4 Flow Control IRQ Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100D0 +
+

Description:

+

IOMSTR4 IRQ select for flow control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOM4IRQ +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5:0IOM4IRQRWIOMSTR4 IRQ pad select.

+
+
+
+
+ +
+
+

IOM5IRQ - IOM5 Flow Control IRQ Select

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100D4 +
+

Description:

+

IOMSTR5 IRQ select for flow control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOM5IRQ +
0x3f
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5:0IOM5IRQRWIOMSTR5 IRQ pad select.

+
+
+
+
+ +
+
+

LOOPBACK - IOM to IOS Loopback Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100D8 +
+

Description:

+

IOM to IOS loopback control.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		LOOPBACK +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED

+
2:0LOOPBACKRWIOM to IOS loopback control.

+ LOOP0 = 0x0 - Loop IOM0 to IOS
+ LOOP1 = 0x1 - Loop IOM1 to IOS
+ LOOP2 = 0x2 - Loop IOM2 to IOS
+ LOOP3 = 0x3 - Loop IOM3 to IOS
+ LOOP4 = 0x4 - Loop IOM4 to IOS
+ LOOP5 = 0x5 - Loop IOM5 to IOS
+ LOOPNONE = 0x6 - No loopback connections
+
+
+
+ +
+
+

GPIOOBS - GPIO Observation Mode Sample register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100DC +
+

Description:

+

GPIO Observation mode sample register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OBS_DATA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15:0OBS_DATARWSample of the data output on the GPIO observation port. May have async sampling issues, as the data is not synronized to the read operation. Intended for debug purposes only

+
+
+
+
+ +
+
+

ALTPADCFGA - Alternate Pad Configuration reg0 (Pads 3,2,1,0)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100E0 +
+

Description:

+

This register has additional configuration control for pads 3, 2, 1, 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD3_SR +
0x0		RSVD +
0x0		PAD3_DS1 +
0x0		RSVD +
0x0		PAD2_SR +
0x0		RSVD +
0x0		PAD2_DS1 +
0x0		RSVD +
0x0		PAD1_SR +
0x0		RSVD +
0x0		PAD1_DS1 +
0x0		RSVD +
0x0		PAD0_SR +
0x0		RSVD +
0x0		PAD0_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD3_SRRWPad 3 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD3_DS1RWPad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD2_SRRWPad 2 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD2_DS1RWPad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD1_SRRWPad 1 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD1_DS1RWPad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD0_SRRWPad 0 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD0_DS1RWPad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGB - Alternate Pad Configuration reg1 (Pads 7,6,5,4)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100E4 +
+

Description:

+

This register has additional configuration control for pads 7, 6, 5, 4

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD7_SR +
0x0		RSVD +
0x0		PAD7_DS1 +
0x0		RSVD +
0x0		PAD6_SR +
0x0		RSVD +
0x0		PAD6_DS1 +
0x0		RSVD +
0x0		PAD5_SR +
0x0		RSVD +
0x0		PAD5_DS1 +
0x0		RSVD +
0x0		PAD4_SR +
0x0		RSVD +
0x0		PAD4_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD7_SRRWPad 7 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD7_DS1RWPad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD6_SRRWPad 6 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD6_DS1RWPad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD5_SRRWPad 5 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD5_DS1RWPad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD4_SRRWPad 4 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD4_DS1RWPad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGC - Alternate Pad Configuration reg2 (Pads 11,10,9,8)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100E8 +
+

Description:

+

This register has additional configuration control for pads 11, 10, 9, 8

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD11_SR +
0x0		RSVD +
0x0		PAD11_DS1 +
0x0		RSVD +
0x0		PAD10_SR +
0x0		RSVD +
0x0		PAD10_DS1 +
0x0		RSVD +
0x0		PAD9_SR +
0x0		RSVD +
0x0		PAD9_DS1 +
0x0		RSVD +
0x0		PAD8_SR +
0x0		RSVD +
0x0		PAD8_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD11_SRRWPad 11 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD11_DS1RWPad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD10_SRRWPad 10 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD10_DS1RWPad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD9_SRRWPad 9 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD9_DS1RWPad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD8_SRRWPad 8 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD8_DS1RWPad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGD - Alternate Pad Configuration reg3 (Pads 15,14,13,12)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100EC +
+

Description:

+

This register has additional configuration control for pads 15, 14, 13, 12

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD15_SR +
0x0		RSVD +
0x0		PAD15_DS1 +
0x0		RSVD +
0x0		PAD14_SR +
0x0		RSVD +
0x0		PAD14_DS1 +
0x0		RSVD +
0x0		PAD13_SR +
0x0		RSVD +
0x0		PAD13_DS1 +
0x0		RSVD +
0x0		PAD12_SR +
0x0		RSVD +
0x0		PAD12_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD15_SRRWPad 15 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD15_DS1RWPad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD14_SRRWPad 14 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD14_DS1RWPad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD13_SRRWPad 13 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD13_DS1RWPad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD12_SRRWPad 12 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD12_DS1RWPad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGE - Alternate Pad Configuration reg4 (Pads 19,18,17,16)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100F0 +
+

Description:

+

This register has additional configuration control for pads 19, 18, 17, 16

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD19_SR +
0x0		RSVD +
0x0		PAD19_DS1 +
0x0		RSVD +
0x0		PAD18_SR +
0x0		RSVD +
0x0		PAD18_DS1 +
0x0		RSVD +
0x0		PAD17_SR +
0x0		RSVD +
0x0		PAD17_DS1 +
0x0		RSVD +
0x0		PAD16_SR +
0x0		RSVD +
0x0		PAD16_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD19_SRRWPad 19 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD19_DS1RWPad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD18_SRRWPad 18 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD18_DS1RWPad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD17_SRRWPad 17 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD17_DS1RWPad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD16_SRRWPad 16 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD16_DS1RWPad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGF - Alternate Pad Configuration reg5 (Pads 23,22,21,20)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100F4 +
+

Description:

+

This register has additional configuration control for pads 23, 22, 21, 20

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD23_SR +
0x0		RSVD +
0x0		PAD23_DS1 +
0x0		RSVD +
0x0		PAD22_SR +
0x0		RSVD +
0x0		PAD22_DS1 +
0x0		RSVD +
0x0		PAD21_SR +
0x0		RSVD +
0x0		PAD21_DS1 +
0x0		RSVD +
0x0		PAD20_SR +
0x0		RSVD +
0x0		PAD20_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD23_SRRWPad 23 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD23_DS1RWPad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD22_SRRWPad 22 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD22_DS1RWPad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD21_SRRWPad 21 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD21_DS1RWPad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD20_SRRWPad 20 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD20_DS1RWPad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGG - Alternate Pad Configuration reg6 (Pads 27,26,25,24)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100F8 +
+

Description:

+

This register has additional configuration control for pads 27, 26, 25, 24

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD27_SR +
0x0		RSVD +
0x0		PAD27_DS1 +
0x0		RSVD +
0x0		PAD26_SR +
0x0		RSVD +
0x0		PAD26_DS1 +
0x0		RSVD +
0x0		PAD25_SR +
0x0		RSVD +
0x0		PAD25_DS1 +
0x0		RSVD +
0x0		PAD24_SR +
0x0		RSVD +
0x0		PAD24_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD27_SRRWPad 27 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD27_DS1RWPad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD26_SRRWPad 26 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD26_DS1RWPad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD25_SRRWPad 25 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD25_DS1RWPad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD24_SRRWPad 24 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD24_DS1RWPad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGH - Alternate Pad Configuration reg7 (Pads 31,30,29,28)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400100FC +
+

Description:

+

This register has additional configuration control for pads 31, 30, 29, 28

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD31_SR +
0x0		RSVD +
0x0		PAD31_DS1 +
0x0		RSVD +
0x0		PAD30_SR +
0x0		RSVD +
0x0		PAD30_DS1 +
0x0		RSVD +
0x0		PAD29_SR +
0x0		RSVD +
0x0		PAD29_DS1 +
0x0		RSVD +
0x0		PAD28_SR +
0x0		RSVD +
0x0		PAD28_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD31_SRRWPad 31 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD31_DS1RWPad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD30_SRRWPad 30 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD30_DS1RWPad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD29_SRRWPad 29 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD29_DS1RWPad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD28_SRRWPad 28 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD28_DS1RWPad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGI - Alternate Pad Configuration reg8 (Pads 35,34,33,32)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010100 +
+

Description:

+

This register has additional configuration control for pads 35, 34, 33, 32

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD35_SR +
0x0		RSVD +
0x0		PAD35_DS1 +
0x0		RSVD +
0x0		PAD34_SR +
0x0		RSVD +
0x0		PAD34_DS1 +
0x0		RSVD +
0x0		PAD33_SR +
0x0		RSVD +
0x0		PAD33_DS1 +
0x0		RSVD +
0x0		PAD32_SR +
0x0		RSVD +
0x0		PAD32_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD35_SRRWPad 35 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD35_DS1RWPad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD34_SRRWPad 34 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD34_DS1RWPad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD33_SRRWPad 33 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD33_DS1RWPad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD32_SRRWPad 32 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD32_DS1RWPad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGJ - Alternate Pad Configuration reg9 (Pads 39,38,37,36)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010104 +
+

Description:

+

This register has additional configuration control for pads 39, 38, 37, 36

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD39_SR +
0x0		RSVD +
0x0		PAD39_DS1 +
0x0		RSVD +
0x0		PAD38_SR +
0x0		RSVD +
0x0		PAD38_DS1 +
0x0		RSVD +
0x0		PAD37_SR +
0x0		RSVD +
0x0		PAD37_DS1 +
0x0		RSVD +
0x0		PAD36_SR +
0x0		RSVD +
0x0		PAD36_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD39_SRRWPad 39 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD39_DS1RWPad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD38_SRRWPad 38 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD38_DS1RWPad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD37_SRRWPad 37 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD37_DS1RWPad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD36_SRRWPad 36 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD36_DS1RWPad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGK - Alternate Pad Configuration reg10 (Pads 43,42,41,40)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010108 +
+

Description:

+

This register has additional configuration control for pads 43, 42, 41, 40

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD43_SR +
0x0		RSVD +
0x0		PAD43_DS1 +
0x0		RSVD +
0x0		PAD42_SR +
0x0		RSVD +
0x0		PAD42_DS1 +
0x0		RSVD +
0x0		PAD41_SR +
0x0		RSVD +
0x0		PAD41_DS1 +
0x0		RSVD +
0x0		PAD40_SR +
0x0		RSVD +
0x0		PAD40_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD43_SRRWPad 43 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD43_DS1RWPad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD42_SRRWPad 42 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD42_DS1RWPad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD41_SRRWPad 41 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD41_DS1RWPad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD40_SRRWPad 40 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD40_DS1RWPad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGL - Alternate Pad Configuration reg11 (Pads 47,46,45,44)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001010C +
+

Description:

+

This register has additional configuration control for pads 47, 46, 45, 44

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD47_SR +
0x0		RSVD +
0x0		PAD47_DS1 +
0x0		RSVD +
0x0		PAD46_SR +
0x0		RSVD +
0x0		PAD46_DS1 +
0x0		RSVD +
0x0		PAD45_SR +
0x0		RSVD +
0x0		PAD45_DS1 +
0x0		RSVD +
0x0		PAD44_SR +
0x0		RSVD +
0x0		PAD44_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:29RSVDRORESERVED

+
28PAD47_SRRWPad 47 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
27:25RSVDRORESERVED

+
24PAD47_DS1RWPad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength.

+
23:21RSVDRORESERVED

+
20PAD46_SRRWPad 46 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
19:17RSVDRORESERVED

+
16PAD46_DS1RWPad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength.

+
15:13RSVDRORESERVED

+
12PAD45_SRRWPad 45 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD45_DS1RWPad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD44_SRRWPad 44 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD44_DS1RWPad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

ALTPADCFGM - Alternate Pad Configuration reg12 (Pads 49,48)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010110 +
+

Description:

+

This register has additional configuration control for pads 49, 48

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PAD49_SR +
0x0		RSVD +
0x0		PAD49_DS1 +
0x0		RSVD +
0x0		PAD48_SR +
0x0		RSVD +
0x0		PAD48_DS1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:13RSVDRORESERVED

+
12PAD49_SRRWPad 49 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
11:9RSVDRORESERVED

+
8PAD49_DS1RWPad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength.

+
7:5RSVDRORESERVED

+
4PAD48_SRRWPad 48 slew rate selection.

+ SR_EN = 0x1 - Enables Slew rate control on pad
3:1RSVDRORESERVED

+
0PAD48_DS1RWPad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength.

+
+
+
+
+ +
+
+

INT0EN - GPIO Interrupt Registers 31-0: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO31 +
0x0		GPIO30 +
0x0		GPIO29 +
0x0		GPIO28 +
0x0		GPIO27 +
0x0		GPIO26 +
0x0		GPIO25 +
0x0		GPIO24 +
0x0		GPIO23 +
0x0		GPIO22 +
0x0		GPIO21 +
0x0		GPIO20 +
0x0		GPIO19 +
0x0		GPIO18 +
0x0		GPIO17 +
0x0		GPIO16 +
0x0		GPIO15 +
0x0		GPIO14 +
0x0		GPIO13 +
0x0		GPIO12 +
0x0		GPIO11 +
0x0		GPIO10 +
0x0		GPIO9 +
0x0		GPIO8 +
0x0		GPIO7 +
0x0		GPIO6 +
0x0		GPIO5 +
0x0		GPIO4 +
0x0		GPIO3 +
0x0		GPIO2 +
0x0		GPIO1 +
0x0		GPIO0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO31RWGPIO31 interrupt.

+
30GPIO30RWGPIO30 interrupt.

+
29GPIO29RWGPIO29 interrupt.

+
28GPIO28RWGPIO28 interrupt.

+
27GPIO27RWGPIO27 interrupt.

+
26GPIO26RWGPIO26 interrupt.

+
25GPIO25RWGPIO25 interrupt.

+
24GPIO24RWGPIO24 interrupt.

+
23GPIO23RWGPIO23 interrupt.

+
22GPIO22RWGPIO22 interrupt.

+
21GPIO21RWGPIO21 interrupt.

+
20GPIO20RWGPIO20 interrupt.

+
19GPIO19RWGPIO19 interrupt.

+
18GPIO18RWGPIO18interrupt.

+
17GPIO17RWGPIO17 interrupt.

+
16GPIO16RWGPIO16 interrupt.

+
15GPIO15RWGPIO15 interrupt.

+
14GPIO14RWGPIO14 interrupt.

+
13GPIO13RWGPIO13 interrupt.

+
12GPIO12RWGPIO12 interrupt.

+
11GPIO11RWGPIO11 interrupt.

+
10GPIO10RWGPIO10 interrupt.

+
9GPIO9RWGPIO9 interrupt.

+
8GPIO8RWGPIO8 interrupt.

+
7GPIO7RWGPIO7 interrupt.

+
6GPIO6RWGPIO6 interrupt.

+
5GPIO5RWGPIO5 interrupt.

+
4GPIO4RWGPIO4 interrupt.

+
3GPIO3RWGPIO3 interrupt.

+
2GPIO2RWGPIO2 interrupt.

+
1GPIO1RWGPIO1 interrupt.

+
0GPIO0RWGPIO0 interrupt.

+
+
+
+
+ +
+
+

INT0STAT - GPIO Interrupt Registers 31-0: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO31 +
0x0		GPIO30 +
0x0		GPIO29 +
0x0		GPIO28 +
0x0		GPIO27 +
0x0		GPIO26 +
0x0		GPIO25 +
0x0		GPIO24 +
0x0		GPIO23 +
0x0		GPIO22 +
0x0		GPIO21 +
0x0		GPIO20 +
0x0		GPIO19 +
0x0		GPIO18 +
0x0		GPIO17 +
0x0		GPIO16 +
0x0		GPIO15 +
0x0		GPIO14 +
0x0		GPIO13 +
0x0		GPIO12 +
0x0		GPIO11 +
0x0		GPIO10 +
0x0		GPIO9 +
0x0		GPIO8 +
0x0		GPIO7 +
0x0		GPIO6 +
0x0		GPIO5 +
0x0		GPIO4 +
0x0		GPIO3 +
0x0		GPIO2 +
0x0		GPIO1 +
0x0		GPIO0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO31RWGPIO31 interrupt.

+
30GPIO30RWGPIO30 interrupt.

+
29GPIO29RWGPIO29 interrupt.

+
28GPIO28RWGPIO28 interrupt.

+
27GPIO27RWGPIO27 interrupt.

+
26GPIO26RWGPIO26 interrupt.

+
25GPIO25RWGPIO25 interrupt.

+
24GPIO24RWGPIO24 interrupt.

+
23GPIO23RWGPIO23 interrupt.

+
22GPIO22RWGPIO22 interrupt.

+
21GPIO21RWGPIO21 interrupt.

+
20GPIO20RWGPIO20 interrupt.

+
19GPIO19RWGPIO19 interrupt.

+
18GPIO18RWGPIO18interrupt.

+
17GPIO17RWGPIO17 interrupt.

+
16GPIO16RWGPIO16 interrupt.

+
15GPIO15RWGPIO15 interrupt.

+
14GPIO14RWGPIO14 interrupt.

+
13GPIO13RWGPIO13 interrupt.

+
12GPIO12RWGPIO12 interrupt.

+
11GPIO11RWGPIO11 interrupt.

+
10GPIO10RWGPIO10 interrupt.

+
9GPIO9RWGPIO9 interrupt.

+
8GPIO8RWGPIO8 interrupt.

+
7GPIO7RWGPIO7 interrupt.

+
6GPIO6RWGPIO6 interrupt.

+
5GPIO5RWGPIO5 interrupt.

+
4GPIO4RWGPIO4 interrupt.

+
3GPIO3RWGPIO3 interrupt.

+
2GPIO2RWGPIO2 interrupt.

+
1GPIO1RWGPIO1 interrupt.

+
0GPIO0RWGPIO0 interrupt.

+
+
+
+
+ +
+
+

INT0CLR - GPIO Interrupt Registers 31-0: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO31 +
0x0		GPIO30 +
0x0		GPIO29 +
0x0		GPIO28 +
0x0		GPIO27 +
0x0		GPIO26 +
0x0		GPIO25 +
0x0		GPIO24 +
0x0		GPIO23 +
0x0		GPIO22 +
0x0		GPIO21 +
0x0		GPIO20 +
0x0		GPIO19 +
0x0		GPIO18 +
0x0		GPIO17 +
0x0		GPIO16 +
0x0		GPIO15 +
0x0		GPIO14 +
0x0		GPIO13 +
0x0		GPIO12 +
0x0		GPIO11 +
0x0		GPIO10 +
0x0		GPIO9 +
0x0		GPIO8 +
0x0		GPIO7 +
0x0		GPIO6 +
0x0		GPIO5 +
0x0		GPIO4 +
0x0		GPIO3 +
0x0		GPIO2 +
0x0		GPIO1 +
0x0		GPIO0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO31RWGPIO31 interrupt.

+
30GPIO30RWGPIO30 interrupt.

+
29GPIO29RWGPIO29 interrupt.

+
28GPIO28RWGPIO28 interrupt.

+
27GPIO27RWGPIO27 interrupt.

+
26GPIO26RWGPIO26 interrupt.

+
25GPIO25RWGPIO25 interrupt.

+
24GPIO24RWGPIO24 interrupt.

+
23GPIO23RWGPIO23 interrupt.

+
22GPIO22RWGPIO22 interrupt.

+
21GPIO21RWGPIO21 interrupt.

+
20GPIO20RWGPIO20 interrupt.

+
19GPIO19RWGPIO19 interrupt.

+
18GPIO18RWGPIO18interrupt.

+
17GPIO17RWGPIO17 interrupt.

+
16GPIO16RWGPIO16 interrupt.

+
15GPIO15RWGPIO15 interrupt.

+
14GPIO14RWGPIO14 interrupt.

+
13GPIO13RWGPIO13 interrupt.

+
12GPIO12RWGPIO12 interrupt.

+
11GPIO11RWGPIO11 interrupt.

+
10GPIO10RWGPIO10 interrupt.

+
9GPIO9RWGPIO9 interrupt.

+
8GPIO8RWGPIO8 interrupt.

+
7GPIO7RWGPIO7 interrupt.

+
6GPIO6RWGPIO6 interrupt.

+
5GPIO5RWGPIO5 interrupt.

+
4GPIO4RWGPIO4 interrupt.

+
3GPIO3RWGPIO3 interrupt.

+
2GPIO2RWGPIO2 interrupt.

+
1GPIO1RWGPIO1 interrupt.

+
0GPIO0RWGPIO0 interrupt.

+
+
+
+
+ +
+
+

INT0SET - GPIO Interrupt Registers 31-0: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001020C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
GPIO31 +
0x0		GPIO30 +
0x0		GPIO29 +
0x0		GPIO28 +
0x0		GPIO27 +
0x0		GPIO26 +
0x0		GPIO25 +
0x0		GPIO24 +
0x0		GPIO23 +
0x0		GPIO22 +
0x0		GPIO21 +
0x0		GPIO20 +
0x0		GPIO19 +
0x0		GPIO18 +
0x0		GPIO17 +
0x0		GPIO16 +
0x0		GPIO15 +
0x0		GPIO14 +
0x0		GPIO13 +
0x0		GPIO12 +
0x0		GPIO11 +
0x0		GPIO10 +
0x0		GPIO9 +
0x0		GPIO8 +
0x0		GPIO7 +
0x0		GPIO6 +
0x0		GPIO5 +
0x0		GPIO4 +
0x0		GPIO3 +
0x0		GPIO2 +
0x0		GPIO1 +
0x0		GPIO0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31GPIO31RWGPIO31 interrupt.

+
30GPIO30RWGPIO30 interrupt.

+
29GPIO29RWGPIO29 interrupt.

+
28GPIO28RWGPIO28 interrupt.

+
27GPIO27RWGPIO27 interrupt.

+
26GPIO26RWGPIO26 interrupt.

+
25GPIO25RWGPIO25 interrupt.

+
24GPIO24RWGPIO24 interrupt.

+
23GPIO23RWGPIO23 interrupt.

+
22GPIO22RWGPIO22 interrupt.

+
21GPIO21RWGPIO21 interrupt.

+
20GPIO20RWGPIO20 interrupt.

+
19GPIO19RWGPIO19 interrupt.

+
18GPIO18RWGPIO18interrupt.

+
17GPIO17RWGPIO17 interrupt.

+
16GPIO16RWGPIO16 interrupt.

+
15GPIO15RWGPIO15 interrupt.

+
14GPIO14RWGPIO14 interrupt.

+
13GPIO13RWGPIO13 interrupt.

+
12GPIO12RWGPIO12 interrupt.

+
11GPIO11RWGPIO11 interrupt.

+
10GPIO10RWGPIO10 interrupt.

+
9GPIO9RWGPIO9 interrupt.

+
8GPIO8RWGPIO8 interrupt.

+
7GPIO7RWGPIO7 interrupt.

+
6GPIO6RWGPIO6 interrupt.

+
5GPIO5RWGPIO5 interrupt.

+
4GPIO4RWGPIO4 interrupt.

+
3GPIO3RWGPIO3 interrupt.

+
2GPIO2RWGPIO2 interrupt.

+
1GPIO1RWGPIO1 interrupt.

+
0GPIO0RWGPIO0 interrupt.

+
+
+
+
+ +
+
+

INT1EN - GPIO Interrupt Registers 49-32: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010210 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		GPIO49 +
0x0		GPIO48 +
0x0		GPIO47 +
0x0		GPIO46 +
0x0		GPIO45 +
0x0		GPIO44 +
0x0		GPIO43 +
0x0		GPIO42 +
0x0		GPIO41 +
0x0		GPIO40 +
0x0		GPIO39 +
0x0		GPIO38 +
0x0		GPIO37 +
0x0		GPIO36 +
0x0		GPIO35 +
0x0		GPIO34 +
0x0		GPIO33 +
0x0		GPIO32 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17GPIO49RWGPIO49 interrupt.

+
16GPIO48RWGPIO48 interrupt.

+
15GPIO47RWGPIO47 interrupt.

+
14GPIO46RWGPIO46 interrupt.

+
13GPIO45RWGPIO45 interrupt.

+
12GPIO44RWGPIO44 interrupt.

+
11GPIO43RWGPIO43 interrupt.

+
10GPIO42RWGPIO42 interrupt.

+
9GPIO41RWGPIO41 interrupt.

+
8GPIO40RWGPIO40 interrupt.

+
7GPIO39RWGPIO39 interrupt.

+
6GPIO38RWGPIO38 interrupt.

+
5GPIO37RWGPIO37 interrupt.

+
4GPIO36RWGPIO36 interrupt.

+
3GPIO35RWGPIO35 interrupt.

+
2GPIO34RWGPIO34 interrupt.

+
1GPIO33RWGPIO33 interrupt.

+
0GPIO32RWGPIO32 interrupt.

+
+
+
+
+ +
+
+

INT1STAT - GPIO Interrupt Registers 49-32: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010214 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		GPIO49 +
0x0		GPIO48 +
0x0		GPIO47 +
0x0		GPIO46 +
0x0		GPIO45 +
0x0		GPIO44 +
0x0		GPIO43 +
0x0		GPIO42 +
0x0		GPIO41 +
0x0		GPIO40 +
0x0		GPIO39 +
0x0		GPIO38 +
0x0		GPIO37 +
0x0		GPIO36 +
0x0		GPIO35 +
0x0		GPIO34 +
0x0		GPIO33 +
0x0		GPIO32 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17GPIO49RWGPIO49 interrupt.

+
16GPIO48RWGPIO48 interrupt.

+
15GPIO47RWGPIO47 interrupt.

+
14GPIO46RWGPIO46 interrupt.

+
13GPIO45RWGPIO45 interrupt.

+
12GPIO44RWGPIO44 interrupt.

+
11GPIO43RWGPIO43 interrupt.

+
10GPIO42RWGPIO42 interrupt.

+
9GPIO41RWGPIO41 interrupt.

+
8GPIO40RWGPIO40 interrupt.

+
7GPIO39RWGPIO39 interrupt.

+
6GPIO38RWGPIO38 interrupt.

+
5GPIO37RWGPIO37 interrupt.

+
4GPIO36RWGPIO36 interrupt.

+
3GPIO35RWGPIO35 interrupt.

+
2GPIO34RWGPIO34 interrupt.

+
1GPIO33RWGPIO33 interrupt.

+
0GPIO32RWGPIO32 interrupt.

+
+
+
+
+ +
+
+

INT1CLR - GPIO Interrupt Registers 49-32: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40010218 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		GPIO49 +
0x0		GPIO48 +
0x0		GPIO47 +
0x0		GPIO46 +
0x0		GPIO45 +
0x0		GPIO44 +
0x0		GPIO43 +
0x0		GPIO42 +
0x0		GPIO41 +
0x0		GPIO40 +
0x0		GPIO39 +
0x0		GPIO38 +
0x0		GPIO37 +
0x0		GPIO36 +
0x0		GPIO35 +
0x0		GPIO34 +
0x0		GPIO33 +
0x0		GPIO32 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17GPIO49RWGPIO49 interrupt.

+
16GPIO48RWGPIO48 interrupt.

+
15GPIO47RWGPIO47 interrupt.

+
14GPIO46RWGPIO46 interrupt.

+
13GPIO45RWGPIO45 interrupt.

+
12GPIO44RWGPIO44 interrupt.

+
11GPIO43RWGPIO43 interrupt.

+
10GPIO42RWGPIO42 interrupt.

+
9GPIO41RWGPIO41 interrupt.

+
8GPIO40RWGPIO40 interrupt.

+
7GPIO39RWGPIO39 interrupt.

+
6GPIO38RWGPIO38 interrupt.

+
5GPIO37RWGPIO37 interrupt.

+
4GPIO36RWGPIO36 interrupt.

+
3GPIO35RWGPIO35 interrupt.

+
2GPIO34RWGPIO34 interrupt.

+
1GPIO33RWGPIO33 interrupt.

+
0GPIO32RWGPIO32 interrupt.

+
+
+
+
+ +
+
+

INT1SET - GPIO Interrupt Registers 49-32: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4001021C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		GPIO49 +
0x0		GPIO48 +
0x0		GPIO47 +
0x0		GPIO46 +
0x0		GPIO45 +
0x0		GPIO44 +
0x0		GPIO43 +
0x0		GPIO42 +
0x0		GPIO41 +
0x0		GPIO40 +
0x0		GPIO39 +
0x0		GPIO38 +
0x0		GPIO37 +
0x0		GPIO36 +
0x0		GPIO35 +
0x0		GPIO34 +
0x0		GPIO33 +
0x0		GPIO32 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED

+
17GPIO49RWGPIO49 interrupt.

+
16GPIO48RWGPIO48 interrupt.

+
15GPIO47RWGPIO47 interrupt.

+
14GPIO46RWGPIO46 interrupt.

+
13GPIO45RWGPIO45 interrupt.

+
12GPIO44RWGPIO44 interrupt.

+
11GPIO43RWGPIO43 interrupt.

+
10GPIO42RWGPIO42 interrupt.

+
9GPIO41RWGPIO41 interrupt.

+
8GPIO40RWGPIO40 interrupt.

+
7GPIO39RWGPIO39 interrupt.

+
6GPIO38RWGPIO38 interrupt.

+
5GPIO37RWGPIO37 interrupt.

+
4GPIO36RWGPIO36 interrupt.

+
3GPIO35RWGPIO35 interrupt.

+
2GPIO34RWGPIO34 interrupt.

+
1GPIO33RWGPIO33 interrupt.

+
0GPIO32RWGPIO32 interrupt.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/iomstr_regs.html b/docs/apollo2/pages/iomstr_regs.html new file mode 100644 index 0000000..7fc1e81 --- /dev/null +++ b/docs/apollo2/pages/iomstr_regs.html @@ -0,0 +1,3253 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
IOMSTR - I2C/SPI Master
+
+
+ + +
+
+
+

IOMSTR Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + FIFO - FIFO Access Port +
+   + 0x00000100: + +   + FIFOPTR - Current FIFO Pointers +
+   + 0x00000104: + +   + TLNGTH - Transfer Length +
+   + 0x00000108: + +   + FIFOTHR - FIFO Threshold Configuration +
+   + 0x0000010C: + +   + CLKCFG - I/O Clock Configuration +
+   + 0x00000110: + +   + CMD - Command Register +
+   + 0x00000114: + +   + CMDRPT - Command Repeat Register +
+   + 0x00000118: + +   + STATUS - Status Register +
+   + 0x0000011C: + +   + CFG - I/O Master Configuration +
+   + 0x00000200: + +   + INTEN - IO Master Interrupts: Enable +
+   + 0x00000204: + +   + INTSTAT - IO Master Interrupts: Status +
+   + 0x00000208: + +   + INTCLR - IO Master Interrupts: Clear +
+   + 0x0000020C: + +   + INTSET - IO Master Interrupts: Set +
+
+
+ +
+
+

FIFO - FIFO Access Port

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004000 +
+   + Instance 1 Address: + +   + 0x50005000 +
+   + Instance 2 Address: + +   + 0x50006000 +
+   + Instance 3 Address: + +   + 0x50007000 +
+   + Instance 4 Address: + +   + 0x50008000 +
+   + Instance 5 Address: + +   + 0x50009000 +
+

Description:

+

FIFO Access Port

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
FIFO +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0FIFORWFIFO access port.

+
+
+
+
+ +
+
+

FIFOPTR - Current FIFO Pointers

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004100 +
+   + Instance 1 Address: + +   + 0x50005100 +
+   + Instance 2 Address: + +   + 0x50006100 +
+   + Instance 3 Address: + +   + 0x50007100 +
+   + Instance 4 Address: + +   + 0x50008100 +
+   + Instance 5 Address: + +   + 0x50009100 +
+

Description:

+

Current FIFO Pointers

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOREM +
0x0		RSVD +
0x0		FIFOSIZ +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED

+
23:16FIFOREMROThe number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)).

+
15:8RSVDRORESERVED

+
7:0FIFOSIZROThe number of bytes currently in the FIFO.

+
+
+
+
+ +
+
+

TLNGTH - Transfer Length

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004104 +
+   + Instance 1 Address: + +   + 0x50005104 +
+   + Instance 2 Address: + +   + 0x50006104 +
+   + Instance 3 Address: + +   + 0x50007104 +
+   + Instance 4 Address: + +   + 0x50008104 +
+   + Instance 5 Address: + +   + 0x50009104 +
+

Description:

+

Transfer Length

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		TLNGTH +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:12RSVDRORESERVED

+
11:0TLNGTHRORemaining transfer length.

+
+
+
+
+ +
+
+

FIFOTHR - FIFO Threshold Configuration

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004108 +
+   + Instance 1 Address: + +   + 0x50005108 +
+   + Instance 2 Address: + +   + 0x50006108 +
+   + Instance 3 Address: + +   + 0x50007108 +
+   + Instance 4 Address: + +   + 0x50008108 +
+   + Instance 5 Address: + +   + 0x50009108 +
+

Description:

+

FIFO Threshold Configuration

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOWTHR +
0x0		RSVD +
0x0		FIFORTHR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:15RSVDRORESERVED

+
14:8FIFOWTHRRWFIFO write threshold.

+
7RSVDRORESERVED

+
6:0FIFORTHRRWFIFO read threshold.

+
+
+
+
+ +
+
+

CLKCFG - I/O Clock Configuration

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x5000410C +
+   + Instance 1 Address: + +   + 0x5000510C +
+   + Instance 2 Address: + +   + 0x5000610C +
+   + Instance 3 Address: + +   + 0x5000710C +
+   + Instance 4 Address: + +   + 0x5000810C +
+   + Instance 5 Address: + +   + 0x5000910C +
+

Description:

+

I/O Clock Configuration

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
TOTPER +
0x0		LOWPER +
0x0		RSVD +
0x0		DIVEN +
0x0		DIV3 +
0x0		FSEL +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24TOTPERRWClock total count minus 1.

+
23:16LOWPERRWClock low count minus 1.

+
15:13RSVDRORESERVED

+
12DIVENRWEnable clock division by TOTPER.

+ DIS = 0x0 - Disable TOTPER division.
+ EN = 0x1 - Enable TOTPER division.
11DIV3RWEnable divide by 3.

+ DIS = 0x0 - Select divide by 1.
+ EN = 0x1 - Select divide by 3.
10:8FSELRWSelect the input clock frequency.

+ MIN_PWR = 0x0 - Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active.
+ HFRC = 0x1 - Selects the HFRC as the input clock.
+ HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock.
+ HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock.
+ HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock.
+ HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock.
+ HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock.
+ HFRC_DIV64 = 0x7 - Selects the HFRC / 64 as the input clock.
7:0RSVDRORESERVED

+
+
+
+
+ +
+
+

CMD - Command Register

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004110 +
+   + Instance 1 Address: + +   + 0x50005110 +
+   + Instance 2 Address: + +   + 0x50006110 +
+   + Instance 3 Address: + +   + 0x50007110 +
+   + Instance 4 Address: + +   + 0x50008110 +
+   + Instance 5 Address: + +   + 0x50009110 +
+

Description:

+

Command Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CMD +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CMDRWThis register holds the I/O Command

+
+
+
+
+ +
+
+

CMDRPT - Command Repeat Register

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004114 +
+   + Instance 1 Address: + +   + 0x50005114 +
+   + Instance 2 Address: + +   + 0x50006114 +
+   + Instance 3 Address: + +   + 0x50007114 +
+   + Instance 4 Address: + +   + 0x50008114 +
+   + Instance 5 Address: + +   + 0x50009114 +
+

Description:

+

Command Repeat Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CMDRPT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:5RSVDRORESERVED

+
4:0CMDRPTRWThese bits hold the Command repeat count.

+
+
+
+
+ +
+
+

STATUS - Status Register

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004118 +
+   + Instance 1 Address: + +   + 0x50005118 +
+   + Instance 2 Address: + +   + 0x50006118 +
+   + Instance 3 Address: + +   + 0x50007118 +
+   + Instance 4 Address: + +   + 0x50008118 +
+   + Instance 5 Address: + +   + 0x50009118 +
+

Description:

+

Status Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IDLEST +
0x0		CMDACT +
0x0		ERR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED

+
2IDLESTROThis bit indicates if the I/O state machine is IDLE.

+ IDLE = 0x1 - The I/O state machine is in the idle state.
1CMDACTROThis bit indicates if the I/O Command is active.

+ ACTIVE = 0x1 - An I/O command is active.
0ERRROThis bit indicates if an error interrupt has occurred.

+ ERROR = 0x1 - An error has been indicated by the IOM.
+
+
+
+ +
+
+

CFG - I/O Master Configuration

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x5000411C +
+   + Instance 1 Address: + +   + 0x5000511C +
+   + Instance 2 Address: + +   + 0x5000611C +
+   + Instance 3 Address: + +   + 0x5000711C +
+   + Instance 4 Address: + +   + 0x5000811C +
+   + Instance 5 Address: + +   + 0x5000911C +
+

Description:

+

I/O Master Configuration

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
IFCEN +
0x0		RSVD +
0x0		RDFCPOL +
0x0		WTFCPOL +
0x1		WTFCIRQ +
0x0		FCDEL +
0x0		MOSIINV +
0x0		RDFC +
0x0		WTFC +
0x0		RSVD +
0x0		STARTRD +
0x0		FULLDUP +
0x0		SPHA +
0x0		SPOL +
0x0		IFCSEL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31IFCENRWThis bit enables the IO Master.

+ DIS = 0x0 - Disable the IO Master.
+ EN = 0x1 - Enable the IO Master.
30:15RSVDRORESERVED

+
14RDFCPOLRWThis bit selects the read flow control signal polarity.

+ HIGH = 0x0 - Flow control signal high creates flow control.
+ LOW = 0x1 - Flow control signal low creates flow control.
13WTFCPOLRWThis bit selects the write flow control signal polarity.

+ HIGH = 0x0 - Flow control signal high creates flow control.
+ LOW = 0x1 - Flow control signal low creates flow control.
12WTFCIRQRWThis bit selects the write mode flow control signal.

+ MISO = 0x0 - MISO is used as the write mode flow control signal.
+ IRQ = 0x1 - IRQ is used as the write mode flow control signal.
11FCDELRWThis bit must be left at the default value of 0.

+
10MOSIINVRWThis bit invewrts MOSI when flow control is enabled.

+ NORMAL = 0x0 - MOSI is set to 0 in read mode and 1 in write mode.
+ INVERT = 0x1 - MOSI is set to 1 in read mode and 0 in write mode.
9RDFCRWThis bit enables read mode flow control.

+ DIS = 0x0 - Read mode flow control disabled.
+ EN = 0x1 - Read mode flow control enabled.
8WTFCRWThis bit enables write mode flow control.

+ DIS = 0x0 - Write mode flow control disabled.
+ EN = 0x1 - Write mode flow control enabled.
7:6RSVDRORESERVED

+
5:4STARTRDRWThis bit selects the preread timing.

+ PRERD0 = 0x0 - 0 read delay cycles.
+ PRERD1 = 0x1 - 1 read delay cycles.
+ PRERD2 = 0x2 - 2 read delay cycles.
+ PRERD3 = 0x3 - 3 read delay cycles.
3FULLDUPRWThis bit selects full duplex mode.

+ NORMAL = 0x0 - 128 byte FIFO in half duplex mode.
+ FULLDUP = 0x1 - 64 byte FIFO in full duplex mode.
2SPHARWThis bit selects SPI phase.

+ SAMPLE_LEADING_EDGE = 0x0 - Sample on the leading (first) clock edge.
+ SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge.
1SPOLRWThis bit selects SPI polarity.

+ CLK_BASE_0 = 0x0 - The base value of the clock is 0.
+ CLK_BASE_1 = 0x1 - The base value of the clock is 1.
0IFCSELRWThis bit selects the I/O interface.

+ I2C = 0x0 - Selects I2C interface for the I/O Master.
+ SPI = 0x1 - Selects SPI interface for the I/O Master.
+
+
+
+ +
+
+

INTEN - IO Master Interrupts: Enable

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004200 +
+   + Instance 1 Address: + +   + 0x50005200 +
+   + Instance 2 Address: + +   + 0x50006200 +
+   + Instance 3 Address: + +   + 0x50007200 +
+   + Instance 4 Address: + +   + 0x50008200 +
+   + Instance 5 Address: + +   + 0x50009200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ARB +
0x0		STOP +
0x0		START +
0x0		ICMD +
0x0		IACC +
0x0		WTLEN +
0x0		NAK +
0x0		FOVFL +
0x0		FUNDFL +
0x0		THR +
0x0		CMDCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED

+
10ARBRWThis is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.

+
9STOPRWThis is the STOP command interrupt. A STOP bit was detected by the IOM.

+
8STARTRWThis is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.

+
7ICMDRWThis is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.

+
6IACCRWThis is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.

+
5WTLENRWThis is the WTLEN interrupt.

+
4NAKRWThis is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.

+
3FOVFLRWThis is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).

+
2FUNDFLRWThis is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).

+
1THRRWThis is the FIFO Threshold interrupt.

+
0CMDCMPRWThis is the Command Complete interrupt.

+
+
+
+
+ +
+
+

INTSTAT - IO Master Interrupts: Status

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004204 +
+   + Instance 1 Address: + +   + 0x50005204 +
+   + Instance 2 Address: + +   + 0x50006204 +
+   + Instance 3 Address: + +   + 0x50007204 +
+   + Instance 4 Address: + +   + 0x50008204 +
+   + Instance 5 Address: + +   + 0x50009204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ARB +
0x0		STOP +
0x0		START +
0x0		ICMD +
0x0		IACC +
0x0		WTLEN +
0x0		NAK +
0x0		FOVFL +
0x0		FUNDFL +
0x0		THR +
0x0		CMDCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED

+
10ARBRWThis is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.

+
9STOPRWThis is the STOP command interrupt. A STOP bit was detected by the IOM.

+
8STARTRWThis is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.

+
7ICMDRWThis is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.

+
6IACCRWThis is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.

+
5WTLENRWThis is the WTLEN interrupt.

+
4NAKRWThis is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.

+
3FOVFLRWThis is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).

+
2FUNDFLRWThis is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).

+
1THRRWThis is the FIFO Threshold interrupt.

+
0CMDCMPRWThis is the Command Complete interrupt.

+
+
+
+
+ +
+
+

INTCLR - IO Master Interrupts: Clear

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x50004208 +
+   + Instance 1 Address: + +   + 0x50005208 +
+   + Instance 2 Address: + +   + 0x50006208 +
+   + Instance 3 Address: + +   + 0x50007208 +
+   + Instance 4 Address: + +   + 0x50008208 +
+   + Instance 5 Address: + +   + 0x50009208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ARB +
0x0		STOP +
0x0		START +
0x0		ICMD +
0x0		IACC +
0x0		WTLEN +
0x0		NAK +
0x0		FOVFL +
0x0		FUNDFL +
0x0		THR +
0x0		CMDCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED

+
10ARBRWThis is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.

+
9STOPRWThis is the STOP command interrupt. A STOP bit was detected by the IOM.

+
8STARTRWThis is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.

+
7ICMDRWThis is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.

+
6IACCRWThis is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.

+
5WTLENRWThis is the WTLEN interrupt.

+
4NAKRWThis is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.

+
3FOVFLRWThis is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).

+
2FUNDFLRWThis is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).

+
1THRRWThis is the FIFO Threshold interrupt.

+
0CMDCMPRWThis is the Command Complete interrupt.

+
+
+
+
+ +
+
+

INTSET - IO Master Interrupts: Set

+
+
+

Address:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x5000420C +
+   + Instance 1 Address: + +   + 0x5000520C +
+   + Instance 2 Address: + +   + 0x5000620C +
+   + Instance 3 Address: + +   + 0x5000720C +
+   + Instance 4 Address: + +   + 0x5000820C +
+   + Instance 5 Address: + +   + 0x5000920C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ARB +
0x0		STOP +
0x0		START +
0x0		ICMD +
0x0		IACC +
0x0		WTLEN +
0x0		NAK +
0x0		FOVFL +
0x0		FUNDFL +
0x0		THR +
0x0		CMDCMP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED

+
10ARBRWThis is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.

+
9STOPRWThis is the STOP command interrupt. A STOP bit was detected by the IOM.

+
8STARTRWThis is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.

+
7ICMDRWThis is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.

+
6IACCRWThis is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.

+
5WTLENRWThis is the WTLEN interrupt.

+
4NAKRWThis is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.

+
3FOVFLRWThis is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).

+
2FUNDFLRWThis is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).

+
1THRRWThis is the FIFO Threshold interrupt.

+
0CMDCMPRWThis is the Command Complete interrupt.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/ioslave_regs.html b/docs/apollo2/pages/ioslave_regs.html new file mode 100644 index 0000000..50bcc16 --- /dev/null +++ b/docs/apollo2/pages/ioslave_regs.html @@ -0,0 +1,3052 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
IOSLAVE - I2C/SPI Slave
+
+
+ + +
+
+
+

IOSLAVE Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000100: + +   + FIFOPTR - Current FIFO Pointer +
+   + 0x00000104: + +   + FIFOCFG - FIFO Configuration +
+   + 0x00000108: + +   + FIFOTHR - FIFO Threshold Configuration +
+   + 0x0000010C: + +   + FUPD - FIFO Update Status +
+   + 0x00000110: + +   + FIFOCTR - Overall FIFO Counter +
+   + 0x00000114: + +   + FIFOINC - Overall FIFO Counter Increment +
+   + 0x00000118: + +   + CFG - I/O Slave Configuration +
+   + 0x0000011C: + +   + PRENC - I/O Slave Interrupt Priority Encode +
+   + 0x00000120: + +   + IOINTCTL - I/O Interrupt Control +
+   + 0x00000124: + +   + GENADD - General Address Data +
+   + 0x00000200: + +   + INTEN - IO Slave Interrupts: Enable +
+   + 0x00000204: + +   + INTSTAT - IO Slave Interrupts: Status +
+   + 0x00000208: + +   + INTCLR - IO Slave Interrupts: Clear +
+   + 0x0000020C: + +   + INTSET - IO Slave Interrupts: Set +
+   + 0x00000210: + +   + REGACCINTEN - Register Access Interrupts: Enable +
+   + 0x00000214: + +   + REGACCINTSTAT - Register Access Interrupts: Status +
+   + 0x00000218: + +   + REGACCINTCLR - Register Access Interrupts: Clear +
+   + 0x0000021C: + +   + REGACCINTSET - Register Access Interrupts: Set +
+
+
+ +
+
+

FIFOPTR - Current FIFO Pointer

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000100 +
+

Description:

+

Current FIFO Pointer

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOSIZ +
0x0		FIFOPTR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15:8FIFOSIZRWThe number of bytes currently in the hardware FIFO.

+
7:0FIFOPTRRWCurrent FIFO pointer.

+
+
+
+
+ +
+
+

FIFOCFG - FIFO Configuration

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000104 +
+

Description:

+

FIFO Configuration

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ROBASE +
0x20		RSVD +
0x0		RSVD +
0x0		FIFOMAX +
0x0		RSVD +
0x0		FIFOBASE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:24ROBASERWDefines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1)

+
23:16RSVDRORESERVED

+
15:14RSVDRORESERVED

+
13:8FIFOMAXRWThese bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F.

+
7:5RSVDRORESERVED

+
4:0FIFOBASERWThese bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).

+
+
+
+
+ +
+
+

FIFOTHR - FIFO Threshold Configuration

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000108 +
+

Description:

+

FIFO Threshold Configuration

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOTHR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED

+
7:0FIFOTHRRWFIFO size interrupt threshold.

+
+
+
+
+ +
+
+

FUPD - FIFO Update Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5000010C +
+

Description:

+

FIFO Update Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		IOREAD +
0x0		FIFOUPD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED

+
1IOREADROThis bitfield indicates an IO read is active.

+
0FIFOUPDRWThis bit indicates that a FIFO update is underway.

+
+
+
+
+ +
+
+

FIFOCTR - Overall FIFO Counter

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000110 +
+

Description:

+

Overall FIFO Counter

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOCTR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9:0FIFOCTRRWVirtual FIFO byte count

+
+
+
+
+ +
+
+

FIFOINC - Overall FIFO Counter Increment

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000114 +
+

Description:

+

Overall FIFO Counter Increment

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOINC +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9:0FIFOINCWOIncrement the Overall FIFO Counter by this value on a write

+
+
+
+
+ +
+
+

CFG - I/O Slave Configuration

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000118 +
+

Description:

+

I/O Slave Configuration

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
IFCEN +
0x0		RSVD +
0x0		I2CADDR +
0x0		RSVD +
0x0		STARTRD +
0x0		RSVD +
0x0		LSB +
0x0		SPOL +
0x0		IFCSEL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31IFCENRWIOSLAVE interface enable.

+ DIS = 0x0 - Disable the IOSLAVE
+ EN = 0x1 - Enable the IOSLAVE
30:20RSVDRORESERVED

+
19:8I2CADDRRW7-bit or 10-bit I2C device address.

+
7:5RSVDRORESERVED

+
4STARTRDRWThis bit holds the cycle to initiate an I/O RAM read.

+ LATE = 0x0 - Initiate I/O RAM read late in each transferred byte.
+ EARLY = 0x1 - Initiate I/O RAM read early in each transferred byte.
3RSVDRORESERVED

+
2LSBRWThis bit selects the transfer bit ordering.

+ MSB_FIRST = 0x0 - Data is assumed to be sent and received with MSB first.
+ LSB_FIRST = 0x1 - Data is assumed to be sent and received with LSB first.
1SPOLRWThis bit selects SPI polarity.

+ SPI_MODES_0_3 = 0x0 - Polarity 0, handles SPI modes 0 and 3.
+ SPI_MODES_1_2 = 0x1 - Polarity 1, handles SPI modes 1 and 2.
0IFCSELRWThis bit selects the I/O interface.

+ I2C = 0x0 - Selects I2C interface for the IO Slave.
+ SPI = 0x1 - Selects SPI interface for the IO Slave.
+
+
+
+ +
+
+

PRENC - I/O Slave Interrupt Priority Encode

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5000011C +
+

Description:

+

I/O Slave Interrupt Priority Encode

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PRENC +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:5RSVDRORESERVED

+
4:0PRENCROThese bits hold the priority encode of the REGACC interrupts.

+
+
+
+
+ +
+
+

IOINTCTL - I/O Interrupt Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000120 +
+

Description:

+

I/O Interrupt Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
IOINTSET +
0x0		RSVD +
0x0		IOINTCLR +
0x0		IOINT +
0x0		IOINTEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24IOINTSETWOThese bits set the IOINT interrupts when written with a 1.

+
23:17RSVDRORESERVED

+
16IOINTCLRWOThis bit clears all of the IOINT interrupts when written with a 1.

+
15:8IOINTROThese bits read the IOINT interrupts.

+
7:0IOINTENROThese read-only bits indicate whether the IOINT interrupts are enabled.

+
+
+
+
+ +
+
+

GENADD - General Address Data

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000124 +
+

Description:

+

General Address Data

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		GADATA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED

+
7:0GADATAROThe data supplied on the last General Address reference.

+
+
+
+
+ +
+
+

INTEN - IO Slave Interrupts: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		XCMPWR +
0x0		XCMPWF +
0x0		XCMPRR +
0x0		XCMPRF +
0x0		IOINTW +
0x0		GENAD +
0x0		FRDERR +
0x0		FUNDFL +
0x0		FOVFL +
0x0		FSIZE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9XCMPWRRWTransfer complete interrupt, write to register space.

+
8XCMPWFRWTransfer complete interrupt, write to FIFO space.

+
7XCMPRRRWTransfer complete interrupt, read from register space.

+
6XCMPRFRWTransfer complete interrupt, read from FIFO space.

+
5IOINTWRWI2C Interrupt Write interrupt.

+
4GENADRWI2C General Address interrupt.

+
3FRDERRRWFIFO Read Error interrupt.

+
2FUNDFLRWFIFO Underflow interrupt.

+
1FOVFLRWFIFO Overflow interrupt.

+
0FSIZERWFIFO Size interrupt.

+
+
+
+
+ +
+
+

INTSTAT - IO Slave Interrupts: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		XCMPWR +
0x0		XCMPWF +
0x0		XCMPRR +
0x0		XCMPRF +
0x0		IOINTW +
0x0		GENAD +
0x0		FRDERR +
0x0		FUNDFL +
0x0		FOVFL +
0x0		FSIZE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9XCMPWRRWTransfer complete interrupt, write to register space.

+
8XCMPWFRWTransfer complete interrupt, write to FIFO space.

+
7XCMPRRRWTransfer complete interrupt, read from register space.

+
6XCMPRFRWTransfer complete interrupt, read from FIFO space.

+
5IOINTWRWI2C Interrupt Write interrupt.

+
4GENADRWI2C General Address interrupt.

+
3FRDERRRWFIFO Read Error interrupt.

+
2FUNDFLRWFIFO Underflow interrupt.

+
1FOVFLRWFIFO Overflow interrupt.

+
0FSIZERWFIFO Size interrupt.

+
+
+
+
+ +
+
+

INTCLR - IO Slave Interrupts: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		XCMPWR +
0x0		XCMPWF +
0x0		XCMPRR +
0x0		XCMPRF +
0x0		IOINTW +
0x0		GENAD +
0x0		FRDERR +
0x0		FUNDFL +
0x0		FOVFL +
0x0		FSIZE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9XCMPWRRWTransfer complete interrupt, write to register space.

+
8XCMPWFRWTransfer complete interrupt, write to FIFO space.

+
7XCMPRRRWTransfer complete interrupt, read from register space.

+
6XCMPRFRWTransfer complete interrupt, read from FIFO space.

+
5IOINTWRWI2C Interrupt Write interrupt.

+
4GENADRWI2C General Address interrupt.

+
3FRDERRRWFIFO Read Error interrupt.

+
2FUNDFLRWFIFO Underflow interrupt.

+
1FOVFLRWFIFO Overflow interrupt.

+
0FSIZERWFIFO Size interrupt.

+
+
+
+
+ +
+
+

INTSET - IO Slave Interrupts: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5000020C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		XCMPWR +
0x0		XCMPWF +
0x0		XCMPRR +
0x0		XCMPRF +
0x0		IOINTW +
0x0		GENAD +
0x0		FRDERR +
0x0		FUNDFL +
0x0		FOVFL +
0x0		FSIZE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED

+
9XCMPWRRWTransfer complete interrupt, write to register space.

+
8XCMPWFRWTransfer complete interrupt, write to FIFO space.

+
7XCMPRRRWTransfer complete interrupt, read from register space.

+
6XCMPRFRWTransfer complete interrupt, read from FIFO space.

+
5IOINTWRWI2C Interrupt Write interrupt.

+
4GENADRWI2C General Address interrupt.

+
3FRDERRRWFIFO Read Error interrupt.

+
2FUNDFLRWFIFO Underflow interrupt.

+
1FOVFLRWFIFO Overflow interrupt.

+
0FSIZERWFIFO Size interrupt.

+
+
+
+
+ +
+
+

REGACCINTEN - Register Access Interrupts: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000210 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
REGACC +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0REGACCRWRegister access interrupts.

+
+
+
+
+ +
+
+

REGACCINTSTAT - Register Access Interrupts: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000214 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
REGACC +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0REGACCRWRegister access interrupts.

+
+
+
+
+ +
+
+

REGACCINTCLR - Register Access Interrupts: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50000218 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
REGACC +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0REGACCRWRegister access interrupts.

+
+
+
+
+ +
+
+

REGACCINTSET - Register Access Interrupts: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5000021C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
REGACC +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0REGACCRWRegister access interrupts.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/itm_regs.html b/docs/apollo2/pages/itm_regs.html new file mode 100644 index 0000000..881b262 --- /dev/null +++ b/docs/apollo2/pages/itm_regs.html @@ -0,0 +1,6319 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
ITM - ARM ITM Registers.
+
+
+ + +
+
+
+

ITM Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0xE0000000: + +   + STIM0 - Stimulus Port Register 0 +
+   + 0xE0000004: + +   + STIM1 - Stimulus Port Register 1 +
+   + 0xE0000008: + +   + STIM2 - Stimulus Port Register 2 +
+   + 0xE000000C: + +   + STIM3 - Stimulus Port Register 3 +
+   + 0xE0000010: + +   + STIM4 - Stimulus Port Register 4 +
+   + 0xE0000014: + +   + STIM5 - Stimulus Port Register 5 +
+   + 0xE0000018: + +   + STIM6 - Stimulus Port Register 6 +
+   + 0xE000001C: + +   + STIM7 - Stimulus Port Register 7 +
+   + 0xE0000020: + +   + STIM8 - Stimulus Port Register 8 +
+   + 0xE0000024: + +   + STIM9 - Stimulus Port Register 9 +
+   + 0xE0000028: + +   + STIM10 - Stimulus Port Register 10 +
+   + 0xE000002C: + +   + STIM11 - Stimulus Port Register 11 +
+   + 0xE0000030: + +   + STIM12 - Stimulus Port Register 12 +
+   + 0xE0000034: + +   + STIM13 - Stimulus Port Register 13 +
+   + 0xE0000038: + +   + STIM14 - Stimulus Port Register 14 +
+   + 0xE000003C: + +   + STIM15 - Stimulus Port Register 15 +
+   + 0xE0000040: + +   + STIM16 - Stimulus Port Register 16 +
+   + 0xE0000044: + +   + STIM17 - Stimulus Port Register 17 +
+   + 0xE0000048: + +   + STIM18 - Stimulus Port Register 18 +
+   + 0xE000004C: + +   + STIM19 - Stimulus Port Register 19 +
+   + 0xE0000050: + +   + STIM20 - Stimulus Port Register 20 +
+   + 0xE0000054: + +   + STIM21 - Stimulus Port Register 21 +
+   + 0xE0000058: + +   + STIM22 - Stimulus Port Register 22 +
+   + 0xE000005C: + +   + STIM23 - Stimulus Port Register 23 +
+   + 0xE0000060: + +   + STIM24 - Stimulus Port Register 24 +
+   + 0xE0000064: + +   + STIM25 - Stimulus Port Register 25 +
+   + 0xE0000068: + +   + STIM26 - Stimulus Port Register 26 +
+   + 0xE000006C: + +   + STIM27 - Stimulus Port Register 27 +
+   + 0xE0000070: + +   + STIM28 - Stimulus Port Register 28 +
+   + 0xE0000074: + +   + STIM29 - Stimulus Port Register 29 +
+   + 0xE0000078: + +   + STIM30 - Stimulus Port Register 30 +
+   + 0xE000007C: + +   + STIM31 - Stimulus Port Register 31 +
+   + 0xE0000E00: + +   + TER - Trace Enable Register. +
+   + 0xE0000E40: + +   + TPR - Trace Privilege Register. +
+   + 0xE0000E80: + +   + TCR - Trace Control Register. +
+   + 0xE0000FB0: + +   + LOCKAREG - Lock Access Register +
+   + 0xE0000FB4: + +   + LOCKSREG - Lock Status Register +
+   + 0xE0000FD0: + +   + PID4 - Peripheral Identification Register 4 +
+   + 0xE0000FD4: + +   + PID5 - Peripheral Identification Register 5 +
+   + 0xE0000FD8: + +   + PID6 - Peripheral Identification Register 6 +
+   + 0xE0000FDC: + +   + PID7 - Peripheral Identification Register 7 +
+   + 0xE0000FE0: + +   + PID0 - Peripheral Identification Register 0 +
+   + 0xE0000FE4: + +   + PID1 - Peripheral Identification Register 1 +
+   + 0xE0000FE8: + +   + PID2 - Peripheral Identification Register 2 +
+   + 0xE0000FEC: + +   + PID3 - Peripheral Identification Register 3 +
+   + 0xE0000FF0: + +   + CID0 - Component Identification Register 1 +
+   + 0xE0000FF4: + +   + CID1 - Component Identification Register 1 +
+   + 0xE0000FF8: + +   + CID2 - Component Identification Register 2 +
+   + 0xE0000FFC: + +   + CID3 - Component Identification Register 3 +
+
+
+ +
+
+

STIM0 - Stimulus Port Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000000 +
+

Description:

+

Stimulus Port Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM0RWStimulus Port Register 0.

+
+
+
+
+ +
+
+

STIM1 - Stimulus Port Register 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000004 +
+

Description:

+

Stimulus Port Register 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM1RWStimulus Port Register 1.

+
+
+
+
+ +
+
+

STIM2 - Stimulus Port Register 2

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000008 +
+

Description:

+

Stimulus Port Register 2

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM2 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM2RWStimulus Port Register 2.

+
+
+
+
+ +
+
+

STIM3 - Stimulus Port Register 3

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000000C +
+

Description:

+

Stimulus Port Register 3

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM3RWStimulus Port Register 3.

+
+
+
+
+ +
+
+

STIM4 - Stimulus Port Register 4

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000010 +
+

Description:

+

Stimulus Port Register 4

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM4 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM4RWStimulus Port Register 4.

+
+
+
+
+ +
+
+

STIM5 - Stimulus Port Register 5

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000014 +
+

Description:

+

Stimulus Port Register 5

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM5 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM5RWStimulus Port Register 5.

+
+
+
+
+ +
+
+

STIM6 - Stimulus Port Register 6

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000018 +
+

Description:

+

Stimulus Port Register 6

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM6 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM6RWStimulus Port Register 6.

+
+
+
+
+ +
+
+

STIM7 - Stimulus Port Register 7

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000001C +
+

Description:

+

Stimulus Port Register 7

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM7 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM7RWStimulus Port Register 7.

+
+
+
+
+ +
+
+

STIM8 - Stimulus Port Register 8

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000020 +
+

Description:

+

Stimulus Port Register 8

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM8 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM8RWStimulus Port Register 8.

+
+
+
+
+ +
+
+

STIM9 - Stimulus Port Register 9

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000024 +
+

Description:

+

Stimulus Port Register 9

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM9 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM9RWStimulus Port Register 9.

+
+
+
+
+ +
+
+

STIM10 - Stimulus Port Register 10

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000028 +
+

Description:

+

Stimulus Port Register 10

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM10 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM10RWStimulus Port Register 10.

+
+
+
+
+ +
+
+

STIM11 - Stimulus Port Register 11

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000002C +
+

Description:

+

Stimulus Port Register 11

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM11 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM11RWStimulus Port Register 11.

+
+
+
+
+ +
+
+

STIM12 - Stimulus Port Register 12

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000030 +
+

Description:

+

Stimulus Port Register 12

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM12 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM12RWStimulus Port Register 12.

+
+
+
+
+ +
+
+

STIM13 - Stimulus Port Register 13

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000034 +
+

Description:

+

Stimulus Port Register 13

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM13 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM13RWStimulus Port Register 13.

+
+
+
+
+ +
+
+

STIM14 - Stimulus Port Register 14

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000038 +
+

Description:

+

Stimulus Port Register 14

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM14 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM14RWStimulus Port Register 14.

+
+
+
+
+ +
+
+

STIM15 - Stimulus Port Register 15

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000003C +
+

Description:

+

Stimulus Port Register 15

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM15 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM15RWStimulus Port Register 15.

+
+
+
+
+ +
+
+

STIM16 - Stimulus Port Register 16

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000040 +
+

Description:

+

Stimulus Port Register 16

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM16 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM16RWStimulus Port Register 16.

+
+
+
+
+ +
+
+

STIM17 - Stimulus Port Register 17

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000044 +
+

Description:

+

Stimulus Port Register 17

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM17 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM17RWStimulus Port Register 17.

+
+
+
+
+ +
+
+

STIM18 - Stimulus Port Register 18

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000048 +
+

Description:

+

Stimulus Port Register 18

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM18 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM18RWStimulus Port Register 18.

+
+
+
+
+ +
+
+

STIM19 - Stimulus Port Register 19

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000004C +
+

Description:

+

Stimulus Port Register 19

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM19 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM19RWStimulus Port Register 19.

+
+
+
+
+ +
+
+

STIM20 - Stimulus Port Register 20

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000050 +
+

Description:

+

Stimulus Port Register 20

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM20 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM20RWStimulus Port Register 20.

+
+
+
+
+ +
+
+

STIM21 - Stimulus Port Register 21

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000054 +
+

Description:

+

Stimulus Port Register 21

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM21 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM21RWStimulus Port Register 21.

+
+
+
+
+ +
+
+

STIM22 - Stimulus Port Register 22

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000058 +
+

Description:

+

Stimulus Port Register 22

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM22 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM22RWStimulus Port Register 22.

+
+
+
+
+ +
+
+

STIM23 - Stimulus Port Register 23

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000005C +
+

Description:

+

Stimulus Port Register 23

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM23 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM23RWStimulus Port Register 23.

+
+
+
+
+ +
+
+

STIM24 - Stimulus Port Register 24

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000060 +
+

Description:

+

Stimulus Port Register 24

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM24 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM24RWStimulus Port Register 24.

+
+
+
+
+ +
+
+

STIM25 - Stimulus Port Register 25

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000064 +
+

Description:

+

Stimulus Port Register 25

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM25 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM25RWStimulus Port Register 25.

+
+
+
+
+ +
+
+

STIM26 - Stimulus Port Register 26

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000068 +
+

Description:

+

Stimulus Port Register 26

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM26 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM26RWStimulus Port Register 26.

+
+
+
+
+ +
+
+

STIM27 - Stimulus Port Register 27

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000006C +
+

Description:

+

Stimulus Port Register 27

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM27 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM27RWStimulus Port Register 27.

+
+
+
+
+ +
+
+

STIM28 - Stimulus Port Register 28

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000070 +
+

Description:

+

Stimulus Port Register 28

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM28 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM28RWStimulus Port Register 28.

+
+
+
+
+ +
+
+

STIM29 - Stimulus Port Register 29

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000074 +
+

Description:

+

Stimulus Port Register 29

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM29 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM29RWStimulus Port Register 29.

+
+
+
+
+ +
+
+

STIM30 - Stimulus Port Register 30

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000078 +
+

Description:

+

Stimulus Port Register 30

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM30 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM30RWStimulus Port Register 30.

+
+
+
+
+ +
+
+

STIM31 - Stimulus Port Register 31

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000007C +
+

Description:

+

Stimulus Port Register 31

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIM31 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIM31RWStimulus Port Register 31.

+
+
+
+
+ +
+
+

TER - Trace Enable Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000E00 +
+

Description:

+

Trace Enable Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
STIMENA +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0STIMENARWBit mask to enable tracing on ITM stimulus ports. One bit per stimulus port..

+
+
+
+
+ +
+
+

TPR - Trace Privilege Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000E40 +
+

Description:

+

Trace Privilege Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PRIVMASK +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED.

+
3:0PRIVMASKRWBit mask to enable tracing on ITM stimulus ports. bit[0] = stimulus ports[7:0], bit[1] = stimulus ports[15:8], bit[2] = stimulus ports[23:16], bit[3] = stimulus ports[31:24].

+
+
+
+
+ +
+
+

TCR - Trace Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000E80 +
+

Description:

+

Trace Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BUSY +
0x0		ATB_ID +
0x0		RSVD +
0x0		TS_FREQ +
0x0		TS_PRESCALE +
0x0		RSVD +
0x0		SWV_ENABLE +
0x0		DWT_ENABLE +
0x0		SYNC_ENABLE +
0x0		TS_ENABLE +
0x0		ITM_ENABLE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED.

+
23BUSYRWSet when ITM events present and being drained.

+
22:16ATB_IDRWATB ID for CoreSight system.

+
15:12RSVDRORESERVED.

+
11:10TS_FREQRWGlobal Timestamp Frequency.

+
9:8TS_PRESCALERWTimestamp prescaler: 0b00 = no prescaling 0b01 = divide by 4 0b10 = divide by 16 0b11 = divide by 64.

+
7:5RSVDRORESERVED.

+
4SWV_ENABLERWEnable SWV (Serial Wire Viewer) behavior - count on TPIUEMIT and TPIUBAUD: Aka SWOENA Enables asynchronous clocking of the timestamp counter.

+
3DWT_ENABLERWEnables the DWT stimulus.

+
2SYNC_ENABLERWEnables sync packets for TPIU.

+
1TS_ENABLERWEnables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of cycles. This provides a time reference for packets and inter-packet gaps.

+
0ITM_ENABLERWEnable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.

+
+
+
+
+ +
+
+

LOCKAREG - Lock Access Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FB0 +
+

Description:

+

Lock Access Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
LOCKAREG +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0LOCKAREGRWKey register value.

+ Key = 0xC5ACCE55 - Key
+
+
+
+ +
+
+

LOCKSREG - Lock Status Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FB4 +
+

Description:

+

Lock Status Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BYTEACC +
0x0		ACCESS +
0x0		PRESENT +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED.

+
2BYTEACCROYou cannot implement 8-bit lock accesses.

+
1ACCESSROWrite access to component is blocked. All writes are ignored, reads are permitted.

+
0PRESENTROIndicates that a lock mechanism exists for this component.

+
+
+
+
+ +
+
+

PID4 - Peripheral Identification Register 4

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FD0 +
+

Description:

+

Peripheral Identification Register 4

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID4 +
0x4
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID4R0Peripheral Identification 4.

+
+
+
+
+ +
+
+

PID5 - Peripheral Identification Register 5

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FD4 +
+

Description:

+

Peripheral Identification Register 5

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID5 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID5R0Peripheral Identification 5.

+
+
+
+
+ +
+
+

PID6 - Peripheral Identification Register 6

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FD8 +
+

Description:

+

Peripheral Identification Register 6

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID6 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID6R0Peripheral Identification 6.

+
+
+
+
+ +
+
+

PID7 - Peripheral Identification Register 7

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FDC +
+

Description:

+

Peripheral Identification Register 7

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID7 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID7R0Peripheral Identification 7.

+
+
+
+
+ +
+
+

PID0 - Peripheral Identification Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FE0 +
+

Description:

+

Peripheral Identification Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID0 +
0x1
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID0R0Peripheral Identification 0.

+
+
+
+
+ +
+
+

PID1 - Peripheral Identification Register 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FE4 +
+

Description:

+

Peripheral Identification Register 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID1 +
0xb0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID1R0Peripheral Identification 1.

+
+
+
+
+ +
+
+

PID2 - Peripheral Identification Register 2

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FE8 +
+

Description:

+

Peripheral Identification Register 2

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID2 +
0x3b
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID2R0Peripheral Identification 2.

+
+
+
+
+ +
+
+

PID3 - Peripheral Identification Register 3

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FEC +
+

Description:

+

Peripheral Identification Register 3

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PID3 +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PID3R0Peripheral Identification 3.

+
+
+
+
+ +
+
+

CID0 - Component Identification Register 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FF0 +
+

Description:

+

Component Identification Register 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CID0 +
0xd
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CID0R0Component Identification 1.

+
+
+
+
+ +
+
+

CID1 - Component Identification Register 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FF4 +
+

Description:

+

Component Identification Register 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CID1 +
0xe0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CID1R0Component Identification 1.

+
+
+
+
+ +
+
+

CID2 - Component Identification Register 2

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FF8 +
+

Description:

+

Component Identification Register 2

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CID2 +
0x5
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CID2R0Component Identification 2.

+
+
+
+
+ +
+
+

CID3 - Component Identification Register 3

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0000FFC +
+

Description:

+

Component Identification Register 3

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CID3 +
0xb1
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CID3R0Component Identification 3.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/jedec_regs.html b/docs/apollo2/pages/jedec_regs.html new file mode 100644 index 0000000..bdbfaae --- /dev/null +++ b/docs/apollo2/pages/jedec_regs.html @@ -0,0 +1,1698 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
JEDEC - JEDED JEP-106 Identification.
+
+
+ + +
+
+
+

JEDEC Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0xF0000FD0: + +   + PID4 - JEP Continuation Register +
+   + 0xF0000FD4: + +   + PID5 - JEP reserved Register +
+   + 0xF0000FD8: + +   + PID6 - JEP reserved Register +
+   + 0xF0000FDC: + +   + PID7 - JEP reserved Register +
+   + 0xF0000FE0: + +   + PID0 - Ambiq Partnum low byte +
+   + 0xF0000FE4: + +   + PID1 - Ambiq part number high-nibble, JEPID low-nibble. +
+   + 0xF0000FE8: + +   + PID2 - Ambiq chip revision low-nibble, JEPID high-nibble +
+   + 0xF0000FEC: + +   + PID3 - Ambiq chip revision high-nibble. +
+   + 0xF0000FF0: + +   + CID0 - Coresight ROM Table. +
+   + 0xF0000FF4: + +   + CID1 - Coresight ROM Table. +
+   + 0xF0000FF8: + +   + CID2 - Coresight ROM Table. +
+   + 0xF0000FFC: + +   + CID3 - Coresight ROM Table. +
+
+
+ +
+
+

PID4 - JEP Continuation Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FD0 +
+

Description:

+

JEP Continuation Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		JEPCONT +
0x8
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED.

+
3:0JEPCONTROContains the JEP Continuation bits.

+
+
+
+
+ +
+
+

PID5 - JEP reserved Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FD4 +
+

Description:

+

JEP reserved Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROContains the value of 0x00000000.

+
+
+
+
+ +
+
+

PID6 - JEP reserved Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FD8 +
+

Description:

+

JEP reserved Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROContains the value of 0x00000000.

+
+
+
+
+ +
+
+

PID7 - JEP reserved Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FDC +
+

Description:

+

JEP reserved Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROContains the value of 0x00000000.

+
+
+
+
+ +
+
+

PID0 - Ambiq Partnum low byte

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FE0 +
+

Description:

+

Ambiq Partnum low byte

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PNL8 +
0xdf
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
27:4RSVDRORESERVED.

+
7:0PNL8ROContains the low 8 bits of the Ambiq Micro device part number.

+
+
+
+
+ +
+
+

PID1 - Ambiq part number high-nibble, JEPID low-nibble.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FE4 +
+

Description:

+

Ambiq part number high-nibble, JEPID low-nibble.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
JEPIDL +
0xb		RSVD +
0x0		PNH4 +
0xe
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
7:4JEPIDLROContains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID is therefore 0x9B.

+
27:4RSVDRORESERVED.

+
3:0PNH4ROContains the high 4 bits of the Ambiq Micro device part number.

+
+
+
+
+ +
+
+

PID2 - Ambiq chip revision low-nibble, JEPID high-nibble

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FE8 +
+

Description:

+

Ambiq chip revision low-nibble, JEPID high-nibble

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CHIPREVH4 +
0x2		RSVD +
0x0		JEPIDH +
0x9
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
7:4CHIPREVH4ROContains the high 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip.

+
27:4RSVDRORESERVED.

+
3:0JEPIDHROContains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this field is hard-coded to 1. The full JEPID is therefore 0x9B.

+
+
+
+
+ +
+
+

PID3 - Ambiq chip revision high-nibble.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FEC +
+

Description:

+

Ambiq chip revision high-nibble.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CHIPREVL4 +
0x2		RSVD +
0x0		ZERO +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
7:4CHIPREVL4ROContains the low 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip.

+
27:4RSVDRORESERVED.

+
3:0ZEROROThis field is hard-coded to 0x0.

+
+
+
+
+ +
+
+

CID0 - Coresight ROM Table.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FF0 +
+

Description:

+

Coresight ROM Table.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CID +
0xd
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
27:4RSVDRORESERVED.

+
7:0CIDROCoresight ROM Table, CID0.

+
+
+
+
+ +
+
+

CID1 - Coresight ROM Table.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FF4 +
+

Description:

+

Coresight ROM Table.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CID +
0x10
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
27:4RSVDRORESERVED.

+
7:0CIDROCoresight ROM Table, CID1.

+
+
+
+
+ +
+
+

CID2 - Coresight ROM Table.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FF8 +
+

Description:

+

Coresight ROM Table.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CID +
0x5
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
27:4RSVDRORESERVED.

+
7:0CIDROCoresight ROM Table, CID2.

+
+
+
+
+ +
+
+

CID3 - Coresight ROM Table.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xF0000FFC +
+

Description:

+

Coresight ROM Table.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CID +
0xb1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
27:4RSVDRORESERVED.

+
7:0CIDROCoresight ROM Table, CID3.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/mcuctrl_regs.html b/docs/apollo2/pages/mcuctrl_regs.html new file mode 100644 index 0000000..5ec3821 --- /dev/null +++ b/docs/apollo2/pages/mcuctrl_regs.html @@ -0,0 +1,4075 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
MCUCTRL - MCU Miscellaneous Control Logic
+
+
+ + +
+
+
+

MCUCTRL Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CHIP_INFO - Chip Information Register +
+   + 0x00000004: + +   + CHIPID0 - Unique Chip ID 0 +
+   + 0x00000008: + +   + CHIPID1 - Unique Chip ID 1 +
+   + 0x0000000C: + +   + CHIPREV - Chip Revision +
+   + 0x00000010: + +   + VENDORID - Unique Vendor ID +
+   + 0x00000014: + +   + DEBUGGER - Debugger Access Control +
+   + 0x00000060: + +   + BUCK - Analog Buck Control +
+   + 0x00000068: + +   + BUCK3 - Buck control reg 3 +
+   + 0x00000080: + +   + LDOREG1 - Analog LDO Reg 1 +
+   + 0x00000088: + +   + LDOREG3 - LDO Control Register 3 +
+   + 0x00000100: + +   + BODPORCTRL - BOD and PDR control Register +
+   + 0x00000104: + +   + ADCPWRDLY - ADC Power Up Delay Control +
+   + 0x0000010C: + +   + ADCCAL - ADC Calibration Control +
+   + 0x00000110: + +   + ADCBATTLOAD - ADC Battery Load Enable +
+   + 0x00000114: + +   + BUCKTRIM - Trim settings for Core and Mem buck modules +
+   + 0x00000124: + +   + XTALGENCTRL - XTAL Oscillator General Control +
+   + 0x000001A0: + +   + BOOTLOADERLOW - Determines whether the bootloader code is visible at address 0x00000000 +
+   + 0x000001A4: + +   + SHADOWVALID - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space. +
+   + 0x000001C0: + +   + ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred. +
+   + 0x000001C4: + +   + DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred. +
+   + 0x000001C8: + +   + SYSFAULTADDR - System bus address which was present when a bus fault occurred. +
+   + 0x000001CC: + +   + FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register. +
+   + 0x000001D0: + +   + FAULTCAPTUREEN - Enable the fault capture registers +
+   + 0x00000200: + +   + DBGR1 - Read-only debug register 1 +
+   + 0x00000204: + +   + DBGR2 - Read-only debug register 2 +
+   + 0x00000220: + +   + PMUENABLE - Control bit to enable/disable the PMU +
+   + 0x00000250: + +   + TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface. +
+
+
+ +
+
+

CHIP_INFO - Chip Information Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020000 +
+

Description:

+

Chip Information Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PARTNUM +
0x3000000
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PARTNUMROBCD part number.

+ APOLLO2 = 0x3000000 - Apollo2 part number is 0x03XXXXXX.
+ APOLLO = 0x1000000 - Apollo part number is 0x01XXXXXX.
+ PN_M = 0xFF000000 - Mask for the PN field.
+
+
+
+ +
+
+

CHIPID0 - Unique Chip ID 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020004 +
+

Description:

+

Unique Chip ID 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROUnique chip ID 0.

+ APOLLO2 = 0x0 - Apollo2 CHIPID0. The lower 32-bits of the 64-bit CHIPID value, which is unique for each part.
+
+
+
+ +
+
+

CHIPID1 - Unique Chip ID 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020008 +
+

Description:

+

Unique Chip ID 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROUnique chip ID 1.

+ APOLLO2 = 0x0 - Apollo2 CHIPID1. The upper 32-bits of the 64-bit CHIPID value, which is unique for each part.
+
+
+
+ +
+
+

CHIPREV - Chip Revision

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4002000C +
+

Description:

+

Chip Revision

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		REVMAJ +
0x1		REVMIN +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED.

+
7:4REVMAJROMajor Revision ID.

+ B = 0x2 - Apollo2 revision B
+ A = 0x1 - Apollo2 revision A
3:0REVMINROMinor Revision ID.

+ REV0 = 0x0 - Apollo2 minor revision value. Succeeding minor revisions will increment from this value.
+ REV2 = 0x2 - Apollo2 minor revision value.
+
+
+
+ +
+
+

VENDORID - Unique Vendor ID

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020010 +
+

Description:

+

Unique Vendor ID

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUEROUnique Vendor ID

+ AMBIQ = 0x414D4251 - Ambiq Vendor ID
+
+
+
+ +
+
+

DEBUGGER - Debugger Access Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020014 +
+

Description:

+

Debugger Access Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		LOCKOUT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED

+
0LOCKOUTRWLockout of debugger (SWD).

+
+
+
+
+ +
+
+

BUCK - Analog Buck Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020060 +
+

Description:

+

Analog Buck Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		MEMBUCKRST +
0x0		COREBUCKRST +
0x0		BYPBUCKMEM +
0x0		MEMBUCKPWD +
0x0		SLEEPBUCKANA +
0x0		COREBUCKPWD +
0x0		BYPBUCKCORE +
0x0		BUCKSWE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED.

+
7MEMBUCKRSTRWReset control override for Mem Buck; 0=enabled, 1=reset; Value is propagated only when the BUCKSWE bit is active, otherwise contrl is from the power control module.

+
6COREBUCKRSTRWReset control override for Core Buck; 0=enabled, 1=reset; Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.

+
5BYPBUCKMEMRWNot used. Additional control of buck is available in the power control module

+
4MEMBUCKPWDRWMemory buck power down override. 1=Powered Down; 0=Enabled; Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.

+ EN = 0x0 - Memory Buck Enable.
3SLEEPBUCKANARWHFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the hfrc_freq_clkgen internal bus (see internal Shelby-1473)

+
2COREBUCKPWDRWCore buck power down override. 1=Powered Down; 0=Enabled; Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.

+ EN = 0x0 - Core Buck enable.
1BYPBUCKCORERWNot used. Additional control of buck is available in the power control module

+
0BUCKSWERWBuck Register Software Override Enable. This will enable the override values for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to the control logic, instead of the normal power control module signal. Note - Must take care to have correct value for ALL the register bits when this SWE is enabled.

+ OVERRIDE_DIS = 0x0 - BUCK Software Override Disable.
+ OVERRIDE_EN = 0x1 - BUCK Software Override Enable.
+
+
+
+ +
+
+

BUCK3 - Buck control reg 3

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020068 +
+

Description:

+

Buck control reg 3

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		MEMBUCKLOTON +
0x0		MEMBUCKBURSTEN +
0x0		MEMBUCKZXTRIM +
0x0		MEMBUCKHYSTTRIM +
0x0		COREBUCKLOTON +
0x0		COREBUCKBURSTEN +
0x0		COREBUCKZXTRIM +
0x0		COREBUCKHYSTTRIM +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:22RSVDRORESERVED.

+
21:18MEMBUCKLOTONRWMEM Buck low TON trim value

+
17MEMBUCKBURSTENRWMEM Buck burst enable 0=disable, 0=disabled, 1=enable.

+
16:13MEMBUCKZXTRIMRWMemory buck zero crossing trim value

+
12:11MEMBUCKHYSTTRIMRWHysterisis trim for mem buck

+
10:7COREBUCKLOTONRWCore Buck low TON trim value

+
6COREBUCKBURSTENRWCore Buck burst enable. 0=disabled, 1=enabled

+
5:2COREBUCKZXTRIMRWCore buck zero crossing trim value

+
1:0COREBUCKHYSTTRIMRWHysterisis trim for core buck

+
+
+
+
+ +
+
+

LDOREG1 - Analog LDO Reg 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020080 +
+

Description:

+

Analog LDO Reg 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CORELDOIBSTRM +
0x0		CORELDOLPTRIM +
0x0		TRIMCORELDOR3 +
0x0		TRIMCORELDOR1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:21RSVDROReserved

+
20CORELDOIBSTRMRWCORE LDO IBIAS Trim

+
19:14CORELDOLPTRIMRWCORE LDO Low Power Trim

+
13:10TRIMCORELDOR3RWCORE LDO tempco trim (R3).

+
9:0TRIMCORELDOR1RWCORE LDO Active mode ouput trim (R1).

+
+
+
+
+ +
+
+

LDOREG3 - LDO Control Register 3

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020088 +
+

Description:

+

LDO Control Register 3

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		TRIMMEMLDOR1 +
0x0		MEMLDOLPALTTRIM +
0x0		MEMLDOLPTRIM +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:18RSVDRORESERVED.

+
17:12TRIMMEMLDOR1RWMEM LDO active mode trim (R1).

+
11:6MEMLDOLPALTTRIMRWMEM LDO TRIM for low power mode with ADC active

+
5:0MEMLDOLPTRIMRWMEM LDO TRIM for low power mode with ADC inactive

+
+
+
+
+ +
+
+

BODPORCTRL - BOD and PDR control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020100 +
+

Description:

+

BOD and PDR control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BODEXTREFSEL +
0x0		PDREXTREFSEL +
0x0		PWDBOD +
0x0		PWDPDR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED.

+
3BODEXTREFSELRWBOD External Reference Select.

+ SELECT = 0x1 - BOD external reference select.
2PDREXTREFSELRWPDR External Reference Select.

+ SELECT = 0x1 - PDR external reference select.
1PWDBODRWBOD Power Down.

+ PWR_DN = 0x1 - BOD power down.
0PWDPDRRWPDR Power Down.

+ PWR_DN = 0x1 - PDR power down
+
+
+
+ +
+
+

ADCPWRDLY - ADC Power Up Delay Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020104 +
+

Description:

+

ADC Power Up Delay Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADCPWR1 +
0x0		ADCPWR0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED.

+
15:8ADCPWR1RWADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.

+
7:0ADCPWR0RWADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.

+
+
+
+
+ +
+
+

ADCCAL - ADC Calibration Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4002010C +
+

Description:

+

ADC Calibration Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADCCALIBRATED +
0x0		CALONPWRUP +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED.

+
1ADCCALIBRATEDROStatus for ADC Calibration

+ FALSE = 0x0 - ADC is not calibrated
+ TRUE = 0x1 - ADC is calibrated
0CALONPWRUPRWRun ADC Calibration on initial power up sequence

+ DIS = 0x0 - Disable automatic calibration on initial power up
+ EN = 0x1 - Enable automatic calibration on initial power up
+
+
+
+ +
+
+

ADCBATTLOAD - ADC Battery Load Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020110 +
+

Description:

+

ADC Battery Load Enable

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BATTLOAD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0BATTLOADRWEnable the ADC battery load resistor

+ DIS = 0x0 - Battery load is disconnected
+ EN = 0x1 - Battery load is enabled
+
+
+
+ +
+
+

BUCKTRIM - Trim settings for Core and Mem buck modules

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020114 +
+

Description:

+

Trim settings for Core and Mem buck modules

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RSVD2 +
0x0		RSVD +
0x0		RSVD +
0x0		COREBUCKR1_HI +
0x0		RSVD +
0x0		COREBUCKR1_LO +
0x0		RSVD +
0x0		MEMBUCKR1 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED.

+
29:24RSVD2RWRESERVED.

+
23:22RSVDRORESERVED.

+
21:20RSVDRWRESERVED.

+
19:16COREBUCKR1_HIRWCore Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO for the full trim value.

+
15:14RSVDRORESERVED.

+
13:8COREBUCKR1_LORWCore Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI for the full trim value.

+
7:6RSVDRORESERVED.

+
5:0MEMBUCKR1RWTrim values for BUCK regulator.

+
+
+
+
+ +
+
+

XTALGENCTRL - XTAL Oscillator General Control

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020124 +
+

Description:

+

XTAL Oscillator General Control

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		XTALKSBIASTRIM +
0x0		XTALBIASTRIM +
0x0		ACWARMUP +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:14RSVDRORESERVED.

+
13:8XTALKSBIASTRIMRWXTAL IBIAS Kick start trim . This trim value is used during the startup process to enable a faster lock and is applied when the kickstart signal is active.

+
7:2XTALBIASTRIMRWXTAL IBIAS trim

+
1:0ACWARMUPRWAuto-calibration delay control

+ 1SEC = 0x0 - Warmup period of 1-2 seconds
+ 2SEC = 0x1 - Warmup period of 2-4 seconds
+ 4SEC = 0x2 - Warmup period of 4-8 seconds
+ 8SEC = 0x3 - Warmup period of 8-16 seconds
+
+
+
+ +
+
+

BOOTLOADERLOW - Determines whether the bootloader code is visible at address 0x00000000

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201A0 +
+

Description:

+

Determines whether the bootloader code is visible at address 0x00000000

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		VALUE +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0VALUERWDetermines whether the bootloader code is visible at address 0x00000000 or not.

+ ADDR0 = 0x1 - Bootloader code at 0x00000000.
+
+
+
+ +
+
+

SHADOWVALID - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201A4 +
+

Description:

+

Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BL_DSLEEP +
0x1		VALID +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED.

+
1BL_DSLEEPROIndicates whether the bootloader should sleep or deep sleep if no image loaded.

+ DEEPSLEEP = 0x1 - Bootloader will go to deep sleep if no flash image loaded
0VALIDROIndicates whether the shadow registers contain valid data from the Flash Information Space.

+ VALID = 0x1 - Flash information space contains valid data.
+
+
+
+ +
+
+

ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201C0 +
+

Description:

+

ICODE bus address which was present when a bus fault occurred.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ADDR +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ADDRROThe ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.

+
+
+
+
+ +
+
+

DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201C4 +
+

Description:

+

DCODE bus address which was present when a bus fault occurred.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ADDR +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ADDRROThe DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.

+
+
+
+
+ +
+
+

SYSFAULTADDR - System bus address which was present when a bus fault occurred.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201C8 +
+

Description:

+

System bus address which was present when a bus fault occurred.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ADDR +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ADDRROSYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.

+
+
+
+
+ +
+
+

FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201CC +
+

Description:

+

Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SYS +
0x0		DCODE +
0x0		ICODE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED.

+
2SYSRWSYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.

+ NOFAULT = 0x0 - No bus fault has been detected.
+ FAULT = 0x1 - Bus fault detected.
1DCODERWDCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.

+ NOFAULT = 0x0 - No DCODE fault has been detected.
+ FAULT = 0x1 - DCODE fault detected.
0ICODERWThe ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.

+ NOFAULT = 0x0 - No ICODE fault has been detected.
+ FAULT = 0x1 - ICODE fault detected.
+
+
+
+ +
+
+

FAULTCAPTUREEN - Enable the fault capture registers

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x400201D0 +
+

Description:

+

Enable the fault capture registers

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ENABLE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0ENABLERWFault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.

+ DIS = 0x0 - Disable fault capture.
+ EN = 0x1 - Enable fault capture.
+
+
+
+ +
+
+

DBGR1 - Read-only debug register 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020200 +
+

Description:

+

Read-only debug register 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ONETO8 +
0x12345678
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ONETO8RORead-only register for communication validation

+
+
+
+
+ +
+
+

DBGR2 - Read-only debug register 2

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020204 +
+

Description:

+

Read-only debug register 2

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
COOLCODE +
0xc001c0de
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0COOLCODERORead-only register for communication validation

+
+
+
+
+ +
+
+

PMUENABLE - Control bit to enable/disable the PMU

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020220 +
+

Description:

+

Control bit to enable/disable the PMU

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ENABLE +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0ENABLERWPMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.

+ DIS = 0x0 - Disable MCU power management.
+ EN = 0x1 - Enable MCU power management.
+
+
+
+ +
+
+

TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40020250 +
+

Description:

+

TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CLKSEL +
0x0		RSVD +
0x0		ENABLE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED.

+
10:8CLKSELRWThis field selects the frequency of the ARM M4 TPIU port.

+ LOW_PWR = 0x0 - Low power state.
+ 0MHz = 0x0 - Low power state.
+ HFRC_DIV_2 = 0x1 - Selects HFRC divided by 2 as the source TPIU clk
+ HFRC_DIV_8 = 0x2 - Selects HFRC divided by 8 as the source TPIU clk
+ HFRC_DIV_16 = 0x3 - Selects HFRC divided by 16 as the source TPIU clk
+ HFRC_DIV_32 = 0x4 - Selects HFRC divided by 32 as the source TPIU clk
7:1RSVDRORESERVED.

+
0ENABLERWTPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.

+ DIS = 0x0 - Disable the TPIU.
+ EN = 0x1 - Enable the TPIU.
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/nvic_regs.html b/docs/apollo2/pages/nvic_regs.html new file mode 100644 index 0000000..ba4d709 --- /dev/null +++ b/docs/apollo2/pages/nvic_regs.html @@ -0,0 +1,1954 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
NVIC - Nested Vectored Interrupt Controller
+
+
+ + +
+
+
+

NVIC Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0xE000E100: + +   + ISER0 - Interrupt Set-Enable Register 0 +
+   + 0xE000E180: + +   + ICER0 - Interrupt Clear-Enable Register 0 +
+   + 0xE000E200: + +   + ISPR0 - Interrupt Set-Pending Register 0 +
+   + 0xE000E280: + +   + ICPR0 - Interrupt Clear-Pending Register 0 +
+   + 0xE000E300: + +   + IABR0 - Interrupt Active Bit Register 0 +
+   + 0xE000E400: + +   + IPR0 - Interrupt Priority Register 0 +
+   + 0xE000E404: + +   + IPR1 - Interrupt Priority Register 1 +
+   + 0xE000E408: + +   + IPR2 - Interrupt Priority Register 2 +
+   + 0xE000E40C: + +   + IPR3 - Interrupt Priority Register 3 +
+   + 0xE000E410: + +   + IPR4 - Interrupt Priority Register 4 +
+   + 0xE000E414: + +   + IPR5 - Interrupt Priority Register 5 +
+   + 0xE000E418: + +   + IPR6 - Interrupt Priority Register 6 +
+   + 0xE000E41C: + +   + IPR7 - Interrupt Priority Register 7 +
+
+
+ +
+
+

ISER0 - Interrupt Set-Enable Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E100 +
+

Description:

+

Interrupt Set-Enable Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
BITS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0BITSRWNVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.

+
+
+
+
+ +
+
+

ICER0 - Interrupt Clear-Enable Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E180 +
+

Description:

+

Interrupt Clear-Enable Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
BITS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0BITSRWNVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.

+
+
+
+
+ +
+
+

ISPR0 - Interrupt Set-Pending Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E200 +
+

Description:

+

Interrupt Set-Pending Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
BITS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0BITSRWNVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.

+
+
+
+
+ +
+
+

ICPR0 - Interrupt Clear-Pending Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E280 +
+

Description:

+

Interrupt Clear-Pending Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
BITS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0BITSRWNVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.

+
+
+
+
+ +
+
+

IABR0 - Interrupt Active Bit Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E300 +
+

Description:

+

Interrupt Active Bit Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
BITS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0BITSRONVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.

+
+
+
+
+ +
+
+

IPR0 - Interrupt Priority Register 0

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E400 +
+

Description:

+

Interrupt Priority Register 0

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 3.

+
23:16PRI_N2RWPriority assignment for interrupt vector 2.

+
15:8PRI_N1RWPriority assignment for interrupt vector 1.

+
7:0PRI_N0RWPriority assignment for interrupt vector 0.

+
+
+
+
+ +
+
+

IPR1 - Interrupt Priority Register 1

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E404 +
+

Description:

+

Interrupt Priority Register 1

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 7.

+
23:16PRI_N2RWPriority assignment for interrupt vector 6.

+
15:8PRI_N1RWPriority assignment for interrupt vector 5.

+
7:0PRI_N0RWPriority assignment for interrupt vector 4.

+
+
+
+
+ +
+
+

IPR2 - Interrupt Priority Register 2

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E408 +
+

Description:

+

Interrupt Priority Register 2

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 11.

+
23:16PRI_N2RWPriority assignment for interrupt vector 10.

+
15:8PRI_N1RWPriority assignment for interrupt vector 9.

+
7:0PRI_N0RWPriority assignment for interrupt vector 8.

+
+
+
+
+ +
+
+

IPR3 - Interrupt Priority Register 3

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E40C +
+

Description:

+

Interrupt Priority Register 3

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 15.

+
23:16PRI_N2RWPriority assignment for interrupt vector 14.

+
15:8PRI_N1RWPriority assignment for interrupt vector 13.

+
7:0PRI_N0RWPriority assignment for interrupt vector 12.

+
+
+
+
+ +
+
+

IPR4 - Interrupt Priority Register 4

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E410 +
+

Description:

+

Interrupt Priority Register 4

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 19.

+
23:16PRI_N2RWPriority assignment for interrupt vector 18.

+
15:8PRI_N1RWPriority assignment for interrupt vector 17.

+
7:0PRI_N0RWPriority assignment for interrupt vector 16.

+
+
+
+
+ +
+
+

IPR5 - Interrupt Priority Register 5

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E414 +
+

Description:

+

Interrupt Priority Register 5

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 23.

+
23:16PRI_N2RWPriority assignment for interrupt vector 22.

+
15:8PRI_N1RWPriority assignment for interrupt vector 21.

+
7:0PRI_N0RWPriority assignment for interrupt vector 20.

+
+
+
+
+ +
+
+

IPR6 - Interrupt Priority Register 6

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E418 +
+

Description:

+

Interrupt Priority Register 6

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 27.

+
23:16PRI_N2RWPriority assignment for interrupt vector 26.

+
15:8PRI_N1RWPriority assignment for interrupt vector 25.

+
7:0PRI_N0RWPriority assignment for interrupt vector 24.

+
+
+
+
+ +
+
+

IPR7 - Interrupt Priority Register 7

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E41C +
+

Description:

+

Interrupt Priority Register 7

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_N3 +
0x0		PRI_N2 +
0x0		PRI_N1 +
0x0		PRI_N0 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_N3RWPriority assignment for interrupt vector 31.

+
23:16PRI_N2RWPriority assignment for interrupt vector 30.

+
15:8PRI_N1RWPriority assignment for interrupt vector 29.

+
7:0PRI_N0RWPriority assignment for interrupt vector 28.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/pdm_regs.html b/docs/apollo2/pages/pdm_regs.html new file mode 100644 index 0000000..951c397 --- /dev/null +++ b/docs/apollo2/pages/pdm_regs.html @@ -0,0 +1,1802 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
PDM - PDM Audio
+
+
+ + +
+
+
+

PDM Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + PCFG - PDM Configuration Register +
+   + 0x00000004: + +   + VCFG - Voice Configuration Register +
+   + 0x00000008: + +   + FR - Voice Status Register +
+   + 0x0000000C: + +   + FRD - FIFO Read +
+   + 0x00000010: + +   + FLUSH - FIFO Flush +
+   + 0x00000014: + +   + FTHR - FIFO Threshold +
+   + 0x00000200: + +   + INTEN - IO Master Interrupts: Enable +
+   + 0x00000204: + +   + INTSTAT - IO Master Interrupts: Status +
+   + 0x00000208: + +   + INTCLR - IO Master Interrupts: Clear +
+   + 0x0000020C: + +   + INTSET - IO Master Interrupts: Set +
+
+
+ +
+
+

PCFG - PDM Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011000 +
+

Description:

+

PDM Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
LRSWAP +
0x0		PGARIGHT +
0x0		PGALEFT +
0x0		RSVD +
0x0		MCLKDIV +
0x0		SINCRATE +
0x30		ADCHPD +
0x1		HPCUTOFF +
0xb		CYCLES +
0x1		SOFTMUTE +
0x0		PDMCORE +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31LRSWAPRWLeft/right channel swap.

+ EN = 0x1 - Swap left and right channels (FIFO Read RIGHT_LEFT).
+ NOSWAP = 0x0 - No channel swapping (IFO Read LEFT_RIGHT).
30:27PGARIGHTRWRight channel PGA gain.

+ M15DB = 0xF - -1.5 db gain.
+ M300DB = 0xE - -3.0 db gain.
+ M45DB = 0xD - -4.5 db gain.
+ M60DB = 0xC - -6.0 db gain.
+ M75DB = 0xB - -7.5 db gain.
+ M90DB = 0xA - -9.0 db gain.
+ M105DB = 0x9 - -10.5 db gain.
+ M120DB = 0x8 - -12.0 db gain.
+ P105DB = 0x7 - 10.5 db gain.
+ P90DB = 0x6 - 9.0 db gain.
+ P75DB = 0x5 - 7.5 db gain.
+ P60DB = 0x4 - 6.0 db gain.
+ P45DB = 0x3 - 4.5 db gain.
+ P30DB = 0x2 - 3.0 db gain.
+ P15DB = 0x1 - 1.5 db gain.
+ 0DB = 0x0 - 0.0 db gain.
26:23PGALEFTRWLeft channel PGA gain.

+ M15DB = 0xF - -1.5 db gain.
+ M300DB = 0xE - -3.0 db gain.
+ M45DB = 0xD - -4.5 db gain.
+ M60DB = 0xC - -6.0 db gain.
+ M75DB = 0xB - -7.5 db gain.
+ M90DB = 0xA - -9.0 db gain.
+ M105DB = 0x9 - -10.5 db gain.
+ M120DB = 0x8 - -12.0 db gain.
+ P105DB = 0x7 - 10.5 db gain.
+ P90DB = 0x6 - 9.0 db gain.
+ P75DB = 0x5 - 7.5 db gain.
+ P60DB = 0x4 - 6.0 db gain.
+ P45DB = 0x3 - 4.5 db gain.
+ P30DB = 0x2 - 3.0 db gain.
+ P15DB = 0x1 - 1.5 db gain.
+ 0DB = 0x0 - 0.0 db gain.
22:19RSVDROThis bitfield is reserved for future use.

+
18:17MCLKDIVRWPDM_CLK frequency divisor.

+ MCKDIV4 = 0x3 - Divide input clock by 4
+ MCKDIV3 = 0x2 - Divide input clock by 3
+ MCKDIV2 = 0x1 - Divide input clock by 2
+ MCKDIV1 = 0x0 - Divide input clock by 1
16:10SINCRATERWSINC decimation rate.

+
9ADCHPDRWHigh pass filter disable.

+ EN = 0x0 - Enable high pass filter.
+ DIS = 0x1 - Disable high pass filter.
8:5HPCUTOFFRWHigh pass filter coefficients.

+
4:2CYCLESRWNumber of clocks during gain-setting changes.

+
1SOFTMUTERWSoft mute control.

+ EN = 0x1 - Enable Soft Mute.
+ DIS = 0x0 - Disable Soft Mute.
0PDMCORERWData Streaming Control.

+ EN = 0x1 - Enable Data Streaming.
+ DIS = 0x0 - Disable Data Streaming.
+
+
+
+ +
+
+

VCFG - Voice Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011004 +
+

Description:

+

Voice Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
IOCLKEN +
0x0		RSTB +
0x0		PDMCLKSEL +
0x0		PDMCLK +
0x0		RSVD +
0x0		I2SMODE +
0x0		BCLKINV +
0x0		RSVD +
0x0		DMICKDEL +
0x0		SELAP +
0x0		RSVD +
0x0		PCMPACK +
0x0		RSVD +
0x0		CHSET +
0x1		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31IOCLKENRWEnable the IO clock.

+ DIS = 0x0 - Disable FIFO read.
+ EN = 0x1 - Enable FIFO read.
30RSTBRWReset the IP core.

+ RESET = 0x0 - Reset the core.
+ NORM = 0x1 - Enable the core.
29:27PDMCLKSELRWSelect the PDM input clock.

+ DISABLE = 0x0 - Static value.
+ 12MHz = 0x1 - PDM clock is 12 MHz.
+ 6MHz = 0x2 - PDM clock is 6 MHz.
+ 3MHz = 0x3 - PDM clock is 3 MHz.
+ 1_5MHz = 0x4 - PDM clock is 1.5 MHz.
+ 750KHz = 0x5 - PDM clock is 750 KHz.
+ 375KHz = 0x6 - PDM clock is 375 KHz.
+ 187KHz = 0x7 - PDM clock is 187.5 KHz.
26PDMCLKRWEnable the serial clock.

+ DIS = 0x0 - Disable serial clock.
+ EN = 0x1 - Enable serial clock.
25:21RSVDROThis bitfield is reserved for future use.

+
20I2SMODERWI2S interface enable.

+ DIS = 0x0 - Disable I2S interface.
+ EN = 0x1 - Enable I2S interface.
19BCLKINVRWI2S BCLK input inversion.

+ INV = 0x0 - BCLK inverted.
+ NORM = 0x1 - BCLK not inverted.
18RSVDROThis bitfield is reserved for future use.

+
17DMICKDELRWPDM clock sampling delay.

+ 0CYC = 0x0 - No delay.
+ 1CYC = 0x1 - 1 cycle delay.
16SELAPRWSelect PDM input clock source.

+ I2S = 0x1 - Clock source from I2S BCLK.
+ INTERNAL = 0x0 - Clock source from internal clock generator.
15:9RSVDROThis bitfield is reserved for future use.

+
8PCMPACKRWPCM data packing enable.

+ DIS = 0x0 - Disable PCM packing.
+ EN = 0x1 - Enable PCM packing.
7:5RSVDROThis bitfield is reserved for future use.

+
4:3CHSETRWSet PCM channels.

+ DIS = 0x0 - Channel disabled.
+ LEFT = 0x1 - Mono left channel.
+ RIGHT = 0x2 - Mono right channel.
+ STEREO = 0x3 - Stereo channels.
2:0RSVDROThis bitfield is reserved for future use.

+
+
+
+
+ +
+
+

FR - Voice Status Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011008 +
+

Description:

+

Voice Status Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOCNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:9RSVDROThis bitfield is reserved for future use.

+
8:0FIFOCNTROValid 32-bit entries currently in the FIFO.

+
+
+
+
+ +
+
+

FRD - FIFO Read

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5001100C +
+

Description:

+

FIFO Read

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
FIFOREAD +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0FIFOREADROFIFO read data.

+
+
+
+
+ +
+
+

FLUSH - FIFO Flush

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011010 +
+

Description:

+

FIFO Flush

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOFLUSH +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDROThis bitfield is reserved for future use.

+
0FIFOFLUSHWOFIFO FLUSH.

+
+
+
+
+ +
+
+

FTHR - FIFO Threshold

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011014 +
+

Description:

+

FIFO Threshold

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		FIFOTHR +
0xc0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDROThis bitfield is reserved for future use.

+
7:0FIFOTHRRWFIFO interrupt threshold.

+
+
+
+
+ +
+
+

INTEN - IO Master Interrupts: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		UNDFL +
0x0		OVF +
0x0		THR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED

+
2UNDFLRWThis is the FIFO underflow interrupt.

+
1OVFRWThis is the FIFO overflow interrupt.

+
0THRRWThis is the FIFO threshold interrupt.

+
+
+
+
+ +
+
+

INTSTAT - IO Master Interrupts: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		UNDFL +
0x0		OVF +
0x0		THR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED

+
2UNDFLRWThis is the FIFO underflow interrupt.

+
1OVFRWThis is the FIFO overflow interrupt.

+
0THRRWThis is the FIFO threshold interrupt.

+
+
+
+
+ +
+
+

INTCLR - IO Master Interrupts: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x50011208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		UNDFL +
0x0		OVF +
0x0		THR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED

+
2UNDFLRWThis is the FIFO underflow interrupt.

+
1OVFRWThis is the FIFO overflow interrupt.

+
0THRRWThis is the FIFO threshold interrupt.

+
+
+
+
+ +
+
+

INTSET - IO Master Interrupts: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x5001120C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		UNDFL +
0x0		OVF +
0x0		THR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED

+
2UNDFLRWThis is the FIFO underflow interrupt.

+
1OVFRWThis is the FIFO overflow interrupt.

+
0THRRWThis is the FIFO threshold interrupt.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/pwrctrl_regs.html b/docs/apollo2/pages/pwrctrl_regs.html new file mode 100644 index 0000000..6ace59b --- /dev/null +++ b/docs/apollo2/pages/pwrctrl_regs.html @@ -0,0 +1,1927 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
PWRCTRL - PWR Controller Register Bank
+
+
+ + +
+
+
+

PWRCTRL Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + SUPPLYSRC - Memory and Core Voltage Supply Source Select Register +
+   + 0x00000004: + +   + POWERSTATUS - Power Status Register for MCU supplies and peripherals +
+   + 0x00000008: + +   + DEVICEEN - DEVICE ENABLES for SHELBY +
+   + 0x0000000C: + +   + SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode +
+   + 0x00000010: + +   + MEMEN - Disables individual banks of the MEMORY array +
+   + 0x00000014: + +   + PWRONSTATUS - POWER ON Status +
+   + 0x00000018: + +   + SRAMCTRL - SRAM Control register +
+   + 0x0000001C: + +   + ADCSTATUS - Power Status Register for ADC Block +
+   + 0x00000020: + +   + MISCOPT - Power Optimization Control Bits +
+
+
+ +
+
+

SUPPLYSRC - Memory and Core Voltage Supply Source Select Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021000 +
+

Description:

+

Memory and Core Voltage Supply Source Select Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SWITCH_LDO_IN_SLEEP +
0x1		COREBUCKEN +
0x0		MEMBUCKEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED.

+
2SWITCH_LDO_IN_SLEEPRWSwitches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in DEEP SLEEP. If all the devices are off then this does not matter and LDO (low power mode) is used

+ EN = 0x1 - Automatically switch from CORE BUCK to CORE LDO when CPU is in DEEP SLEEP
1COREBUCKENRWEnables and Selects the Core Buck as the supply for the low-voltage power domain.

+ EN = 0x1 - Enable the Core Buck for the low-voltage power domain.
0MEMBUCKENRWEnables and select the Memory Buck as the supply for the Flash and SRAM power domain.

+ EN = 0x1 - Enable the Memory Buck as the supply for flash and SRAM.
+
+
+
+ +
+
+

POWERSTATUS - Power Status Register for MCU supplies and peripherals

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021004 +
+

Description:

+

Power Status Register for MCU supplies and peripherals

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		COREBUCKON +
0x0		MEMBUCKON +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED.

+
1COREBUCKONROIndicates whether the Core low-voltage domain is supplied from the LDO or the Buck.

+ LDO = 0x0 - Indicates the the LDO is supplying the Core low-voltage.
+ BUCK = 0x1 - Indicates the the Buck is supplying the Core low-voltage.
0MEMBUCKONROIndicate whether the Memory power domain is supplied from the LDO or the Buck.

+ LDO = 0x0 - Indicates the LDO is supplying the memory power domain.
+ BUCK = 0x1 - Indicates the Buck is supplying the memory power domain.
+
+
+
+ +
+
+

DEVICEEN - DEVICE ENABLES for SHELBY

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021008 +
+

Description:

+

DEVICE ENABLES for SHELBY

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PWRPDM +
0x0		PWRADC +
0x0		PWRUART1 +
0x0		PWRUART0 +
0x0		IO_MASTER5 +
0x0		IO_MASTER4 +
0x0		IO_MASTER3 +
0x0		IO_MASTER2 +
0x0		IO_MASTER1 +
0x0		IO_MASTER0 +
0x0		IO_SLAVE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDRORESERVED.

+
10PWRPDMRWEnable PDM Digital Block

+ EN = 0x1 - Enable PDM
+ DIS = 0x0 - Disables PDM
9PWRADCRWEnable ADC Digital Block

+ EN = 0x1 - Enable ADC
+ DIS = 0x0 - Disables ADC
8PWRUART1RWEnable UART 1

+ EN = 0x1 - Enable UART 1
+ DIS = 0x0 - Disables UART 1
7PWRUART0RWEnable UART 0

+ EN = 0x1 - Enable UART 0
+ DIS = 0x0 - Disables UART 0
6IO_MASTER5RWEnable IO MASTER 5

+ EN = 0x1 - Enable IO MASTER 5
+ DIS = 0x0 - Disables IO MASTER 5
5IO_MASTER4RWEnable IO MASTER 4

+ EN = 0x1 - Enable IO MASTER 4
+ DIS = 0x0 - Disables IO MASTER 4
4IO_MASTER3RWEnable IO MASTER 3

+ EN = 0x1 - Enable IO MASTER 3
+ DIS = 0x0 - Disables IO MASTER 3
3IO_MASTER2RWEnable IO MASTER 2

+ EN = 0x1 - Enable IO MASTER 2
+ DIS = 0x0 - Disables IO MASTER 2
2IO_MASTER1RWEnable IO MASTER 1

+ EN = 0x1 - Enable IO MASTER 1
+ DIS = 0x0 - Disables IO MASTER 1
1IO_MASTER0RWEnable IO MASTER 0

+ EN = 0x1 - Enable IO MASTER 0
+ DIS = 0x0 - Disables IO MASTER 0
0IO_SLAVERWEnable IO SLAVE

+ EN = 0x1 - Enable IO SLAVE
+ DIS = 0x0 - Disables IO SLAVE
+
+
+
+ +
+
+

SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4002100C +
+

Description:

+

Powerdown an SRAM Banks in Deep Sleep mode

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CACHE_PWD_SLP +
0x0		RSVD +
0x0		SRAMSLEEPPOWERDOWN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CACHE_PWD_SLPRWEnable CACHE BANKS to power down in deep sleep

+ EN = 0x1 - CACHE BANKS POWER DOWN in CORE SLEEP
+ DIS = 0x0 - CACHE BANKS STAYS in Retention in CORE SLEEP
30:11RSVDRORESERVED.

+
10:0SRAMSLEEPPOWERDOWNRWSelects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.

+ NONE = 0x0 - All banks retained
+ GROUP0_SRAM0 = 0x1 - 0KB-8KB SRAM
+ GROUP0_SRAM1 = 0x2 - 8KB-16KB SRAM
+ GROUP0_SRAM2 = 0x4 - 16KB-24KB SRAM
+ GROUP0_SRAM3 = 0x8 - 24KB-32KB SRAM
+ GROUP1 = 0x10 - 32KB-64KB SRAMs
+ GROUP2 = 0x20 - 64KB-96KB SRAMs
+ GROUP3 = 0x40 - 96KB-128KB SRAMs
+ GROUP4 = 0x80 - 128KB-160KB SRAMs
+ GROUP5 = 0x100 - 160KB-192KB SRAMs
+ GROUP6 = 0x200 - 192KB-224KB SRAMs
+ GROUP7 = 0x400 - 224KB-256KB SRAMs
+ SRAM8K = 0x1 - Do not Retain lower 8KB
+ SRAM16K = 0x3 - Do not Retain lower 16KB
+ SRAM32K = 0xF - Do not Retain lower 32KB
+ SRAM64K = 0x1F - Do not Retain lower 64KB
+ SRAM128K = 0x7F - Do not Retain lower 128KB
+ ALLBUTLOWER8K = 0x7FE - All banks but lower 8k powered down.
+ ALLBUTLOWER16K = 0x7FC - All banks but lower 16k powered down.
+ ALLBUTLOWER24K = 0x7F8 - All banks but lower 24k powered down.
+ ALLBUTLOWER32K = 0x7F0 - All banks but lower 32k powered down.
+ ALLBUTLOWER64K = 0x7E0 - All banks but lower 64k powered down.
+ ALLBUTLOWER128K = 0x780 - All banks but lower 128k powered down.
+ ALL = 0x7FF - All banks powered down.
+
+
+
+ +
+
+

MEMEN - Disables individual banks of the MEMORY array

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021010 +
+

Description:

+

Disables individual banks of the MEMORY array

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CACHEB2 +
0x1		RSVD +
0x0		CACHEB0 +
0x1		RSVD +
0x0		FLASH1 +
0x1		FLASH0 +
0x1		SRAMEN +
0x7ff
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CACHEB2RWEnable CACHE BANK 2

+ EN = 0x1 - Enable CACHE BANK 2
+ DIS = 0x0 - Disable CACHE BANK 2
30RSVDROReserved

+
29CACHEB0RWEnable CACHE BANK 0

+ EN = 0x1 - Enable CACHE BANK 0
+ DIS = 0x0 - Disable CACHE BANK 0
28:13RSVDRORESERVED.

+
12FLASH1RWEnable FLASH1

+ EN = 0x1 - Enable FLASH1
+ DIS = 0x0 - Disables FLASH1
11FLASH0RWEnable FLASH 0

+ EN = 0x1 - Enable FLASH 0
+ DIS = 0x0 - Disables FLASH 0
10:0SRAMENRWEnables power for selected SRAM banks (else an access to its address space to generate a Hard Fault).

+ NONE = 0x0 - All banks disabled
+ GROUP0_SRAM0 = 0x1 - 0KB-8KB SRAM
+ GROUP0_SRAM1 = 0x2 - 8KB-16KB SRAM
+ GROUP0_SRAM2 = 0x4 - 16KB-24KB SRAM
+ GROUP0_SRAM3 = 0x8 - 24KB-32KB SRAM
+ GROUP1 = 0x10 - 32KB-64KB SRAMs
+ GROUP2 = 0x20 - 64KB-96KB SRAMs
+ GROUP3 = 0x40 - 96KB-128KB SRAMs
+ GROUP4 = 0x80 - 128KB-160KB SRAMs
+ GROUP5 = 0x100 - 160KB-192KB SRAMs
+ GROUP6 = 0x200 - 192KB-224KB SRAMs
+ GROUP7 = 0x400 - 224KB-256KB SRAMs
+ SRAM8K = 0x1 - ENABLE lower 8KB
+ SRAM16K = 0x3 - ENABLE lower 16KB
+ SRAM32K = 0xF - ENABLE lower 32KB
+ SRAM64K = 0x1F - ENABLE lower 64KB
+ SRAM128K = 0x7F - ENABLE lower 128KB
+ SRAM256K = 0x7FF - ENABLE lower 256KB
+ ALL = 0x7FF - All banks ENABLED
+
+
+
+ +
+
+

PWRONSTATUS - POWER ON Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021014 +
+

Description:

+

POWER ON Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RSVD +
0x0		RSVD +
0x0		RSVD +
0x0		PD_CACHEB2 +
0x0		RSVD +
0x0		PD_CACHEB0 +
0x0		PD_GRP7_SRAM +
0x0		PD_GRP6_SRAM +
0x0		PD_GRP5_SRAM +
0x0		PD_GRP4_SRAM +
0x0		PD_GRP3_SRAM +
0x0		PD_GRP2_SRAM +
0x0		PD_GRP1_SRAM +
0x0		PD_GRP0_SRAM3 +
0x0		PD_GRP0_SRAM2 +
0x0		PD_GRP0_SRAM1 +
0x0		PD_GRP0_SRAM0 +
0x0		PDADC +
0x0		PD_FLAM1 +
0x0		PD_FLAM0 +
0x0		PD_PDM +
0x0		PDC +
0x0		PDB +
0x0		PDA +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31RSVDRORESERVED

+
30RSVDRORESERVED

+
29RSVDRORESERVED

+
28:22RSVDROThis bitfield is reserved for future use.

+
21PD_CACHEB2ROThis bit is 1 if power is supplied to CACHE BANK 2

+
20RSVDROReserved

+
19PD_CACHEB0ROThis bit is 1 if power is supplied to CACHE BANK 0

+
18PD_GRP7_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP7

+
17PD_GRP6_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP6

+
16PD_GRP5_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP5

+
15PD_GRP4_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP4

+
14PD_GRP3_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP3

+
13PD_GRP2_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP2

+
12PD_GRP1_SRAMROThis bit is 1 if power is supplied to SRAM domain PD_GRP1

+
11PD_GRP0_SRAM3ROThis bit is 1 if power is supplied to SRAM domain PD_SRAM0_3

+
10PD_GRP0_SRAM2ROThis bit is 1 if power is supplied to SRAM domain PD_SRAM0_2

+
9PD_GRP0_SRAM1ROThis bit is 1 if power is supplied to SRAM domain SRAM0_1

+
8PD_GRP0_SRAM0ROThis bit is 1 if power is supplied to SRAM domain SRAM0_0

+
7PDADCROThis bit is 1 if power is supplied to domain PD_ADC

+
6PD_FLAM1ROThis bit is 1 if power is supplied to domain PD_FLAM1

+
5PD_FLAM0ROThis bit is 1 if power is supplied to domain PD_FLAM0

+
4PD_PDMROThis bit is 1 if power is supplied to domain PD_PDM

+
3PDCROThis bit is 1 if power is supplied to power domain C, which supplies IOM3-5.

+
2PDBROThis bit is 1 if power is supplied to power domain B, which supplies IOM0-2.

+
1PDAROThis bit is 1 if power is supplied to power domain A, which supplies IOS and UART0,1.

+
0RSVDRORESERVED

+
+
+
+
+ +
+
+

SRAMCTRL - SRAM Control register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021018 +
+

Description:

+

SRAM Control register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SRAM_MASTER_CLKGATE +
0x0		SRAM_CLKGATE +
0x0		SRAM_LIGHT_SLEEP +
0x1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDROThis bitfield is reserved for future use.

+
2SRAM_MASTER_CLKGATERWEnables top-level clock gating in the SRAM block. This bit should be enabled for lowest power operation.

+ EN = 0x1 - Enable Master SRAM Clock Gate
+ DIS = 0x0 - Disables Master SRAM Clock Gating
1SRAM_CLKGATERWEnables individual per-RAM clock gating in the SRAM block. This bit should be enabled for lowest power operation.

+ EN = 0x1 - Enable Individual SRAM Clock Gating
+ DIS = 0x0 - Disables Individual SRAM Clock Gating
0SRAM_LIGHT_SLEEPRWEnable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will be put into light sleep mode while inactive. NOTE: if the SRAM is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.

+ EN = 0x1 - Enable LIGHT SLEEP for SRAMs
+ DIS = 0x0 - Disables LIGHT SLEEP for SRAMs
+
+
+
+ +
+
+

ADCSTATUS - Power Status Register for ADC Block

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4002101C +
+

Description:

+

Power Status Register for ADC Block

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ADC_REFBUF_PWD +
0x0		ADC_REFKEEP_PWD +
0x0		ADC_VBAT_PWD +
0x0		ADC_VPTAT_PWD +
0x0		ADC_BGT_PWD +
0x0		ADC_PWD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED.

+
5ADC_REFBUF_PWDROThis bit indicates that the ADC REFBUF is powered down

+
4ADC_REFKEEP_PWDROThis bit indicates that the ADC REFKEEP is powered down

+
3ADC_VBAT_PWDROThis bit indicates that the ADC VBAT resistor divider is powered down

+
2ADC_VPTAT_PWDROThis bit indicates that the ADC temperature sensor input buffer is powered down

+
1ADC_BGT_PWDROThis bit indicates that the ADC Band Gap is powered down

+
0ADC_PWDROThis bit indicates that the ADC is powered down

+
+
+
+
+ +
+
+

MISCOPT - Power Optimization Control Bits

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40021020 +
+

Description:

+

Power Optimization Control Bits

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		DIS_LDOLPMODE_TIMERS +
0x0		RSVD01 +
0x0		RSVD00 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:3RSVDRORESERVED.

+
2DIS_LDOLPMODE_TIMERSRWSetting this bit will enable the MEM LDO to be in LPMODE during deep sleep even when the ctimers or stimers are running

+
1RSVD01RWRESERVED - this field should not be modified

+
0RSVD00RWRESERVED - this field should not be modified

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/rstgen_regs.html b/docs/apollo2/pages/rstgen_regs.html new file mode 100644 index 0000000..6da41a1 --- /dev/null +++ b/docs/apollo2/pages/rstgen_regs.html @@ -0,0 +1,1505 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
RSTGEN - MCU Reset Generator
+
+
+ + +
+
+
+

RSTGEN Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CFG - Configuration Register +
+   + 0x00000004: + +   + SWPOI - Software POI Reset +
+   + 0x00000008: + +   + SWPOR - Software POR Reset +
+   + 0x0000000C: + +   + STAT - Status Register +
+   + 0x00000010: + +   + CLRSTAT - Clear the status register +
+   + 0x00000014: + +   + TPIU_RST - TPIU reset +
+   + 0x00000200: + +   + INTEN - Reset Interrupt register: Enable +
+   + 0x00000204: + +   + INTSTAT - Reset Interrupt register: Status +
+   + 0x00000208: + +   + INTCLR - Reset Interrupt register: Clear +
+   + 0x0000020C: + +   + INTSET - Reset Interrupt register: Set +
+
+
+ +
+
+

CFG - Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000000 +
+

Description:

+

Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WDREN +
0x0		BODHREN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED.

+
1WDRENRWWatchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset.

+
0BODHRENRWBrown out high (2.1v) reset enable.

+
+
+
+
+ +
+
+

SWPOI - Software POI Reset

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000004 +
+

Description:

+

Software POI Reset

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SWPOIKEY +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED.

+
7:0SWPOIKEYWO0x1B generates a software POI reset.

+ KEYVALUE = 0x1B - Writing 0x1B key value generates a software POI reset.
+
+
+
+ +
+
+

SWPOR - Software POR Reset

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000008 +
+

Description:

+

Software POR Reset

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SWPORKEY +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDRORESERVED.

+
7:0SWPORKEYWO0xD4 generates a software POR reset.

+ KEYVALUE = 0xD4 - Writing 0xD4 key value generates a software POR reset.
+
+
+
+ +
+
+

STAT - Status Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000000C +
+

Description:

+

Status Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WDRSTAT +
0x0		DBGRSTAT +
0x0		POIRSTAT +
0x0		SWRSTAT +
0x0		BORSTAT +
0x0		PORSTAT +
0x0		EXRSTAT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:7RSVDRORESERVED.

+
6WDRSTATROReset was initiated by a Watchdog Timer Reset.

+
5DBGRSTATROReset was a initiated by Debugger Reset.

+
4POIRSTATROReset was a initiated by Software POI Reset.

+
3SWRSTATROReset was a initiated by SW POR or AIRCR Reset.

+
2BORSTATROReset was initiated by a Brown-Out Reset.

+
1PORSTATROReset was initiated by a Power-On Reset.

+
0EXRSTATROReset was initiated by an External Reset.

+
+
+
+
+ +
+
+

CLRSTAT - Clear the status register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000010 +
+

Description:

+

Clear the status register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CLRSTAT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0CLRSTATWOWriting a 1 to this bit clears all bits in the RST_STAT.

+
+
+
+
+ +
+
+

TPIU_RST - TPIU reset

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000014 +
+

Description:

+

TPIU reset

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		TPIURST +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRWRESERVED.

+
0TPIURSTRWStatic reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset.

+
+
+
+
+ +
+
+

INTEN - Reset Interrupt register: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BODH +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0BODHRWEnables an interrupt that triggers when VCC is below BODH level.

+
+
+
+
+ +
+
+

INTSTAT - Reset Interrupt register: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BODH +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0BODHRWEnables an interrupt that triggers when VCC is below BODH level.

+
+
+
+
+ +
+
+

INTCLR - Reset Interrupt register: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40000208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BODH +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0BODHRWEnables an interrupt that triggers when VCC is below BODH level.

+
+
+
+
+ +
+
+

INTSET - Reset Interrupt register: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000020C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		BODH +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDRORESERVED.

+
0BODHRWEnables an interrupt that triggers when VCC is below BODH level.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/rtc_regs.html b/docs/apollo2/pages/rtc_regs.html new file mode 100644 index 0000000..b59bee8 --- /dev/null +++ b/docs/apollo2/pages/rtc_regs.html @@ -0,0 +1,1713 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
RTC - Real Time Clock
+
+
+ + +
+
+
+

RTC Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CTRLOW - RTC Counters Lower +
+   + 0x00000004: + +   + CTRUP - RTC Counters Upper +
+   + 0x00000008: + +   + ALMLOW - RTC Alarms Lower +
+   + 0x0000000C: + +   + ALMUP - RTC Alarms Upper +
+   + 0x00000010: + +   + RTCCTL - RTC Control Register +
+   + 0x000000C0: + +   + INTEN - RTC Interrupt Register: Enable +
+   + 0x000000C4: + +   + INTSTAT - RTC Interrupt Register: Status +
+   + 0x000000C8: + +   + INTCLR - RTC Interrupt Register: Clear +
+   + 0x000000CC: + +   + INTSET - RTC Interrupt Register: Set +
+
+
+ +
+
+

CTRLOW - RTC Counters Lower

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004040 +
+

Description:

+

RTC Counters Lower

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CTRHR +
0x1		RSVD +
0x0		CTRMIN +
0x0		RSVD +
0x0		CTRSEC +
0x0		CTR100 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:24CTRHRRWHours Counter

+
23RSVDRORESERVED

+
22:16CTRMINRWMinutes Counter

+
15RSVDRORESERVED

+
14:8CTRSECRWSeconds Counter

+
7:0CTR100RW100ths of a second Counter

+
+
+
+
+ +
+
+

CTRUP - RTC Counters Upper

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004044 +
+

Description:

+

RTC Counters Upper

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CTERR +
0x0		RSVD +
0x0		CEB +
0x0		CB +
0x0		CTRWKDY +
0x0		CTRYR +
0x0		RSVD +
0x0		CTRMO +
0x0		RSVD +
0x0		CTRDATE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31CTERRROCounter read error status

+ NOERR = 0x0 - No read error occurred
+ RDERR = 0x1 - Read error occurred
30:29RSVDRORESERVED

+
28CEBRWCentury enable

+ DIS = 0x0 - Disable the Century bit from changing
+ EN = 0x1 - Enable the Century bit to change
27CBRWCentury

+ 2000 = 0x0 - Century is 2000s
+ 1900_2100 = 0x1 - Century is 1900s/2100s
26:24CTRWKDYRWWeekdays Counter

+
23:16CTRYRRWYears Counter

+
15:13RSVDRORESERVED

+
12:8CTRMORWMonths Counter

+
7:6RSVDRORESERVED

+
5:0CTRDATERWDate Counter

+
+
+
+
+ +
+
+

ALMLOW - RTC Alarms Lower

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004048 +
+

Description:

+

RTC Alarms Lower

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALMHR +
0x0		RSVD +
0x0		ALMMIN +
0x0		RSVD +
0x0		ALMSEC +
0x0		ALM100 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:30RSVDRORESERVED

+
29:24ALMHRRWHours Alarm

+
23RSVDRORESERVED

+
22:16ALMMINRWMinutes Alarm

+
15RSVDRORESERVED

+
14:8ALMSECRWSeconds Alarm

+
7:0ALM100RW100ths of a second Alarm

+
+
+
+
+ +
+
+

ALMUP - RTC Alarms Upper

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000404C +
+

Description:

+

RTC Alarms Upper

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALMWKDY +
0x0		RSVD +
0x0		ALMMO +
0x0		RSVD +
0x0		ALMDATE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:19RSVDRORESERVED

+
18:16ALMWKDYRWWeekdays Alarm

+
15:13RSVDRORESERVED

+
12:8ALMMORWMonths Alarm

+
7:6RSVDRORESERVED

+
5:0ALMDATERWDate Alarm

+
+
+
+
+ +
+
+

RTCCTL - RTC Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004050 +
+

Description:

+

RTC Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		HR1224 +
0x0		RSTOP +
0x0		RPT +
0x0		WRTC +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDRORESERVED

+
5HR1224RWHours Counter mode

+ 24HR = 0x0 - Hours in 24 hour mode
+ 12HR = 0x1 - Hours in 12 hour mode
4RSTOPRWRTC input clock control

+ RUN = 0x0 - Allow the RTC input clock to run
+ STOP = 0x1 - Stop the RTC input clock
3:1RPTRWAlarm repeat interval

+ DIS = 0x0 - Alarm interrupt disabled
+ YEAR = 0x1 - Interrupt every year
+ MONTH = 0x2 - Interrupt every month
+ WEEK = 0x3 - Interrupt every week
+ DAY = 0x4 - Interrupt every day
+ HR = 0x5 - Interrupt every hour
+ MIN = 0x6 - Interrupt every minute
+ SEC = 0x7 - Interrupt every second/10th/100th
0WRTCRWCounter write control

+ DIS = 0x0 - Counter writes are disabled
+ EN = 0x1 - Counter writes are enabled
+
+
+
+ +
+
+

INTEN - RTC Interrupt Register: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004100 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ +
+
+

INTSTAT - RTC Interrupt Register: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004104 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ +
+
+

INTCLR - RTC Interrupt Register: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40004108 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ +
+
+

INTSET - RTC Interrupt Register: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000410C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ALM +
0x0		OF +
0x0		ACC +
0x0		ACF +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED

+
3ALMRWRTC Alarm interrupt

+
2OFRWXT Oscillator Fail interrupt

+
1ACCRWAutocalibration Complete interrupt

+
0ACFRWAutocalibration Fail interrupt

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/sysctrl_regs.html b/docs/apollo2/pages/sysctrl_regs.html new file mode 100644 index 0000000..a77779c --- /dev/null +++ b/docs/apollo2/pages/sysctrl_regs.html @@ -0,0 +1,3936 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
SYSCTRL - ARM System Control Block Registers.
+
+
+ + +
+
+
+

SYSCTRL Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0xE000E004: + +   + ICTR - Interrupt Controller Type Register (NVIC) +
+   + 0xE000E008: + +   + ACTLR - Auxilliary Control Register +
+   + 0xE000ED04: + +   + ICSR - Interrupt Control and State Register +
+   + 0xE000ED08: + +   + VTOR - Vector Table Offset Register. +
+   + 0xE000ED0C: + +   + AIRCR - Application Interrupt and Reset Control Register. +
+   + 0xE000ED10: + +   + SCR - System Control Register. +
+   + 0xE000ED14: + +   + CCR - Configuration and Control Register. +
+   + 0xE000ED18: + +   + SHPR1 - System Handler Priority Register 1. +
+   + 0xE000ED1C: + +   + SHPR2 - System Handler Priority Register 2. +
+   + 0xE000ED20: + +   + SHPR3 - System Handler Priority Register 3. +
+   + 0xE000ED24: + +   + SHCSR - System Handler Control and State Register. +
+   + 0xE000ED28: + +   + CFSR - Configurable Fault Status Register. +
+   + 0xE000ED2C: + +   + HFSR - Hard Fault Status Register. +
+   + 0xE000ED34: + +   + MMFAR - MemManage Fault Address Register. +
+   + 0xE000ED38: + +   + BFAR - Bus Fault Address Register. +
+   + 0xE000ED88: + +   + CPACR - Coprocessor Access Control Register. +
+   + 0xE000EDFC: + +   + DEMCR - Debug Exception and Monitor Control Register +
+   + 0xE000EF00: + +   + STIR - Software Triggered Interrupt Register +
+   + 0xE000EF34: + +   + FPCCR - Floating-Point Context Control Register. +
+   + 0xE000EF38: + +   + FPCAR - Floating-Point Context Address Register. +
+   + 0xE000EF3C: + +   + FPDSCR - Floating-Point Default Status Control Register. +
+
+
+ +
+
+

ICTR - Interrupt Controller Type Register (NVIC)

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E004 +
+

Description:

+

Interrupt Controller Type Register (NVIC)

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		INTLINESNUM +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDRORESERVED.

+
3:0INTLINESNUMRWTotal number of interrupt lines in groups of 32.

+
+
+
+
+ +
+
+

ACTLR - Auxilliary Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E008 +
+

Description:

+

Auxilliary Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		DISFPCA +
0x0		DISOOFP +
0x0		RSVD +
0x0		DISFOLD +
0x0		DISDEFWBUF +
0x0		DISMCYCINT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
30:10RSVDRORESERVED.

+
9DISFPCARWDisables lazy stacking of floating point context.

+
8DISOOFPRWDisables floating point instructions completing out of order with respect to integer instructions.

+
6:3RSVDRORESERVED.

+
2DISFOLDRWDisables folding of IT instructions.

+
1DISDEFWBUFRWDisables write buffer use during default memory map accesses.

+
0DISMCYCINTRWDisables interruption of multi-cycle instructions.

+
+
+
+
+ +
+
+

ICSR - Interrupt Control and State Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED04 +
+

Description:

+

Interrupt Control and State Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
NMIPENDSET +
0x0		PENDSVSET +
0x0		RSVD +
0x0		PENDSVCLR +
0x0		PENDSTSET +
0x0		PENDSTCLR +
0x0		RSVD +
0x0		ISRPREEMPT +
0x0		ISRPENDING +
0x0		RSVD +
0x0		VECTPENDING +
0x0		RETTOBASE +
0x0		RSVD +
0x0		VECTACTIVE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31NMIPENDSETRWPend an NMI exception.

+
28PENDSVSETRWSet the PendSV interrupt as pending.

+
29:28RSVDRORESERVED.

+
27PENDSVCLRWORemove the pending status of the PendSV exception.

+
26PENDSTSETRWSet the SysTick exception as pending.

+
25PENDSTCLRWORemove the pending status of the SysTick exception.

+
24RSVDRORESERVED.

+
23ISRPREEMPTROIndicates whether a pending exception will be serviced on exit from debug halt state.

+
22ISRPENDINGROIndicates whether an external interrupt, generated by the NVIC, is pending.

+
21RSVDRORESERVED.

+
20:12VECTPENDINGROThe exception number of the highest priority pending exception.

+
11RETTOBASEROIndicates whether there is an active exception other than the exception shown by IPSR.

+
10:9RSVDRORESERVED.

+
8:0VECTACTIVEROThe exception number of the current executing exception.

+
+
+
+
+ +
+
+

VTOR - Vector Table Offset Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED08 +
+

Description:

+

Vector Table Offset Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VALUE +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0VALUERWVector table base address.

+
+
+
+
+ +
+
+

AIRCR - Application Interrupt and Reset Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED0C +
+

Description:

+

Application Interrupt and Reset Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
VECTKEY +
0x0		ENDIANNESS +
0x0		RSVD +
0x0		PRIGROUP +
0x0		RSVD +
0x0		SYSRESETREQ +
0x0		VECTCLRACTIVE +
0x0		VECTRESET +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16VECTKEYRWRegister writes must write 0x5FA to this field, otherwise the write is ignored.

+
15ENDIANNESSROIndicates endianness of memory architecture. (Little = 0, Big = 1)

+
14:11RSVDRORESERVED.

+
10:8PRIGROUPRWPriority grouping, indicates the binary point position.

+
7:3RSVDRORESERVED.

+
2SYSRESETREQRWWriting a 1 to this bit reqests a local reset.

+
1VECTCLRACTIVEWOWriting a 1 to this bit clears all active state information for fixed and configurable exceptions.

+
0VECTRESETWOWriting a 1 to this bit causes a local system reset.

+
+
+
+
+ +
+
+

SCR - System Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED10 +
+

Description:

+

System Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SEVONPEND +
0x0		RSVD +
0x0		SLEEPDEEP +
0x0		SLEEPONEXIT +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:5RSVDRORESERVED.

+
4SEVONPENDRWDetermines whether a pending interrupt is a wakeup event.

+
3RSVDRORESERVED.

+
2SLEEPDEEPRWDetermines whether the sleep mode should be regular or deep sleep

+
1SLEEPONEXITRWDetermines whether the processor shoudl automatically sleep when an ISR returns to the base-level.

+
0RSVDRORESERVED.

+
+
+
+
+ +
+
+

CCR - Configuration and Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED14 +
+

Description:

+

Configuration and Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		STKALIGN +
0x0		BFHFNMIGN +
0x0		RSVD +
0x0		DIV0TRP +
0x0		UNALIGNTRP +
0x0		RSVD +
0x0		USERSETMPEND +
0x0		NONBASETHRDENA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:10RSVDRORESERVED.

+
9STKALIGNRWSet to force 8-byte alignment for the stack pointer.

+
8BFHFNMIGNRWSet to ignore precise data access faults during hard fault handlers.

+
7:5RSVDRORESERVED.

+
4DIV0TRPRWSet to enable trapping on divide-by-zero.

+
3UNALIGNTRPRWSet to enable trapping of unaligned word or halfword accesses.

+
2RSVDRORESERVED.

+
1USERSETMPENDRWSet to allow unpriveleged software to access the STIR

+
0NONBASETHRDENARWSet to enable the processor to enter Thread mode at an execution priority other than base level.

+
+
+
+
+ +
+
+

SHPR1 - System Handler Priority Register 1.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED18 +
+

Description:

+

System Handler Priority Register 1.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_7 +
0x0		PRI_6 +
0x0		PRI_5 +
0x0		PRI_4 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_7RWReserved for priority of system handler 7.

+
23:16PRI_6RWPriority of system handler 6, UsageFault.

+
15:8PRI_5RWPriority of system handler 5, BusFault.

+
7:0PRI_4RWPriority of system handler 4, MemManage.

+
+
+
+
+ +
+
+

SHPR2 - System Handler Priority Register 2.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED1C +
+

Description:

+

System Handler Priority Register 2.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_11 +
0x0		PRI_10 +
0x0		PRI_9 +
0x0		PRI_8 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_11RWPriority of system handler 11, SVCall.

+
23:16PRI_10RWReserved for priority of system handler 10.

+
15:8PRI_9RWReserved for priority of system handler 9.

+
7:0PRI_8RWReserved for priority of system handler 8.

+
+
+
+
+ +
+
+

SHPR3 - System Handler Priority Register 3.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED20 +
+

Description:

+

System Handler Priority Register 3.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PRI_15 +
0x0		PRI_14 +
0x0		PRI_13 +
0x0		PRI_12 +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24PRI_15RWPriority of system handler 15, SysTick.

+
23:16PRI_14RWPriority of system handler 14, PendSV.

+
15:8PRI_13RWReserved for priority of system handler 13.

+
7:0PRI_12RWPriority of system handler 12, DebugMonitor.

+
+
+
+
+ +
+
+

SHCSR - System Handler Control and State Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED24 +
+

Description:

+

System Handler Control and State Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		USAGEFAULTENA +
0x0		BUSFAULTENA +
0x0		MEMFAULTENA +
0x0		SVCALLPENDED +
0x0		BUSFAULTPENDED +
0x0		MEMFAULTPENDED +
0x0		USGFAULTPENDED +
0x0		SYSTICKACT +
0x0		PENDSVACT +
0x0		RSVD +
0x0		MONITORACT +
0x0		SVCALLACT +
0x0		RSVD +
0x0		USGFAULTACT +
0x0		RSVD +
0x0		BUSFAULTACT +
0x0		MEMFAULTACT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:19RSVDRORESERVED.

+
18USAGEFAULTENARWSet to enable UsageFault.

+
17BUSFAULTENARWSet to enable BusFault.

+
16MEMFAULTENARWSet to enable MemManageFault.

+
15SVCALLPENDEDRWSet to pend the SVCall exception.

+
14BUSFAULTPENDEDRWSet to pend the BusFault exception.

+
13MEMFAULTPENDEDRWSet to pend the MemManageFault exception.

+
12USGFAULTPENDEDRWSet to pend the UsageFault exception.

+
11SYSTICKACTRWSet when SysTick is active.

+
10PENDSVACTRWSet when PendSV is active.

+
9RSVDRORESERVED.

+
8MONITORACTRWSet when Monitor is active.

+
7SVCALLACTRWSet when SVCall is active.

+
6:4RSVDRORESERVED.

+
3USGFAULTACTRWSet when UsageFault is active.

+
2RSVDRORESERVED.

+
1BUSFAULTACTRWSet when BusFault is active.

+
0MEMFAULTACTRWSet when MemManageFault is active.

+
+
+
+
+ +
+
+

CFSR - Configurable Fault Status Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED28 +
+

Description:

+

Configurable Fault Status Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		DIVBYZERO +
0x0		UNALIGNED +
0x0		RSVD +
0x0		NOCP +
0x0		INVPC +
0x0		INVSTATE +
0x0		UNDEFINSTR +
0x0		BFARVALID +
0x0		RSVD +
0x0		LSPERR +
0x0		STKERR +
0x0		UNSTKERR +
0x0		IMPRECISERR +
0x0		PRECISERR +
0x0		IBUSERR +
0x0		MMARVALID +
0x0		RSVD +
0x0		MLSPERR +
0x0		MSTKERR +
0x0		MUNSTKER +
0x0		RSVD +
0x0		DACCVIOL +
0x0		IACCVIOL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:26RSVDRORESERVED.

+
25DIVBYZERORWDivide by zero error has occurred.

+
24UNALIGNEDRWUnaligned access error has occurred.

+
23:20RSVDRORESERVED.

+
19NOCPRWA coprocessor access error has occurred.

+
18INVPCRWAn integrity check error has occurred on EXC_RETURN.

+
17INVSTATERWInstruction executed with invalid EPSR.T or EPSR.IT field.

+
16UNDEFINSTRRWProcessor attempted to execute an undefined instruction.

+
15BFARVALIDRWBFAR has valid contents.

+
14RSVDRORESERVED.

+
13LSPERRRWA bus fault occurred during FP lazy state preservation.

+
12STKERRRWA derived bus fault has occurred on exception entry.

+
11UNSTKERRRWA derived bus fault has occurred on exception return.

+
10IMPRECISERRRWImprecise data access error has occurred.

+
9PRECISERRRWA precise data access has occurrred. The faulting address is in BFAR.

+
8IBUSERRRWA bus fault on an instruction prefetch has occurred.

+
7MMARVALIDRWMMAR has valid contents.

+
6RSVDRORESERVED.

+
5MLSPERRRWMemManage fault occurred during FP lazy state preservation.

+
4MSTKERRRWDerived MemManage fault occurred on exception entry.

+
3MUNSTKERRWDerived MemManage fault occurred on exception return.

+
2RSVDRORESERVED.

+
1DACCVIOLRWData access violation. Address is in MMAR.

+
0IACCVIOLRWMPU or Execute Never default memory map access violation.

+
+
+
+
+ +
+
+

HFSR - Hard Fault Status Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED2C +
+

Description:

+

Hard Fault Status Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
DEBUGEVT +
0x0		FORCED +
0x0		RSVD +
0x0		VECTTBL +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31DEBUGEVTRWDebug event has occurred.

+
30FORCEDRWProcessor has elevated a configurable-priority fault to a HardFault.

+
29:2RSVDRORESERVED.

+
1VECTTBLRWVector table read fault has occurred.

+
0RSVDRORESERVED.

+
+
+
+
+ +
+
+

MMFAR - MemManage Fault Address Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED34 +
+

Description:

+

MemManage Fault Address Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ADDRESS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ADDRESSRWAddress of the memory location that caused an MMU fault.

+
+
+
+
+ +
+
+

BFAR - Bus Fault Address Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED38 +
+

Description:

+

Bus Fault Address Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ADDRESS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ADDRESSRWAddress of the memory location that caused an Bus fault.

+
+
+
+
+ +
+
+

CPACR - Coprocessor Access Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000ED88 +
+

Description:

+

Coprocessor Access Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CP11 +
0x0		CP10 +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED.

+
23:22CP11RWAccess priveleges for the Floating point unit. Must always match CP10.

+
21:20CP10RWAccess priveleges for the Floating point unit. Must always match CP11.

+
19:0RSVDRORESERVED.

+
+
+
+
+ +
+
+

DEMCR - Debug Exception and Monitor Control Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000EDFC +
+

Description:

+

Debug Exception and Monitor Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		TRCENA +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:25RSVDRORESERVED.

+
24TRCENARWGlobal enable for all DWT and ITM features.

+
23:0RSVDRORESERVED.

+
+
+
+
+ +
+
+

STIR - Software Triggered Interrupt Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000EF00 +
+

Description:

+

Software Triggered Interrupt Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
INTID +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0INTIDRWVector number of the interrupt that should be triggered.

+
+
+
+
+ +
+
+

FPCCR - Floating-Point Context Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000EF34 +
+

Description:

+

Floating-Point Context Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ASPEN +
0x0		LSPEN +
0x0		RSVD +
0x0		MONRDY +
0x0		RSVD +
0x0		BFRDY +
0x0		MMRDY +
0x0		HFRDY +
0x0		THREAD +
0x0		RSVD +
0x0		USER +
0x0		LSPACT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31ASPENRWSet to enable automatic saving of FP registers on exception entry.

+
30LSPENRWSet to enable lazy context saving of FP registers on exception entry.

+
29:9RSVDRORESERVED.

+
8MONRDYRWAble to set DebugMonitor exception to pending on last FP stack allocation.

+
7RSVDRWRESERVED.

+
6BFRDYRWAble to set BusFault exception to pending on last FP stack allocation.

+
5MMRDYRWAble to set MemManage exception to pending on last FP stack allocation.

+
4HFRDYRWAble to set HardFault exception to pending on last FP stack allocation.

+
3THREADRWRunning from Thread mode on last FP stack allocation.

+
2RSVDRORESERVED.

+
1USERRWRunning from unprivileged mode on last FP stack allocation.

+
0LSPACTRWLazy state preservation is active.

+
+
+
+
+ +
+
+

FPCAR - Floating-Point Context Address Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000EF38 +
+

Description:

+

Floating-Point Context Address Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
ADDRESS +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0ADDRESSRWAddress of the unpopulated floating-point register space allocated on the exception stack frame.

+
+
+
+
+ +
+
+

FPDSCR - Floating-Point Default Status Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000EF3C +
+

Description:

+

Floating-Point Default Status Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		AHP +
0x0		DN +
0x0		FZ +
0x0		RMODE +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDRORESERVED.

+
26AHPRWDefault value for FPSCR.AHP.

+
25DNRWDefault value for FPSCR.DN.

+
24FZRWDefault value for FPSCR.FZ.

+
23:22RMODERWDefault value for FPSCR.RMode.

+
21:0RSVDRORESERVED.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/systick_regs.html b/docs/apollo2/pages/systick_regs.html new file mode 100644 index 0000000..eb1c591 --- /dev/null +++ b/docs/apollo2/pages/systick_regs.html @@ -0,0 +1,673 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
SYSTICK - ARM System Timer (SysTick) Block Registers.
+
+
+ + +
+
+
+

SYSTICK Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + +
+   + 0xE000E010: + +   + SYSTCSR - SysTick Control and Status Register. +
+   + 0xE000E014: + +   + SYSTRVR - SysTick Reload Value Register. +
+   + 0xE000E018: + +   + SYSTCVR - SysTick Current Value Register. +
+   + 0xE000E01C: + +   + SYSTCALIB - SysTick Calibration Value Register. +
+
+
+ +
+
+

SYSTCSR - SysTick Control and Status Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E010 +
+

Description:

+

SysTick Control and Status Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		COUNTFLAG +
0x0		RSVD +
0x0		TICKINT +
0x0		ENABLE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:17RSVDRORESERVED.

+
16COUNTFLAGROReturns 1 if timer counted to 0 since last time this was read.

+
15:2RSVDRORESERVED.

+
1TICKINTRWEnables SysTick exception request. Software can use COUNTFLAG to determine if SysTick has ever counted to zero. 0 = counting down to zero does not assert the SysTick exception request; 1 = counting down to zero asserts the SysTick exception request.

+
0ENABLERWEnables the counter. 0 = counter disabled; 1 = counter enabled.

+
+
+
+
+ +
+
+

SYSTRVR - SysTick Reload Value Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E014 +
+

Description:

+

SysTick Reload Value Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RELOAD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED.

+
23:0RELOADRWValue to load into the SYSTCVR register when the counter is enabled and when it reaches 0.

+
+
+
+
+ +
+
+

SYSTCVR - SysTick Current Value Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E018 +
+

Description:

+

SysTick Current Value Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CURRENT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:24RSVDRORESERVED.

+
23:0CURRENTRWReads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYSTCSR COUNTFLAG bit to 0.

+
+
+
+
+ +
+
+

SYSTCALIB - SysTick Calibration Value Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE000E01C +
+

Description:

+

SysTick Calibration Value Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
NOREF +
0x0		SKEW +
0x0		RSVD +
0x0		TENMS +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31NOREFROIndicates whether the device provides a reference clock to the processor. 0 = reference clock provided; 1 = no reference clock provided. If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes.

+
30SKEWROIndicates whether the TENMS value is exact. 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. An inexact TENMS value can affect the suitability of SysTick as a software real time clock.

+
29:24RSVDRORESERVED.

+
23:0TENMSRWReload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/tpiu_regs.html b/docs/apollo2/pages/tpiu_regs.html new file mode 100644 index 0000000..73d36cc --- /dev/null +++ b/docs/apollo2/pages/tpiu_regs.html @@ -0,0 +1,1050 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
TPIU - ARM Trace Port Interface Unit
+
+
+ + +
+
+
+

TPIU Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0xE0040000: + +   + SSPSR - Supported Parallel Port Sizes. +
+   + 0xE0040004: + +   + CSPSR - Current Parallel Port Size. +
+   + 0xE0040010: + +   + ACPR - Asynchronous Clock Prescaler. +
+   + 0xE00400F0: + +   + SPPR - Selected Pin Protocol. +
+   + 0xE0040304: + +   + FFCR - Formatter and Flush Control Register. +
+   + 0xE0040F00: + +   + ITCTRL - Specifies normal or integration mode for the TPIU. +
+   + 0xE0040FC8: + +   + TYPE - TPIU Type. +
+
+
+ +
+
+

SSPSR - Supported Parallel Port Sizes.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0040000 +
+

Description:

+

Supported Parallel Port Sizes.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
SWIDTH0 +
0x1
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
0SWIDTH0ROParallel Port Width 1 supported

+
+
+
+
+ +
+
+

CSPSR - Current Parallel Port Size.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0040004 +
+

Description:

+

Current Parallel Port Size.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
CWIDTH +
0x1
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0CWIDTHRWOne-hot representation of the current port width.

+ 1BIT = 0x1 - Set width to 1.
+
+
+
+ +
+
+

ACPR - Asynchronous Clock Prescaler.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0040010 +
+

Description:

+

Asynchronous Clock Prescaler.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SWOSCALER +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDRORESERVED

+
15:0SWOSCALERRWPrescaler value for the baudrate of SWO.

+ 115200 = 0x33 - Set divisor correctly for 115200 baud.
+
+
+
+ +
+
+

SPPR - Selected Pin Protocol.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE00400F0 +
+

Description:

+

Selected Pin Protocol.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		TXMODE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED

+
1:0TXMODERWSelects the protocol used for trace output.

+ PARALLEL = 0x0 - Parallel trace port.
+ MANCHESTER = 0x1 - Manchester encoded.
+ NRZ = 0x2 - Non-return-to-zero encoding.
+ UART = 0x2 - UART encoding.
+
+
+
+ +
+
+

FFCR - Formatter and Flush Control Register.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0040304 +
+

Description:

+

Formatter and Flush Control Register.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x1		ENFCONT +
0x0		RSVD +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDRORESERVED

+
1ENFCONTRWEnable continuous formatting.

+
0RSVDRORESERVED

+
+
+
+
+ +
+
+

ITCTRL - Specifies normal or integration mode for the TPIU.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0040F00 +
+

Description:

+

Specifies normal or integration mode for the TPIU.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		MODE +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
30:1RSVDRORESERVED

+
1:0MODERWSpecifies the current mode for the TPIU.

+ NORMAL = 0x0 - Normal mode.
+ TEST = 0x1 - Integration test mode.
+ DATA_TEST = 0x2 - Integration data test mode.
+
+
+
+ +
+
+

TYPE - TPIU Type.

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0xE0040FC8 +
+

Description:

+

TPIU Type.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		NRZVALID +
0x1		MANCVALID +
0x1		PTINVALID +
0x1		FIFOSZ +
0x2
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:12RSVDRORESERVED

+
11NRZVALIDRO1 Indicates UART/NRZ support.

+
10MANCVALIDRO1 Indicates Manchester support.

+
9PTINVALIDRO0 Indicates Parallel Trace support.

+
8:6FIFOSZROFIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size of 8 bytes.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/uart_regs.html b/docs/apollo2/pages/uart_regs.html new file mode 100644 index 0000000..eebfeab --- /dev/null +++ b/docs/apollo2/pages/uart_regs.html @@ -0,0 +1,2816 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
UART - Serial UART
+
+
+ + +
+
+
+

UART Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + DR - UART Data Register +
+   + 0x00000004: + +   + RSR - UART Status Register +
+   + 0x00000018: + +   + FR - Flag Register +
+   + 0x00000020: + +   + ILPR - IrDA Counter +
+   + 0x00000024: + +   + IBRD - Integer Baud Rate Divisor +
+   + 0x00000028: + +   + FBRD - Fractional Baud Rate Divisor +
+   + 0x0000002C: + +   + LCRH - Line Control High +
+   + 0x00000030: + +   + CR - Control Register +
+   + 0x00000034: + +   + IFLS - FIFO Interrupt Level Select +
+   + 0x00000038: + +   + IER - Interrupt Enable +
+   + 0x0000003C: + +   + IES - Interrupt Status +
+   + 0x00000040: + +   + MIS - Masked Interrupt Status +
+   + 0x00000044: + +   + IEC - Interrupt Clear +
+
+
+ +
+
+

DR - UART Data Register

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C000 +
+   + Instance 1 Address: + +   + 0x4001D000 +
+

Description:

+

UART Data Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OEDATA +
0x0		BEDATA +
0x0		PEDATA +
0x0		FEDATA +
0x0		DATA +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:12RSVDROThis bitfield is reserved for future use.

+
11OEDATAROThis is the overrun error indicator.

+ NOERR = 0x0 - No error on UART OEDATA, overrun error indicator.
+ ERR = 0x1 - Error on UART OEDATA, overrun error indicator.
10BEDATAROThis is the break error indicator.

+ NOERR = 0x0 - No error on UART BEDATA, break error indicator.
+ ERR = 0x1 - Error on UART BEDATA, break error indicator.
9PEDATAROThis is the parity error indicator.

+ NOERR = 0x0 - No error on UART PEDATA, parity error indicator.
+ ERR = 0x1 - Error on UART PEDATA, parity error indicator.
8FEDATAROThis is the framing error indicator.

+ NOERR = 0x0 - No error on UART FEDATA, framing error indicator.
+ ERR = 0x1 - Error on UART FEDATA, framing error indicator.
7:0DATARWThis is the UART data port.

+
+
+
+
+ +
+
+

RSR - UART Status Register

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C004 +
+   + Instance 1 Address: + +   + 0x4001D004 +
+

Description:

+

UART Status Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OESTAT +
0x0		BESTAT +
0x0		PESTAT +
0x0		FESTAT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:4RSVDROThis bitfield is reserved for future use.

+
3OESTATRWThis is the overrun error indicator.

+ NOERR = 0x0 - No error on UART OESTAT, overrun error indicator.
+ ERR = 0x1 - Error on UART OESTAT, overrun error indicator.
2BESTATRWThis is the break error indicator.

+ NOERR = 0x0 - No error on UART BESTAT, break error indicator.
+ ERR = 0x1 - Error on UART BESTAT, break error indicator.
1PESTATRWThis is the parity error indicator.

+ NOERR = 0x0 - No error on UART PESTAT, parity error indicator.
+ ERR = 0x1 - Error on UART PESTAT, parity error indicator.
0FESTATRWThis is the framing error indicator.

+ NOERR = 0x0 - No error on UART FESTAT, framing error indicator.
+ ERR = 0x1 - Error on UART FESTAT, framing error indicator.
+
+
+
+ +
+
+

FR - Flag Register

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C018 +
+   + Instance 1 Address: + +   + 0x4001D018 +
+

Description:

+

Flag Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		TXBUSY +
0x0		TXFE +
0x0		RXFF +
0x0		TXFF +
0x0		RXFE +
0x0		BUSY +
0x0		DCD +
0x0		DSR +
0x0		CTS +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:9RSVDROThis bitfield is reserved for future use.

+
8TXBUSYROThis bit holds the transmit BUSY indicator.

+
7TXFEROThis bit holds the transmit FIFO empty indicator.

+ XMTFIFO_EMPTY = 0x1 - Transmit fifo is empty.
6RXFFROThis bit holds the receive FIFO full indicator.

+ RCVFIFO_FULL = 0x1 - Receive fifo is full.
5TXFFROThis bit holds the transmit FIFO full indicator.

+ XMTFIFO_FULL = 0x1 - Transmit fifo is full.
4RXFEROThis bit holds the receive FIFO empty indicator.

+ RCVFIFO_EMPTY = 0x1 - Receive fifo is empty.
3BUSYROThis bit holds the busy indicator.

+ BUSY = 0x1 - UART busy indicator.
2DCDROThis bit holds the data carrier detect indicator.

+ DETECTED = 0x1 - Data carrier detect detected.
1DSRROThis bit holds the data set ready indicator.

+ READY = 0x1 - Data set ready.
0CTSROThis bit holds the clear to send indicator.

+ CLEARTOSEND = 0x1 - Clear to send is indicated.
+
+
+
+ +
+
+

ILPR - IrDA Counter

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C020 +
+   + Instance 1 Address: + +   + 0x4001D020 +
+

Description:

+

IrDA Counter

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		ILPDVSR +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDROThis bitfield is reserved for future use.

+
7:0ILPDVSRRWThese bits hold the IrDA counter divisor.

+
+
+
+
+ +
+
+

IBRD - Integer Baud Rate Divisor

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C024 +
+   + Instance 1 Address: + +   + 0x4001D024 +
+

Description:

+

Integer Baud Rate Divisor

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		DIVINT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDROThis bitfield is reserved for future use.

+
15:0DIVINTRWThese bits hold the baud integer divisor.

+
+
+
+
+ +
+
+

FBRD - Fractional Baud Rate Divisor

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C028 +
+   + Instance 1 Address: + +   + 0x4001D028 +
+

Description:

+

Fractional Baud Rate Divisor

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		DIVFRAC +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDROThis bitfield is reserved for future use.

+
5:0DIVFRACRWThese bits hold the baud fractional divisor.

+
+
+
+
+ +
+
+

LCRH - Line Control High

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C02C +
+   + Instance 1 Address: + +   + 0x4001D02C +
+

Description:

+

Line Control High

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		SPS +
0x0		WLEN +
0x0		FEN +
0x0		STP2 +
0x0		EPS +
0x0		PEN +
0x0		BRK +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDROThis bitfield is reserved for future use.

+
7SPSRWThis bit holds the stick parity select.

+
6:5WLENRWThese bits hold the write length.

+
4FENRWThis bit holds the FIFO enable.

+
3STP2RWThis bit holds the two stop bits select.

+
2EPSRWThis bit holds the even parity select.

+
1PENRWThis bit holds the parity enable.

+
0BRKRWThis bit holds the break set.

+
+
+
+
+ +
+
+

CR - Control Register

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C030 +
+   + Instance 1 Address: + +   + 0x4001D030 +
+

Description:

+

Control Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CTSEN +
0x0		RTSEN +
0x0		OUT2 +
0x0		OUT1 +
0x0		RTS +
0x0		DTR +
0x0		RXE +
0x1		TXE +
0x1		LBE +
0x0		CLKSEL +
0x0		CLKEN +
0x0		SIRLP +
0x0		SIREN +
0x0		UARTEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:16RSVDROThis bitfield is reserved for future use.

+
15CTSENRWThis bit enables CTS hardware flow control.

+
14RTSENRWThis bit enables RTS hardware flow control.

+
13OUT2RWThis bit holds modem Out2.

+
12OUT1RWThis bit holds modem Out1.

+
11RTSRWThis bit enables request to send.

+
10DTRRWThis bit enables data transmit ready.

+
9RXERWThis bit is the receive enable.

+
8TXERWThis bit is the transmit enable.

+
7LBERWThis bit is the loopback enable.

+
6:4CLKSELRWThis bitfield is the UART clock select.

+ NOCLK = 0x0 - No UART clock. This is the low power default.
+ 24MHZ = 0x1 - 24 MHz clock.
+ 12MHZ = 0x2 - 12 MHz clock.
+ 6MHZ = 0x3 - 6 MHz clock.
+ 3MHZ = 0x4 - 3 MHz clock.
+ RSVD5 = 0x5 - Reserved.
+ RSVD6 = 0x6 - Reserved.
+ RSVD7 = 0x7 - Reserved.
3CLKENRWThis bit is the UART clock enable.

+
2SIRLPRWThis bit is the SIR low power select.

+
1SIRENRWThis bit is the SIR ENDEC enable.

+
0UARTENRWThis bit is the UART enable.

+
+
+
+
+ +
+
+

IFLS - FIFO Interrupt Level Select

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C034 +
+   + Instance 1 Address: + +   + 0x4001D034 +
+

Description:

+

FIFO Interrupt Level Select

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RXIFLSEL +
0x2		TXIFLSEL +
0x2
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:6RSVDROThis bitfield is reserved for future use.

+
5:3RXIFLSELRWThese bits hold the receive FIFO interrupt level.

+
2:0TXIFLSELRWThese bits hold the transmit FIFO interrupt level.

+
+
+
+
+ +
+
+

IER - Interrupt Enable

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C038 +
+   + Instance 1 Address: + +   + 0x4001D038 +
+

Description:

+

Interrupt Enable

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OEIM +
0x0		BEIM +
0x0		PEIM +
0x0		FEIM +
0x0		RTIM +
0x0		TXIM +
0x0		RXIM +
0x0		DSRMIM +
0x0		DCDMIM +
0x0		CTSMIM +
0x0		TXCMPMIM +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDROThis bitfield is reserved for future use.

+
10OEIMRWThis bit holds the overflow interrupt enable.

+
9BEIMRWThis bit holds the break error interrupt enable.

+
8PEIMRWThis bit holds the parity error interrupt enable.

+
7FEIMRWThis bit holds the framing error interrupt enable.

+
6RTIMRWThis bit holds the receive timeout interrupt enable.

+
5TXIMRWThis bit holds the transmit interrupt enable.

+
4RXIMRWThis bit holds the receive interrupt enable.

+
3DSRMIMRWThis bit holds the modem DSR interrupt enable.

+
2DCDMIMRWThis bit holds the modem DCD interrupt enable.

+
1CTSMIMRWThis bit holds the modem CTS interrupt enable.

+
0TXCMPMIMRWThis bit holds the modem TXCMP interrupt enable.

+
+
+
+
+ +
+
+

IES - Interrupt Status

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C03C +
+   + Instance 1 Address: + +   + 0x4001D03C +
+

Description:

+

Interrupt Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OERIS +
0x0		BERIS +
0x0		PERIS +
0x0		FERIS +
0x0		RTRIS +
0x0		TXRIS +
0x0		RXRIS +
0x0		DSRMRIS +
0x0		DCDMRIS +
0x0		CTSMRIS +
0x0		TXCMPMRIS +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDROThis bitfield is reserved for future use.

+
10OERISROThis bit holds the overflow interrupt status.

+
9BERISROThis bit holds the break error interrupt status.

+
8PERISROThis bit holds the parity error interrupt status.

+
7FERISROThis bit holds the framing error interrupt status.

+
6RTRISROThis bit holds the receive timeout interrupt status.

+
5TXRISROThis bit holds the transmit interrupt status.

+
4RXRISROThis bit holds the receive interrupt status.

+
3DSRMRISROThis bit holds the modem DSR interrupt status.

+
2DCDMRISROThis bit holds the modem DCD interrupt status.

+
1CTSMRISROThis bit holds the modem CTS interrupt status.

+
0TXCMPMRISROThis bit holds the modem TXCMP interrupt status.

+
+
+
+
+ +
+
+

MIS - Masked Interrupt Status

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C040 +
+   + Instance 1 Address: + +   + 0x4001D040 +
+

Description:

+

Masked Interrupt Status

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OEMIS +
0x0		BEMIS +
0x0		PEMIS +
0x0		FEMIS +
0x0		RTMIS +
0x0		TXMIS +
0x0		RXMIS +
0x0		DSRMMIS +
0x0		DCDMMIS +
0x0		CTSMMIS +
0x0		TXCMPMMIS +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDROThis bitfield is reserved for future use.

+
10OEMISROThis bit holds the overflow interrupt status masked.

+
9BEMISROThis bit holds the break error interrupt status masked.

+
8PEMISROThis bit holds the parity error interrupt status masked.

+
7FEMISROThis bit holds the framing error interrupt status masked.

+
6RTMISROThis bit holds the receive timeout interrupt status masked.

+
5TXMISROThis bit holds the transmit interrupt status masked.

+
4RXMISROThis bit holds the receive interrupt status masked.

+
3DSRMMISROThis bit holds the modem DSR interrupt status masked.

+
2DCDMMISROThis bit holds the modem DCD interrupt status masked.

+
1CTSMMISROThis bit holds the modem CTS interrupt status masked.

+
0TXCMPMMISROThis bit holds the modem TXCMP interrupt status masked.

+
+
+
+
+ +
+
+

IEC - Interrupt Clear

+
+
+

Address:

+ + + + + + + + + + + +
+   + Instance 0 Address: + +   + 0x4001C044 +
+   + Instance 1 Address: + +   + 0x4001D044 +
+

Description:

+

Interrupt Clear

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OEIC +
0x0		BEIC +
0x0		PEIC +
0x0		FEIC +
0x0		RTIC +
0x0		TXIC +
0x0		RXIC +
0x0		DSRMIC +
0x0		DCDMIC +
0x0		CTSMIC +
0x0		TXCMPMIC +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:11RSVDROThis bitfield is reserved for future use.

+
10OEICWOThis bit holds the overflow interrupt clear.

+
9BEICWOThis bit holds the break error interrupt clear.

+
8PEICWOThis bit holds the parity error interrupt clear.

+
7FEICWOThis bit holds the framing error interrupt clear.

+
6RTICWOThis bit holds the receive timeout interrupt clear.

+
5TXICWOThis bit holds the transmit interrupt clear.

+
4RXICWOThis bit holds the receive interrupt clear.

+
3DSRMICWOThis bit holds the modem DSR interrupt clear.

+
2DCDMICWOThis bit holds the modem DCD interrupt clear.

+
1CTSMICWOThis bit holds the modem CTS interrupt clear.

+
0TXCMPMICWOThis bit holds the modem TXCMP interrupt clear.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/vcomp_regs.html b/docs/apollo2/pages/vcomp_regs.html new file mode 100644 index 0000000..8089644 --- /dev/null +++ b/docs/apollo2/pages/vcomp_regs.html @@ -0,0 +1,1133 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
VCOMP - Voltage Comparator
+
+
+ + +
+
+
+

VCOMP Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CFG - Configuration Register +
+   + 0x00000004: + +   + STAT - Status Register +
+   + 0x00000008: + +   + PWDKEY - Key Register for Powering Down the Voltage Comparator +
+   + 0x00000200: + +   + INTEN - Voltage Comparator Interrupt registers: Enable +
+   + 0x00000204: + +   + INTSTAT - Voltage Comparator Interrupt registers: Status +
+   + 0x00000208: + +   + INTCLR - Voltage Comparator Interrupt registers: Clear +
+   + 0x0000020C: + +   + INTSET - Voltage Comparator Interrupt registers: Set +
+
+
+ +
+
+

CFG - Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C000 +
+

Description:

+

The Voltage Comparator Configuration Register contains the software control for selecting beween the 4 options for the positive input as well as the multiple options for the reference input.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		LVLSEL +
0x0		RSVD +
0x0		NSEL +
0x0		RSVD +
0x0		PSEL +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:20RSVDROThis bitfield is reserved for future use.

+
19:16LVLSELRWWhen the reference input NSEL is set to NSEL_DAC, this bitfield selects the voltage level for the negative input to the comparator.

+ 0P58V = 0x0 - Set Reference input to 0.58 Volts.
+ 0P77V = 0x1 - Set Reference input to 0.77 Volts.
+ 0P97V = 0x2 - Set Reference input to 0.97 Volts.
+ 1P16V = 0x3 - Set Reference input to 1.16 Volts.
+ 1P35V = 0x4 - Set Reference input to 1.35 Volts.
+ 1P55V = 0x5 - Set Reference input to 1.55 Volts.
+ 1P74V = 0x6 - Set Reference input to 1.74 Volts.
+ 1P93V = 0x7 - Set Reference input to 1.93 Volts.
+ 2P13V = 0x8 - Set Reference input to 2.13 Volts.
+ 2P32V = 0x9 - Set Reference input to 2.32 Volts.
+ 2P51V = 0xA - Set Reference input to 2.51 Volts.
+ 2P71V = 0xB - Set Reference input to 2.71 Volts.
+ 2P90V = 0xC - Set Reference input to 2.90 Volts.
+ 3P09V = 0xD - Set Reference input to 3.09 Volts.
+ 3P29V = 0xE - Set Reference input to 3.29 Volts.
+ 3P48V = 0xF - Set Reference input to 3.48 Volts.
15:10RSVDROThis bitfield is reserved for future use.

+
9:8NSELRWThis bitfield selects the negative input to the comparator.

+ VREFEXT1 = 0x0 - Use external reference 1 for reference input.
+ VREFEXT2 = 0x1 - Use external reference 2 for reference input.
+ VREFEXT3 = 0x2 - Use external reference 3 for reference input.
+ DAC = 0x3 - Use DAC output selected by LVLSEL for reference input.
7:2RSVDROThis bitfield is reserved for future use.

+
1:0PSELRWThis bitfield selects the positive input to the comparator.

+ VDDADJ = 0x0 - Use VDDADJ for the positive input.
+ VTEMP = 0x1 - Use the temperature sensor output for the positive input. Note: If this channel is selected for PSEL, the bandap circuit required for temperature comparisons will automatically turn on. The bandgap circuit requires 11us to stabalize.
+ VEXT1 = 0x2 - Use external voltage 0 for positive input.
+ VEXT2 = 0x3 - Use external voltage 1 for positive input.
+
+
+
+ +
+
+

STAT - Status Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C004 +
+

Description:

+

Status Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		PWDSTAT +
0x0		CMPOUT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDROThis bitfield is reserved for future use.

+
1PWDSTATROThis bit indicates the power down state of the voltage comparator.

+ POWERED_DOWN = 0x1 - The voltage comparator is powered down.
0CMPOUTROThis bit is 1 if the positive input of the comparator is greater than the negative input.

+ VOUT_LOW = 0x0 - The negative input of the comparator is greater than the positive input.
+ VOUT_HIGH = 0x1 - The positive input of the comparator is greater than the negative input.
+
+
+
+ +
+
+

PWDKEY - Key Register for Powering Down the Voltage Comparator

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C008 +
+

Description:

+

Key Register for Powering Down the Voltage Comparator

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
PWDKEY +
0x0
+
+ + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:0PWDKEYRWKey register value.

+ Key = 0x37 - Key
+
+
+
+ +
+
+

INTEN - Voltage Comparator Interrupt registers: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OUTHI +
0x0		OUTLOW +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDROThis bitfield is reserved for future use.

+
1OUTHIRWThis bit is the vcompout high interrupt.

+
0OUTLOWRWThis bit is the vcompout low interrupt.

+
+
+
+
+ +
+
+

INTSTAT - Voltage Comparator Interrupt registers: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OUTHI +
0x0		OUTLOW +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDROThis bitfield is reserved for future use.

+
1OUTHIRWThis bit is the vcompout high interrupt.

+
0OUTLOWRWThis bit is the vcompout low interrupt.

+
+
+
+
+ +
+
+

INTCLR - Voltage Comparator Interrupt registers: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OUTHI +
0x0		OUTLOW +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDROThis bitfield is reserved for future use.

+
1OUTHIRWThis bit is the vcompout high interrupt.

+
0OUTLOWRWThis bit is the vcompout low interrupt.

+
+
+
+
+ +
+
+

INTSET - Voltage Comparator Interrupt registers: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4000C20C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		OUTHI +
0x0		OUTLOW +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:2RSVDROThis bitfield is reserved for future use.

+
1OUTHIRWThis bit is the vcompout high interrupt.

+
0OUTLOWRWThis bit is the vcompout low interrupt.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/pages/wdt_regs.html b/docs/apollo2/pages/wdt_regs.html new file mode 100644 index 0000000..7427e6b --- /dev/null +++ b/docs/apollo2/pages/wdt_regs.html @@ -0,0 +1,1228 @@ + + + + + + + + AmbiqSuite User Guide: AmbiqSuite Apollo Device Register Overview + + + + + + + + + +
+ +
+ + + + + + + +
+
Apollo Register Documentation  v${version}
+
+
+ + + + +
+ + + +
+
+
WDT - Watchdog Timer
+
+
+ + +
+
+
+

WDT Register Index

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+   + 0x00000000: + +   + CFG - Configuration Register +
+   + 0x00000004: + +   + RSTRT - Restart the watchdog timer +
+   + 0x00000008: + +   + LOCK - Locks the WDT +
+   + 0x0000000C: + +   + COUNT - Current Counter Value for WDT +
+   + 0x00000200: + +   + INTEN - WDT Interrupt register: Enable +
+   + 0x00000204: + +   + INTSTAT - WDT Interrupt register: Status +
+   + 0x00000208: + +   + INTCLR - WDT Interrupt register: Clear +
+   + 0x0000020C: + +   + INTSET - WDT Interrupt register: Set +
+
+
+ +
+
+

CFG - Configuration Register

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40024000 +
+

Description:

+

Configuration Register

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		CLKSEL +
0x0		INTVAL +
0xff		RESVAL +
0xff		RSVD +
0x0		RESEN +
0x0		INTEN +
0x0		WDTEN +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:27RSVDROThis bitfield is reserved for future use.

+
26:24CLKSELRWSelect the frequency for the WDT. All values not enumerated below are undefined.

+ OFF = 0x0 - Low Power Mode.
+ 128HZ = 0x1 - 128 Hz LFRC clock.
+ 16HZ = 0x2 - 16 Hz LFRC clock.
+ 1HZ = 0x3 - 1 Hz LFRC clock.
+ 1_16HZ = 0x4 - 1/16th Hz LFRC clock.
23:16INTVALRWThis bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt.

+
15:8RESVALRWThis bitfield is the compare value for counter bits 7:0 to generate a watchdog reset.

+
7:3RSVDROThis bitfield is reserved for future use.

+
2RESENRWThis bitfield enables the WDT reset.

+
1INTENRWThis bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC.

+
0WDTENRWThis bitfield enables the WDT.

+
+
+
+
+ +
+
+

RSTRT - Restart the watchdog timer

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40024004 +
+

Description:

+

Restart the watchdog timer

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		RSTRT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDROThis bitfield is reserved for future use.

+
7:0RSTRTWOWriting 0xB2 to WDTRSTRT restarts the watchdog timer.

+ KEYVALUE = 0xB2 - This is the key value to write to WDTRSTRT to restart the WDT.
+
+
+
+ +
+
+

LOCK - Locks the WDT

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40024008 +
+

Description:

+

Locks the WDT

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		LOCK +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDROThis bitfield is reserved for future use.

+
7:0LOCKWOWriting 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set.

+ KEYVALUE = 0x3A - This is the key value to write to WDTLOCK to lock the WDT.
+
+
+
+ +
+
+

COUNT - Current Counter Value for WDT

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4002400C +
+

Description:

+

Current Counter Value for WDT

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		COUNT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:8RSVDROThis bitfield is reserved for future use.

+
7:0COUNTRORead-Only current value of the WDT counter

+
+
+
+
+ +
+
+

INTEN - WDT Interrupt register: Enable

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40024200 +
+

Description:

+

Set bits in this register to allow this module to generate the corresponding interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WDTINT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDROThis bitfield is reserved for future use.

+
0WDTINTRWWatchdog Timer Interrupt.

+
+
+
+
+ +
+
+

INTSTAT - WDT Interrupt register: Status

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40024204 +
+

Description:

+

Read bits from this register to discover the cause of a recent interrupt.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WDTINT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDROThis bitfield is reserved for future use.

+
0WDTINTRWWatchdog Timer Interrupt.

+
+
+
+
+ +
+
+

INTCLR - WDT Interrupt register: Clear

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x40024208 +
+

Description:

+

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WDTINT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDROThis bitfield is reserved for future use.

+
0WDTINTRWWatchdog Timer Interrupt.

+
+
+
+
+ +
+
+

INTSET - WDT Interrupt register: Set

+
+
+

Address:

+ + + + + + +
+   + Instance 0 Address: + +   + 0x4002420C +
+

Description:

+

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

+

Example Macro Usage:

+ 
//
+// All macro-based register writes follow the same basic format. For
+// single-instance modules, you may use the simpler AM_REG macro. For
+// multi-instance macros, you will need to specify the instance number using
+// the AM_REGn macro format.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
+//
+// For registers that do not have specific enumeration values, you may use this alternate format instead.
+//
+// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
+//
+// For example, the following three lines of code are equivalent methods of
+// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
+//
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
+AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);
+

Register Fields:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210
RSVD +
0x0		WDTINT +
0x0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsNameRWDescription
31:1RSVDROThis bitfield is reserved for future use.

+
0WDTINTRWWatchdog Timer Interrupt.

+
+
+
+
+ + + +
+ + + + + diff --git a/docs/apollo2/resources/am_logo.png b/docs/apollo2/resources/am_logo.png new file mode 100644 index 0000000..64cdd22 Binary files /dev/null and b/docs/apollo2/resources/am_logo.png differ diff --git a/docs/apollo2/resources/ambiqmicro_logo.png b/docs/apollo2/resources/ambiqmicro_logo.png new file mode 100644 index 0000000..7bdf262 Binary files /dev/null and b/docs/apollo2/resources/ambiqmicro_logo.png differ diff --git a/docs/apollo2/resources/bootstrap.css b/docs/apollo2/resources/bootstrap.css new file mode 100644 index 0000000..892bea8 --- /dev/null +++ b/docs/apollo2/resources/bootstrap.css @@ -0,0 +1,6180 @@ +/*! + * Bootstrap v3.2.0 (http://getbootstrap.com) + * Copyright 2011-2014 Twitter, Inc. + * Licensed under MIT (https://github.com/twbs/bootstrap/blob/master/LICENSE) + */ + +/*! + * Generated using the Bootstrap Customizer (http://getbootstrap.com/customize/?id=fd189dcc77ecaabcdca5) + * Config saved to config.json and https://gist.github.com/fd189dcc77ecaabcdca5 + */ +/*! normalize.css v3.0.1 | MIT License | git.io/normalize */ +html { + font-family: sans-serif; + -ms-text-size-adjust: 100%; + -webkit-text-size-adjust: 100%; +} +body { + margin: 0; +} +article, +aside, +details, +figcaption, +figure, +footer, +header, +hgroup, +main, +nav, +section, +summary { + display: block; +} +audio, +canvas, +progress, +video { + display: inline-block; + vertical-align: baseline; +} +audio:not([controls]) { + display: none; + height: 0; +} +[hidden], +template { + display: none; +} +a { + background: transparent; +} +a:active, +a:hover { + outline: 0; +} +abbr[title] { + border-bottom: 1px dotted; +} +b, +strong { + font-weight: bold; +} +dfn { + font-style: italic; +} +h1 { + font-size: 2em; + margin: 0.67em 0; +} +mark { + background: #ff0; + color: #000; +} +small { + font-size: 80%; +} +sub, +sup { + font-size: 75%; + line-height: 0; + position: relative; + vertical-align: baseline; +} +sup { + top: -0.5em; +} +sub { + bottom: -0.25em; +} +img { + border: 0; +} +svg:not(:root) { + overflow: hidden; +} +figure { + margin: 1em 40px; +} +hr { + -moz-box-sizing: content-box; + box-sizing: content-box; + height: 0; +} +pre { + overflow: auto; +} +code, +kbd, +pre, +samp { + font-family: monospace, monospace; + font-size: 1em; +} +button, +input, +optgroup, +select, +textarea { + color: inherit; + font: inherit; + margin: 0; +} +button { + overflow: visible; +} +button, +select { + text-transform: none; +} +button, +html input[type="button"], +input[type="reset"], +input[type="submit"] { + -webkit-appearance: button; + cursor: pointer; +} +button[disabled], +html input[disabled] { + cursor: default; +} +button::-moz-focus-inner, +input::-moz-focus-inner { + border: 0; + padding: 0; +} +input { + line-height: normal; +} +input[type="checkbox"], +input[type="radio"] { + box-sizing: border-box; + padding: 0; +} +input[type="number"]::-webkit-inner-spin-button, +input[type="number"]::-webkit-outer-spin-button { + height: auto; +} +input[type="search"] { + -webkit-appearance: textfield; + -moz-box-sizing: content-box; + -webkit-box-sizing: content-box; + box-sizing: content-box; +} +input[type="search"]::-webkit-search-cancel-button, +input[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; +} +fieldset { + border: 1px solid #c0c0c0; + margin: 0 2px; + padding: 0.35em 0.625em 0.75em; +} +legend { + border: 0; + padding: 0; +} +textarea { + overflow: auto; +} +optgroup { + font-weight: bold; +} +table { + border-collapse: collapse; + border-spacing: 0; +} +td, +th { + padding: 0; +} +@media print { + * { + text-shadow: none !important; + color: #000 !important; + background: transparent !important; + box-shadow: none !important; + } + a, + a:visited { + text-decoration: underline; + } + a[href]:after { + content: " (" attr(href) ")"; + } + abbr[title]:after { + content: " (" attr(title) ")"; + } + a[href^="javascript:"]:after, + a[href^="#"]:after { + content: ""; + } + pre, + blockquote { + border: 1px solid #999; + page-break-inside: avoid; + } + thead { + display: table-header-group; + } + tr, + img { + page-break-inside: avoid; + } + img { + max-width: 100% !important; + } + p, + h2, + h3 { + orphans: 3; + widows: 3; + } + h2, + h3 { + page-break-after: avoid; + } + select { + background: #fff !important; + } + .navbar { + display: none; + } + .table td, + .table th { + background-color: #fff !important; + } + .btn > .caret, + .dropup > .btn > .caret { + border-top-color: #000 !important; + } + .label { + border: 1px solid #000; + } + .table { + border-collapse: collapse !important; + } + .table-bordered th, + .table-bordered td { + border: 1px solid #ddd !important; + } +} +@font-face { + font-family: 'Glyphicons Halflings'; + src: url('../fonts/glyphicons-halflings-regular.eot'); + src: url('../fonts/glyphicons-halflings-regular.eot?#iefix') format('embedded-opentype'), url('../fonts/glyphicons-halflings-regular.woff') format('woff'), url('../fonts/glyphicons-halflings-regular.ttf') format('truetype'), url('../fonts/glyphicons-halflings-regular.svg#glyphicons_halflingsregular') format('svg'); +} +.glyphicon { + position: relative; + top: 1px; + display: inline-block; + font-family: 'Glyphicons Halflings'; + font-style: normal; + font-weight: normal; + line-height: 1; + -webkit-font-smoothing: antialiased; + -moz-osx-font-smoothing: grayscale; +} +.glyphicon-asterisk:before { + content: "\2a"; +} +.glyphicon-plus:before { + content: "\2b"; +} +.glyphicon-euro:before { + content: "\20ac"; +} +.glyphicon-minus:before { + content: "\2212"; +} +.glyphicon-cloud:before { + content: "\2601"; +} +.glyphicon-envelope:before { + content: "\2709"; +} +.glyphicon-pencil:before { + content: "\270f"; +} +.glyphicon-glass:before { + content: "\e001"; +} +.glyphicon-music:before { + content: "\e002"; +} +.glyphicon-search:before { + content: "\e003"; +} +.glyphicon-heart:before { + content: "\e005"; +} +.glyphicon-star:before { + content: "\e006"; +} +.glyphicon-star-empty:before { + content: "\e007"; +} +.glyphicon-user:before { + content: "\e008"; +} +.glyphicon-film:before { + content: "\e009"; +} +.glyphicon-th-large:before { + content: "\e010"; +} +.glyphicon-th:before { + content: "\e011"; +} +.glyphicon-th-list:before { + content: "\e012"; +} +.glyphicon-ok:before { + content: "\e013"; +} +.glyphicon-remove:before { + content: "\e014"; +} +.glyphicon-zoom-in:before { + content: "\e015"; +} +.glyphicon-zoom-out:before { + content: "\e016"; +} +.glyphicon-off:before { + content: "\e017"; +} +.glyphicon-signal:before { + content: "\e018"; +} +.glyphicon-cog:before { + content: "\e019"; +} +.glyphicon-trash:before { + content: "\e020"; +} +.glyphicon-home:before { + content: "\e021"; +} +.glyphicon-file:before { + content: "\e022"; +} +.glyphicon-time:before { + content: "\e023"; +} +.glyphicon-road:before { + content: "\e024"; +} +.glyphicon-download-alt:before { + content: "\e025"; +} +.glyphicon-download:before { + content: "\e026"; +} +.glyphicon-upload:before { + content: "\e027"; +} +.glyphicon-inbox:before { + content: "\e028"; +} +.glyphicon-play-circle:before { + content: "\e029"; +} +.glyphicon-repeat:before { + content: "\e030"; +} +.glyphicon-refresh:before { + content: "\e031"; +} +.glyphicon-list-alt:before { + content: "\e032"; +} +.glyphicon-lock:before { + content: "\e033"; +} +.glyphicon-flag:before { + content: "\e034"; +} +.glyphicon-headphones:before { + content: "\e035"; +} +.glyphicon-volume-off:before { + content: "\e036"; +} +.glyphicon-volume-down:before { + content: "\e037"; +} +.glyphicon-volume-up:before { + content: "\e038"; +} +.glyphicon-qrcode:before { + content: "\e039"; +} +.glyphicon-barcode:before { + content: "\e040"; +} +.glyphicon-tag:before { + content: "\e041"; +} +.glyphicon-tags:before { + content: "\e042"; +} +.glyphicon-book:before { + content: "\e043"; +} +.glyphicon-bookmark:before { + content: "\e044"; +} +.glyphicon-print:before { + content: "\e045"; +} +.glyphicon-camera:before { + content: "\e046"; +} +.glyphicon-font:before { + content: "\e047"; +} +.glyphicon-bold:before { + content: "\e048"; +} +.glyphicon-italic:before { + content: "\e049"; +} +.glyphicon-text-height:before { + content: "\e050"; +} +.glyphicon-text-width:before { + content: "\e051"; +} +.glyphicon-align-left:before { + content: "\e052"; +} +.glyphicon-align-center:before { + content: "\e053"; +} +.glyphicon-align-right:before { + content: "\e054"; +} +.glyphicon-align-justify:before { + content: "\e055"; +} +.glyphicon-list:before { + content: "\e056"; +} +.glyphicon-indent-left:before { + content: "\e057"; +} +.glyphicon-indent-right:before { + content: "\e058"; +} +.glyphicon-facetime-video:before { + content: "\e059"; +} +.glyphicon-picture:before { + content: "\e060"; +} +.glyphicon-map-marker:before { + content: "\e062"; +} +.glyphicon-adjust:before { + content: "\e063"; +} +.glyphicon-tint:before { + content: "\e064"; +} +.glyphicon-edit:before { + content: "\e065"; +} +.glyphicon-share:before { + content: "\e066"; +} +.glyphicon-check:before { + content: "\e067"; +} +.glyphicon-move:before { + content: "\e068"; +} +.glyphicon-step-backward:before { + content: "\e069"; +} +.glyphicon-fast-backward:before { + content: "\e070"; +} +.glyphicon-backward:before { + content: "\e071"; +} +.glyphicon-play:before { + content: "\e072"; +} +.glyphicon-pause:before { + content: "\e073"; +} +.glyphicon-stop:before { + content: "\e074"; +} +.glyphicon-forward:before { + content: "\e075"; +} +.glyphicon-fast-forward:before { + content: "\e076"; +} +.glyphicon-step-forward:before { + content: "\e077"; +} +.glyphicon-eject:before { + content: "\e078"; +} +.glyphicon-chevron-left:before { + content: "\e079"; +} +.glyphicon-chevron-right:before { + content: "\e080"; +} +.glyphicon-plus-sign:before { + content: "\e081"; +} +.glyphicon-minus-sign:before { + content: "\e082"; +} +.glyphicon-remove-sign:before { + content: "\e083"; +} +.glyphicon-ok-sign:before { + content: "\e084"; +} +.glyphicon-question-sign:before { + content: "\e085"; +} +.glyphicon-info-sign:before { + content: "\e086"; +} +.glyphicon-screenshot:before { + content: "\e087"; +} +.glyphicon-remove-circle:before { + content: "\e088"; +} +.glyphicon-ok-circle:before { + content: "\e089"; +} +.glyphicon-ban-circle:before { + content: "\e090"; +} +.glyphicon-arrow-left:before { + content: "\e091"; +} +.glyphicon-arrow-right:before { + content: "\e092"; +} +.glyphicon-arrow-up:before { + content: "\e093"; +} +.glyphicon-arrow-down:before { + content: "\e094"; +} +.glyphicon-share-alt:before { + content: "\e095"; +} +.glyphicon-resize-full:before { + content: "\e096"; +} +.glyphicon-resize-small:before { + content: "\e097"; +} +.glyphicon-exclamation-sign:before { + content: "\e101"; +} +.glyphicon-gift:before { + content: "\e102"; +} +.glyphicon-leaf:before { + content: "\e103"; +} +.glyphicon-fire:before { + content: "\e104"; +} +.glyphicon-eye-open:before { + content: "\e105"; +} +.glyphicon-eye-close:before { + content: "\e106"; +} +.glyphicon-warning-sign:before { + content: "\e107"; +} +.glyphicon-plane:before { + content: "\e108"; +} +.glyphicon-calendar:before { + content: "\e109"; +} +.glyphicon-random:before { + content: "\e110"; +} +.glyphicon-comment:before { + content: "\e111"; +} +.glyphicon-magnet:before { + content: "\e112"; +} +.glyphicon-chevron-up:before { + content: "\e113"; +} +.glyphicon-chevron-down:before { + content: "\e114"; +} +.glyphicon-retweet:before { + content: "\e115"; +} +.glyphicon-shopping-cart:before { + content: "\e116"; +} +.glyphicon-folder-close:before { + content: "\e117"; +} +.glyphicon-folder-open:before { + content: "\e118"; +} +.glyphicon-resize-vertical:before { + content: "\e119"; +} +.glyphicon-resize-horizontal:before { + content: "\e120"; +} +.glyphicon-hdd:before { + content: "\e121"; +} +.glyphicon-bullhorn:before { + content: "\e122"; +} +.glyphicon-bell:before { + content: "\e123"; +} +.glyphicon-certificate:before { + content: "\e124"; +} +.glyphicon-thumbs-up:before { + content: "\e125"; +} +.glyphicon-thumbs-down:before { + content: "\e126"; +} +.glyphicon-hand-right:before { + content: "\e127"; +} +.glyphicon-hand-left:before { + content: "\e128"; +} +.glyphicon-hand-up:before { + content: "\e129"; +} +.glyphicon-hand-down:before { + content: "\e130"; +} +.glyphicon-circle-arrow-right:before { + content: "\e131"; +} +.glyphicon-circle-arrow-left:before { + content: "\e132"; +} +.glyphicon-circle-arrow-up:before { + content: "\e133"; +} +.glyphicon-circle-arrow-down:before { + content: "\e134"; +} +.glyphicon-globe:before { + content: "\e135"; +} +.glyphicon-wrench:before { + content: "\e136"; +} +.glyphicon-tasks:before { + content: "\e137"; +} +.glyphicon-filter:before { + content: "\e138"; +} +.glyphicon-briefcase:before { + content: "\e139"; +} +.glyphicon-fullscreen:before { + content: "\e140"; +} +.glyphicon-dashboard:before { + content: "\e141"; +} +.glyphicon-paperclip:before { + content: "\e142"; +} +.glyphicon-heart-empty:before { + content: "\e143"; +} +.glyphicon-link:before { + content: "\e144"; +} +.glyphicon-phone:before { + content: "\e145"; +} +.glyphicon-pushpin:before { + content: "\e146"; +} +.glyphicon-usd:before { + content: "\e148"; +} +.glyphicon-gbp:before { + content: "\e149"; +} +.glyphicon-sort:before { + content: "\e150"; +} +.glyphicon-sort-by-alphabet:before { + content: "\e151"; +} +.glyphicon-sort-by-alphabet-alt:before { + content: "\e152"; +} +.glyphicon-sort-by-order:before { + content: "\e153"; +} +.glyphicon-sort-by-order-alt:before { + content: "\e154"; +} +.glyphicon-sort-by-attributes:before { + content: "\e155"; +} +.glyphicon-sort-by-attributes-alt:before { + content: "\e156"; +} +.glyphicon-unchecked:before { + content: "\e157"; +} +.glyphicon-expand:before { + content: "\e158"; +} +.glyphicon-collapse-down:before { + content: "\e159"; +} +.glyphicon-collapse-up:before { + content: "\e160"; +} +.glyphicon-log-in:before { + content: "\e161"; +} +.glyphicon-flash:before { + content: "\e162"; +} +.glyphicon-log-out:before { + content: "\e163"; +} +.glyphicon-new-window:before { + content: "\e164"; +} +.glyphicon-record:before { + content: "\e165"; +} +.glyphicon-save:before { + content: "\e166"; +} +.glyphicon-open:before { + content: "\e167"; +} +.glyphicon-saved:before { + content: "\e168"; +} +.glyphicon-import:before { + content: "\e169"; +} +.glyphicon-export:before { + content: "\e170"; +} +.glyphicon-send:before { + content: "\e171"; +} +.glyphicon-floppy-disk:before { + content: "\e172"; +} +.glyphicon-floppy-saved:before { + content: "\e173"; +} +.glyphicon-floppy-remove:before { + content: "\e174"; +} +.glyphicon-floppy-save:before { + content: "\e175"; +} +.glyphicon-floppy-open:before { + content: "\e176"; +} +.glyphicon-credit-card:before { + content: "\e177"; +} +.glyphicon-transfer:before { + content: "\e178"; +} +.glyphicon-cutlery:before { + content: "\e179"; +} +.glyphicon-header:before { + content: "\e180"; +} +.glyphicon-compressed:before { + content: "\e181"; +} +.glyphicon-earphone:before { + content: "\e182"; +} +.glyphicon-phone-alt:before { + content: "\e183"; +} +.glyphicon-tower:before { + content: "\e184"; +} +.glyphicon-stats:before { + content: "\e185"; +} +.glyphicon-sd-video:before { + content: "\e186"; +} +.glyphicon-hd-video:before { + content: "\e187"; +} +.glyphicon-subtitles:before { + content: "\e188"; +} +.glyphicon-sound-stereo:before { + content: "\e189"; +} +.glyphicon-sound-dolby:before { + content: "\e190"; +} +.glyphicon-sound-5-1:before { + content: "\e191"; +} +.glyphicon-sound-6-1:before { + content: "\e192"; +} +.glyphicon-sound-7-1:before { + content: "\e193"; +} +.glyphicon-copyright-mark:before { + content: "\e194"; +} +.glyphicon-registration-mark:before { + content: "\e195"; +} +.glyphicon-cloud-download:before { + content: "\e197"; +} +.glyphicon-cloud-upload:before { + content: "\e198"; +} +.glyphicon-tree-conifer:before { + content: "\e199"; +} +.glyphicon-tree-deciduous:before { + content: "\e200"; +} +* { + -webkit-box-sizing: border-box; + -moz-box-sizing: border-box; + box-sizing: border-box; +} +*:before, +*:after { + -webkit-box-sizing: border-box; + -moz-box-sizing: border-box; + box-sizing: border-box; +} +html { + font-size: 10px; + -webkit-tap-highlight-color: rgba(0, 0, 0, 0); +} +body { + font-family: "Helvetica Neue", Helvetica, Arial, sans-serif; + font-size: 14px; + line-height: 1.42857143; + color: #333333; + background-color: #ffffff; +} +input, +button, +select, +textarea { + font-family: inherit; + font-size: inherit; + line-height: inherit; +} +a { + color: #0079c2; + text-decoration: none; +} +a:hover, +a:focus { + color: #004976; + text-decoration: underline; +} +a:focus { + outline: thin dotted; + outline: 5px auto -webkit-focus-ring-color; + outline-offset: -2px; +} +figure { + margin: 0; +} +img { + vertical-align: middle; +} +.img-responsive, +.thumbnail > img, +.thumbnail a > img, +.carousel-inner > .item > img, +.carousel-inner > .item > a > img { + display: block; + width: 100% \9; + max-width: 100%; + height: auto; +} +.img-rounded { + border-radius: 6px; +} +.img-thumbnail { + padding: 4px; + line-height: 1.42857143; + background-color: #ffffff; + border: 1px solid #dddddd; + border-radius: 4px; + -webkit-transition: all 0.2s ease-in-out; + -o-transition: all 0.2s ease-in-out; + transition: all 0.2s ease-in-out; + display: inline-block; + width: 100% \9; + max-width: 100%; + height: auto; +} +.img-circle { + border-radius: 50%; +} +hr { + margin-top: 20px; + margin-bottom: 20px; + border: 0; + border-top: 1px solid #eeeeee; +} +.sr-only { + position: absolute; + width: 1px; + height: 1px; + margin: -1px; + padding: 0; + overflow: hidden; + clip: rect(0, 0, 0, 0); + border: 0; +} +.sr-only-focusable:active, +.sr-only-focusable:focus { + position: static; + width: auto; + height: auto; + margin: 0; + overflow: visible; + clip: auto; +} +h1, +h2, +h3, +h4, +h5, +h6, +.h1, +.h2, +.h3, +.h4, +.h5, +.h6 { + font-family: inherit; + font-weight: 500; + line-height: 1.1; + color: inherit; +} +h1 small, +h2 small, +h3 small, +h4 small, +h5 small, +h6 small, +.h1 small, +.h2 small, +.h3 small, +.h4 small, +.h5 small, +.h6 small, +h1 .small, +h2 .small, +h3 .small, +h4 .small, +h5 .small, +h6 .small, +.h1 .small, +.h2 .small, +.h3 .small, +.h4 .small, +.h5 .small, +.h6 .small { + font-weight: normal; + line-height: 1; + color: #777777; +} +h1, +.h1, +h2, +.h2, +h3, +.h3 { + margin-top: 20px; + margin-bottom: 10px; +} +h1 small, +.h1 small, +h2 small, +.h2 small, +h3 small, +.h3 small, +h1 .small, +.h1 .small, +h2 .small, +.h2 .small, +h3 .small, +.h3 .small { + font-size: 65%; +} +h4, +.h4, +h5, +.h5, +h6, +.h6 { + margin-top: 10px; + margin-bottom: 10px; +} +h4 small, +.h4 small, +h5 small, +.h5 small, +h6 small, +.h6 small, +h4 .small, +.h4 .small, +h5 .small, +.h5 .small, +h6 .small, +.h6 .small { + font-size: 75%; +} +h1, +.h1 { + font-size: 36px; +} +h2, +.h2 { + font-size: 30px; +} +h3, +.h3 { + font-size: 24px; +} +h4, +.h4 { + font-size: 18px; +} +h5, +.h5 { + font-size: 14px; +} +h6, +.h6 { + font-size: 12px; +} +p { + margin: 0 0 10px; +} +.lead { + margin-bottom: 20px; + font-size: 16px; + font-weight: 300; + line-height: 1.4; +} +@media (min-width: 768px) { + .lead { + font-size: 21px; + } +} +small, +.small { + font-size: 85%; +} +cite { + font-style: normal; +} +mark, +.mark { + background-color: #fcf8e3; + padding: .2em; +} +.text-left { + text-align: left; +} +.text-right { + text-align: right; +} +.text-center { + text-align: center; +} +.text-justify { + text-align: justify; +} +.text-nowrap { + white-space: nowrap; +} +.text-lowercase { + text-transform: lowercase; +} +.text-uppercase { + text-transform: uppercase; +} +.text-capitalize { + text-transform: capitalize; +} +.text-muted { + color: #777777; +} +.text-primary { + color: #0079c2; +} +a.text-primary:hover { + color: #00598f; +} +.text-success { + color: #3c763d; +} +a.text-success:hover { + color: #2b542c; +} +.text-info { + color: #31708f; +} +a.text-info:hover { + color: #245269; +} +.text-warning { + color: #8a6d3b; +} +a.text-warning:hover { + color: #66512c; +} +.text-danger { + color: #a94442; +} +a.text-danger:hover { + color: #843534; +} +.bg-primary { + color: #fff; + background-color: #0079c2; +} +a.bg-primary:hover { + background-color: #00598f; +} +.bg-success { + background-color: #dff0d8; +} +a.bg-success:hover { + background-color: #c1e2b3; +} +.bg-info { + background-color: #d9edf7; +} +a.bg-info:hover { + background-color: #afd9ee; +} +.bg-warning { + background-color: #fcf8e3; +} +a.bg-warning:hover { + background-color: #f7ecb5; +} +.bg-danger { + background-color: #f2dede; +} +a.bg-danger:hover { + background-color: #e4b9b9; +} +.page-header { + padding-bottom: 9px; + margin: 40px 0 20px; + border-bottom: 1px solid #eeeeee; +} +ul, +ol { + margin-top: 0; + margin-bottom: 10px; +} +ul ul, +ol ul, +ul ol, +ol ol { + margin-bottom: 0; +} +.list-unstyled { + padding-left: 0; + list-style: none; +} +.list-inline { + padding-left: 0; + list-style: none; + margin-left: -5px; +} +.list-inline > li { + display: inline-block; + padding-left: 5px; + padding-right: 5px; +} +dl { + margin-top: 0; + margin-bottom: 20px; +} +dt, +dd { + line-height: 1.42857143; +} +dt { + font-weight: bold; +} +dd { + margin-left: 0; +} +@media (min-width: 768px) { + .dl-horizontal dt { + float: left; + width: 160px; + clear: left; + text-align: right; + overflow: hidden; + text-overflow: ellipsis; + white-space: nowrap; + } + .dl-horizontal dd { + margin-left: 180px; + } +} +abbr[title], +abbr[data-original-title] { + cursor: help; + border-bottom: 1px dotted #777777; +} +.initialism { + font-size: 90%; + text-transform: uppercase; +} +blockquote { + padding: 10px 20px; + margin: 0 0 20px; + font-size: 17.5px; + border-left: 5px solid #eeeeee; +} +blockquote p:last-child, +blockquote ul:last-child, +blockquote ol:last-child { + margin-bottom: 0; +} +blockquote footer, +blockquote small, +blockquote .small { + display: block; + font-size: 80%; + line-height: 1.42857143; + color: #777777; +} +blockquote footer:before, +blockquote small:before, +blockquote .small:before { + content: '\2014 \00A0'; +} +.blockquote-reverse, +blockquote.pull-right { + padding-right: 15px; + padding-left: 0; + border-right: 5px solid #eeeeee; + border-left: 0; + text-align: right; +} +.blockquote-reverse footer:before, +blockquote.pull-right footer:before, +.blockquote-reverse small:before, +blockquote.pull-right small:before, +.blockquote-reverse .small:before, +blockquote.pull-right .small:before { + content: ''; +} +.blockquote-reverse footer:after, +blockquote.pull-right footer:after, +.blockquote-reverse small:after, +blockquote.pull-right small:after, +.blockquote-reverse .small:after, +blockquote.pull-right .small:after { + content: '\00A0 \2014'; +} +blockquote:before, +blockquote:after { + content: ""; +} +address { + margin-bottom: 20px; + font-style: normal; + line-height: 1.42857143; +} +code, +kbd, +pre, +samp { + font-family: Menlo, Monaco, Consolas, "Courier New", monospace; +} +code { + padding: 2px 4px; + font-size: 90%; + color: #c7254e; + background-color: #f9f2f4; + border-radius: 4px; +} +kbd { + padding: 2px 4px; + font-size: 90%; + color: #ffffff; + background-color: #333333; + border-radius: 3px; + box-shadow: inset 0 -1px 0 rgba(0, 0, 0, 0.25); +} +kbd kbd { + padding: 0; + font-size: 100%; + box-shadow: none; +} +pre { + display: block; + padding: 9.5px; + margin: 0 0 10px; + font-size: 13px; + line-height: 1.42857143; + word-break: break-all; + word-wrap: break-word; + color: #333333; + background-color: #f5f5f5; + border: 1px solid #cccccc; + border-radius: 4px; +} +pre code { + padding: 0; + font-size: inherit; + color: inherit; + white-space: pre-wrap; + background-color: transparent; + border-radius: 0; +} +.pre-scrollable { + max-height: 340px; + overflow-y: scroll; +} +.container { + margin-right: auto; + margin-left: auto; + padding-left: 15px; + padding-right: 15px; +} +@media (min-width: 768px) { + .container { + width: 750px; + } +} +@media (min-width: 992px) { + .container { + width: 970px; + } +} +@media (min-width: 1200px) { + .container { + width: 1170px; + } +} +.container-fluid { + margin-right: auto; + margin-left: auto; + padding-left: 15px; + padding-right: 15px; +} +.row { + margin-left: -15px; + margin-right: -15px; +} +.col-xs-1, .col-sm-1, .col-md-1, .col-lg-1, .col-xs-2, .col-sm-2, .col-md-2, .col-lg-2, .col-xs-3, .col-sm-3, .col-md-3, .col-lg-3, .col-xs-4, .col-sm-4, .col-md-4, .col-lg-4, .col-xs-5, .col-sm-5, .col-md-5, .col-lg-5, .col-xs-6, .col-sm-6, .col-md-6, .col-lg-6, .col-xs-7, .col-sm-7, .col-md-7, .col-lg-7, .col-xs-8, .col-sm-8, .col-md-8, .col-lg-8, .col-xs-9, .col-sm-9, .col-md-9, .col-lg-9, .col-xs-10, .col-sm-10, .col-md-10, .col-lg-10, .col-xs-11, .col-sm-11, .col-md-11, .col-lg-11, .col-xs-12, .col-sm-12, .col-md-12, .col-lg-12 { + position: relative; + min-height: 1px; + padding-left: 15px; + padding-right: 15px; +} +.col-xs-1, .col-xs-2, .col-xs-3, .col-xs-4, .col-xs-5, .col-xs-6, .col-xs-7, .col-xs-8, .col-xs-9, .col-xs-10, .col-xs-11, .col-xs-12 { + float: left; +} +.col-xs-12 { + width: 100%; +} +.col-xs-11 { + width: 91.66666667%; +} +.col-xs-10 { + width: 83.33333333%; +} +.col-xs-9 { + width: 75%; +} +.col-xs-8 { + width: 66.66666667%; +} +.col-xs-7 { + width: 58.33333333%; +} +.col-xs-6 { + width: 50%; +} +.col-xs-5 { + width: 41.66666667%; +} +.col-xs-4 { + width: 33.33333333%; +} +.col-xs-3 { + width: 25%; +} +.col-xs-2 { + width: 16.66666667%; +} +.col-xs-1 { + width: 8.33333333%; +} +.col-xs-pull-12 { + right: 100%; +} +.col-xs-pull-11 { + right: 91.66666667%; +} +.col-xs-pull-10 { + right: 83.33333333%; +} +.col-xs-pull-9 { + right: 75%; +} +.col-xs-pull-8 { + right: 66.66666667%; +} +.col-xs-pull-7 { + right: 58.33333333%; +} +.col-xs-pull-6 { + right: 50%; +} +.col-xs-pull-5 { + right: 41.66666667%; +} +.col-xs-pull-4 { + right: 33.33333333%; +} +.col-xs-pull-3 { + right: 25%; +} +.col-xs-pull-2 { + right: 16.66666667%; +} +.col-xs-pull-1 { + right: 8.33333333%; +} +.col-xs-pull-0 { + right: auto; +} +.col-xs-push-12 { + left: 100%; +} +.col-xs-push-11 { + left: 91.66666667%; +} +.col-xs-push-10 { + left: 83.33333333%; +} +.col-xs-push-9 { + left: 75%; +} +.col-xs-push-8 { + left: 66.66666667%; +} +.col-xs-push-7 { + left: 58.33333333%; +} +.col-xs-push-6 { + left: 50%; +} +.col-xs-push-5 { + left: 41.66666667%; +} +.col-xs-push-4 { + left: 33.33333333%; +} +.col-xs-push-3 { + left: 25%; +} +.col-xs-push-2 { + left: 16.66666667%; +} +.col-xs-push-1 { + left: 8.33333333%; +} +.col-xs-push-0 { + left: auto; +} +.col-xs-offset-12 { + margin-left: 100%; +} +.col-xs-offset-11 { + margin-left: 91.66666667%; +} +.col-xs-offset-10 { + margin-left: 83.33333333%; +} +.col-xs-offset-9 { + margin-left: 75%; +} +.col-xs-offset-8 { + margin-left: 66.66666667%; +} +.col-xs-offset-7 { + margin-left: 58.33333333%; +} +.col-xs-offset-6 { + margin-left: 50%; +} +.col-xs-offset-5 { + margin-left: 41.66666667%; +} +.col-xs-offset-4 { + margin-left: 33.33333333%; +} +.col-xs-offset-3 { + margin-left: 25%; +} +.col-xs-offset-2 { + margin-left: 16.66666667%; +} +.col-xs-offset-1 { + margin-left: 8.33333333%; +} +.col-xs-offset-0 { + margin-left: 0%; +} +@media (min-width: 768px) { + .col-sm-1, .col-sm-2, .col-sm-3, .col-sm-4, .col-sm-5, .col-sm-6, .col-sm-7, .col-sm-8, .col-sm-9, .col-sm-10, .col-sm-11, .col-sm-12 { + float: left; + } + .col-sm-12 { + width: 100%; + } + .col-sm-11 { + width: 91.66666667%; + } + .col-sm-10 { + width: 83.33333333%; + } + .col-sm-9 { + width: 75%; + } + .col-sm-8 { + width: 66.66666667%; + } + .col-sm-7 { + width: 58.33333333%; + } + .col-sm-6 { + width: 50%; + } + .col-sm-5 { + width: 41.66666667%; + } + .col-sm-4 { + width: 33.33333333%; + } + .col-sm-3 { + width: 25%; + } + .col-sm-2 { + width: 16.66666667%; + } + .col-sm-1 { + width: 8.33333333%; + } + .col-sm-pull-12 { + right: 100%; + } + .col-sm-pull-11 { + right: 91.66666667%; + } + .col-sm-pull-10 { + right: 83.33333333%; + } + .col-sm-pull-9 { + right: 75%; + } + .col-sm-pull-8 { + right: 66.66666667%; + } + .col-sm-pull-7 { + right: 58.33333333%; + } + .col-sm-pull-6 { + right: 50%; + } + .col-sm-pull-5 { + right: 41.66666667%; + } + .col-sm-pull-4 { + right: 33.33333333%; + } + .col-sm-pull-3 { + right: 25%; + } + .col-sm-pull-2 { + right: 16.66666667%; + } + .col-sm-pull-1 { + right: 8.33333333%; + } + .col-sm-pull-0 { + right: auto; + } + .col-sm-push-12 { + left: 100%; + } + .col-sm-push-11 { + left: 91.66666667%; + } + .col-sm-push-10 { + left: 83.33333333%; + } + .col-sm-push-9 { + left: 75%; + } + .col-sm-push-8 { + left: 66.66666667%; + } + .col-sm-push-7 { + left: 58.33333333%; + } + .col-sm-push-6 { + left: 50%; + } + .col-sm-push-5 { + left: 41.66666667%; + } + .col-sm-push-4 { + left: 33.33333333%; + } + .col-sm-push-3 { + left: 25%; + } + .col-sm-push-2 { + left: 16.66666667%; + } + .col-sm-push-1 { + left: 8.33333333%; + } + .col-sm-push-0 { + left: auto; + } + .col-sm-offset-12 { + margin-left: 100%; + } + .col-sm-offset-11 { + margin-left: 91.66666667%; + } + .col-sm-offset-10 { + margin-left: 83.33333333%; + } + .col-sm-offset-9 { + margin-left: 75%; + } + .col-sm-offset-8 { + margin-left: 66.66666667%; + } + .col-sm-offset-7 { + margin-left: 58.33333333%; + } + .col-sm-offset-6 { + margin-left: 50%; + } + .col-sm-offset-5 { + margin-left: 41.66666667%; + } + .col-sm-offset-4 { + margin-left: 33.33333333%; + } + .col-sm-offset-3 { + margin-left: 25%; + } + .col-sm-offset-2 { + margin-left: 16.66666667%; + } + .col-sm-offset-1 { + margin-left: 8.33333333%; + } + .col-sm-offset-0 { + margin-left: 0%; + } +} +@media (min-width: 992px) { + .col-md-1, .col-md-2, .col-md-3, .col-md-4, .col-md-5, .col-md-6, .col-md-7, .col-md-8, .col-md-9, .col-md-10, .col-md-11, .col-md-12 { + float: left; + } + .col-md-12 { + width: 100%; + } + .col-md-11 { + width: 91.66666667%; + } + .col-md-10 { + width: 83.33333333%; + } + .col-md-9 { + width: 75%; + } + .col-md-8 { + width: 66.66666667%; + } + .col-md-7 { + width: 58.33333333%; + } + .col-md-6 { + width: 50%; + } + .col-md-5 { + width: 41.66666667%; + } + .col-md-4 { + width: 33.33333333%; + } + .col-md-3 { + width: 25%; + } + .col-md-2 { + width: 16.66666667%; + } + .col-md-1 { + width: 8.33333333%; + } + .col-md-pull-12 { + right: 100%; + } + .col-md-pull-11 { + right: 91.66666667%; + } + .col-md-pull-10 { + right: 83.33333333%; + } + .col-md-pull-9 { + right: 75%; + } + .col-md-pull-8 { + right: 66.66666667%; + } + .col-md-pull-7 { + right: 58.33333333%; + } + .col-md-pull-6 { + right: 50%; + } + .col-md-pull-5 { + right: 41.66666667%; + } + .col-md-pull-4 { + right: 33.33333333%; + } + .col-md-pull-3 { + right: 25%; + } + .col-md-pull-2 { + right: 16.66666667%; + } + .col-md-pull-1 { + right: 8.33333333%; + } + .col-md-pull-0 { + right: auto; + } + .col-md-push-12 { + left: 100%; + } + .col-md-push-11 { + left: 91.66666667%; + } + .col-md-push-10 { + left: 83.33333333%; + } + .col-md-push-9 { + left: 75%; + } + .col-md-push-8 { + left: 66.66666667%; + } + .col-md-push-7 { + left: 58.33333333%; + } + .col-md-push-6 { + left: 50%; + } + .col-md-push-5 { + left: 41.66666667%; + } + .col-md-push-4 { + left: 33.33333333%; + } + .col-md-push-3 { + left: 25%; + } + .col-md-push-2 { + left: 16.66666667%; + } + .col-md-push-1 { + left: 8.33333333%; + } + .col-md-push-0 { + left: auto; + } + .col-md-offset-12 { + margin-left: 100%; + } + .col-md-offset-11 { + margin-left: 91.66666667%; + } + .col-md-offset-10 { + margin-left: 83.33333333%; + } + .col-md-offset-9 { + margin-left: 75%; + } + .col-md-offset-8 { + margin-left: 66.66666667%; + } + .col-md-offset-7 { + margin-left: 58.33333333%; + } + .col-md-offset-6 { + margin-left: 50%; + } + .col-md-offset-5 { + margin-left: 41.66666667%; + } + .col-md-offset-4 { + margin-left: 33.33333333%; + } + .col-md-offset-3 { + margin-left: 25%; + } + .col-md-offset-2 { + margin-left: 16.66666667%; + } + .col-md-offset-1 { + margin-left: 8.33333333%; + } + .col-md-offset-0 { + margin-left: 0%; + } +} +@media (min-width: 1200px) { + .col-lg-1, .col-lg-2, .col-lg-3, .col-lg-4, .col-lg-5, .col-lg-6, .col-lg-7, .col-lg-8, .col-lg-9, .col-lg-10, .col-lg-11, .col-lg-12 { + float: left; + } + .col-lg-12 { + width: 100%; + } + .col-lg-11 { + width: 91.66666667%; + } + .col-lg-10 { + width: 83.33333333%; + } + .col-lg-9 { + width: 75%; + } + .col-lg-8 { + width: 66.66666667%; + } + .col-lg-7 { + width: 58.33333333%; + } + .col-lg-6 { + width: 50%; + } + .col-lg-5 { + width: 41.66666667%; + } + .col-lg-4 { + width: 33.33333333%; + } + .col-lg-3 { + width: 25%; + } + .col-lg-2 { + width: 16.66666667%; + } + .col-lg-1 { + width: 8.33333333%; + } + .col-lg-pull-12 { + right: 100%; + } + .col-lg-pull-11 { + right: 91.66666667%; + } + .col-lg-pull-10 { + right: 83.33333333%; + } + .col-lg-pull-9 { + right: 75%; + } + .col-lg-pull-8 { + right: 66.66666667%; + } + .col-lg-pull-7 { + right: 58.33333333%; + } + .col-lg-pull-6 { + right: 50%; + } + .col-lg-pull-5 { + right: 41.66666667%; + } + .col-lg-pull-4 { + right: 33.33333333%; + } + .col-lg-pull-3 { + right: 25%; + } + .col-lg-pull-2 { + right: 16.66666667%; + } + .col-lg-pull-1 { + right: 8.33333333%; + } + .col-lg-pull-0 { + right: auto; + } + .col-lg-push-12 { + left: 100%; + } + .col-lg-push-11 { + left: 91.66666667%; + } + .col-lg-push-10 { + left: 83.33333333%; + } + .col-lg-push-9 { + left: 75%; + } + .col-lg-push-8 { + left: 66.66666667%; + } + .col-lg-push-7 { + left: 58.33333333%; + } + .col-lg-push-6 { + left: 50%; + } + .col-lg-push-5 { + left: 41.66666667%; + } + .col-lg-push-4 { + left: 33.33333333%; + } + .col-lg-push-3 { + left: 25%; + } + .col-lg-push-2 { + left: 16.66666667%; + } + .col-lg-push-1 { + left: 8.33333333%; + } + .col-lg-push-0 { + left: auto; + } + .col-lg-offset-12 { + margin-left: 100%; + } + .col-lg-offset-11 { + margin-left: 91.66666667%; + } + .col-lg-offset-10 { + margin-left: 83.33333333%; + } + .col-lg-offset-9 { + margin-left: 75%; + } + .col-lg-offset-8 { + margin-left: 66.66666667%; + } + .col-lg-offset-7 { + margin-left: 58.33333333%; + } + .col-lg-offset-6 { + margin-left: 50%; + } + .col-lg-offset-5 { + margin-left: 41.66666667%; + } + .col-lg-offset-4 { + margin-left: 33.33333333%; + } + .col-lg-offset-3 { + margin-left: 25%; + } + .col-lg-offset-2 { + margin-left: 16.66666667%; + } + .col-lg-offset-1 { + margin-left: 8.33333333%; + } + .col-lg-offset-0 { + margin-left: 0%; + } +} +table { + background-color: transparent; +} +th { + text-align: left; +} +.table { + width: 100%; + max-width: 100%; + margin-bottom: 20px; +} +.table > thead > tr > th, +.table > tbody > tr > th, +.table > tfoot > tr > th, +.table > thead > tr > td, +.table > tbody > tr > td, +.table > tfoot > tr > td { + padding: 8px; + line-height: 1.42857143; + vertical-align: top; + border-top: 1px solid #dddddd; +} +.table > thead > tr > th { + vertical-align: bottom; + border-bottom: 2px solid #dddddd; +} +.table > caption + thead > tr:first-child > th, +.table > colgroup + thead > tr:first-child > th, +.table > thead:first-child > tr:first-child > th, +.table > caption + thead > tr:first-child > td, +.table > colgroup + thead > tr:first-child > td, +.table > thead:first-child > tr:first-child > td { + border-top: 0; +} +.table > tbody + tbody { + border-top: 2px solid #dddddd; +} +.table .table { + background-color: #ffffff; +} +.table-condensed > thead > tr > th, +.table-condensed > tbody > tr > th, +.table-condensed > tfoot > tr > th, +.table-condensed > thead > tr > td, +.table-condensed > tbody > tr > td, +.table-condensed > tfoot > tr > td { + padding: 5px; +} +.table-bordered { + border: 1px solid #dddddd; +} +.table-bordered > thead > tr > th, +.table-bordered > tbody > tr > th, +.table-bordered > tfoot > tr > th, +.table-bordered > thead > tr > td, +.table-bordered > tbody > tr > td, +.table-bordered > tfoot > tr > td { + border: 1px solid #dddddd; +} +.table-bordered > thead > tr > th, +.table-bordered > thead > tr > td { + border-bottom-width: 2px; +} +.table-striped > tbody > tr:nth-child(odd) > td, +.table-striped > tbody > tr:nth-child(odd) > th { + background-color: #f9f9f9; +} +.table-hover > tbody > tr:hover > td, +.table-hover > tbody > tr:hover > th { + background-color: #f5f5f5; +} +table col[class*="col-"] { + position: static; + float: none; + display: table-column; +} +table td[class*="col-"], +table th[class*="col-"] { + position: static; + float: none; + display: table-cell; +} +.table > thead > tr > td.active, +.table > tbody > tr > td.active, +.table > tfoot > tr > td.active, +.table > thead > tr > th.active, +.table > tbody > tr > th.active, +.table > tfoot > tr > th.active, +.table > thead > tr.active > td, +.table > tbody > tr.active > td, +.table > tfoot > tr.active > td, +.table > thead > tr.active > th, +.table > tbody > tr.active > th, +.table > tfoot > tr.active > th { + background-color: #f5f5f5; +} +.table-hover > tbody > tr > td.active:hover, +.table-hover > tbody > tr > th.active:hover, +.table-hover > tbody > tr.active:hover > td, +.table-hover > tbody > tr:hover > .active, +.table-hover > tbody > tr.active:hover > th { + background-color: #e8e8e8; +} +.table > thead > tr > td.success, +.table > tbody > tr > td.success, +.table > tfoot > tr > td.success, +.table > thead > tr > th.success, +.table > tbody > tr > th.success, +.table > tfoot > tr > th.success, +.table > thead > tr.success > td, +.table > tbody > tr.success > td, +.table > tfoot > tr.success > td, +.table > thead > tr.success > th, +.table > tbody > tr.success > th, +.table > tfoot > tr.success > th { + background-color: #dff0d8; +} +.table-hover > tbody > tr > td.success:hover, +.table-hover > tbody > tr > th.success:hover, +.table-hover > tbody > tr.success:hover > td, +.table-hover > tbody > tr:hover > .success, +.table-hover > tbody > tr.success:hover > th { + background-color: #d0e9c6; +} +.table > thead > tr > td.info, +.table > tbody > tr > td.info, +.table > tfoot > tr > td.info, +.table > thead > tr > th.info, +.table > tbody > tr > th.info, +.table > tfoot > tr > th.info, +.table > thead > tr.info > td, +.table > tbody > tr.info > td, +.table > tfoot > tr.info > td, +.table > thead > tr.info > th, +.table > tbody > tr.info > th, +.table > tfoot > tr.info > th { + background-color: #d9edf7; +} +.table-hover > tbody > tr > td.info:hover, +.table-hover > tbody > tr > th.info:hover, +.table-hover > tbody > tr.info:hover > td, +.table-hover > tbody > tr:hover > .info, +.table-hover > tbody > tr.info:hover > th { + background-color: #c4e3f3; +} +.table > thead > tr > td.warning, +.table > tbody > tr > td.warning, +.table > tfoot > tr > td.warning, +.table > thead > tr > th.warning, +.table > tbody > tr > th.warning, +.table > tfoot > tr > th.warning, +.table > thead > tr.warning > td, +.table > tbody > tr.warning > td, +.table > tfoot > tr.warning > td, +.table > thead > tr.warning > th, +.table > tbody > tr.warning > th, +.table > tfoot > tr.warning > th { + background-color: #fcf8e3; +} +.table-hover > tbody > tr > td.warning:hover, +.table-hover > tbody > tr > th.warning:hover, +.table-hover > tbody > tr.warning:hover > td, +.table-hover > tbody > tr:hover > .warning, +.table-hover > tbody > tr.warning:hover > th { + background-color: #faf2cc; +} +.table > thead > tr > td.danger, +.table > tbody > tr > td.danger, +.table > tfoot > tr > td.danger, +.table > thead > tr > th.danger, +.table > tbody > tr > th.danger, +.table > tfoot > tr > th.danger, +.table > thead > tr.danger > td, +.table > tbody > tr.danger > td, +.table > tfoot > tr.danger > td, +.table > thead > tr.danger > th, +.table > tbody > tr.danger > th, +.table > tfoot > tr.danger > th { + background-color: #f2dede; +} +.table-hover > tbody > tr > td.danger:hover, +.table-hover > tbody > tr > th.danger:hover, +.table-hover > tbody > tr.danger:hover > td, +.table-hover > tbody > tr:hover > .danger, +.table-hover > tbody > tr.danger:hover > th { + background-color: #ebcccc; +} +@media screen and (max-width: 767px) { + .table-responsive { + width: 100%; + margin-bottom: 15px; + overflow-y: hidden; + overflow-x: auto; + -ms-overflow-style: -ms-autohiding-scrollbar; + border: 1px solid #dddddd; + -webkit-overflow-scrolling: touch; + } + .table-responsive > .table { + margin-bottom: 0; + } + .table-responsive > .table > thead > tr > th, + .table-responsive > .table > tbody > tr > th, + .table-responsive > .table > tfoot > tr > th, + .table-responsive > .table > thead > tr > td, + .table-responsive > .table > tbody > tr > td, + .table-responsive > .table > tfoot > tr > td { + white-space: nowrap; + } + .table-responsive > .table-bordered { + border: 0; + } + .table-responsive > .table-bordered > thead > tr > th:first-child, + .table-responsive > .table-bordered > tbody > tr > th:first-child, + .table-responsive > .table-bordered > tfoot > tr > th:first-child, + .table-responsive > .table-bordered > thead > tr > td:first-child, + .table-responsive > .table-bordered > tbody > tr > td:first-child, + .table-responsive > .table-bordered > tfoot > tr > td:first-child { + border-left: 0; + } + .table-responsive > .table-bordered > thead > tr > th:last-child, + .table-responsive > .table-bordered > tbody > tr > th:last-child, + .table-responsive > .table-bordered > tfoot > tr > th:last-child, + .table-responsive > .table-bordered > thead > tr > td:last-child, + .table-responsive > .table-bordered > tbody > tr > td:last-child, + .table-responsive > .table-bordered > tfoot > tr > td:last-child { + border-right: 0; + } + .table-responsive > .table-bordered > tbody > tr:last-child > th, + .table-responsive > .table-bordered > tfoot > tr:last-child > th, + .table-responsive > .table-bordered > tbody > tr:last-child > td, + .table-responsive > .table-bordered > tfoot > tr:last-child > td { + border-bottom: 0; + } +} +fieldset { + padding: 0; + margin: 0; + border: 0; + min-width: 0; +} +legend { + display: block; + width: 100%; + padding: 0; + margin-bottom: 20px; + font-size: 21px; + line-height: inherit; + color: #333333; + border: 0; + border-bottom: 1px solid #e5e5e5; +} +label { + display: inline-block; + max-width: 100%; + margin-bottom: 5px; + font-weight: bold; +} +input[type="search"] { + -webkit-box-sizing: border-box; + -moz-box-sizing: border-box; + box-sizing: border-box; +} +input[type="radio"], +input[type="checkbox"] { + margin: 4px 0 0; + margin-top: 1px \9; + line-height: normal; +} +input[type="file"] { + display: block; +} +input[type="range"] { + display: block; + width: 100%; +} +select[multiple], +select[size] { + height: auto; +} +input[type="file"]:focus, +input[type="radio"]:focus, +input[type="checkbox"]:focus { + outline: thin dotted; + outline: 5px auto -webkit-focus-ring-color; + outline-offset: -2px; +} +output { + display: block; + padding-top: 7px; + font-size: 14px; + line-height: 1.42857143; + color: #555555; +} +.form-control { + display: block; + width: 100%; + height: 34px; + padding: 6px 12px; + font-size: 14px; + line-height: 1.42857143; + color: #555555; + background-color: #ffffff; + background-image: none; + border: 1px solid #cccccc; + border-radius: 4px; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); + -webkit-transition: border-color ease-in-out .15s, box-shadow ease-in-out .15s; + -o-transition: border-color ease-in-out .15s, box-shadow ease-in-out .15s; + transition: border-color ease-in-out .15s, box-shadow ease-in-out .15s; +} +.form-control:focus { + border-color: #66afe9; + outline: 0; + -webkit-box-shadow: inset 0 1px 1px rgba(0,0,0,.075), 0 0 8px rgba(102, 175, 233, 0.6); + box-shadow: inset 0 1px 1px rgba(0,0,0,.075), 0 0 8px rgba(102, 175, 233, 0.6); +} +.form-control::-moz-placeholder { + color: #777777; + opacity: 1; +} +.form-control:-ms-input-placeholder { + color: #777777; +} +.form-control::-webkit-input-placeholder { + color: #777777; +} +.form-control[disabled], +.form-control[readonly], +fieldset[disabled] .form-control { + cursor: not-allowed; + background-color: #eeeeee; + opacity: 1; +} +textarea.form-control { + height: auto; +} +input[type="search"] { + -webkit-appearance: none; +} +input[type="date"], +input[type="time"], +input[type="datetime-local"], +input[type="month"] { + line-height: 34px; + line-height: 1.42857143 \0; +} +input[type="date"].input-sm, +input[type="time"].input-sm, +input[type="datetime-local"].input-sm, +input[type="month"].input-sm { + line-height: 30px; +} +input[type="date"].input-lg, +input[type="time"].input-lg, +input[type="datetime-local"].input-lg, +input[type="month"].input-lg { + line-height: 46px; +} +.form-group { + margin-bottom: 15px; +} +.radio, +.checkbox { + position: relative; + display: block; + min-height: 20px; + margin-top: 10px; + margin-bottom: 10px; +} +.radio label, +.checkbox label { + padding-left: 20px; + margin-bottom: 0; + font-weight: normal; + cursor: pointer; +} +.radio input[type="radio"], +.radio-inline input[type="radio"], +.checkbox input[type="checkbox"], +.checkbox-inline input[type="checkbox"] { + position: absolute; + margin-left: -20px; + margin-top: 4px \9; +} +.radio + .radio, +.checkbox + .checkbox { + margin-top: -5px; +} +.radio-inline, +.checkbox-inline { + display: inline-block; + padding-left: 20px; + margin-bottom: 0; + vertical-align: middle; + font-weight: normal; + cursor: pointer; +} +.radio-inline + .radio-inline, +.checkbox-inline + .checkbox-inline { + margin-top: 0; + margin-left: 10px; +} +input[type="radio"][disabled], +input[type="checkbox"][disabled], +input[type="radio"].disabled, +input[type="checkbox"].disabled, +fieldset[disabled] input[type="radio"], +fieldset[disabled] input[type="checkbox"] { + cursor: not-allowed; +} +.radio-inline.disabled, +.checkbox-inline.disabled, +fieldset[disabled] .radio-inline, +fieldset[disabled] .checkbox-inline { + cursor: not-allowed; +} +.radio.disabled label, +.checkbox.disabled label, +fieldset[disabled] .radio label, +fieldset[disabled] .checkbox label { + cursor: not-allowed; +} +.form-control-static { + padding-top: 7px; + padding-bottom: 7px; + margin-bottom: 0; +} +.form-control-static.input-lg, +.form-control-static.input-sm { + padding-left: 0; + padding-right: 0; +} +.input-sm, +.form-horizontal .form-group-sm .form-control { + height: 30px; + padding: 5px 10px; + font-size: 12px; + line-height: 1.5; + border-radius: 3px; +} +select.input-sm { + height: 30px; + line-height: 30px; +} +textarea.input-sm, +select[multiple].input-sm { + height: auto; +} +.input-lg, +.form-horizontal .form-group-lg .form-control { + height: 46px; + padding: 10px 16px; + font-size: 18px; + line-height: 1.33; + border-radius: 6px; +} +select.input-lg { + height: 46px; + line-height: 46px; +} +textarea.input-lg, +select[multiple].input-lg { + height: auto; +} +.has-feedback { + position: relative; +} +.has-feedback .form-control { + padding-right: 42.5px; +} +.form-control-feedback { + position: absolute; + top: 25px; + right: 0; + z-index: 2; + display: block; + width: 34px; + height: 34px; + line-height: 34px; + text-align: center; +} +.input-lg + .form-control-feedback { + width: 46px; + height: 46px; + line-height: 46px; +} +.input-sm + .form-control-feedback { + width: 30px; + height: 30px; + line-height: 30px; +} +.has-success .help-block, +.has-success .control-label, +.has-success .radio, +.has-success .checkbox, +.has-success .radio-inline, +.has-success .checkbox-inline { + color: #3c763d; +} +.has-success .form-control { + border-color: #3c763d; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); +} +.has-success .form-control:focus { + border-color: #2b542c; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075), 0 0 6px #67b168; + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075), 0 0 6px #67b168; +} +.has-success .input-group-addon { + color: #3c763d; + border-color: #3c763d; + background-color: #dff0d8; +} +.has-success .form-control-feedback { + color: #3c763d; +} +.has-warning .help-block, +.has-warning .control-label, +.has-warning .radio, +.has-warning .checkbox, +.has-warning .radio-inline, +.has-warning .checkbox-inline { + color: #8a6d3b; +} +.has-warning .form-control { + border-color: #8a6d3b; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); +} +.has-warning .form-control:focus { + border-color: #66512c; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075), 0 0 6px #c0a16b; + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075), 0 0 6px #c0a16b; +} +.has-warning .input-group-addon { + color: #8a6d3b; + border-color: #8a6d3b; + background-color: #fcf8e3; +} +.has-warning .form-control-feedback { + color: #8a6d3b; +} +.has-error .help-block, +.has-error .control-label, +.has-error .radio, +.has-error .checkbox, +.has-error .radio-inline, +.has-error .checkbox-inline { + color: #a94442; +} +.has-error .form-control { + border-color: #a94442; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075); +} +.has-error .form-control:focus { + border-color: #843534; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075), 0 0 6px #ce8483; + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.075), 0 0 6px #ce8483; +} +.has-error .input-group-addon { + color: #a94442; + border-color: #a94442; + background-color: #f2dede; +} +.has-error .form-control-feedback { + color: #a94442; +} +.has-feedback label.sr-only ~ .form-control-feedback { + top: 0; +} +.help-block { + display: block; + margin-top: 5px; + margin-bottom: 10px; + color: #737373; +} +@media (min-width: 768px) { + .form-inline .form-group { + display: inline-block; + margin-bottom: 0; + vertical-align: middle; + } + .form-inline .form-control { + display: inline-block; + width: auto; + vertical-align: middle; + } + .form-inline .input-group { + display: inline-table; + vertical-align: middle; + } + .form-inline .input-group .input-group-addon, + .form-inline .input-group .input-group-btn, + .form-inline .input-group .form-control { + width: auto; + } + .form-inline .input-group > .form-control { + width: 100%; + } + .form-inline .control-label { + margin-bottom: 0; + vertical-align: middle; + } + .form-inline .radio, + .form-inline .checkbox { + display: inline-block; + margin-top: 0; + margin-bottom: 0; + vertical-align: middle; + } + .form-inline .radio label, + .form-inline .checkbox label { + padding-left: 0; + } + .form-inline .radio input[type="radio"], + .form-inline .checkbox input[type="checkbox"] { + position: relative; + margin-left: 0; + } + .form-inline .has-feedback .form-control-feedback { + top: 0; + } +} +.form-horizontal .radio, +.form-horizontal .checkbox, +.form-horizontal .radio-inline, +.form-horizontal .checkbox-inline { + margin-top: 0; + margin-bottom: 0; + padding-top: 7px; +} +.form-horizontal .radio, +.form-horizontal .checkbox { + min-height: 27px; +} +.form-horizontal .form-group { + margin-left: -15px; + margin-right: -15px; +} +@media (min-width: 768px) { + .form-horizontal .control-label { + text-align: right; + margin-bottom: 0; + padding-top: 7px; + } +} +.form-horizontal .has-feedback .form-control-feedback { + top: 0; + right: 15px; +} +@media (min-width: 768px) { + .form-horizontal .form-group-lg .control-label { + padding-top: 14.3px; + } +} +@media (min-width: 768px) { + .form-horizontal .form-group-sm .control-label { + padding-top: 6px; + } +} +.btn { + display: inline-block; + margin-bottom: 0; + font-weight: normal; + text-align: center; + vertical-align: middle; + cursor: pointer; + background-image: none; + border: 1px solid transparent; + white-space: nowrap; + padding: 6px 12px; + font-size: 14px; + line-height: 1.42857143; + border-radius: 4px; + -webkit-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} +.btn:focus, +.btn:active:focus, +.btn.active:focus { + outline: thin dotted; + outline: 5px auto -webkit-focus-ring-color; + outline-offset: -2px; +} +.btn:hover, +.btn:focus { + color: #333333; + text-decoration: none; +} +.btn:active, +.btn.active { + outline: 0; + background-image: none; + -webkit-box-shadow: inset 0 3px 5px rgba(0, 0, 0, 0.125); + box-shadow: inset 0 3px 5px rgba(0, 0, 0, 0.125); +} +.btn.disabled, +.btn[disabled], +fieldset[disabled] .btn { + cursor: not-allowed; + pointer-events: none; + opacity: 0.65; + filter: alpha(opacity=65); + -webkit-box-shadow: none; + box-shadow: none; +} +.btn-default { + color: #333333; + background-color: #ffffff; + border-color: #cccccc; +} +.btn-default:hover, +.btn-default:focus, +.btn-default:active, +.btn-default.active, +.open > .dropdown-toggle.btn-default { + color: #333333; + background-color: #e6e6e6; + border-color: #adadad; +} +.btn-default:active, +.btn-default.active, +.open > .dropdown-toggle.btn-default { + background-image: none; +} +.btn-default.disabled, +.btn-default[disabled], +fieldset[disabled] .btn-default, +.btn-default.disabled:hover, +.btn-default[disabled]:hover, +fieldset[disabled] .btn-default:hover, +.btn-default.disabled:focus, +.btn-default[disabled]:focus, +fieldset[disabled] .btn-default:focus, +.btn-default.disabled:active, +.btn-default[disabled]:active, +fieldset[disabled] .btn-default:active, +.btn-default.disabled.active, +.btn-default[disabled].active, +fieldset[disabled] .btn-default.active { + background-color: #ffffff; + border-color: #cccccc; +} +.btn-default .badge { + color: #ffffff; + background-color: #333333; +} +.btn-primary { + color: #ffffff; + background-color: #0079c2; + border-color: #0069a9; +} +.btn-primary:hover, +.btn-primary:focus, +.btn-primary:active, +.btn-primary.active, +.open > .dropdown-toggle.btn-primary { + color: #ffffff; + background-color: #00598f; + border-color: #00436b; +} +.btn-primary:active, +.btn-primary.active, +.open > .dropdown-toggle.btn-primary { + background-image: none; +} +.btn-primary.disabled, +.btn-primary[disabled], +fieldset[disabled] .btn-primary, +.btn-primary.disabled:hover, +.btn-primary[disabled]:hover, +fieldset[disabled] .btn-primary:hover, +.btn-primary.disabled:focus, +.btn-primary[disabled]:focus, +fieldset[disabled] .btn-primary:focus, +.btn-primary.disabled:active, +.btn-primary[disabled]:active, +fieldset[disabled] .btn-primary:active, +.btn-primary.disabled.active, +.btn-primary[disabled].active, +fieldset[disabled] .btn-primary.active { + background-color: #0079c2; + border-color: #0069a9; +} +.btn-primary .badge { + color: #0079c2; + background-color: #ffffff; +} +.btn-success { + color: #ffffff; + background-color: #5cb85c; + border-color: #4cae4c; +} +.btn-success:hover, +.btn-success:focus, +.btn-success:active, +.btn-success.active, +.open > .dropdown-toggle.btn-success { + color: #ffffff; + background-color: #449d44; + border-color: #398439; +} +.btn-success:active, +.btn-success.active, +.open > .dropdown-toggle.btn-success { + background-image: none; +} +.btn-success.disabled, +.btn-success[disabled], +fieldset[disabled] .btn-success, +.btn-success.disabled:hover, +.btn-success[disabled]:hover, +fieldset[disabled] .btn-success:hover, +.btn-success.disabled:focus, +.btn-success[disabled]:focus, +fieldset[disabled] .btn-success:focus, +.btn-success.disabled:active, +.btn-success[disabled]:active, +fieldset[disabled] .btn-success:active, +.btn-success.disabled.active, +.btn-success[disabled].active, +fieldset[disabled] .btn-success.active { + background-color: #5cb85c; + border-color: #4cae4c; +} +.btn-success .badge { + color: #5cb85c; + background-color: #ffffff; +} +.btn-info { + color: #ffffff; + background-color: #ffffff; + border-color: #f2f2f2; +} +.btn-info:hover, +.btn-info:focus, +.btn-info:active, +.btn-info.active, +.open > .dropdown-toggle.btn-info { + color: #ffffff; + background-color: #e6e6e6; + border-color: #d4d4d4; +} +.btn-info:active, +.btn-info.active, +.open > .dropdown-toggle.btn-info { + background-image: none; +} +.btn-info.disabled, +.btn-info[disabled], +fieldset[disabled] .btn-info, +.btn-info.disabled:hover, +.btn-info[disabled]:hover, +fieldset[disabled] .btn-info:hover, +.btn-info.disabled:focus, +.btn-info[disabled]:focus, +fieldset[disabled] .btn-info:focus, +.btn-info.disabled:active, +.btn-info[disabled]:active, +fieldset[disabled] .btn-info:active, +.btn-info.disabled.active, +.btn-info[disabled].active, +fieldset[disabled] .btn-info.active { + background-color: #ffffff; + border-color: #f2f2f2; +} +.btn-info .badge { + color: #ffffff; + background-color: #ffffff; +} +.btn-warning { + color: #ffffff; + background-color: #f0ad4e; + border-color: #eea236; +} +.btn-warning:hover, +.btn-warning:focus, +.btn-warning:active, +.btn-warning.active, +.open > .dropdown-toggle.btn-warning { + color: #ffffff; + background-color: #ec971f; + border-color: #d58512; +} +.btn-warning:active, +.btn-warning.active, +.open > .dropdown-toggle.btn-warning { + background-image: none; +} +.btn-warning.disabled, +.btn-warning[disabled], +fieldset[disabled] .btn-warning, +.btn-warning.disabled:hover, +.btn-warning[disabled]:hover, +fieldset[disabled] .btn-warning:hover, +.btn-warning.disabled:focus, +.btn-warning[disabled]:focus, +fieldset[disabled] .btn-warning:focus, +.btn-warning.disabled:active, +.btn-warning[disabled]:active, +fieldset[disabled] .btn-warning:active, +.btn-warning.disabled.active, +.btn-warning[disabled].active, +fieldset[disabled] .btn-warning.active { + background-color: #f0ad4e; + border-color: #eea236; +} +.btn-warning .badge { + color: #f0ad4e; + background-color: #ffffff; +} +.btn-danger { + color: #ffffff; + background-color: #d9534f; + border-color: #d43f3a; +} +.btn-danger:hover, +.btn-danger:focus, +.btn-danger:active, +.btn-danger.active, +.open > .dropdown-toggle.btn-danger { + color: #ffffff; + background-color: #c9302c; + border-color: #ac2925; +} +.btn-danger:active, +.btn-danger.active, +.open > .dropdown-toggle.btn-danger { + background-image: none; +} +.btn-danger.disabled, +.btn-danger[disabled], +fieldset[disabled] .btn-danger, +.btn-danger.disabled:hover, +.btn-danger[disabled]:hover, +fieldset[disabled] .btn-danger:hover, +.btn-danger.disabled:focus, +.btn-danger[disabled]:focus, +fieldset[disabled] .btn-danger:focus, +.btn-danger.disabled:active, +.btn-danger[disabled]:active, +fieldset[disabled] .btn-danger:active, +.btn-danger.disabled.active, +.btn-danger[disabled].active, +fieldset[disabled] .btn-danger.active { + background-color: #d9534f; + border-color: #d43f3a; +} +.btn-danger .badge { + color: #d9534f; + background-color: #ffffff; +} +.btn-link { + color: #0079c2; + font-weight: normal; + cursor: pointer; + border-radius: 0; +} +.btn-link, +.btn-link:active, +.btn-link[disabled], +fieldset[disabled] .btn-link { + background-color: transparent; + -webkit-box-shadow: none; + box-shadow: none; +} +.btn-link, +.btn-link:hover, +.btn-link:focus, +.btn-link:active { + border-color: transparent; +} +.btn-link:hover, +.btn-link:focus { + color: #004976; + text-decoration: underline; + background-color: transparent; +} +.btn-link[disabled]:hover, +fieldset[disabled] .btn-link:hover, +.btn-link[disabled]:focus, +fieldset[disabled] .btn-link:focus { + color: #777777; + text-decoration: none; +} +.btn-lg, +.btn-group-lg > .btn { + padding: 10px 16px; + font-size: 18px; + line-height: 1.33; + border-radius: 6px; +} +.btn-sm, +.btn-group-sm > .btn { + padding: 5px 10px; + font-size: 12px; + line-height: 1.5; + border-radius: 3px; +} +.btn-xs, +.btn-group-xs > .btn { + padding: 1px 5px; + font-size: 12px; + line-height: 1.5; + border-radius: 3px; +} +.btn-block { + display: block; + width: 100%; +} +.btn-block + .btn-block { + margin-top: 5px; +} +input[type="submit"].btn-block, +input[type="reset"].btn-block, +input[type="button"].btn-block { + width: 100%; +} +.fade { + opacity: 0; + -webkit-transition: opacity 0.15s linear; + -o-transition: opacity 0.15s linear; + transition: opacity 0.15s linear; +} +.fade.in { + opacity: 1; +} +.collapse { + display: none; +} +.collapse.in { + display: block; +} +tr.collapse.in { + display: table-row; +} +tbody.collapse.in { + display: table-row-group; +} +.collapsing { + position: relative; + height: 0; + overflow: hidden; + -webkit-transition: height 0.35s ease; + -o-transition: height 0.35s ease; + transition: height 0.35s ease; +} +.caret { + display: inline-block; + width: 0; + height: 0; + margin-left: 2px; + vertical-align: middle; + border-top: 4px solid; + border-right: 4px solid transparent; + border-left: 4px solid transparent; +} +.dropdown { + position: relative; +} +.dropdown-toggle:focus { + outline: 0; +} +.dropdown-menu { + position: absolute; + top: 100%; + left: 0; + z-index: 1000; + display: none; + float: left; + min-width: 160px; + padding: 5px 0; + margin: 2px 0 0; + list-style: none; + font-size: 14px; + text-align: left; + background-color: #ffffff; + border: 1px solid #cccccc; + border: 1px solid rgba(0, 0, 0, 0.15); + border-radius: 4px; + -webkit-box-shadow: 0 6px 12px rgba(0, 0, 0, 0.175); + box-shadow: 0 6px 12px rgba(0, 0, 0, 0.175); + background-clip: padding-box; +} +.dropdown-menu.pull-right { + right: 0; + left: auto; +} +.dropdown-menu .divider { + height: 1px; + margin: 9px 0; + overflow: hidden; + background-color: #e5e5e5; +} +.dropdown-menu > li > a { + display: block; + padding: 3px 20px; + clear: both; + font-weight: normal; + line-height: 1.42857143; + color: #333333; + white-space: nowrap; +} +.dropdown-menu > li > a:hover, +.dropdown-menu > li > a:focus { + text-decoration: none; + color: #262626; + background-color: #f5f5f5; +} +.dropdown-menu > .active > a, +.dropdown-menu > .active > a:hover, +.dropdown-menu > .active > a:focus { + color: #ffffff; + text-decoration: none; + outline: 0; + background-color: #0079c2; +} +.dropdown-menu > .disabled > a, +.dropdown-menu > .disabled > a:hover, +.dropdown-menu > .disabled > a:focus { + color: #777777; +} +.dropdown-menu > .disabled > a:hover, +.dropdown-menu > .disabled > a:focus { + text-decoration: none; + background-color: transparent; + background-image: none; + filter: progid:DXImageTransform.Microsoft.gradient(enabled = false); + cursor: not-allowed; +} +.open > .dropdown-menu { + display: block; +} +.open > a { + outline: 0; +} +.dropdown-menu-right { + left: auto; + right: 0; +} +.dropdown-menu-left { + left: 0; + right: auto; +} +.dropdown-header { + display: block; + padding: 3px 20px; + font-size: 12px; + line-height: 1.42857143; + color: #777777; + white-space: nowrap; +} +.dropdown-backdrop { + position: fixed; + left: 0; + right: 0; + bottom: 0; + top: 0; + z-index: 990; +} +.pull-right > .dropdown-menu { + right: 0; + left: auto; +} +.dropup .caret, +.navbar-fixed-bottom .dropdown .caret { + border-top: 0; + border-bottom: 4px solid; + content: ""; +} +.dropup .dropdown-menu, +.navbar-fixed-bottom .dropdown .dropdown-menu { + top: auto; + bottom: 100%; + margin-bottom: 1px; +} +@media (min-width: 768px) { + .navbar-right .dropdown-menu { + left: auto; + right: 0; + } + .navbar-right .dropdown-menu-left { + left: 0; + right: auto; + } +} +.btn-group, +.btn-group-vertical { + position: relative; + display: inline-block; + vertical-align: middle; +} +.btn-group > .btn, +.btn-group-vertical > .btn { + position: relative; + float: left; +} +.btn-group > .btn:hover, +.btn-group-vertical > .btn:hover, +.btn-group > .btn:focus, +.btn-group-vertical > .btn:focus, +.btn-group > .btn:active, +.btn-group-vertical > .btn:active, +.btn-group > .btn.active, +.btn-group-vertical > .btn.active { + z-index: 2; +} +.btn-group > .btn:focus, +.btn-group-vertical > .btn:focus { + outline: 0; +} +.btn-group .btn + .btn, +.btn-group .btn + .btn-group, +.btn-group .btn-group + .btn, +.btn-group .btn-group + .btn-group { + margin-left: -1px; +} +.btn-toolbar { + margin-left: -5px; +} +.btn-toolbar .btn-group, +.btn-toolbar .input-group { + float: left; +} +.btn-toolbar > .btn, +.btn-toolbar > .btn-group, +.btn-toolbar > .input-group { + margin-left: 5px; +} +.btn-group > .btn:not(:first-child):not(:last-child):not(.dropdown-toggle) { + border-radius: 0; +} +.btn-group > .btn:first-child { + margin-left: 0; +} +.btn-group > .btn:first-child:not(:last-child):not(.dropdown-toggle) { + border-bottom-right-radius: 0; + border-top-right-radius: 0; +} +.btn-group > .btn:last-child:not(:first-child), +.btn-group > .dropdown-toggle:not(:first-child) { + border-bottom-left-radius: 0; + border-top-left-radius: 0; +} +.btn-group > .btn-group { + float: left; +} +.btn-group > .btn-group:not(:first-child):not(:last-child) > .btn { + border-radius: 0; +} +.btn-group > .btn-group:first-child > .btn:last-child, +.btn-group > .btn-group:first-child > .dropdown-toggle { + border-bottom-right-radius: 0; + border-top-right-radius: 0; +} +.btn-group > .btn-group:last-child > .btn:first-child { + border-bottom-left-radius: 0; + border-top-left-radius: 0; +} +.btn-group .dropdown-toggle:active, +.btn-group.open .dropdown-toggle { + outline: 0; +} +.btn-group > .btn + .dropdown-toggle { + padding-left: 8px; + padding-right: 8px; +} +.btn-group > .btn-lg + .dropdown-toggle { + padding-left: 12px; + padding-right: 12px; +} +.btn-group.open .dropdown-toggle { + -webkit-box-shadow: inset 0 3px 5px rgba(0, 0, 0, 0.125); + box-shadow: inset 0 3px 5px rgba(0, 0, 0, 0.125); +} +.btn-group.open .dropdown-toggle.btn-link { + -webkit-box-shadow: none; + box-shadow: none; +} +.btn .caret { + margin-left: 0; +} +.btn-lg .caret { + border-width: 5px 5px 0; + border-bottom-width: 0; +} +.dropup .btn-lg .caret { + border-width: 0 5px 5px; +} +.btn-group-vertical > .btn, +.btn-group-vertical > .btn-group, +.btn-group-vertical > .btn-group > .btn { + display: block; + float: none; + width: 100%; + max-width: 100%; +} +.btn-group-vertical > .btn-group > .btn { + float: none; +} +.btn-group-vertical > .btn + .btn, +.btn-group-vertical > .btn + .btn-group, +.btn-group-vertical > .btn-group + .btn, +.btn-group-vertical > .btn-group + .btn-group { + margin-top: -1px; + margin-left: 0; +} +.btn-group-vertical > .btn:not(:first-child):not(:last-child) { + border-radius: 0; +} +.btn-group-vertical > .btn:first-child:not(:last-child) { + border-top-right-radius: 4px; + border-bottom-right-radius: 0; + border-bottom-left-radius: 0; +} +.btn-group-vertical > .btn:last-child:not(:first-child) { + border-bottom-left-radius: 4px; + border-top-right-radius: 0; + border-top-left-radius: 0; +} +.btn-group-vertical > .btn-group:not(:first-child):not(:last-child) > .btn { + border-radius: 0; +} +.btn-group-vertical > .btn-group:first-child:not(:last-child) > .btn:last-child, +.btn-group-vertical > .btn-group:first-child:not(:last-child) > .dropdown-toggle { + border-bottom-right-radius: 0; + border-bottom-left-radius: 0; +} +.btn-group-vertical > .btn-group:last-child:not(:first-child) > .btn:first-child { + border-top-right-radius: 0; + border-top-left-radius: 0; +} +.btn-group-justified { + display: table; + width: 100%; + table-layout: fixed; + border-collapse: separate; +} +.btn-group-justified > .btn, +.btn-group-justified > .btn-group { + float: none; + display: table-cell; + width: 1%; +} +.btn-group-justified > .btn-group .btn { + width: 100%; +} +.btn-group-justified > .btn-group .dropdown-menu { + left: auto; +} +[data-toggle="buttons"] > .btn > input[type="radio"], +[data-toggle="buttons"] > .btn > input[type="checkbox"] { + position: absolute; + z-index: -1; + opacity: 0; + filter: alpha(opacity=0); +} +.input-group { + position: relative; + display: table; + border-collapse: separate; +} +.input-group[class*="col-"] { + float: none; + padding-left: 0; + padding-right: 0; +} +.input-group .form-control { + position: relative; + z-index: 2; + float: left; + width: 100%; + margin-bottom: 0; +} +.input-group-lg > .form-control, +.input-group-lg > .input-group-addon, +.input-group-lg > .input-group-btn > .btn { + height: 46px; + padding: 10px 16px; + font-size: 18px; + line-height: 1.33; + border-radius: 6px; +} +select.input-group-lg > .form-control, +select.input-group-lg > .input-group-addon, +select.input-group-lg > .input-group-btn > .btn { + height: 46px; + line-height: 46px; +} +textarea.input-group-lg > .form-control, +textarea.input-group-lg > .input-group-addon, +textarea.input-group-lg > .input-group-btn > .btn, +select[multiple].input-group-lg > .form-control, +select[multiple].input-group-lg > .input-group-addon, +select[multiple].input-group-lg > .input-group-btn > .btn { + height: auto; +} +.input-group-sm > .form-control, +.input-group-sm > .input-group-addon, +.input-group-sm > .input-group-btn > .btn { + height: 30px; + padding: 5px 10px; + font-size: 12px; + line-height: 1.5; + border-radius: 3px; +} +select.input-group-sm > .form-control, +select.input-group-sm > .input-group-addon, +select.input-group-sm > .input-group-btn > .btn { + height: 30px; + line-height: 30px; +} +textarea.input-group-sm > .form-control, +textarea.input-group-sm > .input-group-addon, +textarea.input-group-sm > .input-group-btn > .btn, +select[multiple].input-group-sm > .form-control, +select[multiple].input-group-sm > .input-group-addon, +select[multiple].input-group-sm > .input-group-btn > .btn { + height: auto; +} +.input-group-addon, +.input-group-btn, +.input-group .form-control { + display: table-cell; +} +.input-group-addon:not(:first-child):not(:last-child), +.input-group-btn:not(:first-child):not(:last-child), +.input-group .form-control:not(:first-child):not(:last-child) { + border-radius: 0; +} +.input-group-addon, +.input-group-btn { + width: 1%; + white-space: nowrap; + vertical-align: middle; +} +.input-group-addon { + padding: 6px 12px; + font-size: 14px; + font-weight: normal; + line-height: 1; + color: #555555; + text-align: center; + background-color: #eeeeee; + border: 1px solid #cccccc; + border-radius: 4px; +} +.input-group-addon.input-sm { + padding: 5px 10px; + font-size: 12px; + border-radius: 3px; +} +.input-group-addon.input-lg { + padding: 10px 16px; + font-size: 18px; + border-radius: 6px; +} +.input-group-addon input[type="radio"], +.input-group-addon input[type="checkbox"] { + margin-top: 0; +} +.input-group .form-control:first-child, +.input-group-addon:first-child, +.input-group-btn:first-child > .btn, +.input-group-btn:first-child > .btn-group > .btn, +.input-group-btn:first-child > .dropdown-toggle, +.input-group-btn:last-child > .btn:not(:last-child):not(.dropdown-toggle), +.input-group-btn:last-child > .btn-group:not(:last-child) > .btn { + border-bottom-right-radius: 0; + border-top-right-radius: 0; +} +.input-group-addon:first-child { + border-right: 0; +} +.input-group .form-control:last-child, +.input-group-addon:last-child, +.input-group-btn:last-child > .btn, +.input-group-btn:last-child > .btn-group > .btn, +.input-group-btn:last-child > .dropdown-toggle, +.input-group-btn:first-child > .btn:not(:first-child), +.input-group-btn:first-child > .btn-group:not(:first-child) > .btn { + border-bottom-left-radius: 0; + border-top-left-radius: 0; +} +.input-group-addon:last-child { + border-left: 0; +} +.input-group-btn { + position: relative; + font-size: 0; + white-space: nowrap; +} +.input-group-btn > .btn { + position: relative; +} +.input-group-btn > .btn + .btn { + margin-left: -1px; +} +.input-group-btn > .btn:hover, +.input-group-btn > .btn:focus, +.input-group-btn > .btn:active { + z-index: 2; +} +.input-group-btn:first-child > .btn, +.input-group-btn:first-child > .btn-group { + margin-right: -1px; +} +.input-group-btn:last-child > .btn, +.input-group-btn:last-child > .btn-group { + margin-left: -1px; +} +.nav { + margin-bottom: 0; + padding-left: 0; + list-style: none; +} +.nav > li { + position: relative; + display: block; +} +.nav > li > a { + position: relative; + display: block; + padding: 10px 15px; +} +.nav > li > a:hover, +.nav > li > a:focus { + text-decoration: none; + background-color: #eeeeee; +} +.nav > li.disabled > a { + color: #777777; +} +.nav > li.disabled > a:hover, +.nav > li.disabled > a:focus { + color: #777777; + text-decoration: none; + background-color: transparent; + cursor: not-allowed; +} +.nav .open > a, +.nav .open > a:hover, +.nav .open > a:focus { + background-color: #eeeeee; + border-color: #0079c2; +} +.nav .nav-divider { + height: 1px; + margin: 9px 0; + overflow: hidden; + background-color: #e5e5e5; +} +.nav > li > a > img { + max-width: none; +} +.nav-tabs { + border-bottom: 1px solid #dddddd; +} +.nav-tabs > li { + float: left; + margin-bottom: -1px; +} +.nav-tabs > li > a { + margin-right: 2px; + line-height: 1.42857143; + border: 1px solid transparent; + border-radius: 4px 4px 0 0; +} +.nav-tabs > li > a:hover { + border-color: #eeeeee #eeeeee #dddddd; +} +.nav-tabs > li.active > a, +.nav-tabs > li.active > a:hover, +.nav-tabs > li.active > a:focus { + color: #555555; + background-color: #ffffff; + border: 1px solid #dddddd; + border-bottom-color: transparent; + cursor: default; +} +.nav-tabs.nav-justified { + width: 100%; + border-bottom: 0; +} +.nav-tabs.nav-justified > li { + float: none; +} +.nav-tabs.nav-justified > li > a { + text-align: center; + margin-bottom: 5px; +} +.nav-tabs.nav-justified > .dropdown .dropdown-menu { + top: auto; + left: auto; +} +@media (min-width: 768px) { + .nav-tabs.nav-justified > li { + display: table-cell; + width: 1%; + } + .nav-tabs.nav-justified > li > a { + margin-bottom: 0; + } +} +.nav-tabs.nav-justified > li > a { + margin-right: 0; + border-radius: 4px; +} +.nav-tabs.nav-justified > .active > a, +.nav-tabs.nav-justified > .active > a:hover, +.nav-tabs.nav-justified > .active > a:focus { + border: 1px solid #dddddd; +} +@media (min-width: 768px) { + .nav-tabs.nav-justified > li > a { + border-bottom: 1px solid #dddddd; + border-radius: 4px 4px 0 0; + } + .nav-tabs.nav-justified > .active > a, + .nav-tabs.nav-justified > .active > a:hover, + .nav-tabs.nav-justified > .active > a:focus { + border-bottom-color: #ffffff; + } +} +.nav-pills > li { + float: left; +} +.nav-pills > li > a { + border-radius: 4px; +} +.nav-pills > li + li { + margin-left: 2px; +} +.nav-pills > li.active > a, +.nav-pills > li.active > a:hover, +.nav-pills > li.active > a:focus { + color: #ffffff; + background-color: #0079c2; +} +.nav-stacked > li { + float: none; +} +.nav-stacked > li + li { + margin-top: 2px; + margin-left: 0; +} +.nav-justified { + width: 100%; +} +.nav-justified > li { + float: none; +} +.nav-justified > li > a { + text-align: center; + margin-bottom: 5px; +} +.nav-justified > .dropdown .dropdown-menu { + top: auto; + left: auto; +} +@media (min-width: 768px) { + .nav-justified > li { + display: table-cell; + width: 1%; + } + .nav-justified > li > a { + margin-bottom: 0; + } +} +.nav-tabs-justified { + border-bottom: 0; +} +.nav-tabs-justified > li > a { + margin-right: 0; + border-radius: 4px; +} +.nav-tabs-justified > .active > a, +.nav-tabs-justified > .active > a:hover, +.nav-tabs-justified > .active > a:focus { + border: 1px solid #dddddd; +} +@media (min-width: 768px) { + .nav-tabs-justified > li > a { + border-bottom: 1px solid #dddddd; + border-radius: 4px 4px 0 0; + } + .nav-tabs-justified > .active > a, + .nav-tabs-justified > .active > a:hover, + .nav-tabs-justified > .active > a:focus { + border-bottom-color: #ffffff; + } +} +.tab-content > .tab-pane { + display: none; +} +.tab-content > .active { + display: block; +} +.nav-tabs .dropdown-menu { + margin-top: -1px; + border-top-right-radius: 0; + border-top-left-radius: 0; +} +.navbar { + position: relative; + min-height: 50px; + margin-bottom: 20px; + border: 1px solid transparent; +} +@media (min-width: 768px) { + .navbar { + border-radius: 4px; + } +} +@media (min-width: 768px) { + .navbar-header { + float: left; + } +} +.navbar-collapse { + overflow-x: visible; + padding-right: 15px; + padding-left: 15px; + border-top: 1px solid transparent; + box-shadow: inset 0 1px 0 rgba(255, 255, 255, 0.1); + -webkit-overflow-scrolling: touch; +} +.navbar-collapse.in { + overflow-y: auto; +} +@media (min-width: 768px) { + .navbar-collapse { + width: auto; + border-top: 0; + box-shadow: none; + } + .navbar-collapse.collapse { + display: block !important; + height: auto !important; + padding-bottom: 0; + overflow: visible !important; + } + .navbar-collapse.in { + overflow-y: visible; + } + .navbar-fixed-top .navbar-collapse, + .navbar-static-top .navbar-collapse, + .navbar-fixed-bottom .navbar-collapse { + padding-left: 0; + padding-right: 0; + } +} +.navbar-fixed-top .navbar-collapse, +.navbar-fixed-bottom .navbar-collapse { + max-height: 340px; +} +@media (max-width: 480px) and (orientation: landscape) { + .navbar-fixed-top .navbar-collapse, + .navbar-fixed-bottom .navbar-collapse { + max-height: 200px; + } +} +.container > .navbar-header, +.container-fluid > .navbar-header, +.container > .navbar-collapse, +.container-fluid > .navbar-collapse { + margin-right: -15px; + margin-left: -15px; +} +@media (min-width: 768px) { + .container > .navbar-header, + .container-fluid > .navbar-header, + .container > .navbar-collapse, + .container-fluid > .navbar-collapse { + margin-right: 0; + margin-left: 0; + } +} +.navbar-static-top { + z-index: 1000; + border-width: 0 0 1px; +} +@media (min-width: 768px) { + .navbar-static-top { + border-radius: 0; + } +} +.navbar-fixed-top, +.navbar-fixed-bottom { + position: fixed; + right: 0; + left: 0; + z-index: 1030; + -webkit-transform: translate3d(0, 0, 0); + transform: translate3d(0, 0, 0); +} +@media (min-width: 768px) { + .navbar-fixed-top, + .navbar-fixed-bottom { + border-radius: 0; + } +} +.navbar-fixed-top { + top: 0; + border-width: 0 0 1px; +} +.navbar-fixed-bottom { + bottom: 0; + margin-bottom: 0; + border-width: 1px 0 0; +} +.navbar-brand { + float: left; + padding: 15px 15px; + font-size: 18px; + line-height: 20px; + height: 50px; +} +.navbar-brand:hover, +.navbar-brand:focus { + text-decoration: none; +} +@media (min-width: 768px) { + .navbar > .container .navbar-brand, + .navbar > .container-fluid .navbar-brand { + margin-left: -15px; + } +} +.navbar-toggle { + position: relative; + float: right; + margin-right: 15px; + padding: 9px 10px; + margin-top: 8px; + margin-bottom: 8px; + background-color: transparent; + background-image: none; + border: 1px solid transparent; + border-radius: 4px; +} +.navbar-toggle:focus { + outline: 0; +} +.navbar-toggle .icon-bar { + display: block; + width: 22px; + height: 2px; + border-radius: 1px; +} +.navbar-toggle .icon-bar + .icon-bar { + margin-top: 4px; +} +@media (min-width: 768px) { + .navbar-toggle { + display: none; + } +} +.navbar-nav { + margin: 7.5px -15px; +} +.navbar-nav > li > a { + padding-top: 10px; + padding-bottom: 10px; + line-height: 20px; +} +@media (max-width: 767px) { + .navbar-nav .open .dropdown-menu { + position: static; + float: none; + width: auto; + margin-top: 0; + background-color: transparent; + border: 0; + box-shadow: none; + } + .navbar-nav .open .dropdown-menu > li > a, + .navbar-nav .open .dropdown-menu .dropdown-header { + padding: 5px 15px 5px 25px; + } + .navbar-nav .open .dropdown-menu > li > a { + line-height: 20px; + } + .navbar-nav .open .dropdown-menu > li > a:hover, + .navbar-nav .open .dropdown-menu > li > a:focus { + background-image: none; + } +} +@media (min-width: 768px) { + .navbar-nav { + float: left; + margin: 0; + } + .navbar-nav > li { + float: left; + } + .navbar-nav > li > a { + padding-top: 15px; + padding-bottom: 15px; + } + .navbar-nav.navbar-right:last-child { + margin-right: -15px; + } +} +@media (min-width: 768px) { + .navbar-left { + float: left !important; + } + .navbar-right { + float: right !important; + } +} +.navbar-form { + margin-left: -15px; + margin-right: -15px; + padding: 10px 15px; + border-top: 1px solid transparent; + border-bottom: 1px solid transparent; + -webkit-box-shadow: inset 0 1px 0 rgba(255, 255, 255, 0.1), 0 1px 0 rgba(255, 255, 255, 0.1); + box-shadow: inset 0 1px 0 rgba(255, 255, 255, 0.1), 0 1px 0 rgba(255, 255, 255, 0.1); + margin-top: 8px; + margin-bottom: 8px; +} +@media (min-width: 768px) { + .navbar-form .form-group { + display: inline-block; + margin-bottom: 0; + vertical-align: middle; + } + .navbar-form .form-control { + display: inline-block; + width: auto; + vertical-align: middle; + } + .navbar-form .input-group { + display: inline-table; + vertical-align: middle; + } + .navbar-form .input-group .input-group-addon, + .navbar-form .input-group .input-group-btn, + .navbar-form .input-group .form-control { + width: auto; + } + .navbar-form .input-group > .form-control { + width: 100%; + } + .navbar-form .control-label { + margin-bottom: 0; + vertical-align: middle; + } + .navbar-form .radio, + .navbar-form .checkbox { + display: inline-block; + margin-top: 0; + margin-bottom: 0; + vertical-align: middle; + } + .navbar-form .radio label, + .navbar-form .checkbox label { + padding-left: 0; + } + .navbar-form .radio input[type="radio"], + .navbar-form .checkbox input[type="checkbox"] { + position: relative; + margin-left: 0; + } + .navbar-form .has-feedback .form-control-feedback { + top: 0; + } +} +@media (max-width: 767px) { + .navbar-form .form-group { + margin-bottom: 5px; + } +} +@media (min-width: 768px) { + .navbar-form { + width: auto; + border: 0; + margin-left: 0; + margin-right: 0; + padding-top: 0; + padding-bottom: 0; + -webkit-box-shadow: none; + box-shadow: none; + } + .navbar-form.navbar-right:last-child { + margin-right: -15px; + } +} +.navbar-nav > li > .dropdown-menu { + margin-top: 0; + border-top-right-radius: 0; + border-top-left-radius: 0; +} +.navbar-fixed-bottom .navbar-nav > li > .dropdown-menu { + border-bottom-right-radius: 0; + border-bottom-left-radius: 0; +} +.navbar-btn { + margin-top: 8px; + margin-bottom: 8px; +} +.navbar-btn.btn-sm { + margin-top: 10px; + margin-bottom: 10px; +} +.navbar-btn.btn-xs { + margin-top: 14px; + margin-bottom: 14px; +} +.navbar-text { + margin-top: 15px; + margin-bottom: 15px; +} +@media (min-width: 768px) { + .navbar-text { + float: left; + margin-left: 15px; + margin-right: 15px; + } + .navbar-text.navbar-right:last-child { + margin-right: 0; + } +} +.navbar-default { + background-color: #f8f8f8; + border-color: #e7e7e7; +} +.navbar-default .navbar-brand { + color: #777777; +} +.navbar-default .navbar-brand:hover, +.navbar-default .navbar-brand:focus { + color: #5e5e5e; + background-color: transparent; +} +.navbar-default .navbar-text { + color: #777777; +} +.navbar-default .navbar-nav > li > a { + color: #777777; +} +.navbar-default .navbar-nav > li > a:hover, +.navbar-default .navbar-nav > li > a:focus { + color: #333333; + background-color: transparent; +} +.navbar-default .navbar-nav > .active > a, +.navbar-default .navbar-nav > .active > a:hover, +.navbar-default .navbar-nav > .active > a:focus { + color: #555555; + background-color: #e7e7e7; +} +.navbar-default .navbar-nav > .disabled > a, +.navbar-default .navbar-nav > .disabled > a:hover, +.navbar-default .navbar-nav > .disabled > a:focus { + color: #cccccc; + background-color: transparent; +} +.navbar-default .navbar-toggle { + border-color: #dddddd; +} +.navbar-default .navbar-toggle:hover, +.navbar-default .navbar-toggle:focus { + background-color: #dddddd; +} +.navbar-default .navbar-toggle .icon-bar { + background-color: #888888; +} +.navbar-default .navbar-collapse, +.navbar-default .navbar-form { + border-color: #e7e7e7; +} +.navbar-default .navbar-nav > .open > a, +.navbar-default .navbar-nav > .open > a:hover, +.navbar-default .navbar-nav > .open > a:focus { + background-color: #e7e7e7; + color: #555555; +} +@media (max-width: 767px) { + .navbar-default .navbar-nav .open .dropdown-menu > li > a { + color: #777777; + } + .navbar-default .navbar-nav .open .dropdown-menu > li > a:hover, + .navbar-default .navbar-nav .open .dropdown-menu > li > a:focus { + color: #333333; + background-color: transparent; + } + .navbar-default .navbar-nav .open .dropdown-menu > .active > a, + .navbar-default .navbar-nav .open .dropdown-menu > .active > a:hover, + .navbar-default .navbar-nav .open .dropdown-menu > .active > a:focus { + color: #555555; + background-color: #e7e7e7; + } + .navbar-default .navbar-nav .open .dropdown-menu > .disabled > a, + .navbar-default .navbar-nav .open .dropdown-menu > .disabled > a:hover, + .navbar-default .navbar-nav .open .dropdown-menu > .disabled > a:focus { + color: #cccccc; + background-color: transparent; + } +} +.navbar-default .navbar-link { + color: #777777; +} +.navbar-default .navbar-link:hover { + color: #333333; +} +.navbar-default .btn-link { + color: #777777; +} +.navbar-default .btn-link:hover, +.navbar-default .btn-link:focus { + color: #333333; +} +.navbar-default .btn-link[disabled]:hover, +fieldset[disabled] .navbar-default .btn-link:hover, +.navbar-default .btn-link[disabled]:focus, +fieldset[disabled] .navbar-default .btn-link:focus { + color: #cccccc; +} +.navbar-inverse { + background-color: #0079c2; + border-color: #00598f; +} +.navbar-inverse .navbar-brand { + color: #ffffff; +} +.navbar-inverse .navbar-brand:hover, +.navbar-inverse .navbar-brand:focus { + color: #ffffff; + background-color: transparent; +} +.navbar-inverse .navbar-text { + color: #ffffff; +} +.navbar-inverse .navbar-nav > li > a { + color: #ffffff; +} +.navbar-inverse .navbar-nav > li > a:hover, +.navbar-inverse .navbar-nav > li > a:focus { + color: #ffffff; + background-color: transparent; +} +.navbar-inverse .navbar-nav > .active > a, +.navbar-inverse .navbar-nav > .active > a:hover, +.navbar-inverse .navbar-nav > .active > a:focus { + color: #ffffff; + background-color: #00598f; +} +.navbar-inverse .navbar-nav > .disabled > a, +.navbar-inverse .navbar-nav > .disabled > a:hover, +.navbar-inverse .navbar-nav > .disabled > a:focus { + color: #444444; + background-color: transparent; +} +.navbar-inverse .navbar-toggle { + border-color: #333333; +} +.navbar-inverse .navbar-toggle:hover, +.navbar-inverse .navbar-toggle:focus { + background-color: #333333; +} +.navbar-inverse .navbar-toggle .icon-bar { + background-color: #ffffff; +} +.navbar-inverse .navbar-collapse, +.navbar-inverse .navbar-form { + border-color: #00639e; +} +.navbar-inverse .navbar-nav > .open > a, +.navbar-inverse .navbar-nav > .open > a:hover, +.navbar-inverse .navbar-nav > .open > a:focus { + background-color: #00598f; + color: #ffffff; +} +@media (max-width: 767px) { + .navbar-inverse .navbar-nav .open .dropdown-menu > .dropdown-header { + border-color: #00598f; + } + .navbar-inverse .navbar-nav .open .dropdown-menu .divider { + background-color: #00598f; + } + .navbar-inverse .navbar-nav .open .dropdown-menu > li > a { + color: #ffffff; + } + .navbar-inverse .navbar-nav .open .dropdown-menu > li > a:hover, + .navbar-inverse .navbar-nav .open .dropdown-menu > li > a:focus { + color: #ffffff; + background-color: transparent; + } + .navbar-inverse .navbar-nav .open .dropdown-menu > .active > a, + .navbar-inverse .navbar-nav .open .dropdown-menu > .active > a:hover, + .navbar-inverse .navbar-nav .open .dropdown-menu > .active > a:focus { + color: #ffffff; + background-color: #00598f; + } + .navbar-inverse .navbar-nav .open .dropdown-menu > .disabled > a, + .navbar-inverse .navbar-nav .open .dropdown-menu > .disabled > a:hover, + .navbar-inverse .navbar-nav .open .dropdown-menu > .disabled > a:focus { + color: #444444; + background-color: transparent; + } +} +.navbar-inverse .navbar-link { + color: #ffffff; +} +.navbar-inverse .navbar-link:hover { + color: #ffffff; +} +.navbar-inverse .btn-link { + color: #ffffff; +} +.navbar-inverse .btn-link:hover, +.navbar-inverse .btn-link:focus { + color: #ffffff; +} +.navbar-inverse .btn-link[disabled]:hover, +fieldset[disabled] .navbar-inverse .btn-link:hover, +.navbar-inverse .btn-link[disabled]:focus, +fieldset[disabled] .navbar-inverse .btn-link:focus { + color: #444444; +} +.breadcrumb { + padding: 8px 15px; + margin-bottom: 20px; + list-style: none; + background-color: #f5f5f5; + border-radius: 4px; +} +.breadcrumb > li { + display: inline-block; +} +.breadcrumb > li + li:before { + content: "/\00a0"; + padding: 0 5px; + color: #cccccc; +} +.breadcrumb > .active { + color: #777777; +} +.pagination { + display: inline-block; + padding-left: 0; + margin: 20px 0; + border-radius: 4px; +} +.pagination > li { + display: inline; +} +.pagination > li > a, +.pagination > li > span { + position: relative; + float: left; + padding: 6px 12px; + line-height: 1.42857143; + text-decoration: none; + color: #0079c2; + background-color: #ffffff; + border: 1px solid #dddddd; + margin-left: -1px; +} +.pagination > li:first-child > a, +.pagination > li:first-child > span { + margin-left: 0; + border-bottom-left-radius: 4px; + border-top-left-radius: 4px; +} +.pagination > li:last-child > a, +.pagination > li:last-child > span { + border-bottom-right-radius: 4px; + border-top-right-radius: 4px; +} +.pagination > li > a:hover, +.pagination > li > span:hover, +.pagination > li > a:focus, +.pagination > li > span:focus { + color: #004976; + background-color: #eeeeee; + border-color: #dddddd; +} +.pagination > .active > a, +.pagination > .active > span, +.pagination > .active > a:hover, +.pagination > .active > span:hover, +.pagination > .active > a:focus, +.pagination > .active > span:focus { + z-index: 2; + color: #ffffff; + background-color: #0079c2; + border-color: #0079c2; + cursor: default; +} +.pagination > .disabled > span, +.pagination > .disabled > span:hover, +.pagination > .disabled > span:focus, +.pagination > .disabled > a, +.pagination > .disabled > a:hover, +.pagination > .disabled > a:focus { + color: #777777; + background-color: #ffffff; + border-color: #dddddd; + cursor: not-allowed; +} +.pagination-lg > li > a, +.pagination-lg > li > span { + padding: 10px 16px; + font-size: 18px; +} +.pagination-lg > li:first-child > a, +.pagination-lg > li:first-child > span { + border-bottom-left-radius: 6px; + border-top-left-radius: 6px; +} +.pagination-lg > li:last-child > a, +.pagination-lg > li:last-child > span { + border-bottom-right-radius: 6px; + border-top-right-radius: 6px; +} +.pagination-sm > li > a, +.pagination-sm > li > span { + padding: 5px 10px; + font-size: 12px; +} +.pagination-sm > li:first-child > a, +.pagination-sm > li:first-child > span { + border-bottom-left-radius: 3px; + border-top-left-radius: 3px; +} +.pagination-sm > li:last-child > a, +.pagination-sm > li:last-child > span { + border-bottom-right-radius: 3px; + border-top-right-radius: 3px; +} +.pager { + padding-left: 0; + margin: 20px 0; + list-style: none; + text-align: center; +} +.pager li { + display: inline; +} +.pager li > a, +.pager li > span { + display: inline-block; + padding: 5px 14px; + background-color: #ffffff; + border: 1px solid #dddddd; + border-radius: 15px; +} +.pager li > a:hover, +.pager li > a:focus { + text-decoration: none; + background-color: #eeeeee; +} +.pager .next > a, +.pager .next > span { + float: right; +} +.pager .previous > a, +.pager .previous > span { + float: left; +} +.pager .disabled > a, +.pager .disabled > a:hover, +.pager .disabled > a:focus, +.pager .disabled > span { + color: #777777; + background-color: #ffffff; + cursor: not-allowed; +} +.label { + display: inline; + padding: .2em .6em .3em; + font-size: 75%; + font-weight: bold; + line-height: 1; + color: #ffffff; + text-align: center; + white-space: nowrap; + vertical-align: baseline; + border-radius: .25em; +} +a.label:hover, +a.label:focus { + color: #ffffff; + text-decoration: none; + cursor: pointer; +} +.label:empty { + display: none; +} +.btn .label { + position: relative; + top: -1px; +} +.label-default { + background-color: #777777; +} +.label-default[href]:hover, +.label-default[href]:focus { + background-color: #5e5e5e; +} +.label-primary { + background-color: #0079c2; +} +.label-primary[href]:hover, +.label-primary[href]:focus { + background-color: #00598f; +} +.label-success { + background-color: #5cb85c; +} +.label-success[href]:hover, +.label-success[href]:focus { + background-color: #449d44; +} +.label-info { + background-color: #ffffff; +} +.label-info[href]:hover, +.label-info[href]:focus { + background-color: #e6e6e6; +} +.label-warning { + background-color: #f0ad4e; +} +.label-warning[href]:hover, +.label-warning[href]:focus { + background-color: #ec971f; +} +.label-danger { + background-color: #d9534f; +} +.label-danger[href]:hover, +.label-danger[href]:focus { + background-color: #c9302c; +} +.badge { + display: inline-block; + min-width: 10px; + padding: 3px 7px; + font-size: 12px; + font-weight: bold; + color: #ffffff; + line-height: 1; + vertical-align: baseline; + white-space: nowrap; + text-align: center; + background-color: #777777; + border-radius: 10px; +} +.badge:empty { + display: none; +} +.btn .badge { + position: relative; + top: -1px; +} +.btn-xs .badge { + top: 0; + padding: 1px 5px; +} +a.badge:hover, +a.badge:focus { + color: #ffffff; + text-decoration: none; + cursor: pointer; +} +a.list-group-item.active > .badge, +.nav-pills > .active > a > .badge { + color: #0079c2; + background-color: #ffffff; +} +.nav-pills > li > a > .badge { + margin-left: 3px; +} +.jumbotron { + padding: 30px; + margin-bottom: 30px; + color: inherit; + background-color: #eeeeee; +} +.jumbotron h1, +.jumbotron .h1 { + color: inherit; +} +.jumbotron p { + margin-bottom: 15px; + font-size: 21px; + font-weight: 200; +} +.jumbotron > hr { + border-top-color: #d5d5d5; +} +.container .jumbotron { + border-radius: 6px; +} +.jumbotron .container { + max-width: 100%; +} +@media screen and (min-width: 768px) { + .jumbotron { + padding-top: 48px; + padding-bottom: 48px; + } + .container .jumbotron { + padding-left: 60px; + padding-right: 60px; + } + .jumbotron h1, + .jumbotron .h1 { + font-size: 63px; + } +} +.thumbnail { + display: block; + padding: 4px; + margin-bottom: 20px; + line-height: 1.42857143; + background-color: #ffffff; + border: 1px solid #dddddd; + border-radius: 4px; + -webkit-transition: all 0.2s ease-in-out; + -o-transition: all 0.2s ease-in-out; + transition: all 0.2s ease-in-out; +} +.thumbnail > img, +.thumbnail a > img { + margin-left: auto; + margin-right: auto; +} +a.thumbnail:hover, +a.thumbnail:focus, +a.thumbnail.active { + border-color: #0079c2; +} +.thumbnail .caption { + padding: 9px; + color: #333333; +} +.alert { + padding: 15px; + margin-bottom: 20px; + border: 1px solid transparent; + border-radius: 4px; +} +.alert h4 { + margin-top: 0; + color: inherit; +} +.alert .alert-link { + font-weight: bold; +} +.alert > p, +.alert > ul { + margin-bottom: 0; +} +.alert > p + p { + margin-top: 5px; +} +.alert-dismissable, +.alert-dismissible { + padding-right: 35px; +} +.alert-dismissable .close, +.alert-dismissible .close { + position: relative; + top: -2px; + right: -21px; + color: inherit; +} +.alert-success { + background-color: #dff0d8; + border-color: #d6e9c6; + color: #3c763d; +} +.alert-success hr { + border-top-color: #c9e2b3; +} +.alert-success .alert-link { + color: #2b542c; +} +.alert-info { + background-color: #d9edf7; + border-color: #bce8f1; + color: #31708f; +} +.alert-info hr { + border-top-color: #a6e1ec; +} +.alert-info .alert-link { + color: #245269; +} +.alert-warning { + background-color: #fcf8e3; + border-color: #faebcc; + color: #8a6d3b; +} +.alert-warning hr { + border-top-color: #f7e1b5; +} +.alert-warning .alert-link { + color: #66512c; +} +.alert-danger { + background-color: #f2dede; + border-color: #ebccd1; + color: #a94442; +} +.alert-danger hr { + border-top-color: #e4b9c0; +} +.alert-danger .alert-link { + color: #843534; +} +@-webkit-keyframes progress-bar-stripes { + from { + background-position: 40px 0; + } + to { + background-position: 0 0; + } +} +@keyframes progress-bar-stripes { + from { + background-position: 40px 0; + } + to { + background-position: 0 0; + } +} +.progress { + overflow: hidden; + height: 20px; + margin-bottom: 20px; + background-color: #f5f5f5; + border-radius: 4px; + -webkit-box-shadow: inset 0 1px 2px rgba(0, 0, 0, 0.1); + box-shadow: inset 0 1px 2px rgba(0, 0, 0, 0.1); +} +.progress-bar { + float: left; + width: 0%; + height: 100%; + font-size: 12px; + line-height: 20px; + color: #ffffff; + text-align: center; + background-color: #0079c2; + -webkit-box-shadow: inset 0 -1px 0 rgba(0, 0, 0, 0.15); + box-shadow: inset 0 -1px 0 rgba(0, 0, 0, 0.15); + -webkit-transition: width 0.6s ease; + -o-transition: width 0.6s ease; + transition: width 0.6s ease; +} +.progress-striped .progress-bar, +.progress-bar-striped { + background-image: -webkit-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: -o-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-size: 40px 40px; +} +.progress.active .progress-bar, +.progress-bar.active { + -webkit-animation: progress-bar-stripes 2s linear infinite; + -o-animation: progress-bar-stripes 2s linear infinite; + animation: progress-bar-stripes 2s linear infinite; +} +.progress-bar[aria-valuenow="1"], +.progress-bar[aria-valuenow="2"] { + min-width: 30px; +} +.progress-bar[aria-valuenow="0"] { + color: #777777; + min-width: 30px; + background-color: transparent; + background-image: none; + box-shadow: none; +} +.progress-bar-success { + background-color: #5cb85c; +} +.progress-striped .progress-bar-success { + background-image: -webkit-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: -o-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); +} +.progress-bar-info { + background-color: #ffffff; +} +.progress-striped .progress-bar-info { + background-image: -webkit-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: -o-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); +} +.progress-bar-warning { + background-color: #f0ad4e; +} +.progress-striped .progress-bar-warning { + background-image: -webkit-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: -o-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); +} +.progress-bar-danger { + background-color: #d9534f; +} +.progress-striped .progress-bar-danger { + background-image: -webkit-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: -o-linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); + background-image: linear-gradient(45deg, rgba(255, 255, 255, 0.15) 25%, transparent 25%, transparent 50%, rgba(255, 255, 255, 0.15) 50%, rgba(255, 255, 255, 0.15) 75%, transparent 75%, transparent); +} +.media, +.media-body { + overflow: hidden; + zoom: 1; +} +.media, +.media .media { + margin-top: 15px; +} +.media:first-child { + margin-top: 0; +} +.media-object { + display: block; +} +.media-heading { + margin: 0 0 5px; +} +.media > .pull-left { + margin-right: 10px; +} +.media > .pull-right { + margin-left: 10px; +} +.media-list { + padding-left: 0; + list-style: none; +} +.list-group { + margin-bottom: 20px; + padding-left: 0; +} +.list-group-item { + position: relative; + display: block; + padding: 10px 15px; + margin-bottom: -1px; + background-color: #ffffff; + border: 1px solid #dddddd; +} +.list-group-item:first-child { + border-top-right-radius: 4px; + border-top-left-radius: 4px; +} +.list-group-item:last-child { + margin-bottom: 0; + border-bottom-right-radius: 4px; + border-bottom-left-radius: 4px; +} +.list-group-item > .badge { + float: right; +} +.list-group-item > .badge + .badge { + margin-right: 5px; +} +a.list-group-item { + color: #555555; +} +a.list-group-item .list-group-item-heading { + color: #333333; +} +a.list-group-item:hover, +a.list-group-item:focus { + text-decoration: none; + color: #555555; + background-color: #f5f5f5; +} +.list-group-item.disabled, +.list-group-item.disabled:hover, +.list-group-item.disabled:focus { + background-color: #eeeeee; + color: #777777; +} +.list-group-item.disabled .list-group-item-h.nepanel-heading { +background: black; +} +eading, +.list-group-item.disabled:hover .list-group-item-heading, +.list-group-item.disabled:focus .list-group-item-heading { + color: inherit; +} +.list-group-item.disabled .list-group-item-text, +.list-group-item.disabled:hover .list-group-item-text, +.list-group-item.disabled:focus .list-group-item-text { + color: #777777; +} +.list-group-item.active, +.list-group-item.active:hover, +.list-group-item.active:focus { + z-index: 2; + color: #ffffff; + background-color: #0079c2; + border-color: #0079c2; +} +.list-group-item.active .list-group-item-heading, +.list-group-item.active:hover .list-group-item-heading, +.list-group-item.active:focus .list-group-item-heading, +.list-group-item.active .list-group-item-heading > small, +.list-group-item.active:hover .list-group-item-heading > small, +.list-group-item.active:focus .list-group-item-heading > small, +.list-group-item.active .list-group-item-heading > .small, +.list-group-item.active:hover .list-group-item-heading > .small, +.list-group-item.active:focus .list-group-item-heading > .small { + color: inherit; +} +.list-group-item.active .list-group-item-text, +.list-group-item.active:hover .list-group-item-text, +.list-group-item.active:focus .list-group-item-text { + color: #8fd5ff; +} +.list-group-item-success { + color: #3c763d; + background-color: #dff0d8; +} +a.list-group-item-success { + color: #3c763d; +} +a.list-group-item-success .list-group-item-heading { + color: inherit; +} +a.list-group-item-success:hover, +a.list-group-item-success:focus { + color: #3c763d; + background-color: #d0e9c6; +} +a.list-group-item-success.active, +a.list-group-item-success.active:hover, +a.list-group-item-success.active:focus { + color: #fff; + background-color: #3c763d; + border-color: #3c763d; +} +.list-group-item-info { + color: #31708f; + background-color: #d9edf7; +} +a.list-group-item-info { + color: #31708f; +} +a.list-group-item-info .list-group-item-heading { + color: inherit; +} +a.list-group-item-info:hover, +a.list-group-item-info:focus { + color: #31708f; + background-color: #c4e3f3; +} +a.list-group-item-info.active, +a.list-group-item-info.active:hover, +a.list-group-item-info.active:focus { + color: #fff; + background-color: #31708f; + border-color: #31708f; +} +.list-group-item-warning { + color: #8a6d3b; + background-color: #fcf8e3; +} +a.list-group-item-warning { + color: #8a6d3b; +} +a.list-group-item-warning .list-group-item-heading { + color: inherit; +} +a.list-group-item-warning:hover, +a.list-group-item-warning:focus { + color: #8a6d3b; + background-color: #faf2cc; +} +a.list-group-item-warning.active, +a.list-group-item-warning.active:hover, +a.list-group-item-warning.active:focus { + color: #fff; + background-color: #8a6d3b; + border-color: #8a6d3b; +} +.list-group-item-danger { + color: #a94442; + background-color: #f2dede; +} +a.list-group-item-danger { + color: #a94442; +} +a.list-group-item-danger .list-group-item-heading { + color: inherit; +} +a.list-group-item-danger:hover, +a.list-group-item-danger:focus { + color: #a94442; + background-color: #ebcccc; +} +a.list-group-item-danger.active, +a.list-group-item-danger.active:hover, +a.list-group-item-danger.active:focus { + color: #fff; + background-color: #a94442; + border-color: #a94442; +} +.list-group-item-heading { + margin-top: 0; + margin-bottom: 5px; +} +.list-group-item-text { + margin-bottom: 0; + line-height: 1.3; +} +.panel { + margin: 10px; + margin-bottom: 20px; + background-color: #ffffff; + border: 1px solid transparent; + border-radius: 4px; + -webkit-box-shadow: 0 1px 1px rgba(0, 0, 0, 0.4); + box-shadow: 0 1px 1px rgba(0, 0, 0, 0.4); +} +.panel-body { + padding: 15px; +} +.panel-heading { + padding: 10px 15px; + border-bottom: 1px solid transparent; + border-top-right-radius: 3px; + border-top-left-radius: 3px; +} +.panel-heading > .dropdown .dropdown-toggle { + color: inherit; +} +.panel-title { + margin-top: 0; + margin-bottom: 0; + font-size: 19px; + text-shadow: 0 1px 0 #000000; + color: inherit; +} +.panel-title > a { + color: inherit; +} +.panel-footer { + padding: 10px 15px; + background-color: #f5f5f5; + border-top: 1px solid #dddddd; + border-bottom-right-radius: 3px; + border-bottom-left-radius: 3px; +} +.panel > .list-group { + margin-bottom: 0; +} +.panel > .list-group .list-group-item { + border-width: 1px 0; + border-radius: 0; +} +.panel > .list-group:first-child .list-group-item:first-child { + border-top: 0; + border-top-right-radius: 3px; + border-top-left-radius: 3px; +} +.panel > .list-group:last-child .list-group-item:last-child { + border-bottom: 0; + border-bottom-right-radius: 3px; + border-bottom-left-radius: 3px; +} +.panel-heading + .list-group .list-group-item:first-child { + border-top-width: 0; +} +.list-group + .panel-footer { + border-top-width: 0; +} +.panel > .table, +.panel > .table-responsive > .table, +.panel > .panel-collapse > .table { + margin-bottom: 0; +} +.panel > .table:first-child, +.panel > .table-responsive:first-child > .table:first-child { + border-top-right-radius: 3px; + border-top-left-radius: 3px; +} +.panel > .table:first-child > thead:first-child > tr:first-child td:first-child, +.panel > .table-responsive:first-child > .table:first-child > thead:first-child > tr:first-child td:first-child, +.panel > .table:first-child > tbody:first-child > tr:first-child td:first-child, +.panel > .table-responsive:first-child > .table:first-child > tbody:first-child > tr:first-child td:first-child, +.panel > .table:first-child > thead:first-child > tr:first-child th:first-child, +.panel > .table-responsive:first-child > .table:first-child > thead:first-child > tr:first-child th:first-child, +.panel > .table:first-child > tbody:first-child > tr:first-child th:first-child, +.panel > .table-responsive:first-child > .table:first-child > tbody:first-child > tr:first-child th:first-child { + border-top-left-radius: 3px; +} +.panel > .table:first-child > thead:first-child > tr:first-child td:last-child, +.panel > .table-responsive:first-child > .table:first-child > thead:first-child > tr:first-child td:last-child, +.panel > .table:first-child > tbody:first-child > tr:first-child td:last-child, +.panel > .table-responsive:first-child > .table:first-child > tbody:first-child > tr:first-child td:last-child, +.panel > .table:first-child > thead:first-child > tr:first-child th:last-child, +.panel > .table-responsive:first-child > .table:first-child > thead:first-child > tr:first-child th:last-child, +.panel > .table:first-child > tbody:first-child > tr:first-child th:last-child, +.panel > .table-responsive:first-child > .table:first-child > tbody:first-child > tr:first-child th:last-child { + border-top-right-radius: 3px; +} +.panel > .table:last-child, +.panel > .table-responsive:last-child > .table:last-child { + border-bottom-right-radius: 3px; + border-bottom-left-radius: 3px; +} +.panel > .table:last-child > tbody:last-child > tr:last-child td:first-child, +.panel > .table-responsive:last-child > .table:last-child > tbody:last-child > tr:last-child td:first-child, +.panel > .table:last-child > tfoot:last-child > tr:last-child td:first-child, +.panel > .table-responsive:last-child > .table:last-child > tfoot:last-child > tr:last-child td:first-child, +.panel > .table:last-child > tbody:last-child > tr:last-child th:first-child, +.panel > .table-responsive:last-child > .table:last-child > tbody:last-child > tr:last-child th:first-child, +.panel > .table:last-child > tfoot:last-child > tr:last-child th:first-child, +.panel > .table-responsive:last-child > .table:last-child > tfoot:last-child > tr:last-child th:first-child { + border-bottom-left-radius: 3px; +} +.panel > .table:last-child > tbody:last-child > tr:last-child td:last-child, +.panel > .table-responsive:last-child > .table:last-child > tbody:last-child > tr:last-child td:last-child, +.panel > .table:last-child > tfoot:last-child > tr:last-child td:last-child, +.panel > .table-responsive:last-child > .table:last-child > tfoot:last-child > tr:last-child td:last-child, +.panel > .table:last-child > tbody:last-child > tr:last-child th:last-child, +.panel > .table-responsive:last-child > .table:last-child > tbody:last-child > tr:last-child th:last-child, +.panel > .table:last-child > tfoot:last-child > tr:last-child th:last-child, +.panel > .table-responsive:last-child > .table:last-child > tfoot:last-child > tr:last-child th:last-child { + border-bottom-right-radius: 3px; +} +.panel > .panel-body + .table, +.panel > .panel-body + .table-responsive { + border-top: 1px solid #dddddd; +} +.panel > .table > tbody:first-child > tr:first-child th, +.panel > .table > tbody:first-child > tr:first-child td { + border-top: 0; +} +.panel > .table-bordered, +.panel > .table-responsive > .table-bordered { + border: 0; +} +.panel > .table-bordered > thead > tr > th:first-child, +.panel > .table-responsive > .table-bordered > thead > tr > th:first-child, +.panel > .table-bordered > tbody > tr > th:first-child, +.panel > .table-responsive > .table-bordered > tbody > tr > th:first-child, +.panel > .table-bordered > tfoot > tr > th:first-child, +.panel > .table-responsive > .table-bordered > tfoot > tr > th:first-child, +.panel > .table-bordered > thead > tr > td:first-child, +.panel > .table-responsive > .table-bordered > thead > tr > td:first-child, +.panel > .table-bordered > tbody > tr > td:first-child, +.panel > .table-responsive > .table-bordered > tbody > tr > td:first-child, +.panel > .table-bordered > tfoot > tr > td:first-child, +.panel > .table-responsive > .table-bordered > tfoot > tr > td:first-child { + border-left: 0; +} +.panel > .table-bordered > thead > tr > th:last-child, +.panel > .table-responsive > .table-bordered > thead > tr > th:last-child, +.panel > .table-bordered > tbody > tr > th:last-child, +.panel > .table-responsive > .table-bordered > tbody > tr > th:last-child, +.panel > .table-bordered > tfoot > tr > th:last-child, +.panel > .table-responsive > .table-bordered > tfoot > tr > th:last-child, +.panel > .table-bordered > thead > tr > td:last-child, +.panel > .table-responsive > .table-bordered > thead > tr > td:last-child, +.panel > .table-bordered > tbody > tr > td:last-child, +.panel > .table-responsive > .table-bordered > tbody > tr > td:last-child, +.panel > .table-bordered > tfoot > tr > td:last-child, +.panel > .table-responsive > .table-bordered > tfoot > tr > td:last-child { + border-right: 0; +} +.panel > .table-bordered > thead > tr:first-child > td, +.panel > .table-responsive > .table-bordered > thead > tr:first-child > td, +.panel > .table-bordered > tbody > tr:first-child > td, +.panel > .table-responsive > .table-bordered > tbody > tr:first-child > td, +.panel > .table-bordered > thead > tr:first-child > th, +.panel > .table-responsive > .table-bordered > thead > tr:first-child > th, +.panel > .table-bordered > tbody > tr:first-child > th, +.panel > .table-responsive > .table-bordered > tbody > tr:first-child > th { + border-bottom: 0; +} +.panel > .table-bordered > tbody > tr:last-child > td, +.panel > .table-responsive > .table-bordered > tbody > tr:last-child > td, +.panel > .table-bordered > tfoot > tr:last-child > td, +.panel > .table-responsive > .table-bordered > tfoot > tr:last-child > td, +.panel > .table-bordered > tbody > tr:last-child > th, +.panel > .table-responsive > .table-bordered > tbody > tr:last-child > th, +.panel > .table-bordered > tfoot > tr:last-child > th, +.panel > .table-responsive > .table-bordered > tfoot > tr:last-child > th { + border-bottom: 0; +} +.panel > .table-responsive { + border: 0; + margin-bottom: 0; +} +.panel-group { + margin-bottom: 20px; +} +.panel-group .panel { + margin-bottom: 0; + border-radius: 4px; +} +.panel-group .panel + .panel { + margin-top: 5px; +} +.panel-group .panel-heading { + border-bottom: 0; +} +.panel-group .panel-heading + .panel-collapse > .panel-body { + border-top: 1px solid #dddddd; +} +.panel-group .panel-footer { + border-top: 0; +} +.panel-group .panel-footer + .panel-collapse .panel-body { + border-bottom: 1px solid #dddddd; +} +.panel-default { + border-color: #dddddd; +} +.panel-default > .panel-heading { + color: white; + background-color: #0079c2; + border-color: #dddddd; +} +.panel-default > .panel-heading + .panel-collapse > .panel-body { + border-top-color: #dddddd; +} +.panel-default > .panel-heading .badge { + color: #f5f5f5; + background-color: #333333; +} +.panel-default > .panel-footer + .panel-collapse > .panel-body { + border-bottom-color: #dddddd; +} +.panel-primary { + border-color: #0079c2; +} +.panel-primary > .panel-heading { + color: #ffffff; + background-color: #0079c2; + border-color: #0079c2; +} +.panel-primary > .panel-heading + .panel-collapse > .panel-body { + border-top-color: #0079c2; +} +.panel-primary > .panel-heading .badge { + color: #0079c2; + background-color: #ffffff; +} +.panel-primary > .panel-footer + .panel-collapse > .panel-body { + border-bottom-color: #0079c2; +} +.panel-success { + border-color: #d6e9c6; +} +.panel-success > .panel-heading { + color: #3c763d; + background-color: #dff0d8; + border-color: #d6e9c6; +} +.panel-success > .panel-heading + .panel-collapse > .panel-body { + border-top-color: #d6e9c6; +} +.panel-success > .panel-heading .badge { + color: #dff0d8; + background-color: #3c763d; +} +.panel-success > .panel-footer + .panel-collapse > .panel-body { + border-bottom-color: #d6e9c6; +} +.panel-info { + border-color: #bce8f1; +} +.panel-info > .panel-heading { + color: #31708f; + background-color: #d9edf7; + border-color: #bce8f1; +} +.panel-info > .panel-heading + .panel-collapse > .panel-body { + border-top-color: #bce8f1; +} +.panel-info > .panel-heading .badge { + color: #d9edf7; + background-color: #31708f; +} +.panel-info > .panel-footer + .panel-collapse > .panel-body { + border-bottom-color: #bce8f1; +} +.panel-warning { + border-color: #faebcc; +} +.panel-warning > .panel-heading { + color: #8a6d3b; + background-color: #fcf8e3; + border-color: #faebcc; +} +.panel-warning > .panel-heading + .panel-collapse > .panel-body { + border-top-color: #faebcc; +} +.panel-warning > .panel-heading .badge { + color: #fcf8e3; + background-color: #8a6d3b; +} +.panel-warning > .panel-footer + .panel-collapse > .panel-body { + border-bottom-color: #faebcc; +} +.panel-danger { + border-color: #ebccd1; +} +.panel-danger > .panel-heading { + color: #a94442; + background-color: #f2dede; + border-color: #ebccd1; +} +.panel-danger > .panel-heading + .panel-collapse > .panel-body { + border-top-color: #ebccd1; +} +.panel-danger > .panel-heading .badge { + color: #f2dede; + background-color: #a94442; +} +.panel-danger > .panel-footer + .panel-collapse > .panel-body { + border-bottom-color: #ebccd1; +} +.embed-responsive { + position: relative; + display: block; + height: 0; + padding: 0; + overflow: hidden; +} +.embed-responsive .embed-responsive-item, +.embed-responsive iframe, +.embed-responsive embed, +.embed-responsive object { + position: absolute; + top: 0; + left: 0; + bottom: 0; + height: 100%; + width: 100%; + border: 0; +} +.embed-responsive.embed-responsive-16by9 { + padding-bottom: 56.25%; +} +.embed-responsive.embed-responsive-4by3 { + padding-bottom: 75%; +} +.well { + min-height: 20px; + padding: 19px; + margin-bottom: 20px; + background-color: #f5f5f5; + border: 1px solid #e3e3e3; + border-radius: 4px; + -webkit-box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.05); + box-shadow: inset 0 1px 1px rgba(0, 0, 0, 0.05); +} +.well blockquote { + border-color: #ddd; + border-color: rgba(0, 0, 0, 0.15); +} +.well-lg { + padding: 24px; + border-radius: 6px; +} +.well-sm { + padding: 9px; + border-radius: 3px; +} +.close { + float: right; + font-size: 21px; + font-weight: bold; + line-height: 1; + color: #000000; + text-shadow: 0 1px 0 #ffffff; + opacity: 0.2; + filter: alpha(opacity=20); +} +.close:hover, +.close:focus { + color: #000000; + text-decoration: none; + cursor: pointer; + opacity: 0.5; + filter: alpha(opacity=50); +} +button.close { + padding: 0; + cursor: pointer; + background: transparent; + border: 0; + -webkit-appearance: none; +} +.modal-open { + overflow: hidden; +} +.modal { + display: none; + overflow: hidden; + position: fixed; + top: 0; + right: 0; + bottom: 0; + left: 0; + z-index: 1050; + -webkit-overflow-scrolling: touch; + outline: 0; +} +.modal.fade .modal-dialog { + -webkit-transform: translate3d(0, -25%, 0); + transform: translate3d(0, -25%, 0); + -webkit-transition: -webkit-transform 0.3s ease-out; + -moz-transition: -moz-transform 0.3s ease-out; + -o-transition: -o-transform 0.3s ease-out; + transition: transform 0.3s ease-out; +} +.modal.in .modal-dialog { + -webkit-transform: translate3d(0, 0, 0); + transform: translate3d(0, 0, 0); +} +.modal-open .modal { + overflow-x: hidden; + overflow-y: auto; +} +.modal-dialog { + position: relative; + width: auto; + margin: 10px; +} +.modal-content { + position: relative; + background-color: #ffffff; + border: 1px solid #999999; + border: 1px solid rgba(0, 0, 0, 0.2); + border-radius: 6px; + -webkit-box-shadow: 0 3px 9px rgba(0, 0, 0, 0.5); + box-shadow: 0 3px 9px rgba(0, 0, 0, 0.5); + background-clip: padding-box; + outline: 0; +} +.modal-backdrop { + position: fixed; + top: 0; + right: 0; + bottom: 0; + left: 0; + z-index: 1040; + background-color: #000000; +} +.modal-backdrop.fade { + opacity: 0; + filter: alpha(opacity=0); +} +.modal-backdrop.in { + opacity: 0.5; + filter: alpha(opacity=50); +} +.modal-header { + padding: 15px; + border-bottom: 1px solid #e5e5e5; + min-height: 16.42857143px; +} +.modal-header .close { + margin-top: -2px; +} +.modal-title { + margin: 0; + line-height: 1.42857143; +} +.modal-body { + position: relative; + padding: 15px; +} +.modal-footer { + padding: 15px; + text-align: right; + border-top: 1px solid #e5e5e5; +} +.modal-footer .btn + .btn { + margin-left: 5px; + margin-bottom: 0; +} +.modal-footer .btn-group .btn + .btn { + margin-left: -1px; +} +.modal-footer .btn-block + .btn-block { + margin-left: 0; +} +.modal-scrollbar-measure { + position: absolute; + top: -9999px; + width: 50px; + height: 50px; + overflow: scroll; +} +@media (min-width: 768px) { + .modal-dialog { + width: 600px; + margin: 30px auto; + } + .modal-content { + -webkit-box-shadow: 0 5px 15px rgba(0, 0, 0, 0.5); + box-shadow: 0 5px 15px rgba(0, 0, 0, 0.5); + } + .modal-sm { + width: 300px; + } +} +@media (min-width: 992px) { + .modal-lg { + width: 900px; + } +} +.tooltip { + position: absolute; + z-index: 1070; + display: block; + visibility: visible; + font-size: 12px; + line-height: 1.4; + opacity: 0; + filter: alpha(opacity=0); +} +.tooltip.in { + opacity: 0.9; + filter: alpha(opacity=90); +} +.tooltip.top { + margin-top: -3px; + padding: 5px 0; +} +.tooltip.right { + margin-left: 3px; + padding: 0 5px; +} +.tooltip.bottom { + margin-top: 3px; + padding: 5px 0; +} +.tooltip.left { + margin-left: -3px; + padding: 0 5px; +} +.tooltip-inner { + max-width: 200px; + padding: 3px 8px; + color: #ffffff; + text-align: center; + text-decoration: none; + background-color: #000000; + border-radius: 4px; +} +.tooltip-arrow { + position: absolute; + width: 0; + height: 0; + border-color: transparent; + border-style: solid; +} +.tooltip.top .tooltip-arrow { + bottom: 0; + left: 50%; + margin-left: -5px; + border-width: 5px 5px 0; + border-top-color: #000000; +} +.tooltip.top-left .tooltip-arrow { + bottom: 0; + left: 5px; + border-width: 5px 5px 0; + border-top-color: #000000; +} +.tooltip.top-right .tooltip-arrow { + bottom: 0; + right: 5px; + border-width: 5px 5px 0; + border-top-color: #000000; +} +.tooltip.right .tooltip-arrow { + top: 50%; + left: 0; + margin-top: -5px; + border-width: 5px 5px 5px 0; + border-right-color: #000000; +} +.tooltip.left .tooltip-arrow { + top: 50%; + right: 0; + margin-top: -5px; + border-width: 5px 0 5px 5px; + border-left-color: #000000; +} +.tooltip.bottom .tooltip-arrow { + top: 0; + left: 50%; + margin-left: -5px; + border-width: 0 5px 5px; + border-bottom-color: #000000; +} +.tooltip.bottom-left .tooltip-arrow { + top: 0; + left: 5px; + border-width: 0 5px 5px; + border-bottom-color: #000000; +} +.tooltip.bottom-right .tooltip-arrow { + top: 0; + right: 5px; + border-width: 0 5px 5px; + border-bottom-color: #000000; +} +.popover { + position: absolute; + top: 0; + left: 0; + z-index: 1060; + display: none; + max-width: 276px; + padding: 1px; + text-align: left; + background-color: #ffffff; + background-clip: padding-box; + border: 1px solid #cccccc; + border: 1px solid rgba(0, 0, 0, 0.2); + border-radius: 6px; + -webkit-box-shadow: 0 5px 10px rgba(0, 0, 0, 0.2); + box-shadow: 0 5px 10px rgba(0, 0, 0, 0.2); + white-space: normal; +} +.popover.top { + margin-top: -10px; +} +.popover.right { + margin-left: 10px; +} +.popover.bottom { + margin-top: 10px; +} +.popover.left { + margin-left: -10px; +} +.popover-title { + margin: 0; + padding: 8px 14px; + font-size: 14px; + font-weight: normal; + line-height: 18px; + background-color: #f7f7f7; + border-bottom: 1px solid #ebebeb; + border-radius: 5px 5px 0 0; +} +.popover-content { + padding: 9px 14px; +} +.popover > .arrow, +.popover > .arrow:after { + position: absolute; + display: block; + width: 0; + height: 0; + border-color: transparent; + border-style: solid; +} +.popover > .arrow { + border-width: 11px; +} +.popover > .arrow:after { + border-width: 10px; + content: ""; +} +.popover.top > .arrow { + left: 50%; + margin-left: -11px; + border-bottom-width: 0; + border-top-color: #999999; + border-top-color: rgba(0, 0, 0, 0.25); + bottom: -11px; +} +.popover.top > .arrow:after { + content: " "; + bottom: 1px; + margin-left: -10px; + border-bottom-width: 0; + border-top-color: #ffffff; +} +.popover.right > .arrow { + top: 50%; + left: -11px; + margin-top: -11px; + border-left-width: 0; + border-right-color: #999999; + border-right-color: rgba(0, 0, 0, 0.25); +} +.popover.right > .arrow:after { + content: " "; + left: 1px; + bottom: -10px; + border-left-width: 0; + border-right-color: #ffffff; +} +.popover.bottom > .arrow { + left: 50%; + margin-left: -11px; + border-top-width: 0; + border-bottom-color: #999999; + border-bottom-color: rgba(0, 0, 0, 0.25); + top: -11px; +} +.popover.bottom > .arrow:after { + content: " "; + top: 1px; + margin-left: -10px; + border-top-width: 0; + border-bottom-color: #ffffff; +} +.popover.left > .arrow { + top: 50%; + right: -11px; + margin-top: -11px; + border-right-width: 0; + border-left-color: #999999; + border-left-color: rgba(0, 0, 0, 0.25); +} +.popover.left > .arrow:after { + content: " "; + right: 1px; + border-right-width: 0; + border-left-color: #ffffff; + bottom: -10px; +} +.carousel { + position: relative; +} +.carousel-inner { + position: relative; + overflow: hidden; + width: 100%; +} +.carousel-inner > .item { + display: none; + position: relative; + -webkit-transition: 0.6s ease-in-out left; + -o-transition: 0.6s ease-in-out left; + transition: 0.6s ease-in-out left; +} +.carousel-inner > .item > img, +.carousel-inner > .item > a > img { + line-height: 1; +} +.carousel-inner > .active, +.carousel-inner > .next, +.carousel-inner > .prev { + display: block; +} +.carousel-inner > .active { + left: 0; +} +.carousel-inner > .next, +.carousel-inner > .prev { + position: absolute; + top: 0; + width: 100%; +} +.carousel-inner > .next { + left: 100%; +} +.carousel-inner > .prev { + left: -100%; +} +.carousel-inner > .next.left, +.carousel-inner > .prev.right { + left: 0; +} +.carousel-inner > .active.left { + left: -100%; +} +.carousel-inner > .active.right { + left: 100%; +} +.carousel-control { + position: absolute; + top: 0; + left: 0; + bottom: 0; + width: 15%; + opacity: 0.5; + filter: alpha(opacity=50); + font-size: 20px; + color: #ffffff; + text-align: center; + text-shadow: 0 1px 2px rgba(0, 0, 0, 0.6); +} +.carousel-control.left { + background-image: -webkit-linear-gradient(left, rgba(0, 0, 0, 0.5) 0%, rgba(0, 0, 0, 0.0001) 100%); + background-image: -o-linear-gradient(left, rgba(0, 0, 0, 0.5) 0%, rgba(0, 0, 0, 0.0001) 100%); + background-image: linear-gradient(to right, rgba(0, 0, 0, 0.5) 0%, rgba(0, 0, 0, 0.0001) 100%); + background-repeat: repeat-x; + filter: progid:DXImageTransform.Microsoft.gradient(startColorstr='#80000000', endColorstr='#00000000', GradientType=1); +} +.carousel-control.right { + left: auto; + right: 0; + background-image: -webkit-linear-gradient(left, rgba(0, 0, 0, 0.0001) 0%, rgba(0, 0, 0, 0.5) 100%); + background-image: -o-linear-gradient(left, rgba(0, 0, 0, 0.0001) 0%, rgba(0, 0, 0, 0.5) 100%); + background-image: linear-gradient(to right, rgba(0, 0, 0, 0.0001) 0%, rgba(0, 0, 0, 0.5) 100%); + background-repeat: repeat-x; + filter: progid:DXImageTransform.Microsoft.gradient(startColorstr='#00000000', endColorstr='#80000000', GradientType=1); +} +.carousel-control:hover, +.carousel-control:focus { + outline: 0; + color: #ffffff; + text-decoration: none; + opacity: 0.9; + filter: alpha(opacity=90); +} +.carousel-control .icon-prev, +.carousel-control .icon-next, +.carousel-control .glyphicon-chevron-left, +.carousel-control .glyphicon-chevron-right { + position: absolute; + top: 50%; + z-index: 5; + display: inline-block; +} +.carousel-control .icon-prev, +.carousel-control .glyphicon-chevron-left { + left: 50%; + margin-left: -10px; +} +.carousel-control .icon-next, +.carousel-control .glyphicon-chevron-right { + right: 50%; + margin-right: -10px; +} +.carousel-control .icon-prev, +.carousel-control .icon-next { + width: 20px; + height: 20px; + margin-top: -10px; + font-family: serif; +} +.carousel-control .icon-prev:before { + content: '\2039'; +} +.carousel-control .icon-next:before { + content: '\203a'; +} +.carousel-indicators { + position: absolute; + bottom: 10px; + left: 50%; + z-index: 15; + width: 60%; + margin-left: -30%; + padding-left: 0; + list-style: none; + text-align: center; +} +.carousel-indicators li { + display: inline-block; + width: 10px; + height: 10px; + margin: 1px; + text-indent: -999px; + border: 1px solid #ffffff; + border-radius: 10px; + cursor: pointer; + background-color: #000 \9; + background-color: rgba(0, 0, 0, 0); +} +.carousel-indicators .active { + margin: 0; + width: 12px; + height: 12px; + background-color: #ffffff; +} +.carousel-caption { + position: absolute; + left: 15%; + right: 15%; + bottom: 20px; + z-index: 10; + padding-top: 20px; + padding-bottom: 20px; + color: #ffffff; + text-align: center; + text-shadow: 0 1px 2px rgba(0, 0, 0, 0.6); +} +.carousel-caption .btn { + text-shadow: none; +} +@media screen and (min-width: 768px) { + .carousel-control .glyphicon-chevron-left, + .carousel-control .glyphicon-chevron-right, + .carousel-control .icon-prev, + .carousel-control .icon-next { + width: 30px; + height: 30px; + margin-top: -15px; + font-size: 30px; + } + .carousel-control .glyphicon-chevron-left, + .carousel-control .icon-prev { + margin-left: -15px; + } + .carousel-control .glyphicon-chevron-right, + .carousel-control .icon-next { + margin-right: -15px; + } + .carousel-caption { + left: 20%; + right: 20%; + padding-bottom: 30px; + } + .carousel-indicators { + bottom: 20px; + } +} +.clearfix:before, +.clearfix:after, +.dl-horizontal dd:before, +.dl-horizontal dd:after, +.container:before, +.container:after, +.container-fluid:before, +.container-fluid:after, +.row:before, +.row:after, +.form-horizontal .form-group:before, +.form-horizontal .form-group:after, +.btn-toolbar:before, +.btn-toolbar:after, +.btn-group-vertical > .btn-group:before, +.btn-group-vertical > .btn-group:after, +.nav:before, +.nav:after, +.navbar:before, +.navbar:after, +.navbar-header:before, +.navbar-header:after, +.navbar-collapse:before, +.navbar-collapse:after, +.pager:before, +.pager:after, +.panel-body:before, +.panel-body:after, +.modal-footer:before, +.modal-footer:after { + content: " "; + display: table; +} +.clearfix:after, +.dl-horizontal dd:after, +.container:after, +.container-fluid:after, +.row:after, +.form-horizontal .form-group:after, +.btn-toolbar:after, +.btn-group-vertical > .btn-group:after, +.nav:after, +.navbar:after, +.navbar-header:after, +.navbar-collapse:after, +.pager:after, +.panel-body:after, +.modal-footer:after { + clear: both; +} +.center-block { + display: block; + margin-left: auto; + margin-right: auto; +} +.pull-right { + float: right !important; +} +.pull-left { + float: left !important; +} +.hide { + display: none !important; +} +.show { + display: block !important; +} +.invisible { + visibility: hidden; +} +.text-hide { + font: 0/0 a; + color: transparent; + text-shadow: none; + background-color: transparent; + border: 0; +} +.hidden { + display: none !important; + visibility: hidden !important; +} +.affix { + position: fixed; + -webkit-transform: translate3d(0, 0, 0); + transform: translate3d(0, 0, 0); +} +@-ms-viewport { + width: device-width; +} +.visible-xs, +.visible-sm, +.visible-md, +.visible-lg { + display: none !important; +} +.visible-xs-block, +.visible-xs-inline, +.visible-xs-inline-block, +.visible-sm-block, +.visible-sm-inline, +.visible-sm-inline-block, +.visible-md-block, +.visible-md-inline, +.visible-md-inline-block, +.visible-lg-block, +.visible-lg-inline, +.visible-lg-inline-block { + display: none !important; +} +@media (max-width: 767px) { + .visible-xs { + display: block !important; + } + table.visible-xs { + display: table; + } + tr.visible-xs { + display: table-row !important; + } + th.visible-xs, + td.visible-xs { + display: table-cell !important; + } +} +@media (max-width: 767px) { + .visible-xs-block { + display: block !important; + } +} +@media (max-width: 767px) { + .visible-xs-inline { + display: inline !important; + } +} +@media (max-width: 767px) { + .visible-xs-inline-block { + display: inline-block !important; + } +} +@media (min-width: 768px) and (max-width: 991px) { + .visible-sm { + display: block !important; + } + table.visible-sm { + display: table; + } + tr.visible-sm { + display: table-row !important; + } + th.visible-sm, + td.visible-sm { + display: table-cell !important; + } +} +@media (min-width: 768px) and (max-width: 991px) { + .visible-sm-block { + display: block !important; + } +} +@media (min-width: 768px) and (max-width: 991px) { + .visible-sm-inline { + display: inline !important; + } +} +@media (min-width: 768px) and (max-width: 991px) { + .visible-sm-inline-block { + display: inline-block !important; + } +} +@media (min-width: 992px) and (max-width: 1199px) { + .visible-md { + display: block !important; + } + table.visible-md { + display: table; + } + tr.visible-md { + display: table-row !important; + } + th.visible-md, + td.visible-md { + display: table-cell !important; + } +} +@media (min-width: 992px) and (max-width: 1199px) { + .visible-md-block { + display: block !important; + } +} +@media (min-width: 992px) and (max-width: 1199px) { + .visible-md-inline { + display: inline !important; + } +} +@media (min-width: 992px) and (max-width: 1199px) { + .visible-md-inline-block { + display: inline-block !important; + } +} +@media (min-width: 1200px) { + .visible-lg { + display: block !important; + } + table.visible-lg { + display: table; + } + tr.visible-lg { + display: table-row !important; + } + th.visible-lg, + td.visible-lg { + display: table-cell !important; + } +} +@media (min-width: 1200px) { + .visible-lg-block { + display: block !important; + } +} +@media (min-width: 1200px) { + .visible-lg-inline { + display: inline !important; + } +} +@media (min-width: 1200px) { + .visible-lg-inline-block { + display: inline-block !important; + } +} +@media (max-width: 767px) { + .hidden-xs { + display: none !important; + } +} +@media (min-width: 768px) and (max-width: 991px) { + .hidden-sm { + display: none !important; + } +} +@media (min-width: 992px) and (max-width: 1199px) { + .hidden-md { + display: none !important; + } +} +@media (min-width: 1200px) { + .hidden-lg { + display: none !important; + } +} +.visible-print { + display: none !important; +} +@media print { + .visible-print { + display: block !important; + } + table.visible-print { + display: table; + } + tr.visible-print { + display: table-row !important; + } + th.visible-print, + td.visible-print { + display: table-cell !important; + } +} +.visible-print-block { + display: none !important; +} +@media print { + .visible-print-block { + display: block !important; + } +} +.visible-print-inline { + display: none !important; +} +@media print { + .visible-print-inline { + display: inline !important; + } +} +.visible-print-inline-block { + display: none !important; +} +@media print { + .visible-print-inline-block { + display: inline-block !important; + } +} +@media print { + .hidden-print { + display: none !important; + } +} diff --git a/docs/apollo2/resources/customdoxygen.css b/docs/apollo2/resources/customdoxygen.css new file mode 100644 index 0000000..76d2908 --- /dev/null +++ b/docs/apollo2/resources/customdoxygen.css @@ -0,0 +1,1388 @@ +/* The standard CSS for doxygen 1.8.4 */ + +body, table, div, p, dl { + // font: 400 14px/22px Roboto,sans-serif; + font: 13px "Lucida Grande", "Lucida Sans Unicode", Helvetica, Arial, Verdana, sans-serif; +} + +table { + word-wrap: break-word; +} + +/* @group Heading Levels */ + +h3{ + padding-left: 10px; +} + +p{ + padding-left: 10px; +} + + +h1.groupheader { + font-size: 28px; + //font-size: 150%; + +} + +.title { + //font: 400 14px/28px Roboto,sans-serif; + font-family: "Lucida Grande", "Lucida Sans Unicode", Helvetica, Arial, Verdana, sans-serif; + font-size: 24px; + font-weight: normal; + margin: 10px 2px; +} + +h2.groupheader { + //border-bottom: 1px solid #879ECB; + border-bottom: none; + //color: #354C7B; + color: rgb(60, 76, 108); + font-size: 24px; + font-weight: normal; + //margin-top: 1.75em; + margin: 42px 0px 20px 0px; + margin-bottom: 20px; + //padding-top: 8px; + //padding-bottom: 4px; + padding: 0px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + //margin-right: 15px; + //margin: 42px 0px 20px 0px; +} + +h1 { + font-size: 28px; +} + +h2 { + color: rgb(60, 76, 108); + font-size: 24px; + font-weight: normal; + margin: 42px 0px 20px 0px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #0079c2; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #00395c; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + //font-family: "Courier New", courier, monospace; + font-family: Courier, Consolas, monospace; + //font-weight: bold; + font-weight: normal; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #0079c2; +} + +a.codeRef, a.codeRef:visited { + color: #0079c2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + //padding: 0px; + //padding: 4px 6px; + //margin: 0px; + //background-color: #FBFCFD; + //border: 1px solid #C4CFE5; + + padding: 6px 10px; + margin: 15px 0px; + border: solid 1px rgb(221, 221, 221); + border-radius: 3px; + + background-color: rgb(248, 248, 248); +} + +div.line { + //font-family: monospace, fixed; + font-family: Consolas, "Liberation Mono", Courier, monospace; + font-size: 13px; + min-height: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + //margin-left: 16px; + //margin-top: 12px; + margin-left: 0px; + margin-top: 9px; + margin-bottom: 4.7px; + + font-size: 19px; + //font-weight: bold; + font-weight: normal; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9CAFD4; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + //border-top: 1px solid #4A6AAA; + border-top: 1px solid #444; +} + +hr.footer { + height: 0px; + border-top: 3px solid #444; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + //background-color: #F9FAFC; + background-color: white; + border: none; + margin: 4px; + padding: 1px 0 0 8px; + + //font-family: "Courier New", courier, monospace; + font-family: Courier, Consolas, monospace; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; + + font-family: "Lucida Grande", "Lucida Sans Unicode", Helvetica, Arial, Verdana, sans-serif; + font-style: italic; +} + +.memSeparator { + //border-bottom: 1px solid #DEE4F0; + border-bottom: none; + line-height: 8px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + //font-family: "Courier New", courier, monospace; + font-family: Courier, Consolas, monospace; + font-weight: bold; + //margin-left: 6px; + margin-left: 0px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border: none; + //border-top: 1px solid #A8B8D9; + //border-left: 1px solid #A8B8D9; + //border-right: 1px solid #A8B8D9; + //padding: 6px 0px 6px 0px; + padding: 6px; + //color: #253555; + color: black; + font-weight: bold; + //text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-shadow: 0px 1px 1px rgba(0, 0, 0, 0.3); + //background-image:url('nav_f.png'); + background-image: none; + //background-repeat:repeat-x; + //background-color: #E2E8F2; + //background-color: rgb(235, 238, 241); + background-color: #ccc; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + //border-top-right-radius: 4px; + //border-top-left-radius: 4px; + border-top-right-radius: 0px; + border-top-left-radius: 0px; + /* firefox specific markup */ + //-moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + //-moz-border-radius-topright: 4px; + //-moz-border-radius-topleft: 4px; + -moz-box-shadow: none; + -moz-border-radius-topright: 0px; + -moz-border-radius-topleft: 0px; + /* webkit specific markup */ + //-webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + //-webkit-border-top-right-radius: 4px; + //-webkit-border-top-left-radius: 4px; + -webkit-box-shadow: none; + -webkit-border-top-right-radius: 0px; + -webkit-border-top-left-radius: 0px; + +} + +.memdoc, dl.reflist dd { + border: none; + //border-bottom: 1px solid #A8B8D9; + //border-left: 1px solid #A8B8D9; + //border-right: 1px solid #A8B8D9; + padding: 6px; + background-color: #FBFCFD; + border-top-width: 0; + //background-image:url('nav_g.png'); + background-image: none; + //background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + //border-bottom-left-radius: 4px; + //border-bottom-right-radius: 4px; + //box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-bottom-left-radius: 0px; + border-bottom-right-radius: 0px; + box-shadow: none; + /* firefox specific markup */ + //-moz-border-radius-bottomleft: 4px; + //-moz-border-radius-bottomright: 4px; + //-moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-bottomleft: 0px; + -moz-border-radius-bottomright: 0px; + -moz-box-shadow: none; + /* webkit specific markup */ + //-webkit-border-bottom-left-radius: 4px; + //-webkit-border-bottom-right-radius: 4px; + //-webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-bottom-left-radius: 0px; + -webkit-border-bottom-right-radius: 0px; + -webkit-box-shadow: none; +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + //color: #602020; + color: rgb(37, 53, 85); + white-space: nowrap; +} +.paramname em { + font-style: italic; + font-weight: normal; + //font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + //font-weight: bold; + //font-family: "Courier New", courier, monospace; + font-family: Courier, Consolas, monospace; + font-style: italic; + font-weight: normal; + text-shadow: rgba(0, 0, 0, 0.3) 0px 1px 1px; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #728DC1; + border-top:1px solid #5373B4; + border-left:1px solid #5373B4; + border-right:1px solid #C4CFE5; + border-bottom:1px solid #C4CFE5; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3D578C; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A8B8D9; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A8B8D9; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + font-size: 90%; + color: #253555; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A8B8D9; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #283A5D; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + //background-image:url('nav_h.png'); + //background-repeat:repeat-x; + //background-color: #F9FAFC; + background-image: none; + background-color: white; + margin: 0px; + //border-bottom: 1px solid #C4CFE5; + border: none; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + //margin-left:-7px; + margin-left: 0px; + padding: 6px 0px 3px 8px; + //padding-left: 8px; + border-left: 6px solid; + border-color: #D0C000; + background-color: #fff799 +} + +dl.warning, dl.attention +{ + //margin-left:-7px; + //padding-left: 3px; + margin-left: 0px; + padding: 6px 0px 3px 8px; + + //border-left:4px solid; + border-left: 6px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + //margin-left:-7px; + //padding-left: 3px; + margin-left: 0px; + padding: 6px 0px 3px 8px; + //border-left: 4px solid; + border-left: 6px solid; + border-color: #505050; +} + +dl.deprecated dt a.el +{ + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +} + +dl.todo +{ + //margin-left:-7px; + //padding-left: 3px; + margin-left: 0px; + padding: 6px 0px 3px 8px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #90A5CE; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#334975; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D8DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4665A2; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 42px; + margin-bottom: 20px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + + +.tabs, .tabs2, .tabs3 { + background-image: none; + background-color: #0079c2; + color: white; + +} + +.tabs2 { + background-color: #0069a8; +} + +.tabs3 { + background-color: #00598f; +} + + + +.tablist li { + background-image: none; +} + + +.tablist a { + background-image: none; + color: white; + //text-shadow: none; + text-shadow: rgba(0, 0, 0, 0.6) 0px 2px 2px; +} + + +.tablist a:hover { + background-image: none; + text-shadow: none; +} + + +.tablist li.current a { + background-image: none; + //color: #ccc; + //text-shadow: none; +} + + +.tabs li.current { + background-color: #80a3b7; + text-shadow: black; +} + +.tabs2 li.current { + background-color: #80a3b7; +} + + +.navpath { + border: none; +} + + +.navpath ul { + background-image: none; + background-color: #80a3b7; + border: none; +} + + +.navpath li { + background-image: none; +} + + +.navpath li.navelem a { + background-image: none; + color: white; + text-shadow: none; +} + + +.navpath li.navelem a:hover { + background-image: none; + color: white; + text-shadow: none; +} + diff --git a/docs/apollo2/resources/dynsections.js b/docs/apollo2/resources/dynsections.js new file mode 100644 index 0000000..5cb79e1 --- /dev/null +++ b/docs/apollo2/resources/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); 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text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/dts/apollo2/am_apollo2.h b/dts/apollo2/am_apollo2.h new file mode 100644 index 0000000..02b3a4a --- /dev/null +++ b/dts/apollo2/am_apollo2.h @@ -0,0 +1,193 @@ +//***************************************************************************** +// +//! @file am_apollo2.h +//! +//! @brief Top DTS Include for Apollo2 class devices. +//! +//! This file provides all bus addresses of an apollo2 device for device tree. +//! +//! @addtogroup hal +// +//! @defgroup apollo2 +//! @ingroup hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2025, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef AM_APOLLO2_H +#define AM_APOLLO2_H + +//----------------------------------------------------------------------------- +// Apollo2 Interrupt Numbers +//----------------------------------------------------------------------------- +#define APOLLO2_BROWNOUT_IRQ 0 +#define APOLLO2_WDT_IRQ 1 +#define APOLLO2_RTC_IRQ 2 // Part of Clock Control and RTC IRQ2 +#define APOLLO2_VCOMP_IRQ 3 +#define APOLLO2_IOSLAVE_IRQ 4 +#define APOLLO2_IOSLAVEACC_IRQ 5 // I2C/SPI Slave Register Access +#define APOLLO2_IOMSTR0_IRQ 6 // I2C/SPI Master0 +#define APOLLO2_IOMSTR1_IRQ 7 // I2C/SPI Master1 +#define APOLLO2_IOMSTR2_IRQ 8 // I2C/SPI Master2 +#define APOLLO2_IOMSTR3_IRQ 9 // I2C/SPI Master3 +#define APOLLO2_IOMSTR4_IRQ 10 // I2C/SPI Master4 +#define APOLLO2_IOMSTR5_IRQ 11 // I2C/SPI Master5 +#define APOLLO2_GPIO_IRQ 12 +#define APOLLO2_CTIMER_IRQ 13 // Counter/Timers +#define APOLLO2_UART0_IRQ 14 +#define APOLLO2_UART1_IRQ 15 +#define APOLLO2_ADC_IRQ 16 +#define APOLLO2_PDM_IRQ 17 +#define APOLLO2_STIMER_IRQ 18 // STimer Capture/Overflow +#define APOLLO2_STIMER_CMPR0_IRQ 19 // STimer Compare [0:7] starts at IRQ19 +#define APOLLO2_STIMER_CMPR1_IRQ 20 +#define APOLLO2_STIMER_CMPR2_IRQ 21 +#define APOLLO2_STIMER_CMPR3_IRQ 22 +#define APOLLO2_STIMER_CMPR4_IRQ 23 +#define APOLLO2_STIMER_CMPR5_IRQ 24 +#define APOLLO2_STIMER_CMPR6_IRQ 25 +#define APOLLO2_STIMER_CMPR7_IRQ 26 +#define APOLLO2_SW_INT0_IRQ 28 // SW INT[0-3] starts at IRQ28 +#define APOLLO2_SW_INT1_IRQ 29 +#define APOLLO2_SW_INT2_IRQ 30 +#define APOLLO2_SW_INT3_IRQ 31 +#define APOLLO2_MAX_IRQ 32 // Reflects max peripheral IRQ + 1 + +//----------------------------------------------------------------------------- +// Apollo2 Peripheral Base Addresses +//----------------------------------------------------------------------------- +#define APOLLO2_RSTGEN 40000000 // Reset / BoD Control +#define APOLLO2_CLKGEN 40004000 // Clock Generator / RTC +#define APOLLO2_CTIMER 40008000 // Timers +#define APOLLO2_VCOMP 4000c000 // Voltage Comparator +#define APOLLO2_GPIO 40010000 // GPIO Control +#define APOLLO2_APBDMA 40011000 +#define APOLLO2_CACHECTRL 40018000 // Flash Cache Control +#define APOLLO2_UART0 4001c000 +#define APOLLO2_UART1 4001d000 +#define APOLLO2_MCUCTRL 40020000 +#define APOLLO2_PWRCTRL 40021000 // Power Control +#define APOLLO2_WDT 40024000 // Watchdog Timer + +#define APOLLO2_IOS 50000000 // I2C/SPI Slave +#define APOLLO2_IOM0 50004000 // I2C/SPI Master0 +#define APOLLO2_IOM1 50005000 // I2C/SPI Master1 +#define APOLLO2_IOM2 50006000 // I2C/SPI Master2 +#define APOLLO2_IOM3 50007000 // I2C/SPI Master3 +#define APOLLO2_IOM4 50008000 // I2C/SPI Master4 +#define APOLLO2_IOM5 50009000 // I2C/SPI Master5 +#define APOLLO2_ADC 50010000 +#define APOLLO2_PDM 50011000 +#define APOLLO2_FLASH_OTP 50020000 + +#define APOLLO2_RSTGEN_BASE 0x40000000UL +#define APOLLO2_CLKGEN_BASE 0x40004000UL +#define APOLLO2_CTIMER_BASE 0x40008000UL +#define APOLLO2_VCOMP_BASE 0x4000c000UL +#define APOLLO2_GPIO_BASE 0x40010000UL +#define APOLLO2_APBDMA_BASE 0x40011000UL +#define APOLLO2_CACHECTRL_BASE 0x40018000UL +#define APOLLO2_UART0_BASE 0x4001c000UL +#define APOLLO2_UART1_BASE 0x4001d000UL +#define APOLLO2_MCUCTRL_BASE 0x40020000UL +#define APOLLO2_PWRCTRL_BASE 0x40021000UL +#define APOLLO2_WDT_BASE 0x40024000UL + +#define APOLLO2_IOS_BASE 0x50000000UL +#define APOLLO2_IOM0_BASE 0x50004000UL +#define APOLLO2_IOM1_BASE 0x50005000UL +#define APOLLO2_IOM2_BASE 0x50006000UL +#define APOLLO2_IOM3_BASE 0x50007000UL +#define APOLLO2_IOM4_BASE 0x50008000UL +#define APOLLO2_IOM5_BASE 0x50009000UL +#define APOLLO2_ADC_BASE 0x50010000UL +#define APOLLO2_PDM_BASE 0x50011000UL +#define APOLLO2_FLASH_OTP_BASE 0x50020000UL + +//----------------------------------------------------------------------------- +// Apollo2 Peripheral Sizes +//----------------------------------------------------------------------------- +#define APOLLO2_RSTGEN_SIZE 0x400UL // 0x400003FF - 0x40000000 + 1 = 0x400 +#define APOLLO2_CLKGEN_SIZE 0x400UL // 0x400041FF - 0x40004000 + 1 = 0x200 (using 0x400 boundary) +#define APOLLO2_CTIMER_SIZE 0x400UL // 0x400083FF - 0x40008000 + 1 = 0x400 +#define APOLLO2_VCOMP_SIZE 0x400UL // 0x4000C3FF - 0x4000C000 + 1 = 0x400 +#define APOLLO2_GPIO_SIZE 0x400UL // 0x400103FF - 0x40010000 + 1 = 0x400 +#define APOLLO2_APBDMA_SIZE 0x400UL +#define APOLLO2_CACHECTRL_SIZE 0x400UL // 0x40018FFF - 0x40018000 + 1 = 0x1000 (using 0x400 boundary) +#define APOLLO2_UART0_SIZE 0x400UL // 0x4001C3FF - 0x4001C000 + 1 = 0x400 +#define APOLLO2_UART1_SIZE 0x400UL // 0x4001D3FF - 0x4001D000 + 1 = 0x400 +#define APOLLO2_MCUCTRL_SIZE 0x400UL // 0x400203FF - 0x40020000 + 1 = 0x400 +#define APOLLO2_PWRCTRL_SIZE 0x400UL // 0x400213FF - 0x40021000 + 1 = 0x400 +#define APOLLO2_WDT_SIZE 0x400UL // 0x400243FF - 0x40024000 + 1 = 0x400 + +#define APOLLO2_IOS_SIZE 0x400UL // 0x500003FF - 0x50000000 + 1 = 0x400 +#define APOLLO2_IOM0_SIZE 0x400UL // 0x500043FF - 0x50004000 + 1 = 0x400 +#define APOLLO2_IOM1_SIZE 0x400UL // 0x500053FF - 0x50005000 + 1 = 0x400 +#define APOLLO2_IOM2_SIZE 0x400UL // 0x500063FF - 0x50006000 + 1 = 0x400 +#define APOLLO2_IOM3_SIZE 0x400UL // 0x500073FF - 0x50007000 + 1 = 0x400 +#define APOLLO2_IOM4_SIZE 0x400UL // 0x500083FF - 0x50008000 + 1 = 0x400 +#define APOLLO2_IOM5_SIZE 0x400UL // 0x500093FF - 0x50009000 + 1 = 0x400 +#define APOLLO2_ADC_SIZE 0x400UL // 0x500103FF - 0x50010000 + 1 = 0x400 +#define APOLLO2_PDM_SIZE 0x400UL // 0x500113FF - 0x50011000 + 1 = 0x400 +#define APOLLO2_FLASH_OTP_SIZE 0x10000UL // 0x5002FFFF - 0x50020000 + 1 = 0x10000 + +//----------------------------------------------------------------------------- +// Apollo2 Memory Regions +//----------------------------------------------------------------------------- +#define APOLLO2_SRAM 10000000 // Low-power SRAM starts at 0x10000000 +#define APOLLO2_SRAM_BASE 0x10000000UL +#define APOLLO2_SRAM_SIZE 0x40000UL // 256KB = 0x40000 bytes + +#define APOLLO2_FLASH 0 // Flash Memory starts at 0x00000000 +#define APOLLO2_FLASH_BASE 0x00000000UL +#define APOLLO2_FLASH_SIZE 0x100000UL // 1MB = 0x100000 bytes + +#define APOLLO2_FLASH_BOOT 0 +#define APOLLO2_FLASH_BOOT_BASE 0x00000000UL +#define APOLLO2_FLASH_BOOT_SIZE 0x8000UL + +#define APOLLO2_FLASH_APP 8000 +#define APOLLO2_FLASH_APP_BASE 0x00008000UL +#define APOLLO2_FLASH_APP_SIZE 0xf8000UL + +#endif // AM_APOLLO2_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/CMakeLists.txt b/mcu/CMakeLists.txt index 1706ddc..36f522f 100644 --- a/mcu/CMakeLists.txt +++ b/mcu/CMakeLists.txt @@ -16,4 +16,7 @@ elseif(CONFIG_SOC_APOLLO3 OR CONFIG_SOC_APOLLO3_BLUE) elseif(CONFIG_SOC_APOLLO510) zephyr_include_directories(apollo510) add_subdirectory(apollo510) +elseif(CONFIG_SOC_APOLLO2) + zephyr_include_directories(apollo2) + add_subdirectory(apollo2) endif() diff --git a/mcu/am_sdk_version.h b/mcu/am_sdk_version.h index 67719b4..d80e795 100644 --- a/mcu/am_sdk_version.h +++ b/mcu/am_sdk_version.h @@ -73,6 +73,10 @@ extern "C" #define AM_HAL_VERSION_MAJ 5 #define AM_HAL_VERSION_MIN 0 #define AM_HAL_VERSION_REV 0 +#elif defined(AM_PART_APOLLO2_API) +#define AM_HAL_VERSION_MAJ 2 +#define AM_HAL_VERSION_MIN 5 +#define AM_HAL_VERSION_REV 1 #else #define AM_HAL_VERSION_MAJ 0 #define AM_HAL_VERSION_MIN 0 diff --git a/mcu/apollo2/CMakeLists.txt b/mcu/apollo2/CMakeLists.txt new file mode 100644 index 0000000..fea4f12 --- /dev/null +++ b/mcu/apollo2/CMakeLists.txt @@ -0,0 +1,60 @@ +# Ambiq HAL +# +# Copyright (c) 2024 Ambiq Micro Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +# Sources and headers necessary for every build. +# These contain definitions and implementation used mostly for +# initializing the SoC, and therefore are always required. +zephyr_library() +zephyr_library_sources(hal/am_hal_global.c) +zephyr_library_sources(hal/am_hal_pwrctrl.c) +zephyr_library_sources(hal/am_hal_queue.c) +zephyr_library_sources(hal/am_hal_cachectrl.c) +zephyr_library_sources(hal/am_hal_interrupt.c) +zephyr_library_sources(hal/am_hal_flash.c) +zephyr_library_sources(hal/am_hal_rtc.c) +zephyr_library_sources(hal/am_hal_mcuctrl.c) +zephyr_library_sources(hal/am_hal_reset.c) +zephyr_library_sources(hal/am_hal_clkgen.c) +zephyr_library_sources(hal/am_hal_sysctrl.c) +zephyr_library_sources(hal/am_hal_debug.c) +zephyr_library_sources(hal/am_hal_itm.c) +zephyr_library_sources(hal/am_hal_systick.c) +zephyr_library_sources(hal/am_hal_uart.c) +zephyr_library_sources(hal/am_hal_ctimer.c) + +# Optional HAL modules +if(CONFIG_AMBIQ_HAL_USE_GPIO) + zephyr_library_sources(hal/am_hal_gpio.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_STIMER) + zephyr_library_sources(hal/am_hal_stimer.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_TIMER) + zephyr_library_sources(hal/am_hal_ctimer.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_WDT) + zephyr_library_sources(hal/am_hal_wdt.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_I2C) + zephyr_library_sources(hal/am_hal_iom.c) + zephyr_library_sources(hal/am_hal_i2c_bit_bang.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_SPI) + zephyr_library_sources(hal/am_hal_iom.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_SPID) + zephyr_library_sources(hal/am_hal_ios.c) +endif() + +if(CONFIG_AMBIQ_HAL_USE_ADC) + zephyr_library_sources(hal/am_hal_adc.c) +endif() diff --git a/mcu/apollo2/Makefile b/mcu/apollo2/Makefile new file mode 100644 index 0000000..db735d9 --- /dev/null +++ b/mcu/apollo2/Makefile @@ -0,0 +1,52 @@ +#****************************************************************************** +# +# Makefile - Rules for building the libraries, examples and docs. +# +# Copyright (c) 2024, Ambiq Micro, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# This is part of revision release_sdk_3_2_0-dd5f40c14b of the AmbiqSuite Development Package. +# +#****************************************************************************** + + +SUBDIRS=$(dir $(wildcard */Makefile)) + +$(SUBDIRS):: + +$(MAKE) -C $@ $(MAKECMDGOALS) + +.PHONY: subdirs all clean +all subdirs clean: $(SUBDIRS) + +ifneq ($(SUBDIRSBUILD),) +.DEFAULT_GOAL := subdirs +else +.DEFAULT_GOAL := all +endif + diff --git a/mcu/apollo2/am_mcu_apollo.h b/mcu/apollo2/am_mcu_apollo.h new file mode 100644 index 0000000..b71a9ce --- /dev/null +++ b/mcu/apollo2/am_mcu_apollo.h @@ -0,0 +1,180 @@ +//***************************************************************************** +// +// am_mcu_apollo.h +//! @file +//! +//! @brief Top Include for Apollo2 class devices. +//! +//! This file provides all the includes necessary for an apollo device. +//! +//! @addtogroup hal Hardware Abstraction Layer (HAL) +// +//! @defgroup apollo2hal HAL for Apollo2 +//! @ingroup hal +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_MCU_APOLLO_H +#define AM_MCU_APOLLO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// AM_PART_APOLLO2_API indicates that this device uses the Apollo3 API. +// +//***************************************************************************** +#define AM_PART_APOLLO2_API 1 + + +//***************************************************************************** +// +// Define AM_CMSIS_REGS to indicate that AM_REGS registers are supported. +// +//***************************************************************************** +#define AM_CMSIS_REGS 1 // 0 = Use AM_REGS + +//***************************************************************************** +// +// C99 +// +//***************************************************************************** +#include +#include +#include +#include +#if AM_CMSIS_REGS +#include "apollo2.h" +#else +#ifdef __IAR_SYSTEMS_ICC__ +#include "intrinsics.h" // __CLZ() and other intrinsics +#endif // AM_CMSIS_REGS +#endif + +//***************************************************************************** +// +// Global HAL +// +//***************************************************************************** +// +// Define this macro to disable and remove parameter validation in functions +// throughout the HAL. +// +//#define AM_HAL_DISABLE_API_VALIDATION + +// +// Define the following macro to disable assert messaging. +// Defining this macro will result in smaller, more efficient HAL code, but +// will eliminate debug messaging. +// +//#define AM_HAL_DEBUG_NO_ASSERT + + +//***************************************************************************** +// +// Registers +// +//***************************************************************************** +#include "regs/am_reg_base_addresses.h" + +#include "regs/am_reg_macros.h" + +#include "regs/am_reg_adc.h" +#include "regs/am_reg_cachectrl.h" +#include "regs/am_reg_clkgen.h" +#include "regs/am_reg_ctimer.h" +#include "regs/am_reg_gpio.h" +#include "regs/am_reg_iomstr.h" +#include "regs/am_reg_ioslave.h" +#include "regs/am_reg_itm.h" +#include "regs/am_reg_jedec.h" +#include "regs/am_reg_mcuctrl.h" +#include "regs/am_reg_nvic.h" +#include "regs/am_reg_pdm.h" +#include "regs/am_reg_pwrctrl.h" +#include "regs/am_reg_rstgen.h" +#include "regs/am_reg_rtc.h" +#include "regs/am_reg_sysctrl.h" +#include "regs/am_reg_systick.h" +#include "regs/am_reg_tpiu.h" +#include "regs/am_reg_uart.h" +#include "regs/am_reg_vcomp.h" +#include "regs/am_reg_wdt.h" + +//***************************************************************************** +// +// HAL +// +//***************************************************************************** +#include "hal/am_hal_adc.h" +#include "hal/am_hal_cachectrl.h" +#include "hal/am_hal_clkgen.h" +#include "hal/am_hal_ctimer.h" +#include "hal/am_hal_debug.h" +#include "hal/am_hal_flash.h" +#include "hal/am_hal_global.h" +#include "hal/am_hal_gpio.h" +#include "hal/am_hal_i2c_bit_bang.h" +#include "hal/am_hal_interrupt.h" +#include "hal/am_hal_iom.h" +#include "hal/am_hal_ios.h" +#include "hal/am_hal_itm.h" +#include "hal/am_hal_mcuctrl.h" +#include "hal/am_hal_otp.h" +#include "hal/am_hal_pdm.h" +#include "hal/am_hal_pin.h" +#include "hal/am_hal_pwrctrl.h" +#include "hal/am_hal_queue.h" +#include "hal/am_hal_reset.h" +#include "hal/am_hal_rtc.h" +#include "hal/am_hal_stimer.h" +#include "hal/am_hal_sysctrl.h" +#include "hal/am_hal_systick.h" +#include "hal/am_hal_tpiu.h" +#include "hal/am_hal_uart.h" +#include "hal/am_hal_vcomp.h" +#include "hal/am_hal_wdt.h" + +#ifdef __cplusplus +} +#endif + +#endif // AM_MCU_APOLLO_H + diff --git a/mcu/apollo2/hal/Makefile b/mcu/apollo2/hal/Makefile new file mode 100644 index 0000000..279ec5b --- /dev/null +++ b/mcu/apollo2/hal/Makefile @@ -0,0 +1,45 @@ +#****************************************************************************** +# +# Makefile - Rules for compiling +# +# Copyright (c) 2020, Ambiq Micro, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# This is part of revision 2.5.1 of the AmbiqSuite Development Package. +# +#****************************************************************************** + +# All makefiles use this to find the top level directory. +SWROOT?=../../.. + +# Include rules for building the HAL. +include $(SWROOT)/makedefs/am_hal.mk + +# Generate pin definitions for apollo2. +CHIP_GENERATION = 2 diff --git a/mcu/apollo2/hal/am_hal_adc.c b/mcu/apollo2/hal/am_hal_adc.c new file mode 100644 index 0000000..bb405e1 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_adc.c @@ -0,0 +1,556 @@ +//***************************************************************************** +// +// am_hal_adc.c +//! @file +//! +//! @brief Functions for interfacing with the Analog to Digital Converter. +//! +//! @addtogroup adc2 Analog-to-Digital Converter (ADC) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Private SRAM view of temperature trims. +//! +//! This static SRAM union is private to the ADC HAL functions. +// +//***************************************************************************** +static union +{ + //! These trim values are loaded as uint32_t values. + struct + { + //! Temperature of the package test head (in degrees Kelvin) + uint32_t ui32CalibrationTemperature; + + //! Voltage corresponding to temperature measured on test head. + uint32_t ui32CalibrationVoltage; + + //! ADC offset voltage measured on the package test head. + uint32_t ui32CalibrationOffset; + + //! Flag if default (guess) or measured. + bool bMeasured; + } ui32; + //! These trim values are accessed as floats when used in temp calculations. + struct + { + //! Temperature of the package test head in degrees Kelvin + float fCalibrationTemperature; + + //! Voltage corresponding to temperature measured on test head. + float fCalibrationVoltage; + + //! ADC offset voltage measured on the package test head. + float fCalibrationOffset; + + //! Flag if default (guess) or measured. + float fMeasuredFlag; + } flt; +} priv_temp_trims; + +//***************************************************************************** +// +//! @brief Configure the ADC. +//! +//! @param psConfig - pointer to the configuration structure for the ADC. +//! +//! This function may be used to perform the initial setup of the ADC based on +//! setting found in a configuration structure. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_config(am_hal_adc_config_t *psConfig) +{ + // + // Set general ADC configuration parameters. + // + AM_REG(ADC, CFG) = (psConfig->ui32Clock | + psConfig->ui32TriggerConfig | + psConfig->ui32Reference | + psConfig->ui32ClockMode | + psConfig->ui32PowerMode | + psConfig->ui32Repeat | + AM_REG_ADC_CFG_ADCEN(1)); + + // + // Grab the temperature trims. + // + priv_temp_trims.ui32.ui32CalibrationTemperature = + am_hal_flash_load_ui32(AM_HAL_ADC_CALIB_TEMP_ADDR); + priv_temp_trims.ui32.ui32CalibrationVoltage = + am_hal_flash_load_ui32(AM_HAL_ADC_CALIB_AMBIENT_ADDR); + priv_temp_trims.ui32.ui32CalibrationOffset = + am_hal_flash_load_ui32(AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR); + + if ( (priv_temp_trims.ui32.ui32CalibrationTemperature == 0xffffffff) || + (priv_temp_trims.ui32.ui32CalibrationVoltage == 0xffffffff) || + (priv_temp_trims.ui32.ui32CalibrationOffset == 0xffffffff) ) + { + // + // Since the device has not been calibrated on the tester, we'll load + // default calibration values. These default values should result + // in worst-case temperature measurements of +-6 degress C. + // + priv_temp_trims.flt.fCalibrationTemperature = AM_HAL_ADC_CALIB_TEMP_DEFAULT; + priv_temp_trims.flt.fCalibrationVoltage = AM_HAL_ADC_CALIB_AMBIENT_DEFAULT; + priv_temp_trims.flt.fCalibrationOffset = AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT; + priv_temp_trims.ui32.bMeasured = false; + } + else + { + priv_temp_trims.ui32.bMeasured = true; + } +} + +//***************************************************************************** +// +//! @brief Get the temperature trim parameters after configuring the ADC. +//! +//! @param pfTemp - pointer to a location to store the calibration temperature. +//! @param pfVoltage - pointer to a location to store the calibration voltage. +//! @param pfOffsetV - pointer to a location to store the calibration offset. +//! +//! This function may be used to access the actual temperature sensor trim +//! values from the private structure. +//! +//! WARNING: only call this after the ADC has been configured with +//! am_hal_adc_config. +//! +//! @return True if the returned values are actual calibrated values. +//! False if the returned values are default (non-measureed) values. +// +//***************************************************************************** +bool +am_hal_adc_temp_trims_get(float * pfTemp, float * pfVoltage, float * pfOffsetV) +{ + // + // Return trim temperature as a float, if you can. + // + if ( pfTemp != NULL ) + { + *pfTemp = priv_temp_trims.flt.fCalibrationTemperature; + } + + // + // Return trim voltage as a float, if you can. + // + if ( pfVoltage != NULL ) + { + *pfVoltage = priv_temp_trims.flt.fCalibrationVoltage; + } + + // + // Return trim ADC offset voltage as a float, if you can. + // + if ( pfOffsetV != NULL ) + { + *pfOffsetV = priv_temp_trims.flt.fCalibrationOffset; + } + + return priv_temp_trims.ui32.bMeasured; +} + +//***************************************************************************** +// +//! @brief Set the ADC window parameters. +//! +//! @param ui32Upper - the upper limit for the ADC window. +//! @param ui32Upper - the lower limit for the ADC window. +//! +//! This function may be used to change the ADC window parameters. Please note +//! that the upper and lower limits are only 16-bits wide in the ADC hardware. +//! This function will ignore the upper 16 bits of these arguments. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_window_set(uint32_t ui32Upper, uint32_t ui32Lower) +{ + // + // Set the window limits for the ADC. + // + AM_BFW(ADC, WULIM, ULIM, ui32Upper); + AM_BFW(ADC, WLLIM, LLIM, ui32Lower); +} + +//***************************************************************************** +// +//! @brief Configure a single ADC slot. +//! +//! @param ui32SlotNumber - the number of the ADC slot to be configured. +//! @param ui32SlotConfig - contains slot-specific options. +//! +//! This function may be used to configure the settings for an individual ADC +//! slot. The parameter \b ui32SlotConfig should be the logical 'OR' of a slot +//! average macro, a slot hold-time macro, a slot channel macro, and +//! optionally, the slot window enable macro. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_slot_config(uint32_t ui32SlotNumber, uint32_t ui32SlotConfig) +{ + uint32_t ui32RegOffset; + + // + // Make sure we're accessing a real slot. + // + am_hal_debug_assert_msg((ui32SlotNumber & 0xFFFFFFFF0) == 0, + "Trying to configure an ADC slot that doesn't exist."); + + // + // Locate the correct register for this ADC slot. + // + ui32RegOffset = (AM_REG_ADCn(0) + AM_REG_ADC_SL0CFG_O + (4 * ui32SlotNumber)); + + // + // Write the register with the caller's configuration value. + // + AM_REGVAL(ui32RegOffset) = ui32SlotConfig; +} + +//***************************************************************************** +// +//! @brief Peek at the next fifo entry. +//! +//! This function reads the oldest value in the ADC sample fifo but doesn't +//! actually advance the fifo to the next entry. This function is useful when +//! you need information from the fifo but you don't want to also empty the +//! fifo. This could be helpful if you want to check the FIFO depth without +//! pulling any data out. +//! +//! The value returned by this function is the raw 32-bit value provided by the +//! ADC hardware. In order to interpret this value, you will need to use one of +//! the following macros. +//! +//! @return 32-bit FIFO entry. +//! +// +//***************************************************************************** +uint32_t +am_hal_adc_fifo_peek(void) +{ + uint32_t ui32FIFOValue; + + // + // Grab a value from the ADC FIFO. + // + ui32FIFOValue = AM_REG(ADC, FIFO); + + // + // Return FIFO entry. + // + return ui32FIFOValue; +} + +//***************************************************************************** +// +//! @brief +//! +//! This function reads the oldest value in the ADC fifo and then pops the +//! fifo. Use this function when you actually want to pull data out of the +//! fifo. +//! +//! @return 32-bit FIFO entry. +//! +// +//***************************************************************************** +uint32_t +am_hal_adc_fifo_pop(void) +{ + uint32_t ui32FIFOValue; + + // + // Grab a value from the ADC FIFO. + // + ui32FIFOValue = AM_REG(ADC, FIFO); + + // + // Pop the FIFO. + // + AM_REG(ADC, FIFO) = 0; + + // + // Return FIFO valid bits. + // + return ui32FIFOValue; +} + +//***************************************************************************** +// +//! @brief Issue Software Trigger to the ADC. +//! +//! This function issues the software trigger to the ADC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_trigger(void) +{ + // + // Write to the Software trigger register in the ADC. + // + AM_REG(ADC, SWT) = 0x37; +} + +//***************************************************************************** +// +//! @brief Enable the ADC. +//! +//! Use this function to enable the ADC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_enable(void) +{ + // + // Enable the ADC. + // + AM_BFW(ADC, CFG, ADCEN, 0x1); +} + +//***************************************************************************** +// +//! @brief Disable the ADC. +//! +//! Use this function to disable the ADC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_disable(void) +{ + // + // Disable the ADC. + // + AM_BFW(ADC, CFG, ADCEN, 0x0); +} + +//***************************************************************************** +// +//! @brief Enable selected ADC Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h. +//! +//! Use this function to enable the ADC interrupts. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupts. + // + AM_REG(ADC, INTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return enabled ADC Interrupts. +//! +//! Use this function to get all enabled ADC interrupts. +//! +//! @return enabled ADC Interrupts. +// +//***************************************************************************** +uint32_t +am_hal_adc_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return AM_REG(ADC, INTEN); +} + +//***************************************************************************** +// +//! @brief Disable selected ADC Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h. +//! +//! Use this function to disable the ADC interrupts. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupts. + // + AM_REG(ADC, INTEN) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clear selected ADC Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h. +//! +//! Use this function to clear the ADC interrupts. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_int_clear(uint32_t ui32Interrupt) +{ + // + // Clear the interrupts. + // + AM_REG(ADC, INTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Set selected ADC Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_adc.h. +//! +//! Use this function to set the ADC interrupts. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_adc_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + AM_REG(ADC, INTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return either enabled or raw selected ADC interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! Use this function to get the ADC interrupt status. +//! +//! @return enabled or raw ADC interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_adc_int_status_get(bool bEnabledOnly) +{ + // + // Return the status. + // + if (bEnabledOnly) + { + uint32_t u32RetVal = AM_REG(ADC, INTEN); + u32RetVal &= AM_REG(ADC, INTSTAT); + return u32RetVal; + } + else + { + return AM_REG(ADC, INTSTAT); + } +} + +//***************************************************************************** +// +//! @brief Return temperature in degrees C of supplied voltage. +//! +//! @param fVoltage - return the temperature corresponding to this voltage. +//! +//! Use this function to convert volts from the temperature sensor into degrees +//! C. Caller converts ADC binary code to volts based on reference used. +//! This routine looks up the trim parameters and returns corrected temperature. +//! +//! The computation is based on a line running through 0 degrees K. +//! We find the slope from the trimmed temperature calibration point. +//! +//! +//! @return the temperature in degrees C. +// +//***************************************************************************** +float +am_hal_adc_volts_to_celsius(float fVoltage) +{ + float fTemp; + + // + // Get calibration temperature from trimmed values & convert to degrees K. + // + float fCalibration_temp = priv_temp_trims.flt.fCalibrationTemperature; + + // + // Get remaining trimmed values. + // + float fCalibration_voltage = priv_temp_trims.flt.fCalibrationVoltage; + float fCalibration_offset = priv_temp_trims.flt.fCalibrationOffset; + + // + // Compute the temperature. + // + fTemp = fCalibration_temp; + fTemp /= (fCalibration_voltage - fCalibration_offset); + fTemp *= (fVoltage - fCalibration_offset); + + // + // Give it back to the caller in Celsius. + // + return fTemp - 273.15f; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_adc.h b/mcu/apollo2/hal/am_hal_adc.h new file mode 100644 index 0000000..49563e6 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_adc.h @@ -0,0 +1,348 @@ +//***************************************************************************** +// +// am_hal_adc.h +//! @file +//! +//! @brief Functions for interfacing with the Analog to Digital Converter +//! +//! @addtogroup adc2 Analog-to-Digital Converter (ADC) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_ADC_H +#define AM_HAL_ADC_H + +//***************************************************************************** +// +//! @name Clock Selection +//! @brief These macros may be used to set the ADC module's clock source. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_CLOCK_OFF AM_REG_ADC_CFG_CLKSEL_OFF +#define AM_HAL_ADC_CLOCK_HFRC AM_REG_ADC_CFG_CLKSEL_HFRC +#define AM_HAL_ADC_CLOCK_DIV2 AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2 +//! @} + +//***************************************************************************** +// +//! @name Trigger Settings +//! @brief ADC trigger setting macros. +//! +//! These macros alter the ADC's trigger source and trigger polarity. Note that +//! the external trigger setting needs to be ORed with a POS or NEG option to +//! define the desired trigger polarity. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_TRIGGER_SOFT AM_REG_ADC_CFG_TRIGSEL_SWT +#define AM_HAL_ADC_TRIGGER_VCOMP AM_REG_ADC_CFG_TRIGSEL_VCOMP +#define AM_HAL_ADC_TRIGGER_EXT0 AM_REG_ADC_CFG_TRIGSEL_EXT0 +#define AM_HAL_ADC_TRIGGER_EXT1 AM_REG_ADC_CFG_TRIGSEL_EXT1 +#define AM_HAL_ADC_TRIGGER_EXT2 AM_REG_ADC_CFG_TRIGSEL_EXT2 +#define AM_HAL_ADC_TRIGGER_EXT3 AM_REG_ADC_CFG_TRIGSEL_EXT3 +#define AM_HAL_ADC_TRIGGER_FALL AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE +#define AM_HAL_ADC_TRIGGER_RISE AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE +//! @} + +//***************************************************************************** +// +//! @name Reference Settings +//! @brief ADC reference voltage setting macros. +//! +//! These macros control the ADC reference voltage source. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_REF_EXT_2P0 AM_REG_ADC_CFG_REFSEL_EXT2P0 +#define AM_HAL_ADC_REF_EXT_1P5 AM_REG_ADC_CFG_REFSEL_EXT1P5 +#define AM_HAL_ADC_REF_INT_2P0 AM_REG_ADC_CFG_REFSEL_INT2P0 +#define AM_HAL_ADC_REF_INT_1P5 AM_REG_ADC_CFG_REFSEL_INT1P5 +//! @} + +//***************************************************************************** +// +//! @name Clock Mode +//! @brief ADC clock mode settings +//! +//! These macros determine whether the ADC shuts down its clock between +//! samples. Shutting down the clock will reduce power consumption, but +//! increase latency. This setting is only valid for LPMODE 0. For other modes, +//! it will be ignored. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_CK_LOW_POWER AM_REG_ADC_CFG_CKMODE_LPCKMODE +#define AM_HAL_ADC_CK_LOW_LATENCY AM_REG_ADC_CFG_CKMODE_LLCKMODE +//! @} + +//***************************************************************************** +// +//! @name Low Power Mode +//! @brief ADC power conservation settings. +//! +//! These macros select the power state to enter between active scans. Each low +//! power mode has its own set of timing constraints. Please see the datasheet +//! for additional timing information on each power mode. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_LPMODE_0 AM_REG_ADC_CFG_LPMODE_MODE0 +#define AM_HAL_ADC_LPMODE_1 AM_REG_ADC_CFG_LPMODE_MODE1 +//! @} + +//***************************************************************************** +// +//! @name Repeat Mode +//! @brief Enable repeating scan mode. +//! +//! Use this macro to enable repeating scans using timer 3. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_REPEAT AM_REG_ADC_CFG_RPTEN(1) +#define AM_HAL_ADC_NO_REPEAT AM_REG_ADC_CFG_RPTEN(0) +//! @} + +//***************************************************************************** +// +//! @name Slot configuration +//! @brief Slot configuration macros +//! +//! These macros may be used to configure an individual ADC slot. +//! @{ +// +//***************************************************************************** + +// Set number of samples to average. +#define AM_HAL_ADC_SLOT_AVG_1 AM_REG_ADC_SL0CFG_ADSEL0(0) +#define AM_HAL_ADC_SLOT_AVG_2 AM_REG_ADC_SL0CFG_ADSEL0(1) +#define AM_HAL_ADC_SLOT_AVG_4 AM_REG_ADC_SL0CFG_ADSEL0(2) +#define AM_HAL_ADC_SLOT_AVG_8 AM_REG_ADC_SL0CFG_ADSEL0(3) +#define AM_HAL_ADC_SLOT_AVG_16 AM_REG_ADC_SL0CFG_ADSEL0(4) +#define AM_HAL_ADC_SLOT_AVG_32 AM_REG_ADC_SL0CFG_ADSEL0(5) +#define AM_HAL_ADC_SLOT_AVG_64 AM_REG_ADC_SL0CFG_ADSEL0(6) +#define AM_HAL_ADC_SLOT_AVG_128 AM_REG_ADC_SL0CFG_ADSEL0(7) + +// Set slot precision mode. +#define AM_HAL_ADC_SLOT_14BIT AM_REG_ADC_SL0CFG_PRMODE0_P14B +#define AM_HAL_ADC_SLOT_12BIT AM_REG_ADC_SL0CFG_PRMODE0_P12B +#define AM_HAL_ADC_SLOT_10BIT AM_REG_ADC_SL0CFG_PRMODE0_P10B +#define AM_HAL_ADC_SLOT_8BIT AM_REG_ADC_SL0CFG_PRMODE0_P8B + +// Select a channel by number. +#define AM_HAL_ADC_SLOT_CHANNEL(n) AM_REG_ADC_SL0CFG_CHSEL0(n) + +// Single-ended channels +#define AM_HAL_ADC_SLOT_CHSEL_SE0 AM_REG_ADC_SL0CFG_CHSEL0_SE0 +#define AM_HAL_ADC_SLOT_CHSEL_SE1 AM_REG_ADC_SL0CFG_CHSEL0_SE1 +#define AM_HAL_ADC_SLOT_CHSEL_SE2 AM_REG_ADC_SL0CFG_CHSEL0_SE2 +#define AM_HAL_ADC_SLOT_CHSEL_SE3 AM_REG_ADC_SL0CFG_CHSEL0_SE3 +#define AM_HAL_ADC_SLOT_CHSEL_SE4 AM_REG_ADC_SL0CFG_CHSEL0_SE4 +#define AM_HAL_ADC_SLOT_CHSEL_SE5 AM_REG_ADC_SL0CFG_CHSEL0_SE5 +#define AM_HAL_ADC_SLOT_CHSEL_SE6 AM_REG_ADC_SL0CFG_CHSEL0_SE6 +#define AM_HAL_ADC_SLOT_CHSEL_SE7 AM_REG_ADC_SL0CFG_CHSEL0_SE7 +#define AM_HAL_ADC_SLOT_CHSEL_SE8 AM_REG_ADC_SL0CFG_CHSEL0_SE8 +#define AM_HAL_ADC_SLOT_CHSEL_SE9 AM_REG_ADC_SL0CFG_CHSEL0_SE9 + +// Differential channels. +#define AM_HAL_ADC_SLOT_CHSEL_DF0 AM_REG_ADC_SL0CFG_CHSEL0_DF0 +#define AM_HAL_ADC_SLOT_CHSEL_DF1 AM_REG_ADC_SL0CFG_CHSEL0_DF1 + +// Miscellaneous other signals. +#define AM_HAL_ADC_SLOT_CHSEL_TEMP AM_REG_ADC_SL0CFG_CHSEL0_TEMP +#define AM_HAL_ADC_SLOT_CHSEL_VSS AM_REG_ADC_SL0CFG_CHSEL0_VSS +#define AM_HAL_ADC_SLOT_CHSEL_VBATT AM_REG_ADC_SL0CFG_CHSEL0_BATT + +// Window enable. +#define AM_HAL_ADC_SLOT_WINDOW_EN AM_REG_ADC_SL0CFG_WCEN0(1) + +// Enable the slot. +#define AM_HAL_ADC_SLOT_ENABLE AM_REG_ADC_SL0CFG_SLEN0(1) +//! @} + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to enable an individual ADC interrupt cause. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_INT_WCINC AM_REG_ADC_INTEN_WCINC(1) +#define AM_HAL_ADC_INT_WCEXC AM_REG_ADC_INTEN_WCEXC(1) +#define AM_HAL_ADC_INT_FIFOOVR2 AM_REG_ADC_INTEN_FIFOOVR2(1) +#define AM_HAL_ADC_INT_FIFOOVR1 AM_REG_ADC_INTEN_FIFOOVR1(1) +#define AM_HAL_ADC_INT_SCNCMP AM_REG_ADC_INTEN_SCNCMP(1) +#define AM_HAL_ADC_INT_CNVCMP AM_REG_ADC_INTEN_CNVCMP(1) +//! @} + +//***************************************************************************** +// +//! @name Temperature Trim Value Locations +//! @brief Temperature calibration cofficients are stored in readable space. +//! +//! These macros are used to access the temperature trim values in readable +//! space. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_CALIB_TEMP_ADDR (0x50023010) +#define AM_HAL_ADC_CALIB_AMBIENT_ADDR (0x50023014) +#define AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR (0x50023018) + +// +// Default coefficients (used when trims not provided): +// TEMP_DEFAULT = Temperature in deg K (e.g. 299.5 - 273.15 = 26.35) +// AMBIENT_DEFAULT = Voltage measurement at default temperature. +// OFFSET_DEFAULT = Default ADC offset at 1v. +// +#define AM_HAL_ADC_CALIB_TEMP_DEFAULT (299.5F) +#define AM_HAL_ADC_CALIB_AMBIENT_DEFAULT (1.02809F) +#define AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT (-0.004281F) +//! @} + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + //! Select the ADC Clock source using one of the clock source macros. + uint32_t ui32Clock; + + //! Select the ADC trigger source using a trigger source macro. + uint32_t ui32TriggerConfig; + + //! Use a macro to select the ADC reference voltage. + uint32_t ui32Reference; + + //! Use a macro to decide whether to disable clocks between samples. + uint32_t ui32ClockMode; + + //! Use a macro to select the ADC power mode. + uint32_t ui32PowerMode; + + //! Select whether the ADC will re-trigger based on a signal from timer 3. + uint32_t ui32Repeat; +} +am_hal_adc_config_t; + +//***************************************************************************** +// +//! @brief ADC Fifo Read macros +//! +//! These are helper macros for interpreting FIFO data. Each ADC FIFO entry +//! contains information about the slot number and the FIFO depth alongside the +//! current sample. These macros perform the correct masking and shifting to +//! read those values. +//! +//! The SAMPLE and FULL_SAMPLE options refer to the fractional part of averaged +//! samples. If you are not using hardware averaging or don't need the +//! fractional part of the ADC sample, you should just use +//! AM_HAL_ADC_FIFO_SAMPLE. +//! +//! If you do need the fractional part, use AM_HAL_ADC_FIFO_FULL_SAMPLE. This +//! macro will keep six bits of precision past the decimal point. Depending on +//! the number of averaged samples, anywhere between 1 and 6 of these bits will +//! be valid. Please consult the datasheet to find out how many bits of data +//! are valid for your chosen averaging settings. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_FIFO_SAMPLE(value) \ + ((((value) & AM_REG_ADC_FIFO_DATA_M) >> AM_REG_ADC_FIFO_DATA_S) >> 6) + +#define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) \ + (((value) & AM_REG_ADC_FIFO_DATA_M) >> AM_REG_ADC_FIFO_DATA_S ) + +#define AM_HAL_ADC_FIFO_SLOT(value) \ + (((value) & AM_REG_ADC_FIFO_SLOTNUM_M) >> AM_REG_ADC_FIFO_SLOTNUM_S) + +#define AM_HAL_ADC_FIFO_COUNT(value) \ + (((value) & AM_REG_ADC_FIFO_COUNT_M) >> AM_REG_ADC_FIFO_COUNT_S) +//! @} + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_adc_config(am_hal_adc_config_t *psConfig); +extern void am_hal_adc_window_set(uint32_t ui32Upper, uint32_t ui32Lower); +extern void am_hal_adc_slot_config(uint32_t ui32SlotNumber, + uint32_t ui32SlotConfig); + +extern uint32_t am_hal_adc_fifo_peek(void); +extern uint32_t am_hal_adc_fifo_pop(void); + +extern void am_hal_adc_trigger(void); +extern void am_hal_adc_enable(void); +extern void am_hal_adc_disable(void); +extern void am_hal_adc_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_adc_int_enable_get(void); +extern void am_hal_adc_int_disable(uint32_t ui32Interrupt); +extern void am_hal_adc_int_clear(uint32_t ui32Interrupt); +extern void am_hal_adc_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_adc_int_status_get(bool bEnabledOnly); +extern float am_hal_adc_volts_to_celsius(float fVoltage); +extern bool am_hal_adc_temp_trims_get(float * pfTemp, float * pfVoltage, float * pfOffsetV); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_ADC_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_cachectrl.c b/mcu/apollo2/hal/am_hal_cachectrl.c new file mode 100644 index 0000000..ced2668 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_cachectrl.c @@ -0,0 +1,576 @@ +//***************************************************************************** +// +// am_hal_cachectrl.c +//! @file +//! +//! @brief Functions for interfacing with the CACHE controller. +//! +//! @addtogroup clkgen2 Clock Generator (CACHE) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Default settings for the cache. +// +//***************************************************************************** +const am_hal_cachectrl_config_t am_hal_cachectrl_defaults = +{ + .ui32EnableCache = 1, + .ui32LRU = 0, + .ui32EnableNCregions = 0, + .ui32Config = AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512, + .ui32SerialCacheMode = 0, + .ui32FlashCachingEnables = 3, + .ui32EnableCacheClockGating = 1, + .ui32EnableLightSleep = 0, + .ui32Dly = 1, + .ui32SMDly = 1, + .ui32EnableDataClockGating = 1, + .ui32EnableCacheMonitoring = 0, +}; + +//***************************************************************************** +// +//! @brief Enable the cache using the supplied settings +//! +//! @param psConfig - pointer to a config structure containing cache settings. +//! +//! This function takes in a structure of cache settings, and uses them to +//! enable the cache. This function will take care of the necessary register +//! writes both in this module and in the power control module, so a separate +//! powerctrl call is not necessary. +//! +//! For most applications, the default cache settings will be the most +//! efficient choice. To use the default cache settings with this function, use +//! the address of the global am_hal_cachectrl_defaults structure as the +//! psConfig argument. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig) +{ + uint32_t ui32ConfigValue; + uint32_t ui32Timeout; + + // + // Pull the configuration data from the structure, and prepare to write the + // cache configuration register. + // + // NOTE: ICACHE and DCACHE settings were left out from this step. This is a + // workaround for a timing issue with early versions of Apollo2 that caused + // the cache to incorrectly mark itself valid during the startup sequence. + // The workaround calls for us to start the cache, manually invalidate it, + // and then enable ICACHE and DCACHE operation. + // + ui32ConfigValue = (AM_REG_CACHECTRL_CACHECFG_ENABLE( 1 ) | + AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU ) | + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( (psConfig->ui32EnableNCregions & 0x1) >> 0 ) | + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( (psConfig->ui32EnableNCregions & 0x2) >> 1 ) | + psConfig->ui32Config | + AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode) | + AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( psConfig->ui32EnableCacheClockGating ) | + AM_REG_CACHECTRL_CACHECFG_CACHE_LS(psConfig->ui32EnableLightSleep ) | + AM_REG_CACHECTRL_CACHECFG_DLY( psConfig->ui32Dly ) | + AM_REG_CACHECTRL_CACHECFG_SMDLY( psConfig->ui32SMDly ) | + AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(psConfig->ui32EnableDataClockGating) | + AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(psConfig->ui32EnableCacheMonitoring) ); + + // + // Make sure the cache is enabled in the power control block. + // + am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE); + + // + // Set the initial cache settings. + // + AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue; + + // + // Wait for the cache ready signal. + // + for (ui32Timeout = 0; ui32Timeout < 50; ui32Timeout++) + { + if (AM_BFM(CACHECTRL, CTRL, CACHE_READY)) + { + break; + } + } + + // + // Manually invalidate the cache (workaround for the issue described above.) + // + AM_BFW(CACHECTRL, CTRL, INVALIDATE, 1); + + // + // Wait for the cache ready signal again. + // + for (ui32Timeout = 0; ui32Timeout < 50; ui32Timeout++) + { + if (AM_BFM(CACHECTRL, CTRL, CACHE_READY)) + { + break; + } + } + + // + // Now that the cache is running, and correctly marked invalid, we can OR in + // the ICACHE and DCACHE settings. + // + ui32ConfigValue |= (AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( (psConfig->ui32FlashCachingEnables & 0x1) >> 0 ) | + AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( (psConfig->ui32FlashCachingEnables & 0x2) >> 1 ) ); + + // + // Write the final configuration settings to the CACHECTRL register. + // + AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue; +} + +//***************************************************************************** +// +//! @brief Disable the cache. +//! +//! Call this function to completely shut down cache features. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_cachectrl_disable(void) +{ + uint32_t ui32CacheCfg; + + // + // Save the cache settings. + // + ui32CacheCfg = AM_REG(CACHECTRL, CACHECFG); + + // + // Remove the ICACHE and DCACHE settings. + // + ui32CacheCfg &= (AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(0) | + AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(0)); + + // + // Write the resulting value back to the register. + // + AM_REG(CACHECTRL, CACHECFG) = ui32CacheCfg; + + // + // Read the CACHECTRL register a few times + // + AM_REG(CACHECTRL, CTRL); + AM_REG(CACHECTRL, CTRL); + AM_REG(CACHECTRL, CTRL); + + // + // Disable the cache completely. + // + AM_BFW(CACHECTRL, CACHECFG, ENABLE, 0); + + // + // Power the cache down in the powerctrl block. + // + am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE_DIS); +} + +//***************************************************************************** +// +//! @brief Set a default cache configuration. +//! +//! This function is used to set a default cache configuration. +// +//***************************************************************************** +void +am_hal_cachectrl_config_default(void) +{ + // + // Set PWRCTRL + // + am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE); + + // + // Write a default configuration to the CACHECFG register. + // + AM_REG(CACHECTRL, CACHECFG) = \ + AM_REG_CACHECTRL_CACHECFG_ENABLE( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_LRU( 0 ) | \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( 0 ) | \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( 0 ) | \ + AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E | \ + AM_REG_CACHECTRL_CACHECFG_SERIAL( 0 ) | \ + AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_CACHE_LS( 0 ) | \ + AM_REG_CACHECTRL_CACHECFG_DLY( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_SMDLY( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE( 1 ) | \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR( 0 ); + + // + // Write a default configuration to the FLASHCFG register. + // + AM_REG(CACHECTRL, FLASHCFG) = AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(1); + + // + // Write a default configuration to the CACHECTRL register. + // + AM_REG(CACHECTRL, CTRL) = \ + AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE(1) | \ + AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE(0) | \ + AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE(1) | \ + AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE(0) | \ + AM_REG_CACHECTRL_CTRL_RESET_STAT(0) | \ + AM_REG_CACHECTRL_CTRL_INVALIDATE(0); + + // + // Write a default configuration to the NCR0START and NCR0END registers. + // + AM_REG(CACHECTRL, NCR0START) = \ + AM_REG_CACHECTRL_NCR0START_ADDR(0); + AM_REG(CACHECTRL, NCR0END) = \ + AM_REG_CACHECTRL_NCR0END_ADDR(0); + + // + // Write a default configuration to the NCR1START and NCR1END registers. + // + AM_REG(CACHECTRL, NCR1START) = \ + AM_REG_CACHECTRL_NCR1START_ADDR(0); + AM_REG(CACHECTRL, NCR1END) = \ + AM_REG_CACHECTRL_NCR1END_ADDR(0); + + // + // Write a default configuration to the DMONn and IMONn registers. + // + AM_REG(CACHECTRL, DMON0) = \ + AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(0); + AM_REG(CACHECTRL, DMON1) = \ + AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(0); + AM_REG(CACHECTRL, DMON2) = \ + AM_REG_CACHECTRL_DMON2_DHIT_COUNT(0); + AM_REG(CACHECTRL, DMON3) = \ + AM_REG_CACHECTRL_DMON3_DLINE_COUNT(0); + AM_REG(CACHECTRL, IMON0) = \ + AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(0); + AM_REG(CACHECTRL, IMON1) = \ + AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(0); + AM_REG(CACHECTRL, IMON2) = \ + AM_REG_CACHECTRL_IMON2_IHIT_COUNT(0); + AM_REG(CACHECTRL, IMON3) = \ + AM_REG_CACHECTRL_IMON3_ILINE_COUNT(0); +} + +//***************************************************************************** +// +//! @brief Enable the flash cache controller via a configuration structure. +//! +//! @param psConfig - Pointer to a data structure containing all of the data +// necessary to configure the CACHECFG register. +//! +//! This function is used to configure all fields of the CACHECFG. +// +//***************************************************************************** +void +am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig) +{ + uint32_t u32ConfigValue; + + // + // Arrange all of the members of the data structure into a single u32 that + // can be written to the register. + // + u32ConfigValue = + AM_REG_CACHECTRL_CACHECFG_ENABLE( psConfig->ui32EnableCache ) | + AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU ) | + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( + (psConfig->ui32EnableNCregions & 0x1) >> 0 ) | + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( + (psConfig->ui32EnableNCregions & 0x2) >> 1 ) | + psConfig->ui32Config | + AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode) | + AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( + (psConfig->ui32FlashCachingEnables & 0x1) >> 0 ) | + AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( + (psConfig->ui32FlashCachingEnables & 0x2) >> 1 ) | + AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( + psConfig->ui32EnableCacheClockGating ) | + AM_REG_CACHECTRL_CACHECFG_CACHE_LS( + psConfig->ui32EnableLightSleep ) | + AM_REG_CACHECTRL_CACHECFG_DLY( psConfig->ui32Dly ) | + AM_REG_CACHECTRL_CACHECFG_SMDLY( psConfig->ui32SMDly ) | + AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE( + psConfig->ui32EnableDataClockGating ) | + AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR( + psConfig->ui32EnableCacheMonitoring ); + + // + // Write the configuration value to the CACHECFG register. + // + AM_REG(CACHECTRL, CACHECFG) = u32ConfigValue; +} + +//***************************************************************************** +// +//! @brief Configure the various flash cache controller enables. +//! +//! @param u32EnableMask - Mask of features to be enabled. +//! @param u32DisableMask - Mask of features to be disabled. +//! +//! This function is used to enable or disable the various flash cache +//! controller configuration enables which consist of the following: +//! AM_HAL_CACHECTRL_CACHECFG_ENABLE Flash cache controller +//! AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE LRU (disabled = LRR) +//! AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE Non-cacheable region 0 +//! AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE Non-cacheable region 1 +//! AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE Serial cache mode +//! AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE Instruction caching +//! AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE Data caching. +//! AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE Cache clock gating +//! AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE Light sleep cache RAMs +//! AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE Data clock gating +//! AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE Cache Monitoring Stats +//! +//! Note that if both an enable and disable are provided in their respective +//! masks, the enable will take precendence. +//! +//! @return The previous status of the flash cache controller enables. +// +//***************************************************************************** +#define CACHECTRL_VALID_ENABLES ( \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_M | \ + AM_REG_CACHECTRL_CACHECFG_LRU_M | \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M | \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M | \ + AM_REG_CACHECTRL_CACHECFG_SERIAL_M | \ + AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M | \ + AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M | \ + AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M | \ + AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M | \ + AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M | \ + AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M ) + +uint32_t +am_hal_cachectrl_cache_enables(uint32_t u32EnableMask, uint32_t u32DisableMask) +{ + uint32_t ui32RetVal = AM_BFR(CACHECTRL, CACHECFG, ENABLE) & + CACHECTRL_VALID_ENABLES; + + // + // Make sure the enable masks include only valid bits. + // + u32EnableMask &= CACHECTRL_VALID_ENABLES; + u32DisableMask &= CACHECTRL_VALID_ENABLES; + + // + // First, do the disables. + // + AM_REG(CACHECTRL, CACHECFG) &= ~u32DisableMask; + + // + // Now set the enables. + // + AM_REG(CACHECTRL, CACHECFG) |= u32EnableMask; + + return ui32RetVal; +} + +//***************************************************************************** +// +//! @brief Select the cache configuration type. +//! +//! This functions only sets the CACHECFG CONFIG field. +//! +//! @param ui32CacheConfig - The cache configuration value. +//! +//! This function can be used to select the type of cache.frequency of the main +//! system clock. The ui32CacheConfig parameter should be set to one of the +//! following values: +//! +//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 : Direct mapped, +//! 128-bit linesize, 256 entries (2 SRAMs active). +//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 : Two-way set associative, +//! 128-bit linesize, 256 entries (4 SRAMs active). +//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 : Two-way set associative, +//! 128-bit linesize, 512 entries (8 SRAMs active). +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig) +{ + // + // Clear the bitfield + // + AM_REG(CACHECTRL, CACHECFG) &= ~AM_REG_CACHECTRL_CACHECFG_CONFIG_M; + + // + // Write the new value to the bitfield. + // + AM_REG(CACHECTRL, CACHECFG) |= ui32CacheConfig & + AM_REG_CACHECTRL_CACHECFG_CONFIG_M; +} + +//***************************************************************************** +// +//! @brief Invalidate the flash cache. +//! +//! This function is used to invalidate the flash cache. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_cachectrl_invalidate_flash_cache(void) +{ + // + // Write the bit to invalidate the flash cache. + // Note - this bit is not sticky, no need to write it back to 0. + // + AM_REG(CACHECTRL, CTRL) |= AM_REG_CACHECTRL_CTRL_INVALIDATE_GO; +} + +//***************************************************************************** +// +//! @brief Reset cache statistics. +//! +//! This function is used to reset cache statistics. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_cachectrl_reset_statistics(void) +{ + // + // Write the bit to reset flash statistics. + // Note - this bit is not sticky, no need to write it back to 0. + // + AM_REG(CACHECTRL, CTRL) |= AM_REG_CACHECTRL_CTRL_RESET_STAT_CLEAR; +} + +//***************************************************************************** +// +//! @brief Get flash cache sleep mode status. +//! +//! This function returns flash cache sleep mode statuses. +//! +//! @return +//! bit0 indicates that flash0 flash sleep mode is enabled. +//! bit1 indicates that flash1 flash sleep mode is enabled. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_sleep_mode_status(void) +{ + uint32_t ui32Status, ui32Ret; + + // + // Get the current sleep mode status bits. + // + ui32Status = AM_REG(CACHECTRL, CTRL); + ui32Ret = (ui32Status & \ + AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS_M) >> \ + (AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS_S - 0); + ui32Ret |= (ui32Status & \ + AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS_M) >> \ + (AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS_S - 1); + + return ui32Ret; +} + +//***************************************************************************** +// +//! @brief Enable or disable flash cache sleep mode. +//! +//! This function enables or disables flash cache sleep mode. +//! @param ui32EnableMask - bit0 for flash0, bit1 for flash1. +//! @param ui32DisableMask - bit0 for flash0, bit1 for flash1. +//! +//! Note that if both an enable and disable are provided in their respective +//! masks, the enable will take precedence. +//! +//! @return Previous status. +//! bit0 indicates that flash0 flash sleep mode was previously enabled. +//! bit1 indicates that flash1 flash sleep mode was previously enabled. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask, + uint32_t ui32DisableMask) +{ + uint32_t ui32Ret = am_hal_cachectrl_sleep_mode_status(); + + if ( ui32DisableMask & 0x1 ) + { + AM_REG(CACHECTRL, CTRL) |= AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE_M; + } + + if ( ui32DisableMask & 0x2 ) + { + AM_REG(CACHECTRL, CTRL) |= AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE_M; + } + + if ( ui32EnableMask & 0x1 ) + { + AM_REG(CACHECTRL, CTRL) |= AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE_M; + } + + if ( ui32EnableMask & 0x2 ) + { + AM_REG(CACHECTRL, CTRL) |= AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE_M; + } + + return ui32Ret; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_cachectrl.h b/mcu/apollo2/hal/am_hal_cachectrl.h new file mode 100644 index 0000000..107cc07 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_cachectrl.h @@ -0,0 +1,211 @@ +//***************************************************************************** +// +// am_hal_cachectrl.h +//! @file +//! +//! @brief Functions for accessing and configuring the CACHE controller. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_CACHECTRL_H +#define AM_HAL_CACHECTRL_H + +//***************************************************************************** +// +// Cache configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Set to 1 to enable the cache. + // + uint8_t ui32EnableCache; + + // + //! Set to 1 to enable the LRU cache replacement policy. + //! Set to 0 to enable the LRR (least recently used) replacement policy. + //! LEE minimizes writes to the TAG SRAM. + // + uint8_t ui32LRU; + + // + //! Set to 3 to enable non-cachable region 1 and non-cachable region 0. + //! Set to 2 to enable non-cachable region 1. + //! Set to 1 to enable non-cachable region 0. + //! Set to 0 to make all regions cacheable. + // + uint8_t ui32EnableNCregions; + + // + //! Set to: + //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 for direct-mapped, + //! 128-bit linesize, 256 entries (2 SRAMs active) + //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 for two-way set associative, + //! 128-bit linesize, 256 entries (4 SRAMs active) + //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 for two-way set associative, + //! 128-bit linesize, 512 entries (8 SRAMs active) + // + uint8_t ui32Config; + + // + //! Set to 1 to enable serial cache mode. + // + uint8_t ui32SerialCacheMode; + + // + //! Set to 3 to enable flash data caching and flash instruction caching. + //! Set to 2 to enable flash data caching. + //! Set to 1 to enable flash instruction caching. + //! Set to 0 to disable flash data caching and flash instruction caching. + // + uint8_t ui32FlashCachingEnables; + + // + //! Set to 1 to enable clock gating of cache RAMs. + // + uint8_t ui32EnableCacheClockGating; + + // + //! Set to 1 to enable light sleep of cache RAMs. + // + uint8_t ui32EnableLightSleep; + + // + //! Set Data RAM delay value (0x0 - 0xF). + // + uint8_t ui32Dly; + + // + //! Set SM Data RAM delay value (0x0 - 0xF). + // + uint8_t ui32SMDly; + + // + //! Set to 1 to enable clock gating of the entire data array. + // + uint8_t ui32EnableDataClockGating; + + // + //! Set to 1 to enable cache monitor statistics. + // + uint8_t ui32EnableCacheMonitoring; +} +am_hal_cachectrl_config_t; + +extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults; + +//***************************************************************************** +// +//! @name Cache enables +//! @brief Configuration selection for the various cache enables. +//! +//! These macros may be used in conjunction with the +//! am_hal_cachectrl_cache_enable() function to enable various cache features. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CACHECTRL_CACHECFG_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_M +#define AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE AM_REG_CACHECTRL_CACHECFG_LRU_M +#define AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M +#define AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M +#define AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE AM_REG_CACHECTRL_CACHECFG_SERIAL_M +#define AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M +#define AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M +#define AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M +#define AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M +#define AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M +#define AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M +//! @} + +//***************************************************************************** +// +//! @name Cache Config +//! @brief Configuration selection for the cache. +//! +//! These macros may be used in conjunction with the +//! am_hal_cachectrl_cache_config() function to select the cache type. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W1_128B_256E +#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_256E +#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E +//! @} + +//***************************************************************************** +// +// Default cache settings +// +//***************************************************************************** +#define AM_HAL_CACHECTRL_DEFAULTS \ + (AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE | \ + AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE | \ + AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE | \ + AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE | \ + AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig); +extern void am_hal_cachectrl_disable(void); +extern void am_hal_cachectrl_config_default(void); +extern void am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig); +extern uint32_t am_hal_cachectrl_cache_enables(uint32_t u32EnableMask, + uint32_t u32DisableMask); +extern void am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig); +extern void am_hal_cachectrl_invalidate_flash_cache(void); +extern void am_hal_cachectrl_reset_statistics(void); +extern uint32_t am_hal_cachectrl_sleep_mode_status(void); +extern uint32_t am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask, + uint32_t ui32DisableMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CACHECTRL_H diff --git a/mcu/apollo2/hal/am_hal_clkgen.c b/mcu/apollo2/hal/am_hal_clkgen.c new file mode 100644 index 0000000..6aaee4d --- /dev/null +++ b/mcu/apollo2/hal/am_hal_clkgen.c @@ -0,0 +1,503 @@ +//***************************************************************************** +// +// am_hal_clkgen.c +//! @file +//! +//! @brief Functions for interfacing with the CLKGEN. +//! +//! @addtogroup clkgen2 Clock Generator (CLKGEN) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// CLKGEN HFADJ register +// +//***************************************************************************** +#define AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT 0x5B8 + +//***************************************************************************** +// +//! @brief Select the clock divisor for the main system clock. +//! +//! @param ui32ClockSetting - The divisor value for the system clock. +//! +//! This function can be used to select the frequency of the main system clock. +//! The \e ui32ClockSetting parameter should be set to one of the following +//! values: +//! +//! AM_HAL_CLKGEN_SYSCLK_MAX +//! AM_HAL_CLKGEN_SYSCLK_48MHZ +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting) +{ + am_hal_debug_assert_msg(ui32ClockSetting == AM_HAL_CLKGEN_SYSCLK_48MHZ, + "am_hal_clkgen_sysclk_select(): invalid clock setting."); + + // + // Unlock the clock control register. + // + AM_REG(CLKGEN, CLKKEY) = AM_REG_CLKGEN_CLKKEY_KEYVAL; + + // + // Set the HFRC divisor to the required operating value. + // + AM_REG(CLKGEN, CCTRL) = ui32ClockSetting; + + // + // Lock the clock configuration registers. + // + AM_REG(CLKGEN, CLKKEY) = 0; +} + +//***************************************************************************** +// +//! @brief Get the current system clock frequency. +//! +//! This function can be used to determine the frequency of the main system +//! clock. The return value is the system clock frequency measured in hertz. +//! +//! @return System clock frequency in Hz +// +//***************************************************************************** +uint32_t +am_hal_clkgen_sysclk_get(void) +{ + uint32_t ui32ClockSetting; + uint32_t ui32ClockFreq; + + // + // Read the value of the clock divider. + // + ui32ClockSetting = AM_REG(CLKGEN, CCTRL) & AM_REG_CLKGEN_CCTRL_CORESEL_M; + + switch ( ui32ClockSetting ) + { + case AM_REG_CLKGEN_CCTRL_CORESEL_HFRC: + ui32ClockFreq = 48000000; + break; + + case AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2: + ui32ClockFreq = 24000000; + break; + } + + return ui32ClockFreq; +} + +//***************************************************************************** +// +//! @brief Enable selected CLKGEN Interrupts. +//! +//! Use this function to enable the interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_clkgen.h +//! +//! @return None +// +//***************************************************************************** +void +am_hal_clkgen_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupts. + // + AM_REG(CLKGEN, INTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return enabled CLKGEN Interrupts. +//! +//! Use this function to get all enabled CLKGEN interrupts. +//! +//! @return enabled CLKGEN interrupts. +// +//***************************************************************************** +uint32_t +am_hal_clkgen_int_enable_get(void) +{ + // + // Return the enabled interrupts. + // + return AM_REG(CLKGEN, INTEN); +} + +//***************************************************************************** +// +//! @brief Disable selected CLKGEN Interrupts. +//! +//! Use this function to disable the CLKGEN interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_clkgen.h +//! +//! @return None +// +//***************************************************************************** +void +am_hal_clkgen_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupts. + // + AM_REG(CLKGEN, INTEN) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Sets the interrupt status. +//! +//! @param ui32IntFlags interrupts to be enabled. +//! +//! This function sets the interrupts. +//! +//! Valid values for ui32IntFlags are: +//! +//! AM_HAL_CLKGEN_INT_RTC_ALARM +//! AM_HAL_CLKGEN_INT_XT_FAIL +//! AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE +//! AM_HAL_CLKGEN_INT AUTOCAL_FAIL +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupt status. + // + AM_REG(CLKGEN, INTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Gets the interrupt configuration. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! This function gets the currently configured interrupts. +//! +//! @return the configured interrupts. +//! +//! Possible values for the return are: +//! +//! AM_HAL_CLKGEN_INT_RTC_ALARM +//! AM_HAL_CLKGEN_INT_XT_FAIL +//! AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE +//! AM_HAL_CLKGEN_INT AUTOCAL_FAIL +// +//***************************************************************************** +uint32_t +am_hal_clkgen_int_status_get(bool bEnabledOnly) +{ + // + // Return the status. + // + if ( bEnabledOnly ) + { + uint32_t u32RetVal = AM_REG(CLKGEN, INTSTAT); + u32RetVal &= AM_REG(CLKGEN, INTEN); + return u32RetVal; + } + else + { + return AM_REG(CLKGEN, INTSTAT); + } +} + +//***************************************************************************** +// +//! @brief Clears the interrupts. +//! +//! @param ui32IntFlags interrupts to be cleared. +//! +//! This function clears the interrupts. +//! +//! Valid values for ui32IntFlags are: +//! +//! AM_HAL_CLKGEN_INT_RTC_ALARM +//! AM_HAL_CLKGEN_INT_XT_FAIL +//! AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE +//! AM_HAL_CLKGEN_INT AUTOCAL_FAIL +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_int_clear(uint32_t ui32Interrupt) +{ + // + // Clear the interrupts. + // + AM_REG(CLKGEN, INTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Starts the desired oscillator(s) (OSC). +//! +//! @param ui32OscFlags oscillator(s) to start. +//! +//! This function starts the desired oscillator(s) (OSC). +//! +//! Valid values for ui32OscFlags are: +//! +//! AM_HAL_CLKGEN_OSC_LFRC +//! AM_HAL_CLKGEN_OSC_XT +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_osc_start(uint32_t ui32OscFlags) +{ + if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) ) + { + // + // Start the oscillator(s). + // Note that these bits are cleared in order to enable the oscillator. + // + AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags; + } +} + +//***************************************************************************** +// +//! @brief Stops the desired oscillator(s) (OSC). +//! +//! @param ui32OscFlags oscillator(s) to stop. +//! +//! This function stops the desired oscillator(s) (OSC). +//! +//! Valid values for ui32OscFlags are: +//! +//! AM_HAL_CLKGEN_OSC_LFRC +//! AM_HAL_CLKGEN_OSC_XT +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_osc_stop(uint32_t ui32OscFlags) +{ + if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) ) + { + // + // Stop the oscillator(s). + // Note that these bits are set in order to stop the oscillator. + // + AM_REG(CLKGEN, OCTRL) |= ui32OscFlags; + } +} + +//***************************************************************************** +// +//! @brief Enables the clock out signal. +//! +//! @param ui32Signal desired location for the clock out signal. +//! +//! This function enables the clock out signal. See am_hal_clkgen.h for +//! available signals. +//! +//! e.g. AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC +//! AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 +//! AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_clkout_enable(uint32_t ui32Signal) +{ + // + // Enable the clock out on desired signal. + // + AM_REG(CLKGEN, CLKOUT) = AM_REG_CLKGEN_CLKOUT_CKEN_M | ui32Signal; +} + +//***************************************************************************** +// +//! @brief Disables the clock out signal. +//! +//! This function disables the clock out signal. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_clkout_disable(void) +{ + // + // Disable the clock out. + // + AM_REG(CLKGEN, CLKOUT) = 0; +} + +//***************************************************************************** +// +//! @brief Enable UART system clock. +//! +//! This function enables or disables the UART system clock. +//! +//! @param ui32Module is 0 or 1 for Apollo2. +//! @param ui32UartEn is one of the following. +//! AM_HAL_CLKGEN_UARTEN_DIS +//! AM_HAL_CLKGEN_UARTEN_EN +//! AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ +//! AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn) +{ + uint32_t ui32Mask; + + if ( (ui32Module >= AM_REG_UART_NUM_MODULES) || + (ui32UartEn > AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV) ) + { + return; + } + + ui32UartEn <<= (ui32Module * AM_HAL_CLKGEN_UARTEN_UARTENn_S(ui32Module)); + ui32Mask = ~(AM_HAL_CLKGEN_UARTEN_UARTENn_M(ui32Module)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the UART clock + // + AM_REG(CLKGEN, UARTEN) &= ui32Mask; + AM_REG(CLKGEN, UARTEN) |= ui32UartEn; + + // + // Begin critical section. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Enables HFRC auto-adjustment at the specified interval. +//! +//! @param ui32Warmup - How long to give the HFRC to stabilize during each +//! calibration attempt. +//! @param ui32Frequency - How often the auto-adjustment should happen. +//! +//! This function enables HFRC auto-adjustment from an external crystal +//! oscillator even when the crystal is not normally being used. +//! +//! ui32Warmup should be one of the following values: +//! +//! AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC +//! AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC +//! +//! ui32Frequency should be one of the following values: +//! +//! AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC +//! AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency) +{ + // + // Set the HFRC Auto-adjust register for the user's chosen settings. Assume + // that the HFRC should be calibrated to 48 MHz and that the crystal is + // running at 32.768 kHz. + // + AM_REG(CLKGEN, HFADJ) = + AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 | + ui32Warmup | + AM_REG_CLKGEN_HFADJ_HFXTADJ(AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT) | + ui32Frequency | + AM_REG_CLKGEN_HFADJ_HFADJEN_EN; +} + +//***************************************************************************** +// +//! @brief Disables HFRC auto-adjustment. +//! +//! This function disables HFRC auto-adjustment. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_clkgen_hfrc_adjust_disable(void) +{ + // + // Disable the clock out. + // + AM_REG(CLKGEN, HFADJ) = + AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 | + AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC | + AM_REG_CLKGEN_HFADJ_HFXTADJ(AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT) | + AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC | + AM_REG_CLKGEN_HFADJ_HFADJEN_DIS; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_clkgen.h b/mcu/apollo2/hal/am_hal_clkgen.h new file mode 100644 index 0000000..23d86d3 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_clkgen.h @@ -0,0 +1,208 @@ +//***************************************************************************** +// +// am_hal_clkgen.h +//! @file +//! +//! @brief Functions for accessing and configuring the CLKGEN. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_CLKGEN_H +#define AM_HAL_CLKGEN_H + +//***************************************************************************** +// +//! @name System Clock max frequency +//! @brief Defines the maximum clock frequency for this device. +//! +//! These macros provide a definition of the maximum clock frequency. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CLKGEN_FREQ_MAX_HZ 48000000 +#define AM_HAL_CLKGEN_FREQ_MAX_KHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000) +#define AM_HAL_CLKGEN_FREQ_MAX_MHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000) +#define AM_HAL_CLKGEN_CORESEL_MAXDIV AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2 +//! @} + +//***************************************************************************** +// +//! @name System Clock Selection +//! @brief Divisor selection for the main system clock. +//! +//! These macros may be used along with the am_hal_clkgen_sysctl_select() +//! function to select the frequency of the main system clock. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CLKGEN_SYSCLK_MAX AM_REG_CLKGEN_CCTRL_CORESEL_HFRC +#define AM_HAL_CLKGEN_SYSCLK_48MHZ AM_REG_CLKGEN_CCTRL_CORESEL_HFRC +//! @} + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits. +//! @{ +// +//***************************************************************************** +#define AM_HAL_CLKGEN_INT_ALM AM_REG_CLKGEN_INTEN_ALM_M +#define AM_HAL_CLKGEN_INT_OF AM_REG_CLKGEN_INTEN_OF_M +#define AM_HAL_CLKGEN_INT_ACC AM_REG_CLKGEN_INTEN_ACC_M +#define AM_HAL_CLKGEN_INT_ACF AM_REG_CLKGEN_INTEN_ACF_M +//! @} + +//***************************************************************************** +// +//! @name OSC Start and Stop +//! @brief OSC Start and Stop defines. +//! +//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x(). +//! @{ +// +//***************************************************************************** +#define AM_HAL_CLKGEN_OSC_LFRC AM_REG_CLKGEN_OCTRL_STOPRC_M +#define AM_HAL_CLKGEN_OSC_XT AM_REG_CLKGEN_OCTRL_STOPXT_M +//! @} + +//***************************************************************************** +// +// OSC Start, Stop, Select defines +// +//***************************************************************************** +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV4 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV16 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_RTC_100Hz AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_100Hz +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2M AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT AM_REG_CLKGEN_CLKOUT_CKSEL_XT +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CG_100Hz AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLK AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLK +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FLASH_CLK AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV256 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8K AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV64K AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FCLKNE AM_REG_CLKGEN_CLKOUT_CKSEL_FCLKNE +#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE + +//***************************************************************************** +// +// UARTEN +// +//***************************************************************************** +#define AM_HAL_CLKGEN_UARTEN_DIS AM_REG_CLKGEN_UARTEN_UART0EN_DIS +#define AM_HAL_CLKGEN_UARTEN_EN AM_REG_CLKGEN_UARTEN_UART0EN_EN +#define AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ +#define AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV + +#define AM_HAL_CLKGEN_UARTEN_UARTENn_S(module) \ + ((module) * \ + (AM_REG_CLKGEN_UARTEN_UART1EN_S - AM_REG_CLKGEN_UARTEN_UART0EN_S)) + +#define AM_HAL_CLKGEN_UARTEN_UARTENn_M(module) \ + (AM_REG_CLKGEN_UARTEN_UART0EN_M << AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)) + +// +// UARTEN: entype is one of DIS, EN, REDUCE_FREQ, EN_POWER_SAV. +// +#define AM_HAL_CLKGEN_UARTEN_UARTENn(module, entype) \ + (AM_REG_CLKGEN_UARTEN_UART0EN_##entype << \ + AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting); +extern uint32_t am_hal_clkgen_sysclk_get(void); +extern void am_hal_clkgen_osc_start(uint32_t ui32OscFlags); +extern void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags); +extern void am_hal_clkgen_clkout_enable(uint32_t ui32Signal); +extern void am_hal_clkgen_clkout_disable(void); +extern void am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn); +extern void am_hal_clkgen_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_clkgen_int_enable_get(void); +extern void am_hal_clkgen_int_disable(uint32_t ui32Interrupt); +extern void am_hal_clkgen_int_clear(uint32_t ui32Interrupt); +extern void am_hal_clkgen_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_clkgen_int_status_get(bool bEnabledOnly); +extern void am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency); +extern void am_hal_clkgen_hfrc_adjust_disable(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CLKGEN_H diff --git a/mcu/apollo2/hal/am_hal_ctimer.c b/mcu/apollo2/hal/am_hal_ctimer.c new file mode 100644 index 0000000..61d2392 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_ctimer.c @@ -0,0 +1,1686 @@ +//***************************************************************************** +// +// am_hal_ctimer.c +//! @file +//! +//! @brief Functions for interfacing with the Counter/Timer module. +//! +//! @addtogroup ctimer2 Counter/Timer (CTIMER) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Address space distance between timer configuration registers. +// +//***************************************************************************** +#define MAX_CTIMERS 4 +#define TIMER_OFFSET (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O) +#define CTIMER_CMPR_OFFSET (AM_REG_CTIMER_CMPRB0_O - AM_REG_CTIMER_CMPRA0_O) + +//***************************************************************************** +// +// Adjacency check +// +// This is related to the timer read workaround. This macro checks to see if +// the two supplied count values are within one "tick" of eachother. It should +// still pass in the event of a timer rollover. +// +//***************************************************************************** +//! Timer read workaround: Do count values differ by one tick or less. +#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) + +//***************************************************************************** +// +//! Array of function pointers for handling CTimer interrupts. +// +//***************************************************************************** +am_hal_ctimer_handler_t am_hal_ctimer_ppfnHandlers[16]; + +//***************************************************************************** +// +//! @brief Check to see if the given CTimer is using the HFRC +//! +//! @note Calls to this function should be from inside a critical section. +//! +//! @return None. +// +//***************************************************************************** +static bool +ctimer_source_hfrc(uint32_t ui32CtimerNum) +{ + uint32_t *pui32ConfigReg; + uint32_t ui32TimerASrc, ui32TimerBSrc; + + // + // Find the correct register to write. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32CtimerNum * TIMER_OFFSET)); + + // + // Determine if this timer is using HFRC as the clock source. + // The value we are looking for is HFRC_DIV4 to HFRC_DIV4K. + // Get the clock sources and 0-base the extracted value. + // + ui32TimerASrc = AM_BFX(CTIMER, CTRL0, TMRA0CLK, *pui32ConfigReg) - + AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4); + ui32TimerBSrc = AM_BFX(CTIMER, CTRL0, TMRB0CLK, *pui32ConfigReg) - + AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4); + + // + // If the source value is 0 to (HFRC_DIV4K - HFRC_DIV4), then it's HFRC. + // + if ( (ui32TimerASrc <= (AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4K) - + AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4))) || + (ui32TimerBSrc <= (AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4K) - + AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4))) ) + { + return true; + } + else + { + return false; + } + +} // ctimer_source_hfrc() + +//***************************************************************************** +// +// @brief Check to see if any of the CTimers or STimer are using the HFRC. +// +// This function should be used to check if the HFRC is being used in order +// to correctly establish power related settings. +// +// Note - Calls to this function should be from inside a critical section. +// +//! @return None. +// +//***************************************************************************** +static bool +timers_use_hfrc(void) +{ + uint32_t ui32TimerASrc, ui32CtimerNum; + + // + // Check STimer to see if it is using HFRC. + // + ui32TimerASrc = AM_BFR(CTIMER, STCFG, CLKSEL); + if ( (ui32TimerASrc == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16) || + (ui32TimerASrc == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) ) + { + return true; + } + + // + // Check the CTimers to see if any are using HFRC as their clock source. + // + for ( ui32CtimerNum = 0; ui32CtimerNum < MAX_CTIMERS; ui32CtimerNum++ ) + { + if ( ctimer_source_hfrc(ui32CtimerNum) ) + { + return true; + } + } + + return false; + +} // timers_use_hfrc() + +//***************************************************************************** +// +// ctimer_clr() +// +// For the appropriate ctimer configuration register, set the CLR bit high +// in the appropriate timer segment (A, B, or both). +// +// The CLR bit is required to be set in order to completely initialize +// the timer at config time. The timer clear occurs asynchrnously during the +// low-to-high transition of the CLR bit. +// +// This function only sets the CLR bit. It is assumed that the actual timer +// configuration will occur following the call to this function and will clear +// the CLR bit at that time. +// +//***************************************************************************** +static void +ctimer_clr(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + // + // Find the address of the correct control register and set the CLR bit + // for the timer segment in that control register. + // + volatile uint32_t *pui32ConfigReg = + (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + AM_CRITICAL_BEGIN + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0CLR_M | + AM_REG_CTIMER_CTRL0_TMRB0CLR_M)); + AM_CRITICAL_END + +} // ctimer_clr() + +//***************************************************************************** +// +//! @brief Convenience function for responding to CTimer interrupts. +//! +//! @param ui32Status is the interrupt status as returned by +//! am_hal_ctimer_int_status_get() +//! +//! This function may be called from am_ctimer_isr() to read the status of +//! the CTimer interrupts, determine which source caused the most recent +//! interrupt, and call an interrupt handler function to respond. The interrupt +//! handler to be called must be first registered with the +//! am_hal_ctimer_int_register() function. +//! +//! In the event that multiple sources are active, the corresponding +//! interrupt handlers will be called in numerical order based on interrupt def. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_service(uint32_t ui32Status) +{ + uint32_t ui32Clz; + + am_hal_ctimer_handler_t pfnHandler; + + ui32Status &= 0xFFFF; + + while ( ui32Status ) + { + // + // Pick one of any remaining active interrupt bits + // +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32Status); +#else + ui32Clz = __builtin_clz(ui32Status); +#endif + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x80000000 >> ui32Clz); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = am_hal_ctimer_ppfnHandlers[31 - ui32Clz]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + pfnHandler(); + } + } +} // am_hal_ctimer_int_service() + +//***************************************************************************** +// +//! @brief Register an interrupt handler for CTimer. +//! +//! @param ui32Interrupt - interrupt number to assign this interrupt handler to. +//! @param pfnHandler - Function to call when this interrupt is received. +//! +//! This function allows the caller to specify a function that should be called +//! any time a Ctimer interrupt is received. Registering an +//! interrupt handler using this function adds the function pointer to an array +//! in SRAM. This interrupt handler will be called by am_hal_ctimer_int_service() +//! whenever the ui32Status parameter indicates that the corresponding interrupt. +//! +//! To remove an interrupt handler that has already been registered, the +//! pfnHandler parameter may be set to zero. +//! +//! @note This function will not have any effect unless the +//! am_hal_ctimer_int_service() function is being used. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_register(uint32_t ui32Interrupt, + am_hal_ctimer_handler_t pfnHandler) +{ + uint32_t intIdx = 0; + + // + // Check to make sure the interrupt number is valid. (Debug builds only) + // + switch (ui32Interrupt) + { + case AM_REG_CTIMER_INTEN_CTMRA0C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA0C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB0C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB0C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA1C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA1C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB1C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB1C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA2C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA2C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB2C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB2C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA3C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA3C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB3C0INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB3C0INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA0C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA0C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB0C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB0C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA1C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA1C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB1C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB1C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA2C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA2C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB2C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB2C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRA3C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRA3C1INT_S; + break; + + case AM_REG_CTIMER_INTEN_CTMRB3C1INT_M: + intIdx = AM_REG_CTIMER_INTEN_CTMRB3C1INT_S; + break; + + default: + am_hal_debug_assert_msg(false, "CTimer interrupt number out of range."); + } + + am_hal_ctimer_ppfnHandlers[intIdx] = pfnHandler; + +} // am_hal_ctimer_int_register() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param psConfig is a pointer to a structure that holds important settings +//! for the timer. +//! +//! This function should be used to perform the initial set-up of the +//! counter-timer. +//! +//! @note This function is deprecated and will eventually be replaced by +//! am_hal_ctimer_config_single(), which performs the same configuration +//! without requiring a structure and without assuming both timer halves +//! are being configured. +//! Please use am_hal_ctimer_config_single() for new development. +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config(uint32_t ui32TimerNumber, + am_hal_ctimer_config_t *psConfig) +{ + uint32_t *pui32ConfigReg; + uint32_t ui32ConfigVal; + + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, AM_HAL_CTIMER_BOTH); + + // + // Start preparing the configuration word for this timer. The configuration + // values for Timer A and Timer B provided in the config structure should + // match the register definitions already, so we will mostly just need to + // OR them together. + // + ui32ConfigVal = ( (psConfig->ui32TimerAConfig) | + (psConfig->ui32TimerBConfig << 16) ); + + // + // OR in the Link bit if the timers need to be linked. + // + ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0; + + // + // Find the correct register to write. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Write our configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // If all of the clock sources are not HRFC disable LDO when sleeping if timers are enabled. + // + if ( timers_use_hfrc() ) + { + AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 0); + } + else + { + AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 1); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_config() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. +//! +//! @param ui32ConfigVal specifies the configuration options for the selected +//! timer. +//! +//! This function should be used to perform the initial set-up of the +//! counter-timer. It can be used to configure either a 16-bit timer (A or B) or a +//! 32-bit timer using the BOTH option. +//! +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! The timer's clock source, mode, interrupt, and external pin behavior are +//! all controlled through the \e ui32Configval parameter. The valid options +//! for ui32ConfigVal include any ORed together combination of the following: +//! +//! Clock configuration macros: +//! +//! AM_HAL_CTIMER_HFRC_24MHZ +//! AM_HAL_CTIMER_LFRC_512HZ +//! ... etc. (See am_hal_ctimer.h for the full set of options.) +//! +//! Mode selection macros: +//! +//! AM_HAL_CTIMER_FN_ONCE +//! AM_HAL_CTIMER_FN_REPEAT +//! AM_HAL_CTIMER_FN_PWM_ONCE +//! AM_HAL_CTIMER_FN_PWM_REPEAT +//! AM_HAL_CTIMER_FN_CONTINUOUS +//! +//! Interrupt control: +//! +//! AM_HAL_CTIMER_INT_ENABLE +//! +//! Pin control: +//! +//! AM_HAL_CTIMER_PIN_ENABLE +//! AM_HAL_CTIMER_PIN_INVERT +//! +//! ADC trigger (Timer 3 only): +//! +//! AM_HAL_CTIMER_ADC_TRIG +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config_single(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal) +{ + volatile uint32_t *pui32ConfigReg; + uint32_t ui32WriteVal; + + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, ui32TimerSegment); + + // + // Find the correct register to write based on the timer number. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Save the value that's already in the register. + // + ui32WriteVal = AM_REGVAL(pui32ConfigReg); + + // + // If we're working with TIMERB, we need to shift our configuration value + // up by 16 bits. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16); + } + + // + // Replace part of the saved register value with the configuration value + // from the caller. + // + ui32WriteVal = (ui32WriteVal & ~(ui32TimerSegment)) | ui32ConfigVal; + + // + // If we're configuring both timers, we need to set the "link" bit. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + ui32WriteVal |= AM_HAL_CTIMER_LINK; + } + + // + // Write our completed configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32WriteVal; + + // + // If all of the clock sources are not HRFC disable LDO when sleeping if timers are enabled. + // + if ( timers_use_hfrc() ) + { + AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 0); + } + else + { + AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 1); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_config_single() + +//***************************************************************************** +// +//! @brief Start a timer +//! +//! @param ui32TimerNumber is the number of the timer to enable +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. Valid values for ui32TimerSegment are: +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! This function will enable a timer to begin incrementing. The \e +//! ui32TimerNumber parameter selects the timer that should be enabled, for +//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows +//! the caller to individually select a segment within a timer to be enabled, +//! such as TIMER0A, TIMER0B, or both. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_start(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + uint32_t ui32ConfigVal; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Read the current value. + // + ui32ConfigVal = *pui32ConfigReg; + + // + // Clear out the "clear" bit. + // + ui32ConfigVal &= ~(ui32TimerSegment & (AM_REG_CTIMER_CTRL0_TMRA0CLR_M | + AM_REG_CTIMER_CTRL0_TMRB0CLR_M)); + + // + // Set the "enable bit" + // + ui32ConfigVal |= (ui32TimerSegment & (AM_REG_CTIMER_CTRL0_TMRA0EN_M | + AM_REG_CTIMER_CTRL0_TMRB0EN_M)); + + // + // Write the value back to the register. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_start() + +//***************************************************************************** +// +//! @brief Stop a timer +//! +//! @param ui32TimerNumber is the number of the timer to disable. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! disabled. +//! +//! This function will stop the selected timer from incrementing. The \e +//! ui32TimerNumber parameter selects the timer that should be disabled, for +//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows +//! the caller to individually select a segment within a timer to be disabled, +//! such as TIMER0A, TIMER0B, or both. +//! +//! This function will stop a counter/timer from counting, but does not return +//! the count value to 'zero'. If you would like to reset the counter back to +//! zero, try the am_hal_ctimer_clear() function instead. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_stop(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Clear the "enable" bit + // + AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0EN_M | + AM_REG_CTIMER_CTRL0_TMRB0EN_M)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_stop() + +//***************************************************************************** +// +//! @brief Stops a timer and resets its value back to zero. +//! +//! @param ui32TimerNumber is the number of the timer to clear. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! cleared. +//! +//! This function will stop a free-running counter-timer, reset its value to +//! zero, and leave the timer disabled. When you would like to restart the +//! counter, you will need to call am_hal_ctimer_start(). +//! +//! The \e ui32TimerSegment parameter allows the caller to individually select +//! a segment within, such as TIMER0A, TIMER0B, or both. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +//! +//! +//! @note Setting the CLR bit is necessary for completing timer initialization +//! including after MCU resets. +//! +// +//***************************************************************************** +void +am_hal_ctimer_clear(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the "clear" bit + // + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0CLR_M | + AM_REG_CTIMER_CTRL0_TMRB0CLR_M)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_clear() + +//***************************************************************************** +// +//! @brief Returns the current free-running value of the selected timer. +//! +//! @param ui32TimerNumber is the number of the timer to read. +//! @param ui32TimerSegment specifies which segment of the timer should be +//! read. +//! +//! This function returns the current free-running value of the selected timer. +//! +//! @note When reading from a linked timer, be sure to use AM_HAL_CTIMER both +//! for the segment argument. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return Current timer value. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t ui32Value = 0; + uint32_t ui32Values[4] = {0, }; + uint32_t ui32TimerAddrTbl[4] = + { + REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR0_O, + REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR1_O, + REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR2_O, + REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR3_O + }; + + // + // Read the timer with back2back reads. This is a workaround for a clock + // domain synchronization issue. Some timer bits may be slow to increment, + // which means that the value in the timer register will sometimes be + // wrong. + // + // The architecture guarantees that: + // + // 1) If the timer is running at a speed close to the core frequency, the + // core and timer clock domains will be synchronized, and no "bad" reads + // will happen. + // + // 2) Bad reads will only happen if the core reads the timer register while + // the timer value is transitioning from one count to the next. + // + // 3) The timer will resolve to the correct value within one 24 MHz clock + // cycle. + // + // If we read the timer three times in a row with back-to-back load + // instructions, then we can guarantee that the timer will only have time + // to increment once, and that only one of the three reads can be wrong. + // This routine will perform the back-to-back reads and return all three + // values. The rest of this fuction determines which value we should + // actually use. + // + am_hal_triple_read(ui32TimerAddrTbl[ui32TimerNumber], ui32Values); + + // + // Shift or mask the values based on the given timer segment. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Values[0] >>= 16; + ui32Values[1] >>= 16; + ui32Values[2] >>= 16; + } + else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) + { + ui32Values[0] &= 0xFFFF; + ui32Values[1] &= 0xFFFF; + ui32Values[2] &= 0xFFFF; + } + + // + // Now, we'll figure out which of the three values is the correct time. + // + if (ui32Values[0] == ui32Values[1]) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32Value = ui32Values[1]; + } + else + { + // + // If the first two values didn't match, then one of them might be bad. + // If one of the first two values is bad, then the third one should + // always be correct. We'll take the third value as the correct time. + // + ui32Value = ui32Values[2]; + + // + // If all of the statements about the architecture are true, the third + // value should be correct, and it should always be within one count of + // either the first or the second value. + // + // Just in case, we'll check against the previous two values to make + // sure that our final answer was reasonable. If it isn't, we will + // flag it as a "bad read", and fail this assert statement. + // + // This shouldn't ever happen, and it hasn't ever happened in any of + // our tests so far. + // + am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) || + adjacent(ui32Values[0], ui32Values[2])), + "Bad CTIMER read"); + } + + return ui32Value; +} // am_hal_ctimer_read() + +//***************************************************************************** +// +//! @brief Enable output to the timer pin +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! This function will enable the output pin for the selected timer. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_pin_enable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the pin enable bit + // + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0PE_M | + AM_REG_CTIMER_CTRL0_TMRB0PE_M)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_pin_enable() + +//***************************************************************************** +// +//! @brief Disable the output pin. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! This function will disable the output pin for the selected timer. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Clear the pin enable bit + // + AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0PE_M | + AM_REG_CTIMER_CTRL0_TMRB0PE_M)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_pin_disable() + +//***************************************************************************** +// +//! @brief Set the polarity of the output pin. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param bInvertOutput determines whether the output should be inverted. If +//! true, the timer output pin for the selected timer segment will be +//! inverted. +//! +//! This function will set the polarity of the the output pin for the selected +//! timer. The \e ui32TimerSegment parameter allows the caller to individually +//! select a segment within, such as TIMER0A, TIMER0B, or both. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_pin_invert(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + bool bInvertOutput) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Figure out if we're supposed to be setting or clearing the polarity bit. + // + if ( bInvertOutput ) + { + // + // Set the polarity bit to invert the output. + // + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0POL_M | + AM_REG_CTIMER_CTRL0_TMRB0POL_M)); + } + else + { + // + // Clear the polarity bit. + // + AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & + (AM_REG_CTIMER_CTRL0_TMRA0POL_M | + AM_REG_CTIMER_CTRL0_TMRB0POL_M)); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_pin_invert() + +//***************************************************************************** +// +//! @brief Set a compare register. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @param ui32CompareReg specifies which compare register should be set +//! (either 0 or 1) +//! +//! @param ui32Value is the value that should be written to the compare +//! register. +//! +//! This function allows the caller to set the values in the compare registers +//! for a timer. These registers control the period and duty cycle of the +//! timers and their associated output pins. Please see the datasheet for +//! further information on the operation of the compare registers. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! @note For simple manipulations of period or duty cycle for timers and PWMs, +//! you may find it easier to use the am_hal_ctimer_period_set() function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, uint32_t ui32Value) +{ + volatile uint32_t *pui32CmprRegA, *pui32CmprRegB; + uint32_t ui32CmprRegA, ui32CmprRegB, ui32ValB; + + // + // Find the correct compare register to write. + // Assume A or BOTH. We'll change later if B. + // + pui32CmprRegA = (uint32_t *)(AM_REG_CTIMERn(0) + + AM_REG_CTIMER_CMPRA0_O + + (ui32TimerNumber * TIMER_OFFSET)); + pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET / 4; + + ui32ValB = ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) ? + ui32Value >> 16 : ui32Value & 0xFFFF; + + // + // Write the compare register with the selected value. + // Begin critical section while CMPR registers are modified. + // + AM_CRITICAL_BEGIN + + ui32CmprRegA = *pui32CmprRegA; + ui32CmprRegB = *pui32CmprRegB; + + if ( ui32CompareReg == 1 ) + { + // + // CMPR reg 1 + // Get the lower 16b (but may not be used if TIMERB). + // + ui32CmprRegA = ( (ui32CmprRegA & AM_REG_CTIMER_CMPRA0_CMPR0A0_M) | + AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Value & 0xFFFF) ); + + // + // Get the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & AM_REG_CTIMER_CMPRA0_CMPR0A0_M) | + AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32ValB) ); + } + else + { + // + // CMPR reg 0 + // Get the lower 16b (but may not be used if TIMERB) + // + ui32CmprRegA = ( (ui32CmprRegA & AM_REG_CTIMER_CMPRA0_CMPR1A0_M) | + AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Value & 0xFFFF) ); + + // + // Set the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & AM_REG_CTIMER_CMPRA0_CMPR1A0_M) | + AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32ValB) ); + } + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + *pui32CmprRegB = ui32CmprRegB; + } + else + { + // + // It's TIMERA or BOTH. + // + *pui32CmprRegA = ui32CmprRegA; + + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + *pui32CmprRegB = ui32CmprRegB; + } + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_compare_set() + +//***************************************************************************** +// +//! @brief Set the period and duty cycle of a timer. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32Period specifies the desired period. This parameter effectively +//! specifies the CTIMER CMPR field(s). The CMPR fields are handled in hardware +//! as (n+1) values, therefore ui32Period is actually specified as 1 less than +//! the desired period. Finally, as mentioned in the data sheet, the CMPR fields +//! cannot be 0 (a value of 1), so neither can ui32Period be 0. +//! +//! @param ui32OnTime set the number of clocks where the output signal is high. +//! +//! This function should be used for simple manipulations of the period and +//! duty cycle of a counter/timer. To set the period and/or duty cycle of a +//! linked timer pair, use AM_HAL_CTIMER_BOTH as the timer segment argument. If +//! you would like to set the period and/or duty cycle for both TIMERA and +//! TIMERB you will need to call this function twice: once for TIMERA, and once +//! for TIMERB. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @note The ui32OnTime parameter will only work if the timer is currently +//! operating in one of the PWM modes. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_period_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32Period, uint32_t ui32OnTime) +{ + volatile uint32_t *pui32ControlReg; + volatile uint32_t *pui32CompareRegA; + volatile uint32_t *pui32CompareRegB; + uint32_t ui32Mode, ui32Comp0, ui32Comp1; + + // + // Find the correct control register to pull the function select field + // from. + // + pui32ControlReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Find the correct compare registers to write. + // + pui32CompareRegA = (uint32_t *)(AM_REG_CTIMERn(0) + + AM_REG_CTIMER_CMPRA0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + pui32CompareRegB = (uint32_t *)(AM_REG_CTIMERn(0) + + AM_REG_CTIMER_CMPRB0_O + + (ui32TimerNumber * TIMER_OFFSET)); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Extract the timer mode from the register based on the ui32TimerSegment + // selected by the user. + // + ui32Mode = *pui32ControlReg; + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Mode = ui32Mode >> 16; + } + + // + // Mask to get to the bits we're interested in. + // + ui32Mode = ui32Mode & AM_REG_CTIMER_CTRL0_TMRA0FN_M; + + // + // If the mode is a PWM mode, we'll need to calculate the correct CMPR0 and + // CMPR1 values here. + // + if (ui32Mode == AM_HAL_CTIMER_FN_PWM_ONCE || + ui32Mode == AM_HAL_CTIMER_FN_PWM_REPEAT) + { + ui32Comp0 = ui32Period - ui32OnTime; + ui32Comp1 = ui32Period; + } + else + { + ui32Comp0 = ui32Period; + ui32Comp1 = 0; + } + + // + // Based on the timer segment argument, write the calculated Compare 0 and + // Compare 1 values to the correct halves of the correct registers. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) + { + // + // For timer A, write the values to the TIMERA compare register. + // + *pui32CompareRegA = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0) | + AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1)); + } + else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + // + // For timer B, write the values to the TIMERA compare register. + // + *pui32CompareRegB = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0) | + AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1)); + } + else + { + // + // For the linked case, write the lower halves of the values to the + // TIMERA compare register, and the upper halves to the TIMERB compare + // register. + // + *pui32CompareRegA = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0) | + AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1)); + + *pui32CompareRegB = (AM_REG_CTIMER_CMPRA0_CMPR0A0(ui32Comp0 >> 16) | + AM_REG_CTIMER_CMPRA0_CMPR1A0(ui32Comp1 >> 16)); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_period_set() + +//***************************************************************************** +// +//! @brief Enable the TIMERA3 ADC trigger +//! +//! This function enables the ADC trigger within TIMERA3. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_adc_trigger_enable(void) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable the ADC trigger. + // + AM_REGn(CTIMER, 0, CTRL3) |= AM_REG_CTIMER_CTRL3_ADCEN_M; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_adc_trigger_enable() + +//***************************************************************************** +// +//! @brief Disable the TIMERA3 ADC trigger +//! +//! This function disables the ADC trigger within TIMERA3. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_adc_trigger_disable(void) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the ADC trigger. + // + AM_REGn(CTIMER, 0, CTRL3) &= ~AM_REG_CTIMER_CTRL3_ADCEN_M; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_adc_trigger_disable() + +//***************************************************************************** +// +//! @brief Enables the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will enable the selected interrupts in the main CTIMER +//! interrupt enable register. In order to receive an interrupt from a timer, +//! you will need to enable the interrupt for that timer in this main register, +//! as well as in the timer control register (accessible though +//! am_hal_ctimer_config()), and in the NVIC. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERA0C0 +//! AM_HAL_CTIMER_INT_TIMERA0C1 +//! AM_HAL_CTIMER_INT_TIMERB0C0 +//! AM_HAL_CTIMER_INT_TIMERB0C1 +//! AM_HAL_CTIMER_INT_TIMERA1C0 +//! AM_HAL_CTIMER_INT_TIMERA1C1 +//! AM_HAL_CTIMER_INT_TIMERB1C0 +//! AM_HAL_CTIMER_INT_TIMERB1C1 +//! AM_HAL_CTIMER_INT_TIMERA2C0 +//! AM_HAL_CTIMER_INT_TIMERA2C1 +//! AM_HAL_CTIMER_INT_TIMERB2C0 +//! AM_HAL_CTIMER_INT_TIMERB2C1 +//! AM_HAL_CTIMER_INT_TIMERA3C0 +//! AM_HAL_CTIMER_INT_TIMERA3C1 +//! AM_HAL_CTIMER_INT_TIMERB3C0 +//! AM_HAL_CTIMER_INT_TIMERB3C1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_enable(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable the interrupt at the module level. + // + AM_REGn(CTIMER, 0, INTEN) |= ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_enable() + +//***************************************************************************** +// +//! @brief Return the enabled timer interrupts. +//! +//! This function will return all enabled interrupts in the main CTIMER +//! interrupt enable register. +//! +//! @return return enabled interrupts. This will be a logical or of: +//! +//! AM_HAL_CTIMER_INT_TIMERA0C0 +//! AM_HAL_CTIMER_INT_TIMERA0C1 +//! AM_HAL_CTIMER_INT_TIMERB0C0 +//! AM_HAL_CTIMER_INT_TIMERB0C1 +//! AM_HAL_CTIMER_INT_TIMERA1C0 +//! AM_HAL_CTIMER_INT_TIMERA1C1 +//! AM_HAL_CTIMER_INT_TIMERB1C0 +//! AM_HAL_CTIMER_INT_TIMERB1C1 +//! AM_HAL_CTIMER_INT_TIMERA2C0 +//! AM_HAL_CTIMER_INT_TIMERA2C1 +//! AM_HAL_CTIMER_INT_TIMERB2C0 +//! AM_HAL_CTIMER_INT_TIMERB2C1 +//! AM_HAL_CTIMER_INT_TIMERA3C0 +//! AM_HAL_CTIMER_INT_TIMERA3C1 +//! AM_HAL_CTIMER_INT_TIMERB3C0 +//! AM_HAL_CTIMER_INT_TIMERB3C1 +//! +//! @return Return the enabled timer interrupts. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return AM_REGn(CTIMER, 0, INTEN); +} // am_hal_ctimer_int_enable_get() + +//***************************************************************************** +// +//! @brief Disables the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will disable the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERA0C0 +//! AM_HAL_CTIMER_INT_TIMERA0C1 +//! AM_HAL_CTIMER_INT_TIMERB0C0 +//! AM_HAL_CTIMER_INT_TIMERB0C1 +//! AM_HAL_CTIMER_INT_TIMERA1C0 +//! AM_HAL_CTIMER_INT_TIMERA1C1 +//! AM_HAL_CTIMER_INT_TIMERB1C0 +//! AM_HAL_CTIMER_INT_TIMERB1C1 +//! AM_HAL_CTIMER_INT_TIMERA2C0 +//! AM_HAL_CTIMER_INT_TIMERA2C1 +//! AM_HAL_CTIMER_INT_TIMERB2C0 +//! AM_HAL_CTIMER_INT_TIMERB2C1 +//! AM_HAL_CTIMER_INT_TIMERA3C0 +//! AM_HAL_CTIMER_INT_TIMERA3C1 +//! AM_HAL_CTIMER_INT_TIMERB3C0 +//! AM_HAL_CTIMER_INT_TIMERB3C1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_disable(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the interrupt at the module level. + // + AM_REGn(CTIMER, 0, INTEN) &= ~ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_disable() + +//***************************************************************************** +// +//! @brief Clears the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will clear the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERA0C0 +//! AM_HAL_CTIMER_INT_TIMERA0C1 +//! AM_HAL_CTIMER_INT_TIMERB0C0 +//! AM_HAL_CTIMER_INT_TIMERB0C1 +//! AM_HAL_CTIMER_INT_TIMERA1C0 +//! AM_HAL_CTIMER_INT_TIMERA1C1 +//! AM_HAL_CTIMER_INT_TIMERB1C0 +//! AM_HAL_CTIMER_INT_TIMERB1C1 +//! AM_HAL_CTIMER_INT_TIMERA2C0 +//! AM_HAL_CTIMER_INT_TIMERA2C1 +//! AM_HAL_CTIMER_INT_TIMERB2C0 +//! AM_HAL_CTIMER_INT_TIMERB2C1 +//! AM_HAL_CTIMER_INT_TIMERA3C0 +//! AM_HAL_CTIMER_INT_TIMERA3C1 +//! AM_HAL_CTIMER_INT_TIMERB3C0 +//! AM_HAL_CTIMER_INT_TIMERB3C1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_clear(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + AM_REGn(CTIMER, 0, INTCLR) = ui32Interrupt; +} // am_hal_ctimer_int_clear() + +//***************************************************************************** +// +//! @brief Sets the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will set the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERA0C0 +//! AM_HAL_CTIMER_INT_TIMERA0C1 +//! AM_HAL_CTIMER_INT_TIMERB0C0 +//! AM_HAL_CTIMER_INT_TIMERB0C1 +//! AM_HAL_CTIMER_INT_TIMERA1C0 +//! AM_HAL_CTIMER_INT_TIMERA1C1 +//! AM_HAL_CTIMER_INT_TIMERB1C0 +//! AM_HAL_CTIMER_INT_TIMERB1C1 +//! AM_HAL_CTIMER_INT_TIMERA2C0 +//! AM_HAL_CTIMER_INT_TIMERA2C1 +//! AM_HAL_CTIMER_INT_TIMERB2C0 +//! AM_HAL_CTIMER_INT_TIMERB2C1 +//! AM_HAL_CTIMER_INT_TIMERA3C0 +//! AM_HAL_CTIMER_INT_TIMERA3C1 +//! AM_HAL_CTIMER_INT_TIMERB3C0 +//! AM_HAL_CTIMER_INT_TIMERB3C1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + AM_REGn(CTIMER, 0, INTSET) = ui32Interrupt; +} // am_hal_ctimer_int_set() + +//***************************************************************************** +// +//! @brief Returns either the enabled or raw timer interrupt status. +//! +//! This function will return the timer interrupt status. +//! +//! @return bEnabledOnly if true returns the status of the enabled interrupts +//! only. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERA0C0 +//! AM_HAL_CTIMER_INT_TIMERA0C1 +//! AM_HAL_CTIMER_INT_TIMERB0C0 +//! AM_HAL_CTIMER_INT_TIMERB0C1 +//! AM_HAL_CTIMER_INT_TIMERA1C0 +//! AM_HAL_CTIMER_INT_TIMERA1C1 +//! AM_HAL_CTIMER_INT_TIMERB1C0 +//! AM_HAL_CTIMER_INT_TIMERB1C1 +//! AM_HAL_CTIMER_INT_TIMERA2C0 +//! AM_HAL_CTIMER_INT_TIMERA2C1 +//! AM_HAL_CTIMER_INT_TIMERB2C0 +//! AM_HAL_CTIMER_INT_TIMERB2C1 +//! AM_HAL_CTIMER_INT_TIMERA3C0 +//! AM_HAL_CTIMER_INT_TIMERA3C1 +//! AM_HAL_CTIMER_INT_TIMERB3C0 +//! AM_HAL_CTIMER_INT_TIMERB3C1 +//! +//! @return Returns either the timer interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_int_status_get(bool bEnabledOnly) +{ + // + // Return the desired status. + // + if ( bEnabledOnly ) + { + uint32_t u32RetVal; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + u32RetVal = AM_REGn(CTIMER, 0, INTSTAT); + u32RetVal &= AM_REGn(CTIMER, 0, INTEN); + + // + // Done with critical section. + // + AM_CRITICAL_END + + return u32RetVal; + } + else + { + return AM_REGn(CTIMER, 0, INTSTAT); + } +} // am_hal_ctimer_int_status_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_ctimer.h b/mcu/apollo2/hal/am_hal_ctimer.h new file mode 100644 index 0000000..e26b042 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_ctimer.h @@ -0,0 +1,278 @@ +//***************************************************************************** +// +// am_hal_ctimer.h +//! @file +//! +//! @brief Functions for accessing and configuring the CTIMER. +//! +//! @addtogroup ctimer2 Counter/Timer (CTIMER) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_CTIMER_H +#define AM_HAL_CTIMER_H + +//***************************************************************************** +// +//! Number of timers +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMERS_NUM 4 + +//***************************************************************************** +// +//! Timer offset value +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMER_OFFSET (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O) + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_TIMERA0C0 AM_REG_CTIMER_INTEN_CTMRA0C0INT_M +#define AM_HAL_CTIMER_INT_TIMERA0C1 AM_REG_CTIMER_INTEN_CTMRA0C1INT_M +#define AM_HAL_CTIMER_INT_TIMERA1C0 AM_REG_CTIMER_INTEN_CTMRA1C0INT_M +#define AM_HAL_CTIMER_INT_TIMERA1C1 AM_REG_CTIMER_INTEN_CTMRA1C1INT_M +#define AM_HAL_CTIMER_INT_TIMERA2C0 AM_REG_CTIMER_INTEN_CTMRA2C0INT_M +#define AM_HAL_CTIMER_INT_TIMERA2C1 AM_REG_CTIMER_INTEN_CTMRA2C1INT_M +#define AM_HAL_CTIMER_INT_TIMERA3C0 AM_REG_CTIMER_INTEN_CTMRA3C0INT_M +#define AM_HAL_CTIMER_INT_TIMERA3C1 AM_REG_CTIMER_INTEN_CTMRA3C1INT_M + +#define AM_HAL_CTIMER_INT_TIMERB0C0 AM_REG_CTIMER_INTEN_CTMRB0C0INT_M +#define AM_HAL_CTIMER_INT_TIMERB0C1 AM_REG_CTIMER_INTEN_CTMRB0C1INT_M +#define AM_HAL_CTIMER_INT_TIMERB1C0 AM_REG_CTIMER_INTEN_CTMRB1C0INT_M +#define AM_HAL_CTIMER_INT_TIMERB1C1 AM_REG_CTIMER_INTEN_CTMRB1C1INT_M +#define AM_HAL_CTIMER_INT_TIMERB2C0 AM_REG_CTIMER_INTEN_CTMRB2C0INT_M +#define AM_HAL_CTIMER_INT_TIMERB2C1 AM_REG_CTIMER_INTEN_CTMRB2C1INT_M +#define AM_HAL_CTIMER_INT_TIMERB3C0 AM_REG_CTIMER_INTEN_CTMRB3C0INT_M +#define AM_HAL_CTIMER_INT_TIMERB3C1 AM_REG_CTIMER_INTEN_CTMRB3C1INT_M + +// +// Deprecated, use the newer macros above. +// +#define AM_HAL_CTIMER_INT_TIMERA0 AM_HAL_CTIMER_INT_TIMERA0C0 +#define AM_HAL_CTIMER_INT_TIMERB0 AM_HAL_CTIMER_INT_TIMERB0C0 +#define AM_HAL_CTIMER_INT_TIMERA1 AM_HAL_CTIMER_INT_TIMERA1C0 +#define AM_HAL_CTIMER_INT_TIMERB1 AM_HAL_CTIMER_INT_TIMERB1C0 +#define AM_HAL_CTIMER_INT_TIMERA2 AM_HAL_CTIMER_INT_TIMERA2C0 +#define AM_HAL_CTIMER_INT_TIMERB2 AM_HAL_CTIMER_INT_TIMERB2C0 +#define AM_HAL_CTIMER_INT_TIMERA3 AM_HAL_CTIMER_INT_TIMERA3C0 +#define AM_HAL_CTIMER_INT_TIMERB3 AM_HAL_CTIMER_INT_TIMERB3C0 +//! @} + +//***************************************************************************** +// +//! @name Configuration options +//! @brief Configuration options for \e am_hal_ctimer_config_t +//! +//! These options are to be used with the \e am_hal_ctimer_config_t structure +//! used by \e am_hal_ctimer_config +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_CLK_PIN AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0) +#define AM_HAL_CTIMER_HFRC_12MHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x1) +#define AM_HAL_CTIMER_HFRC_3MHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x2) +#define AM_HAL_CTIMER_HFRC_187_5KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x3) +#define AM_HAL_CTIMER_HFRC_47KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x4) +#define AM_HAL_CTIMER_HFRC_12KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x5) +#define AM_HAL_CTIMER_XT_32_768KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x6) +#define AM_HAL_CTIMER_XT_16_384KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x7) +#define AM_HAL_CTIMER_XT_2_048KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x8) +#define AM_HAL_CTIMER_XT_256HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x9) +#define AM_HAL_CTIMER_LFRC_512HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xA) +#define AM_HAL_CTIMER_LFRC_32HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xB) +#define AM_HAL_CTIMER_LFRC_1HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xC) +#define AM_HAL_CTIMER_LFRC_1_16HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xD) +#define AM_HAL_CTIMER_RTC_100HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xE) +#define AM_HAL_CTIMER_HCLK AM_REG_CTIMER_CTRL0_TMRA0CLK(0xF) +#define AM_HAL_CTIMER_BUCK AM_REG_CTIMER_CTRL0_TMRA0CLK(0x10) +//! @} + +//***************************************************************************** +// +// Timer function macros. +// +//***************************************************************************** +#define AM_HAL_CTIMER_FN_ONCE AM_REG_CTIMER_CTRL0_TMRA0FN(0) +#define AM_HAL_CTIMER_FN_REPEAT AM_REG_CTIMER_CTRL0_TMRA0FN(1) +#define AM_HAL_CTIMER_FN_PWM_ONCE AM_REG_CTIMER_CTRL0_TMRA0FN(2) +#define AM_HAL_CTIMER_FN_PWM_REPEAT AM_REG_CTIMER_CTRL0_TMRA0FN(3) +#define AM_HAL_CTIMER_FN_CONTINUOUS AM_REG_CTIMER_CTRL0_TMRA0FN(4) + +//***************************************************************************** +// +// Half-timer options. +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_ENABLE AM_REG_CTIMER_CTRL0_TMRA0IE0_M +#define AM_HAL_CTIMER_PIN_ENABLE AM_REG_CTIMER_CTRL0_TMRA0PE_M +#define AM_HAL_CTIMER_PIN_INVERT AM_REG_CTIMER_CTRL0_TMRA0POL_M +#define AM_HAL_CTIMER_CLEAR AM_REG_CTIMER_CTRL0_TMRA0CLR_M + +//***************************************************************************** +// +// Additional timer options. +// +//***************************************************************************** +#define AM_HAL_CTIMER_LINK AM_REG_CTIMER_CTRL0_CTLINK0_M +#define AM_HAL_CTIMER_ADC_TRIG AM_REG_CTIMER_CTRL3_ADCEN_M + +//***************************************************************************** +// +// Timer selection macros. +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMERA 0x0000FFFF +#define AM_HAL_CTIMER_TIMERB 0xFFFF0000 +#define AM_HAL_CTIMER_BOTH 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +// Timer configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit + //! timers. + // + uint32_t ui32Link; + + // + //! Configuration options for TIMERA + // + uint32_t ui32TimerAConfig; + + // + //! Configuration options for TIMERB + // + uint32_t ui32TimerBConfig; + +} +am_hal_ctimer_config_t; + +//***************************************************************************** +// +// Function pointer type for CTimer interrupt handlers. +// +//***************************************************************************** +typedef void (*am_hal_ctimer_handler_t)(void); + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_ctimer_config(uint32_t ui32TimerNumber, + am_hal_ctimer_config_t *psConfig); + +extern void am_hal_ctimer_config_single(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_start(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_stop(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_clear(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_pin_enable(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_pin_invert(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + bool bInvertOutput); + +extern void am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, + uint32_t ui32Value); + +extern void am_hal_ctimer_period_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32Period, + uint32_t ui32OnTime); + +extern void am_hal_ctimer_adc_trigger_enable(void); +extern void am_hal_ctimer_adc_trigger_disable(void); +extern void am_hal_ctimer_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_ctimer_int_enable_get(void); +extern void am_hal_ctimer_int_disable(uint32_t ui32Interrupt); +extern void am_hal_ctimer_int_set(uint32_t ui32Interrupt); +extern void am_hal_ctimer_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_ctimer_int_status_get(bool bEnabledOnly); +extern void am_hal_ctimer_int_register(uint32_t ui32Interrupt, + am_hal_ctimer_handler_t pfnHandler); +extern void am_hal_ctimer_int_service(uint32_t ui32Status); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CTIMER_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_debug.c b/mcu/apollo2/hal/am_hal_debug.c new file mode 100644 index 0000000..b8b796a --- /dev/null +++ b/mcu/apollo2/hal/am_hal_debug.c @@ -0,0 +1,81 @@ +//***************************************************************************** +// +// am_hal_debug.c +//! @file +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Default implementation of a failed ASSERT statement. +//! +//! @param pcFile is the name of the source file where the error occurred. +//! @param ui32Line is the line number where the error occurred. +//! @param pcMessage is an optional message describing the failure. +//! +//! This function is called by am_hal_debug_assert() macro when the supplied +//! condition is not true. The implementation here simply halts the application +//! for further analysis. Individual applications may define their own +//! implementations of am_hal_debug_error() to provide more detailed feedback +//! about the failed am_hal_debug_assert() statement. +//! +//! @return +// +//***************************************************************************** +#if defined (__IAR_SYSTEMS_ICC__) +__weak void +#else +void __attribute__((weak)) +#endif +am_hal_debug_error(const char *pcFile, uint32_t ui32Line, const char *pcMessage) +{ + // + // Halt for analysis. + // + while(1); +} diff --git a/mcu/apollo2/hal/am_hal_debug.h b/mcu/apollo2/hal/am_hal_debug.h new file mode 100644 index 0000000..720ef32 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_debug.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// am_hal_debug.h +//! @file +//! +//! @brief Useful macros for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +//! +//! @addtogroup haldebug3 HAL Debug/Assert Utilities +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_DEBUG_H +#define AM_HAL_DEBUG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Determine DBG_FILENAME +// +//***************************************************************************** +// +// By spec and convention, the standard __FILE__ compiler macro includes a full +// path (absolute or relative) to the file being compiled. This makes recreating +// binaries virtually impossible unless rebuilt on the same or identically +// configured system. +// +// To be able to build consistent binaries on different systems, we want to make +// sure the full pathname is not included in the binary. Only IAR EWARM provides +// an easy mechanism to provide only the filename without the path. For other +// platforms, we will simply use a generic pathname. +// +#if defined (__IAR_SYSTEMS_ICC__) +// +// With EWARM the --no_path_in_file_macros option reduces __FILE__ to only the +// module name. Therefore this define assumes the option is being used. +// +#define DBG_FILENAME __FILE__ +#elif defined(__KEIL__) +// +// Keil provides __MODULE__ which is simply the module name portion of __FILE__. +// +#define DBG_FILENAME __MODULE__ +#elif defined(__ARMCC_VERSION) +#define DBG_FILENAME __MODULE__ +#else +// +// With GCC, we're out of luck. +// +#define DBG_FILENAME "debug_filename.ext" +//#define DBG_FILENAME __FILE__ +#endif + +//***************************************************************************** +// +// Debug assert macros. +// +//***************************************************************************** +#ifndef AM_HAL_DEBUG_NO_ASSERT + +#define am_hal_debug_assert_msg(bCondition, pcMessage) \ + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, pcMessage) + +#define am_hal_debug_assert(bCondition) \ + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, 0) + +#else + +#define am_hal_debug_assert_msg(bCondition, pcMessage) +#define am_hal_debug_assert(bCondition) + +#endif // AM_DEBUG_ASSERT + +//***************************************************************************** +// +// External function prototypes. +// +//***************************************************************************** +extern void am_hal_debug_error(const char *pcFile, uint32_t ui32Line, + const char *pcMessage); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_DEBUG_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_flash.c b/mcu/apollo2/hal/am_hal_flash.c new file mode 100644 index 0000000..55a65a7 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_flash.c @@ -0,0 +1,1601 @@ +//***************************************************************************** +// +// am_hal_flash.c +//! @file +//! +//! @brief Functions for performing Flash operations. +//! +//! @addtogroup flash2 Flash +//! @ingroup apollo2hal +//! +//! IMPORTANT: Interrupts are active during execution of all HAL flash +//! functions. If an interrupt occurs during execution of a flash function +//! that programs or erases flash or INFO space, errors will occur if the +//! interrupt service routine (ISR) is located in on-chip flash. +//! If interrupts are expected during execution of a flash function that +//! programs or erases either flash or INFO space: +//! - Interrupts must be disabled via a critical section handler prior to +//! calling the flash function. +//! - Alternatively, applicable ISRs must be located in non-flash address space +//! (i.e. SRAM, off-chip ROM, etc.). +//! +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +// +// Look-up table +// +const g_am_hal_flash_t g_am_hal_flash = +{ + // + // The basics. + // + // flash_mass_erase() + ((int (*) (uint32_t, uint32_t)) 0x0800004d), + // flash_page_erase() + ((int (*) (uint32_t, uint32_t, uint32_t)) 0x08000051), + // flash_program_main() + ((int (*) (uint32_t, uint32_t *, uint32_t *, uint32_t)) 0x08000055), + // flash_program_info() + ((int (*) (uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t)) 0x08000059), + + // + // Non-blocking variants, but be careful these are not interrupt safe so + // mask interrupts while these very long operations proceed. + // + // flash_mass_erase_nb() + ((int (*)(uint32_t, uint32_t)) 0x0800006d), + // flash_page_erase_nb() + ((int (*)(uint32_t, uint32_t, uint32_t)) 0x08000071), + // flash_nb_operation_complete() + ((bool (*)(void)) 0x0800007d), + + // + // Essentially these are recovery options. + // + // flash_erase_info() + ((int (*)(uint32_t, uint32_t)) 0x08000081), + // flash_erase_main_plus_info() + ((int (*)(uint32_t, uint32_t)) 0x08000089), + // flash_erase_main_plus_info_both_instances() + ((int (*)(uint32_t)) 0x08000091), + // flash_recovery() + ((void (*)(uint32_t)) 0x08000099), + + // + // Useful utilities. + // + // flash_util_read_word() + ((uint32_t (*)(uint32_t*)) 0x08000075), + // flash_util_write_word() + ((void (*)(uint32_t*, uint32_t)) 0x08000079), + // delay_cycles() + ((void (*)(uint32_t)) 0x0800009d), + + // + // The following functions pointers must never be called from user + // programs. They are here primarily to document these entry points + // which are usable from a debugger or debugger script. + // + // flash_program_main_sram() + ((void (*) (void)) 0x0800005d), + // flash_program_info_sram() + ((void (*) (void)) 0x08000061), + // flash_erase_main_pages_sram() + ((void (*) (void)) 0x08000065), + // flash_mass_erase_sram() + ((void (*) (void)) 0x08000069), + // flash_erase_info_sram() + ((void (*)(void)) 0x08000085), + // flash_erase_main_plus_info_sram() + ((void (*)(void)) 0x0800008d) +}; + +const uint32_t ui32SramMaxAddr = 0x10040000; +//***************************************************************************** +// +//! @brief This function performs a mass erase on a flash instance. +//! +//! @param ui32Value - The flash program key. +//! @param ui32FlashInst - The flash instance to erase. +//! +//! This function will erase the desired instance of flash. +//! +//! @note For Apollo2, each flash instance contains a maximum of 512KB. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_mass_erase(uint32_t ui32Value, uint32_t ui32FlashInst) +{ + return g_am_hal_flash.flash_mass_erase(ui32Value, ui32FlashInst); +} + +//***************************************************************************** +// +//! @brief This function performs a page erase on a flash instance. +//! +//! @param ui32Value - The flash program key. +//! @param ui32FlashInst - The flash instance to reference the page number with. +//! @param ui32PageNum - The flash page relative to the specified instance. +//! +//! This function will erase the desired flash page in the desired instance of +//! flash. +//! +//! @note For Apollo2, each flash page is 8KB (or AM_HAL_FLASH_PAGE_SIZE). +//! Each flash instance contains a maximum of 64 pages (or +//! AM_HAL_FLASH_INSTANCE_PAGES). +//! +//! @note When given an absolute flash address, a couple of helpful macros can +//! be utilized when calling this function. +//! For example: +//! am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, +//! AM_HAL_FLASH_ADDR2INST(ui32Addr), +//! AM_HAL_FLASH_ADDR2PAGE(ui32Addr) ); +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_page_erase(uint32_t ui32Value, uint32_t ui32FlashInst, + uint32_t ui32PageNum) +{ + return g_am_hal_flash.flash_page_erase(ui32Value, + ui32FlashInst, + ui32PageNum); +} + +//***************************************************************************** +// +//! @brief This programs up to N words of the Main array on one flash instance. +//! +//! @param ui32Value - The programming key, AM_HAL_FLASH_PROGRAM_KEY. +//! @param pui32Src - Pointer to word aligned array of data to program into +//! the flash instance. +//! @param pui32Dst - Pointer to the word aligned flash location where +//! programming of the flash instance is to begin. +//! @param ui32NumWords - The number of words to be programmed. +//! +//! This function will program multiple words in main flash. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_program_main(uint32_t ui32Value, uint32_t *pui32Src, + uint32_t *pui32Dst, uint32_t ui32NumWords) +{ + uint32_t ui32MaxSrcAddr = (uint32_t)pui32Src + (ui32NumWords << 2); + + // workround, the last word of SRAM cannot be the source + // of programming by BootRom, check to see if it is the last + if (ui32MaxSrcAddr == ui32SramMaxAddr) + { + uint32_t ui32Temp; + int iRetVal; + + // program the other words using the HAL function + if (ui32NumWords > 1) + { + iRetVal = am_hal_flash_program_main( + ui32Value, + pui32Src, + pui32Dst, + ui32NumWords - 1); + // return if anything wrong + if (iRetVal != 0) + { + return iRetVal; + } + } + // program the last word of the pSrc from a local + // variable if it is the last word of SRAM + ui32Temp = *(uint32_t *)(ui32MaxSrcAddr - 4); + return g_am_hal_flash.flash_program_main( + ui32Value, + &ui32Temp, + pui32Dst + ui32NumWords - 1, + 1); + } + + return g_am_hal_flash.flash_program_main(ui32Value, pui32Src, + pui32Dst, ui32NumWords); +} + +//***************************************************************************** +// +//! @brief This function programs multiple words in the customer INFO space. +//! +//! @param ui32Value - The customer INFO space key. +//! @param ui32InfoInst - The INFO space instance, 0 or 1. +//! @param *pui32Src - Pointer to word aligned array of data to program into +//! the customer INFO space. +//! @param ui32Offset - Word offset into customer INFO space (offset of 0 is +//! the first word, 1 is second word, etc.). +//! @param ui32NumWords - The number of words to be programmed, must not +//! exceed AM_HAL_FLASH_INFO_SIZE/4. +//! +//! This function will program multiple words in the customer INFO space. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_program_info(uint32_t ui32Value, uint32_t ui32InfoInst, + uint32_t *pui32Src, uint32_t ui32Offset, + uint32_t ui32NumWords) +{ + uint32_t ui32MaxSrcAddr = (uint32_t)pui32Src + (ui32NumWords << 2); + + // workround, the last word of SRAM cannot be the source + // of programming by BootRom, check to see if it is the last + if (ui32MaxSrcAddr == ui32SramMaxAddr) + { + uint32_t ui32Temp; + int iRetVal; + + // program the other words using the HAL function + if (ui32NumWords > 1) + { + iRetVal = am_hal_flash_program_info( + ui32Value, + ui32InfoInst, + pui32Src, + ui32Offset, + ui32NumWords - 1); + // return if anything wrong + if (iRetVal != 0) + { + return iRetVal; + } + } + // program the last word of the pSrc from a local + // variable if it is the last word of SRAM + ui32Temp = *(uint32_t *)(ui32MaxSrcAddr - 4); + return g_am_hal_flash.flash_program_info( + ui32Value, + ui32InfoInst, + &ui32Temp, + ui32Offset + ui32NumWords - 1, + 1); + } + return g_am_hal_flash.flash_program_info(ui32Value, 0, pui32Src, + ui32Offset, ui32NumWords); +} + +//***************************************************************************** +// +//! @brief This function erases an instance of the customer INFO space. +//! +//! @param ui32ProgramKey - The customer INFO space programming key +//! (AM_HAL_FLASH_PROGRAM_KEY). +//! @param ui32Inst - The flash instance, either 0 or 1. +//! +//! This function will erase the the customer INFO space of the specified +//! instance. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_erase_info(uint32_t ui32ProgramKey, + uint32_t ui32Inst) +{ + return g_am_hal_flash.flash_erase_info(ui32ProgramKey, ui32Inst); +} + +//***************************************************************************** +// +//! @brief This function erases the main instance + the customer INFO space. +//! +//! @param ui32ProgramKey - The customer INFO space key. +//! @param ui32Inst - The flash instance, either 0 or 1. +//! +//! This function will erase the main flash + the customer INFO space of the +//! specified instance. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_erase_main_plus_info(uint32_t ui32ProgramKey, + uint32_t ui32Inst) +{ + return g_am_hal_flash.flash_erase_main_plus_info(ui32ProgramKey, + ui32Inst); +} + +//***************************************************************************** +// +//! @brief This function erases the main flash + the customer INFO space. +//! +//! @param ui32ProgramKey - The customer INFO space key. +//! +//! This function will erase both instances the main flash + the +//! customer INFO space. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +// +//***************************************************************************** +int +am_hal_flash_erase_main_plus_info_both_instances(uint32_t ui32ProgramKey) +{ + return g_am_hal_flash.flash_erase_main_plus_info_both_instances( + ui32ProgramKey); +} + +//***************************************************************************** +// +//! @brief This function erases both main flash instances + both customer INFO +//! space instances. +//! +//! @param ui32RecoveryKey - The recovery key. +//! +//! This function erases both main instances and both customer INFO instances +//! even if the customer INFO space is programmed to not be erasable. This +//! function completely erases the flash main and info instances and wipes the +//! SRAM. Upon completion of the erasure operations, it does a POI (power on +//! initialization) reset. +//! +//! @note The various customer INFO protections that were previously enabled, +//! such as debugger disable, SWO disable, etc., will not recover after calling +//! this function even though customer INFO space is erased. Once activated, +//! these customer enabled protections require a higher-level reset than POI +//! (e.g. POS/POA, which is essentially a power cycle) in order to deactivate. +//! This is true even though only a POI was required in order to activate them. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Never Returns!!! +// +//***************************************************************************** +void +am_hal_flash_recovery(uint32_t ui32RecoveryKey) +{ + g_am_hal_flash.flash_recovery(ui32RecoveryKey); +} + +//***************************************************************************** +// +//! @brief Return ui32 value obtained from anywhere in D Code or System Bus +//! +//! @param ui32Address - return the value corresponding to this location. +//! +//! Use this function to read a value from various peripheral locations +//! that must be read from code running external to flash. +//! +//! @return the value found +// +//***************************************************************************** +uint32_t +am_hal_flash_load_ui32(uint32_t ui32Address) +{ + return g_am_hal_flash.flash_util_read_word((uint32_t*)ui32Address); +} + +//***************************************************************************** +// +//! @brief Use the bootrom to write to a location in SRAM or the system bus. +//! +//! @param ui32Address - Store the data value corresponding to this location. +//! @param ui32Data - 32-bit Data to be stored. +//! +//! Use this function to store a value to various peripheral or SRAM locations +//! that can not be touched from code running in SRAM or FLASH. There is no +//! known need for this function in Apollo2 at this time. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data) +{ + g_am_hal_flash.flash_util_write_word((uint32_t*)ui32Address, + ui32Data); +} + +//***************************************************************************** +// +//! @brief Use the bootrom to implement a spin loop. +//! +//! @param ui32Iterations - Number of iterations to delay. +//! +//! Use this function to implement a CPU busy waiting spin loop without cache +//! or delay uncertainties. +//! +//! Note that the ROM-based function executes at 3 cycles per iteration plus +//! the regular function call, entry, and exit overhead. +//! The call and return overhead, including the call to this function, is +//! somewhere in the neighborhood of 14 cycles, or 4.7 iterations. +//! +//! Example: +//! - MCU operating at 48MHz -> 20.83 ns / cycle +//! - Therefore each iteration (once inside the bootrom function) will consume +//! 62.5ns. +//! - The total overhead (assuming 14 cycles) is 292ns. +//! - For ui32Iterations=28: Total delay time = 0.292 + (0.0625 * 28) = 2.04us. +//! +//! The FLASH_CYCLES_US(n) macro can be used with am_hal_flash_delay() to +//! get an approximate microsecond delay. +//! e.g. For a 2us delay, use: +//! am_hal_flash_delay( FLASH_CYCLES_US(2) ); +//! +//! @note Interrupts are active during execution of this function. Therefore, +//! any interrupt taken will affect the delay timing. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_flash_delay(uint32_t ui32Iterations) +{ + g_am_hal_flash.delay_cycles(ui32Iterations); +} + +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status change. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_change(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value) +{ + while ( ui32usMaxDelay-- ) + { + // + // Check the status + // + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return 1; + } + + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + + return 0; +} // am_hal_flash_delay_status_change() + +//***************************************************************************** +// +//! @brief Static Helper Function to check customer info valid bits erasure. +//! +//! Use this function to test the state of the 128 valid bits at the beginning +//! of customer info space. If these are all erased then return true. +//! +//! @return true if the customer info bits are currently erased. +// +//***************************************************************************** +static bool +customer_info_signature_erased(void) +{ + uint32_t *pui32Signature = (uint32_t *) AM_HAL_FLASH_INFO_ADDR; + + return ( (pui32Signature[3] == 0xFFFFFFFF) && + (pui32Signature[2] == 0xFFFFFFFF) && + (pui32Signature[1] == 0xFFFFFFFF) && + (pui32Signature[0] == 0xFFFFFFFF) ) ? true : false; +} + +//***************************************************************************** +// +//! @brief Static Helper Function to set customer info valid bits +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space. If these bits are not set correctly then the +//! customer protection bits in the INFO space will not be honored by the +//! hardware. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +static int +customer_info_signature_set(void) +{ + uint32_t ui32Valid[4]; + int iRC; + + // + // If they are already set then we are done. + // + if ( am_hal_flash_customer_info_signature_check() ) + { + return 0; + } + + // + // If they are not erased at this point we have an error. + // + if ( !customer_info_signature_erased() ) + { + return (2 << 16); + } + + // + // OK they need to be set so do it. + // + ui32Valid[3] = AM_HAL_FLASH_INFO_SIGNATURE3; + ui32Valid[2] = AM_HAL_FLASH_INFO_SIGNATURE2; + ui32Valid[1] = AM_HAL_FLASH_INFO_SIGNATURE1; + ui32Valid[0] = AM_HAL_FLASH_INFO_SIGNATURE0; + + iRC = g_am_hal_flash.flash_program_info(AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + ui32Valid, // source data + 0, // offset + 4); // number of words + return iRC | ((iRC) ? (1 << 16) : 0); +} + +//***************************************************************************** +// +//! @brief Check that the customer info bits are valid. +//! +//! Use this function to test the state of the 128 valid bits at the beginning +//! of customer info space. If these are not set correctly then the customer +//! protection bits in the INFO space will not be honored by the hardware. +//! +//! @return true if valid. +// +//***************************************************************************** +bool +am_hal_flash_customer_info_signature_check(void) +{ + uint32_t *pui32Signature = (uint32_t *)AM_HAL_FLASH_INFO_ADDR; + + return ( (pui32Signature[3] == AM_HAL_FLASH_INFO_SIGNATURE3) && + (pui32Signature[2] == AM_HAL_FLASH_INFO_SIGNATURE2) && + (pui32Signature[1] == AM_HAL_FLASH_INFO_SIGNATURE1) && + (pui32Signature[0] == AM_HAL_FLASH_INFO_SIGNATURE0) ); +} + +//***************************************************************************** +// +//! @brief INFO signature set. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +bool +am_hal_flash_info_signature_set(void) +{ + // + // Check and set signature. + // + return customer_info_signature_set() ? false : true; +} + +//***************************************************************************** +// +//! @brief Disable FLASH INFO space. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then disable FLASH erasure. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +int32_t +am_hal_flash_info_erase_disable(void) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(); + if ( iRC ) + { + return iRC; + } + + // + // Clear bit in INFO space to disable erasure. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words +} + +//***************************************************************************** +// +//! @brief Check for Disabled FLASH INFO space. +//! +//! Use this function to determine whether FLASH INFO erasure is disabled. +//! +//! @return true if FLASH INFO erase is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_info_erase_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not valid at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SRAM WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M ? false : true; +} + +//***************************************************************************** +// +//! @brief Mask off 1 to 4 quadrants of FLASH INFO space for programming. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then and the mask bits with the INFO +//! space programming disable bits. +//! +//! @param ui32Mask - A mask of the 4 quadrants of info space where +//! bit0 = First quadrant (first 2KB). +//! bit1 = Second quadrant (second 2KB). +//! bit2 = Third quadrant (third 2KB). +//! bit3 = Fourth quadrant (fourth 2KB). +//! +//! @note This function disables only, any quadrant already disabled is not +//! reenabled. That is, any ui32Mask bits specified as 0 are essentially nops. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +int32_t +am_hal_flash_info_program_disable(uint32_t ui32Mask) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(); + if ( iRC ) + { + return iRC; + } + + // + // Make sure we have a valid mask and get the mask into the correct position. + // + ui32Mask <<= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S; + ui32Mask &= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M; + + // + // The security bit set to 1 enables programming, 0 disables programming. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & ~ui32Mask; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words +} + +//***************************************************************************** +// +//! @brief Return a mask specifying which quadrants of customer INFO space have +//! been disabled for programming. +//! +//! Use this function to determine whether programming of customer INFO space +//! has been disabled. +//! +//! @return A 4-bit mask of the disabled quadrants. +//! 0xFFFFFFFF indicates an error. +//! 0x0 indicates all customer INFO space programming is enabled. +//! 0xF indicates all customer INFO space programming is disabled. +//! bit0 indicates the first customer INFO space is disabled for programming. +//! bit1 indicates the second customer INFO space is disabled for programming. +//! bit2 indicates the third customer INFO space is disabled for programming. +//! bit3 indicates the fourth customer INFO space is disabled for programming. +// +//***************************************************************************** +uint32_t +am_hal_flash_info_program_disable_get(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return 0xFFFFFFFF; + } + + // + // If not valid at this point, then INFO programming can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return 0xFFFFFFFF; + } + + // + // Looking good so far, now return a mask of the disabled bits. + // + return ((AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) ^ + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) >> + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S; +} + +//***************************************************************************** +// +//! @brief Enable FLASH debugger protection (FLASH gets wiped if a debugger is +//! connected). +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then set the FLASH wipe bit to zero. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +int32_t +am_hal_flash_wipe_flash_enable(void) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(); + if ( iRC ) + { + return iRC; + } + + // + // Clear the FLASH Wipe bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words +} + +//***************************************************************************** +// +//! @brief check for FLASH wipe protection enabled. +//! +//! Use this function to determine if FLASH wipe protection is enabled. +//! +//! @return true if FLASH wipe protection is enabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_wipe_flash_enable_check(void) +{ + // + // If they are erased at this point then flash wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not valid at this point then flash wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the Flash WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ? false : true; +} + +//***************************************************************************** +// +//! @brief Enable SRAM protection so SRAM gets wiped if a debgger is connected. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then set the SRAM wipe bit to zero. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +int32_t +am_hal_flash_wipe_sram_enable(void) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(); + if ( iRC ) + { + return iRC; + } + + // + // Clear the SRAM Wipe bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words +} + +//***************************************************************************** +// +//! @brief check for SRAM protection enabled. +//! +//! Use this function to determine if SRAM protection is enabled. +//! +//! @return true if SRAM wipe protection is enabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_wipe_sram_enable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SRAM WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ? false : true; +} + +//***************************************************************************** +// +//! @brief Disable Output from ITM/SWO. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Set the SWO disable bit to zero. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +int32_t +am_hal_flash_swo_disable(void) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(); + if ( iRC ) + { + return iRC; + } + + // + // Clear the SWO bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words +} + +//***************************************************************************** +// +//! @brief check for SWO disabled. +//! +//! Use this function to determine if the SWO is disabled. +//! +//! @return true if the ITM/SWO is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_swo_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SWO bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ? false : true; +} + +//***************************************************************************** +// +//! @brief Disable Connections from a debugger on the SWD interface. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Set the debugger disable bit to zero, +//! disabling the debugger after the next POI-level reset. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +// +//***************************************************************************** +int32_t +am_hal_flash_debugger_disable(void) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(); + if ( iRC ) + { + return iRC; + } + + // + // Clear the DEBUGGER bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words +} + +//***************************************************************************** +// +//! @brief check for debugger disabled. +//! +//! Use this function to determine if the debugger is disabled. +//! +//! @return true if the debugger is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_debugger_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the debugger disable bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ? false : true; +} + +//***************************************************************************** +// +//! @brief This static helper function generates a 64-bit protection mask. +//! +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function computes a chunk map for the protection range. +//! +//! @return Inverse of the actual chunk mask. That is, chunks to be protected +//! are represented as 0 in the returned mask, while chunks to be left alone +//! are represented as 1. This value can therefore be directly ANDed with the +//! existing bits in INFO space. +//! Note that -1 is returned if input parameters are invalid - this return +//! value would indicate that no chunks are to be protected. +//! +// +//***************************************************************************** +static uint64_t +generate_chunk_mask(uint32_t *pui32StartAddress, uint32_t *pui32StopAddress) +{ + uint32_t ui32ChunkStart, ui32ChunkStop; + uint32_t ui32Width; + uint64_t ui64Mask; + + // + // Validate the address input parameters + // + if ( (pui32StartAddress > pui32StopAddress) || + (pui32StopAddress > (uint32_t*)AM_HAL_FLASH_LARGEST_VALID_ADDR) ) + { + // + // Argument error, return value to leave all chunks unprotected. + // + return 0xFFFFFFFFFFFFFFFF; + } + + // + // Extract chunk related information + // + ui32ChunkStart = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StartAddress); + ui32ChunkStop = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StopAddress); + ui32Width = ui32ChunkStop - ui32ChunkStart + 1; + + if ( ui32Width == 64 ) + { + ui64Mask = (uint64_t)0xFFFFFFFFFFFFFFFFLLU; + } + else + { + ui64Mask = ( ((uint64_t)0x0000000000000001) << ui32Width) - 1; + ui64Mask <<= ui32ChunkStart; + } + + // + // OK now return the chunk mask (inverted). + // + return ~ui64Mask; +} + +//***************************************************************************** +// +//! @brief This function sets copy protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function will set copy protection bits for a range of flash chunks +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return +//! 0 for success. +//! 0x400000 if the protection bits were already programmed (mask the return +//! value with 0x3FFFFF to ignore this case and treat as success). +//! Otherwise, non-zero for failure. +// +//***************************************************************************** +int32_t +am_hal_flash_copy_protect_set(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + int iRC; + bool bModified = false; + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t ui32Protection[2]; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return 0x100000; + } + + // + // Go get the current settings for copy protection. + // + ui32Protection[0] = pui32Protection[0]; + ui32Protection[1] = pui32Protection[1]; + + // + // AND mask off the necessary protection bits in the lower word. + // + ui32Work = (uint32_t)ui64Mask; + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[0] ) ) + { + bModified = true; + ui32Protection[0] &= ui32Work; + iRC = g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32Protection[0], // source data + (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 0, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x10000; + } + } + + // + // AND mask off the necessary protection bits in the upper word. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[1] ) ) + { + bModified = true; + ui32Protection[1] &= ui32Work; + iRC = g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32Protection[1], // source data + (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 1, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x20000; + } + } + + if ( bModified ) + { + return 0; + } + else + { + return 0x400000; + } +} + +//***************************************************************************** +// +//! @brief This function checks copy protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash. +//! @param pui32StopAddress - Ending address in flash. +//! +//! This function will check copy protection bits for a range of flash chunks +//! it expects all chunks in the range to be protected. +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @return false for at least one chunk in the covered range is not protected, +//! and true if all chunks in the covered range are protected. +//! +// +//***************************************************************************** +bool +am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)ui64Mask; + if ( ~ui32Work & pui32Protection[0] ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ~ui32Work & pui32Protection[1] ) + { + return false; + } + + // + // If we get here, there are no unprotected chunks within specified range. + // + return true; +} + +//***************************************************************************** +// +//! @brief This function sets write protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function will set write protection bits for a range of flash chunks +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @note The various customer INFO-enabled protections generally require a +//! POI level reset, such as am_hal_reset_poi() or a power-cycle, in order to +//! activate. Deactivating the protection is more difficult, see the +//! description in am_hal_flash_recovery() for more information. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return +//! 0 for success. +//! 0x400000 if the protection bits were already programmed (mask the return +//! value with 0x3FFFFF to ignore this case and treat as success). +//! Otherwise, non-zero for failure. +// +//***************************************************************************** +int32_t +am_hal_flash_write_protect_set(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + int iRC; + bool bModified = false; + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t ui32Protection[2]; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return 0x100000; + } + + // + // Go get the current settings for copy protection. + // + ui32Protection[0] = pui32Protection[0]; + ui32Protection[1] = pui32Protection[1]; + + // + // AND mask off the necessary protection bits in the lower word. + // + ui32Work = (uint32_t)ui64Mask; + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[0] ) ) + { + bModified = true; + ui32Protection[0] &= ui32Work; + iRC = g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32Protection[0], // source data + (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 0, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x10000; + } + } + + // + // AND mask off the necessary protection bits in the upper word. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[1] ) ) + { + bModified = true; + ui32Protection[1] &= ui32Work; + iRC = g_am_hal_flash.flash_program_info( + AM_HAL_FLASH_PROGRAM_KEY, + 0, // instance + &ui32Protection[1], // source data + (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 1, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x20000; + } + } + + if ( bModified ) + { + return 0; + } + else + { + return 0x400000; + } +} + +//***************************************************************************** +// +//! @brief This function checks write protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash. +//! @param pui32StopAddress - Ending address in flash. +//! +//! This function will check write protection bits for a range of flash chunks +//! it expects all chunks in the range to be protected. +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @return false for at least one chunk in the covered range is not protected, +//! and true if all chunks in the covered range are protected. +//! +// +//***************************************************************************** +bool +am_hal_flash_write_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)ui64Mask; + if ( ~ui32Work & pui32Protection[0] ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ~ui32Work & pui32Protection[1] ) + { + return false; + } + + // + // If we get here, there are no unprotected chunks within specified range. + // + return true; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_flash.h b/mcu/apollo2/hal/am_hal_flash.h new file mode 100644 index 0000000..71313db --- /dev/null +++ b/mcu/apollo2/hal/am_hal_flash.h @@ -0,0 +1,312 @@ +//***************************************************************************** +// +// am_hal_flash.h +//! @file +//! +//! @brief Functions for performing Flash operations. +//! +//! @addtogroup flash2 Flash +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_FLASH_H +#define AM_HAL_FLASH_H + +#include +#include + +//***************************************************************************** +// +// Flash Program keys. +// +//***************************************************************************** +#define AM_HAL_FLASH_PROGRAM_KEY 0x12344321 +#define AM_HAL_FLASH_RECOVERY_KEY 0xA35C9B6D +#define AM_HAL_FLASH_INFO_KEY 0x12344321 +#define AM_HAL_FLASH_OTP_KEY (AM_HAL_FLASH_INFO_KEY) + +//***************************************************************************** +// +// Some helpful flash values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_ADDR 0x00000000 +#define AM_HAL_FLASH_PAGE_SIZE ( 8 * 1024 ) +#define AM_HAL_FLASH_INFO_SIZE AM_HAL_FLASH_PAGE_SIZE +#define AM_HAL_FLASH_INSTANCE_SIZE ( 512 * 1024 ) +#define AM_HAL_FLASH_INSTANCE_PAGES ( AM_HAL_FLASH_INSTANCE_SIZE / AM_HAL_FLASH_PAGE_SIZE ) +#define AM_HAL_FLASH_TOTAL_SIZE ( AM_HAL_FLASH_INSTANCE_SIZE * 2 ) +#define AM_HAL_FLASH_LARGEST_VALID_ADDR ( AM_HAL_FLASH_ADDR + AM_HAL_FLASH_TOTAL_SIZE - 1 ) + +// +// Macros to describe the flash ROW layout. +// +#define AM_HAL_FLASH_ROW_WIDTH_BYTES (512) + +// +// Convert an absolute flash address to a instance +// +#define AM_HAL_FLASH_ADDR2INST(addr) ( ( addr >> 19 ) & 1 ) + +// +// Convert an absolute flash address to a page number relative to the instance +// +#define AM_HAL_FLASH_ADDR2PAGE(addr) ( ( addr >> 13 ) & 0x3F ) + +// +// Convert an absolute flash address to an absolute page number +// +#define AM_HAL_FLASH_ADDR2ABSPAGE(addr) ( addr >> 13 ) + +//***************************************************************************** +// +// Given an integer number of microseconds, convert to a value representing the +// number of am_hal_flash_delay() cycles that will provide that amount of delay. +// This macro is designed to take into account some of the call overhead. +// +// e.g. To provide a 2us delay: +// am_hal_flash_delay( FLASH_CYCLES_US(2) ); +// +// IMPORTANT - Apollo2 is spec'ed for only 48MHz operation, so this macro +// assumes that. +// +//***************************************************************************** +#define FLASH_CYCLES_US(n) ((n * (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3)) - 4) + +// +// Backward compatibility +// +#define am_hal_flash_program_otp am_hal_flash_program_info +#define am_hal_flash_program_otp_sram am_hal_flash_program_info_sram + +//***************************************************************************** +// +// Structure of function pointers to helper functions for invoking various +// flash operations. The functions we are pointing to here are in the Apollo 2 +// integrated BOOTROM. +// +//***************************************************************************** +typedef struct am_hal_flash_helper_struct +{ + // + // The basics. + // + int (*flash_mass_erase)(uint32_t, uint32_t); + int (*flash_page_erase)(uint32_t, uint32_t, uint32_t); + int (*flash_program_main)(uint32_t, uint32_t *, + uint32_t*, uint32_t); + int (*flash_program_info)(uint32_t, uint32_t, + uint32_t*, uint32_t, uint32_t); + + // + // Non-blocking variants, but be careful these are not interrupt safe so + // mask interrupts while these very long operations proceed. + // + int (*flash_mass_erase_nb)(uint32_t, uint32_t); + int (*flash_page_erase_nb)(uint32_t, uint32_t, uint32_t); + bool (*flash_nb_operation_complete)(void); + + // + // Essentially these are recovery options. + // + int (*flash_erase_info)(uint32_t, uint32_t); + int (*flash_erase_main_plus_info)(uint32_t, uint32_t); + int (*flash_erase_main_plus_info_both_instances)(uint32_t); + void (*flash_recovery)(uint32_t); + + // + // Useful utilities. + // + uint32_t (*flash_util_read_word)(uint32_t*); + void (*flash_util_write_word)(uint32_t*, uint32_t); + void (*delay_cycles)(uint32_t); + + // + // The following functions pointers will generally never be called from + // user programs. They are here primarily to document these entry points + // which are usable from a debugger or debugger script. + // + void (*flash_program_main_sram)(void); + void (*flash_program_info_sram)(void); + void (*flash_erase_main_pages_sram)(void); + void (*flash_mass_erase_sram)(void); + void (*flash_erase_info_sram)(void); + void (*flash_erase_main_plus_info_sram)(void); +} g_am_hal_flash_t; +extern const g_am_hal_flash_t g_am_hal_flash; + + +//***************************************************************************** +// +// Define some FLASH INFO SPACE values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_INFO_ADDR 0x50020000 +#define AM_HAL_FLASH_INFO_SECURITY_O 0x10 +#define AM_HAL_FLASH_INFO_WRITPROT_O 0x20 +#define AM_HAL_FLASH_INFO_COPYPROT_O 0x30 + +#define AM_HAL_FLASH_INFO_SECURITY_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_SECURITY_O) +#define AM_HAL_FLASH_INFO_WRITPROT_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_WRITPROT_O) +#define AM_HAL_FLASH_INFO_COPYPROT_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_COPYPROT_O) + +// +// Define the customer info signature data (at AM_HAL_FLASH_INFO_ADDR). +// These bits must exist in the customer info space in order for many of the +// security and protection functions to work. +// +#define AM_HAL_FLASH_INFO_SIGNATURE0 0x48EAAD88 +#define AM_HAL_FLASH_INFO_SIGNATURE1 0xC9705737 +#define AM_HAL_FLASH_INFO_SIGNATURE2 0x0A6B8458 +#define AM_HAL_FLASH_INFO_SIGNATURE3 0xE41A9D74 + +// +// Define the customer security bits (at AM_HAL_FLASH_INFO_SECURITY_ADDR) +// +#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S 0 +#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S 1 +#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S 2 +#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S 3 +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S 4 +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S 8 +#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S 9 + +#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S)) +#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S)) +#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M ((uint32_t)(0xF << AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S)) +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) +#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) +#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP ((uint32_t)(0x0 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) + +// +// Protection chunk macros +// AM_HAL_FLASH_INFO_CHUNK2ADDR: Convert a chunk number to an address +// AM_HAL_FLASH_INFO_CHUNK2INST: Convert a chunk number to an instance number +// AM_HAL_FLASH_INFO_ADDR2CHUNK: Convert an address to a chunk number +// +#define AM_HAL_FLASH_INFO_CHUNKSIZE (16*1024) + +#define AM_HAL_FLASH_INFO_CHUNK2ADDR(n) (AM_HAL_FLASH_ADDR + (n << 14)) +#define AM_HAL_FLASH_INFO_CHUNK2INST(n) ((n >> 5) & 1 +#define AM_HAL_FLASH_INFO_ADDR2CHUNK(n) ((n) >> 14) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Function prototypes for the helper functions +// +//***************************************************************************** +extern int am_hal_flash_mass_erase(uint32_t ui32Value, uint32_t ui32FlashInst); +extern int am_hal_flash_page_erase(uint32_t ui32Value, uint32_t ui32FlashInst, + uint32_t ui32PageNum); +extern int am_hal_flash_program_main(uint32_t value, uint32_t *pSrc, + uint32_t *pDst, uint32_t NumberOfWords); +extern int am_hal_flash_program_info(uint32_t ui32Value, uint32_t ui32InfoInst, + uint32_t *pui32Src, uint32_t ui32Offset, + uint32_t ui32NumWords); + +// +// Recovery type functions for Customer INFO space. +// +extern int am_hal_flash_erase_info(uint32_t ui32ProgramKey, + uint32_t ui32Instance); +extern int am_hal_flash_erase_main_plus_info(uint32_t ui32ProgramKey, + uint32_t ui32Instance); +extern int am_hal_flash_erase_main_plus_info_both_instances( + uint32_t ui32ProgramKey); +extern void am_hal_flash_recovery(uint32_t ui32RecoveryKey); + +// +// BOOTROM resident reader, writer and delay utility functions. +// +extern uint32_t am_hal_flash_load_ui32(uint32_t ui32Address); +extern void am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data); +extern void am_hal_flash_delay(uint32_t ui32Iterations); +extern uint32_t am_hal_flash_delay_status_change(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value); + +// +// These functions update security/protection bits in the customer INFO blOCK. +// +extern bool am_hal_flash_customer_info_signature_check(void); +extern bool am_hal_flash_info_signature_set(void); +extern int32_t am_hal_flash_info_erase_disable(void); +extern bool am_hal_flash_info_erase_disable_check(void); +extern int32_t am_hal_flash_info_program_disable(uint32_t ui32Mask); +extern uint32_t am_hal_flash_info_program_disable_get(void); +extern int32_t am_hal_flash_wipe_flash_enable(void); +extern bool am_hal_flash_wipe_flash_enable_check(void); +extern int32_t am_hal_flash_wipe_sram_enable(void); +extern bool am_hal_flash_wipe_sram_enable_check(void); +extern int32_t am_hal_flash_swo_disable(void); +extern bool am_hal_flash_swo_disable_check(void); +extern int32_t am_hal_flash_debugger_disable(void); +extern bool am_hal_flash_debugger_disable_check(void); + +extern int32_t am_hal_flash_copy_protect_set(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern bool am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern int32_t am_hal_flash_write_protect_set(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern bool am_hal_flash_write_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_FLASH_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_global.c b/mcu/apollo2/hal/am_hal_global.c new file mode 100644 index 0000000..6ffe835 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_global.c @@ -0,0 +1,149 @@ +//***************************************************************************** +// +// am_hal_global.c +//! @file +//! +//! @brief Locate global variables here. +//! +//! This module contains global variables that are used throughout the HAL. +//! +//! One use in particular is that it uses a global HAL flags variable that +//! contains flags used in various parts of the HAL. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +uint32_t volatile g_ui32HALflags = 0x00000000; + +//***************************************************************************** +// +// Static function for reading the timer value. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + push {r1, r4} // Save r1=ui32Data, r4 + mrs r4, PRIMASK // Save current interrupt state + cpsid i // Disable INTs while reading the reg + ldr r1, [r0, #0] // Read the designated register 3 times + ldr r2, [r0, #0] // " + ldr r3, [r0, #0] // " + msr PRIMASK, r4 // Restore interrupt state + pop {r0, r4} // Get r0=ui32Data, restore r4 + str r1, [r0, #0] // Store 1st read value to array + str r2, [r0, #4] // Store 2nd read value to array + str r3, [r0, #8] // Store 3rd read value to array + bx lr // Return to caller +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm ( + " push {R1, R4}\n" + " mrs R4, PRIMASK\n" + " cpsid i\n" + " nop\n" + " ldr R1, [R0, #0]\n" + " ldr R2, [R0, #0]\n" + " ldr R3, [R0, #0]\n" + " msr PRIMASK, r4\n" + " pop {R0, R4}\n" + " str R1, [R0, #0]\n" + " str R2, [R0, #4]\n" + " str R3, [R0, #8]\n" + : + : [u32TimerAddr] "r" (u32TimerAddr), + [u32Data] "r" (&u32Data[0]) + : "r0", "r1", "r2", "r3", "r4" + ); +} +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm + ( + " push {r1, r4}\n" // Save r1=ui32Data, r4 + " mrs r4, PRIMASK \n" // Save current interrupt state + " cpsid i \n" // Disable INTs while reading the reg + " ldr r1, [r0, #0]\n" // Read the designated register 3 times + " ldr r2, [r0, #0]\n" // " + " ldr r3, [r0, #0]\n" // " + " msr PRIMASK, r4 \n" // Restore interrupt state + " pop {r0, r4}\n" // Get r0=ui32Data, restore r4 + " str r1, [r0, #0]\n" // Store 1st read value to array + " str r2, [r0, #4]\n" // Store 2nd read value to array + " str r3, [r0, #8]\n" // Store 3rd read value to array + " bx lr \n" // Return to caller + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm(" push {r1, r4} "); // Save r1=ui32Data, r4 + __asm(" mrs r4, PRIMASK "); // Save current interrupt state + __asm(" cpsid i "); // Disable INTs while reading the reg + __asm(" ldr r1, [r0, #0]"); // Read the designated register 3 times + __asm(" ldr r2, [r0, #0]"); // " + __asm(" ldr r3, [r0, #0]"); // " + __asm(" msr PRIMASK, r4 "); // Restore interrupt state + __asm(" pop {r0, r4} "); // Get r0=ui32Data, restore r4 + __asm(" str r1, [r0, #0]"); // Store 1st read value to array + __asm(" str r2, [r0, #4]"); // Store 2nd read value to array + __asm(" str r3, [r0, #8]"); // Store 3rd read value to array + __asm(" bx lr "); // Return to caller +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif diff --git a/mcu/apollo2/hal/am_hal_global.h b/mcu/apollo2/hal/am_hal_global.h new file mode 100644 index 0000000..1ad39ff --- /dev/null +++ b/mcu/apollo2/hal/am_hal_global.h @@ -0,0 +1,138 @@ +//***************************************************************************** +// +// am_hal_global.h +//! @file +//! +//! @brief Locate all HAL global variables here. +//! +//! This module contains global variables that are used throughout the HAL, +//! but not necessarily those designated as const (which typically end up in +//! flash). Consolidating globals here will make it easier to manage them. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_GLOBAL_H +#define AM_HAL_GLOBAL_H + +//***************************************************************************** +// +// Device definitions +// +//***************************************************************************** +#define AM_HAL_DEVICE_NAME "Apollo2" + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +//****************************************************************************** +// +// Macros used to access the bit fields in the flags variable. +// +//****************************************************************************** +#define AM_HAL_FLAGS_BFR(flagnm) \ + ((g_ui32HALflags & AM_HAL_FLAGS_##flagnm##_M) >> AM_HAL_FLAGS_##flagnm##_S) + +#define AM_HAL_FLAGS_BFW(flagnm, value) \ + g_ui32HALflags = ((g_ui32HALflags & (~(AM_HAL_FLAGS_##flagnm##_M))) | \ + ((value << AM_HAL_FLAGS_##flagnm##_S) & (AM_HAL_FLAGS_##flagnm##_M)) ) + +//****************************************************************************** +// +// ITMSKIPENABLEDISABLE - Set when the ITM is not to be disabled. This is +// typically needed by Keil debug.ini. +// +//****************************************************************************** +#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S 0 +#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M (1 << AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S) +#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE(n) (((n) << AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S) & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M) + +//****************************************************************************** +// +// ITMBKPT - Breakpoint at the end of itm_enable(), which is needed by +// Keil debug.ini. +// +//****************************************************************************** +#define AM_HAL_FLAGS_ITMBKPT_S 1 +#define AM_HAL_FLAGS_ITMBKPT_M (1 << AM_HAL_FLAGS_ITMBKPT_S) +#define AM_HAL_FLAGS_ITMBKPT(n) (((n) << AM_HAL_FLAGS_ITMBKPT_S) & AM_HAL_FLAGS_ITMBKPT_M) + +//****************************************************************************** +// +// Next available flag or bit field. +// +//****************************************************************************** +#define AM_HAL_FLAGS_NEXTBITFIELD_S 2 +#define AM_HAL_FLAGS_NEXTBITFIELD_M (1 << AM_HAL_FLAGS_NEXTBITFIELD_S) +#define AM_HAL_FLAGS_NEXTBITFIELD(n) (((n) << AM_HAL_FLAGS_NEXTBITFIELD_S) & AM_HAL_FLAGS_NEXTBITFIELD_M) + +//***************************************************************************** +// +// Global Variables extern declarations. +// +//***************************************************************************** +extern volatile uint32_t g_ui32HALflags; + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __cplusplus +} +#endif + +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]); +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]); +#elif defined(__IAR_SYSTEMS_ICC__) +__stackless void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +#endif // AM_HAL_GLOBAL_H diff --git a/mcu/apollo2/hal/am_hal_gpio.c b/mcu/apollo2/hal/am_hal_gpio.c new file mode 100644 index 0000000..b80495a --- /dev/null +++ b/mcu/apollo2/hal/am_hal_gpio.c @@ -0,0 +1,507 @@ +//***************************************************************************** +// +// am_hal_gpio.c +//! @file +//! +//! @brief Functions for interfacing with the GPIO module +//! +//! @addtogroup gpio2 GPIO +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Array of function pointers for handling GPIO interrupts. +// +//***************************************************************************** +am_hal_gpio_handler_t am_hal_gpio_ppfnHandlers[64]; + +//***************************************************************************** +// +//! @brief Read the configuration information for the given pin.. +//! +//! @param ui32GPIONum is the GPIO number whose configuration we want to read. +//! +//! This function reads the PADREG, GPIO CFG, and ALTPAD registers for the +//! given GPIO and returns them in the following format: +//! +//! ( (ALTPAD << 16) | (CFG << 8) | PADREG) +//! +//! This is the same format used by the \e am_hal_gpio_pin_config() +//! function-like macro. +//! +//! @return Pin configuration information. +// +//***************************************************************************** +uint32_t +am_hal_gpio_pin_config_read(uint32_t ui32PinNumber) +{ + uint32_t ui32CfgVal, ui32PadregVal, ui32AltPadVal; + + am_hal_debug_assert_msg(ui32PinNumber <= 63, "Invalid GPIO number."); + + ui32CfgVal = AM_HAL_GPIO_CFG_R(ui32PinNumber); + ui32PadregVal = AM_HAL_GPIO_PADREG_R(ui32PinNumber); + ui32AltPadVal = AM_HAL_GPIO_ALTPADREG_R(ui32PinNumber); + + return ( (ui32CfgVal << CFGVAL_GPIOCFG_S) | + (ui32PadregVal << CFGVAL_PADREG_S) | + (ui32AltPadVal << CFGVAL_ALTPAD_S) ); +} + +//***************************************************************************** +// +//! @brief Get the state of ALL GPIOs from the INPUT READ REGISTER. +//! +//! This function retrieves the state of ALL GPIOs from the INPUT READ +//! REGISTER. +//! +//! @return the state for the requested GPIO or -1 for error. +// +//***************************************************************************** +uint64_t +am_hal_gpio_input_read(void) +{ + // + // Combine upper or lower GPIO words into one 64 bit return value. + // + uint64_t ui64RetVal; + + ui64RetVal = ((uint64_t) AM_REGn(GPIO, 0, RDB)) << 32; + ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, RDA)) << 0; + + return ui64RetVal; +} + +//***************************************************************************** +// +//! @brief Get the state of ALL GPIOs from the DATA OUTPUT REGISTER. +//! +//! This function retrieves the state of ALL GPIOs from the DATA OUTPUT +//! REGISTER. +//! +//! @return the state for the requested GPIO or -1 for error. +// +//***************************************************************************** +uint64_t +am_hal_gpio_out_read(void) +{ + // + // Combine upper or lower GPIO words into one 64 bit return value. + // + uint64_t ui64RetVal; + + ui64RetVal = ((uint64_t) AM_REGn(GPIO, 0, WTB)) << 32; + ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, WTA)) << 0; + + return ui64RetVal; +} + +//***************************************************************************** +// +//! @brief Gets the state of one GPIO from the DATA ENABLE REGISTER. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function gets the state of one GPIO from the DATA ENABLE REGISTER. +//! +//! @return the current state for the requested GPIO. +// +//***************************************************************************** +uint32_t +am_hal_gpio_out_enable_bit_get(uint32_t ui32BitNum) +{ + // + // Return 0 or 1. + // + + return (AM_HAL_GPIO_EN(ui32BitNum) & AM_HAL_GPIO_EN_M(ui32BitNum)) ? 1 : 0; +} + +//***************************************************************************** +// +//! @brief Gets the state of ALL GPIOs from the DATA ENABLE REGISTER. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function gets the state of all GPIOs from the DATA ENABLE REGISTER. +//! +//! @return the current state for the ALL GPIOs. +// +//***************************************************************************** +uint64_t +am_hal_gpio_out_enable_get(void) +{ + // + // Combine upper or lower GPIO words into one 64 bit return value. + // + uint64_t ui64RetVal; + + ui64RetVal = ((uint64_t) AM_REGn(GPIO, 0, ENB)) << 32; + ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, ENA)) << 0; + + return ui64RetVal; +} + +//***************************************************************************** +// +//! @brief Enable selected GPIO Interrupts. +//! +//! @param ui64InterruptMask - GPIOs to enable interrupts on. +//! +//! Use this function to enable the GPIO interrupts. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_gpio_int_enable(uint64_t ui64InterruptMask) +{ + // + // Enable the interrupts. + // + AM_REG(GPIO, INT1EN) |= (ui64InterruptMask >> 32); + AM_REG(GPIO, INT0EN) |= (ui64InterruptMask & 0xFFFFFFFF); +} + +//***************************************************************************** +// +//! @brief Enable selected GPIO Interrupts. +//! +//! Use this function to enable the GPIO interrupts. +//! +//! @return logical or of all enabled interrupts. Use AM_HAL_GPIO_BITx to mask +//! interrupts of interest. +// +//***************************************************************************** +uint64_t +am_hal_gpio_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + uint64_t ui64RetVal; + + ui64RetVal = ((uint64_t) AM_REGn(GPIO, 0, INT1EN)) << 32; + ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, INT0EN)) << 0; + + return ui64RetVal; +} + +//***************************************************************************** +// +//! @brief Disable selected GPIO Interrupts. +//! +//! @param ui64InterruptMask - GPIOs to disable interrupts on. +//! +//! Use this function to disable the GPIO interrupts. +//! +//! ui64InterruptMask should be a logical or of AM_HAL_GPIO_BITx defines. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_gpio_int_disable(uint64_t ui64InterruptMask) +{ + // + // Disable the interrupts. + // + AM_CRITICAL_BEGIN + AM_REG(GPIO, INT1EN) &= ~(ui64InterruptMask >> 32); + AM_REG(GPIO, INT0EN) &= ~(ui64InterruptMask & 0xFFFFFFFF); + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Clear selected GPIO Interrupts. +//! +//! @param ui64InterruptMask - GPIOs to clear interrupts on. +//! +//! Use this function to clear the GPIO interrupts. +//! +//! ui64InterruptMask should be a logical or of AM_HAL_GPIO_BITx defines. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_gpio_int_clear(uint64_t ui64InterruptMask) +{ + // + // Clear the interrupts. + // + AM_CRITICAL_BEGIN + AM_REG(GPIO, INT1CLR) = (ui64InterruptMask >> 32); + AM_REG(GPIO, INT0CLR) = (ui64InterruptMask & 0xFFFFFFFF); + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Set selected GPIO Interrupts. +//! +//! @param ui64InterruptMask - GPIOs to set interrupts on. +//! +//! Use this function to set the GPIO interrupts. +//! +//! ui64InterruptMask should be a logical or of AM_HAL_GPIO_BITx defines. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_gpio_int_set(uint64_t ui64InterruptMask) +{ + // + // Set the interrupts. + // + AM_REG(GPIO, INT1SET) = (ui64InterruptMask >> 32); + AM_REG(GPIO, INT0SET) = (ui64InterruptMask & 0xFFFFFFFF); +} + +//***************************************************************************** +// +//! @brief Set selected GPIO Interrupts. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! Use this function to set the GPIO interrupts. +//! +//! @return None +// +//***************************************************************************** +uint64_t +am_hal_gpio_int_status_get(bool bEnabledOnly) +{ + uint64_t ui64RetVal, ui64Mask; + + // + // Combine upper or lower GPIO words into one 64 bit return value. + // + ui64Mask = 0xFFFFFFFFFFFFFFFF; + + AM_CRITICAL_BEGIN + ui64RetVal = ((uint64_t) AM_REGn(GPIO, 0, INT1STAT)) << 32; + ui64RetVal |= ((uint64_t) AM_REGn(GPIO, 0, INT0STAT)) << 0; + + if ( bEnabledOnly ) + { + ui64Mask = ((uint64_t) AM_REGn(GPIO, 0, INT1EN)) << 32; + ui64Mask |= ((uint64_t) AM_REGn(GPIO, 0, INT0EN)) << 0; + } + + ui64RetVal &= ui64Mask; + AM_CRITICAL_END + + return ui64RetVal; +} + +//***************************************************************************** +// +//! @brief Convenience function for responding to pin interrupts. +//! +//! @param ui64Status is the interrupt status as returned by +//! am_hal_gpio_int_status_get() +//! +//! This function may be called from am_hal_gpio_isr() to read the status of +//! the GPIO interrupts, determine which pin(s) caused the most recent +//! interrupt, and call an interrupt handler function to respond. The interrupt +//! handler to be called must be first registered with the +//! am_hal_gpio_int_register() function. +//! +//! In the event that multiple GPIO interrupts are active, the corresponding +//! interrupt handlers will be called in numerical order by GPIO number +//! starting with the lowest GPIO number. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_gpio_int_service(uint64_t ui64Status) +{ + uint32_t ui32Status; + uint32_t ui32Clz; + + am_hal_gpio_handler_t pfnHandler; + + // + // Handle any active interrupts in the lower 32 bits + // + ui32Status = (uint32_t) ui64Status; + while ( ui32Status ) + { + // + // Pick one of any remaining active interrupt bits + // +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32Status); +#else + ui32Clz = __builtin_clz(ui32Status); +#endif + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x80000000 >> ui32Clz); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = am_hal_gpio_ppfnHandlers[31 - ui32Clz]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + pfnHandler(); + } + } + + // + // Handle any active interrupts in the upper 32 bits + // + ui32Status = (uint32_t) (ui64Status >> 32); + while ( ui32Status ) + { + // + // Pick one of any remaining active interrupt bits + // +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32Status); +#else + ui32Clz = __builtin_clz(ui32Status); +#endif + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x80000000 >> ui32Clz); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = am_hal_gpio_ppfnHandlers[63 - ui32Clz]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + pfnHandler(); + } + } +} + +//***************************************************************************** +// +//! @brief Register an interrupt handler for an individual GPIO pin. +//! +//! @param ui32GPIONumber - GPIO number to assign this interrupt handler to. +//! @param pfnHandler - Function to call when this GPIO interrupt is received. +//! +//! This function allows the caller to specify a function that should be called +//! any time a GPIO interrupt is received on a particular pin. Registering an +//! interrupt handler using this function adds the function pointer to an array +//! in SRAM. This interrupt handler will be called by am_hal_gpio_int_service() +//! whenever the ui64Status parameter indicates that the corresponding pin is +//! asserting it's interrupt. +//! +//! To remove an interrupt handler that has already been registered, the +//! pfnHandler parameter may be set to zero. +//! +//! @note This function will not have any effect unless the +//! am_hal_gpio_int_service() function is being used. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_gpio_int_register(uint32_t ui32GPIONumber, + am_hal_gpio_handler_t pfnHandler) +{ + // + // Check to make sure the GPIO number is valid. (Debug builds only) + // + am_hal_debug_assert_msg(ui32GPIONumber < 64, "GPIO number out of range."); + + am_hal_gpio_ppfnHandlers[ui32GPIONumber] = pfnHandler; +} + +//***************************************************************************** +// +//! @brief Get the state of one GPIO polarity bit. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function gets the state of one GPIO polarity bit. +//! +//! @note When the bit is zero the interrupt polarity is rising edge. +//! When the bit is one the interrupt polarity is falling edge. +//! +//! @return the current polarity. +// +//***************************************************************************** +bool +am_hal_gpio_int_polarity_bit_get(uint32_t ui32BitNum) +{ + // + // Check the GPIO_CFGx register's interrupt polarity bit corresponding to + // this pin number. + // + return (AM_REGVAL(AM_HAL_GPIO_CFG(ui32BitNum)) & + AM_HAL_GPIO_POL_M(ui32BitNum)); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_gpio.h b/mcu/apollo2/hal/am_hal_gpio.h new file mode 100644 index 0000000..495a472 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_gpio.h @@ -0,0 +1,715 @@ +//***************************************************************************** +// +// am_hal_gpio.h +//! @file +//! +//! @brief Functions for accessing and configuring the GPIO module. +//! +//! @addtogroup gpio2 GPIO +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_HAL_GPIO_H +#define AM_HAL_GPIO_H + +// DEVICE ADDRESS IS 8-bits +#define AM_HAL_GPIO_DEV_ADDR_8 (0) + +// DEVICE ADDRESS IS 16-bits +#define AM_HAL_GPIO_DEV_ADDR_16 (1) + +// DEVICE OFFSET IS 8-bits +#define AM_HAL_GPIO_DEV_OFFSET_8 (0x00000000) + +// DEVICE OFFSET IS 16-bits +#define AM_HAL_GPIO_DEV_OFFSET_16 (0x00010000) + +// Maximum number of GPIOs on this device +#define AM_HAL_GPIO_MAX_PADS (50) +#define AM_HAL_GPIO_NUMWORDS ((AM_HAL_GPIO_MAX_PADS + 31) / 32) + +//***************************************************************************** +// +//! @name GPIO Pin defines +//! @brief GPIO Pin defines for use with interrupt functions +//! +//! These macros may be used to with \e am_hal_gpio_int_x(). +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n) +//! @} + +// +// AM_HAL_GPIO_MASKBIT(pMaskNm,n) +// The pMaskNm parameter is not used for Apollo2 and is simply ignored. +// n is the desired bitnumber. +// +#define AM_HAL_GPIO_MASKBIT(pMaskNm, n) pMaskNm = (((uint64_t) 0x1) << n) +// +// AM_HAL_GPIO_MASKBITSMULT(pMaskNm,n) +// The pMaskNm parameter is used for multiple bits operation here. +// n is the desired bitnumber. +// +#define AM_HAL_GPIO_MASKBITSMULT(pMaskNm, n) pMaskNm |= (((uint64_t) 0x1) << n) +#define AM_HAL_GPIO_MASKCREATE(MaskVar) \ + uint64_t p##MaskVar; \ + p##MaskVar=0 +#define AM_HAL_GPIO_MASKCLR(pMaskNm) pMaskNm = 0 + +// +// Helper macros used for unraveling the GPIO configuration value (configval). +// +// Note that the configval, which is passed into functions such as +// am_hal_gpio_pin_config() as well as various helper macros, is a concatenated +// value that contains values used in multiple configuration registers. +// +// The GPIO configuration value fields are arranged as follows: +// [ 7: 0] PADREG configuration. +// [11: 8] GPIOCFG +// [15:12] Unused. +// [23:16] ALTPADREG configuration. +// +// Define macros describing these configval fields. +// +#define CFGVAL_PADREG_S 0 +#define CFGVAL_PADREG_M (0xFF << CFGVAL_PADREG_S) +#define CFGVAL_GPIOCFG_S 8 +#define CFGVAL_GPIOCFG_M (0x0F << CFGVAL_GPIOCFG_S) +#define CFGVAL_ALTPAD_S 16 +#define CFGVAL_ALTPAD_M (0xFF << CFGVAL_ALTPAD_S) + +// +// Extraction macros +// +#define CFGVAL_PADREG_X(x) (((uint32_t)(x) & CFGVAL_PADREG_M) >> \ + CFGVAL_PADREG_S) +#define CFGVAL_GPIOCFG_X(x) (((uint32_t)(x) & CFGVAL_GPIOCFG_M) >> \ + CFGVAL_GPIOCFG_S) +#define CFGVAL_ALTPAD_X(x) (((uint32_t)(x) & CFGVAL_ALTPAD_M) >> \ + CFGVAL_ALTPAD_S) + +//***************************************************************************** +// +// Input options. +// +//***************************************************************************** +#define AM_HAL_GPIO_INPEN (0x02 << CFGVAL_PADREG_S) // Enable input transistors. +#define AM_HAL_GPIO_INCFG_RDZERO (0x01 << CFGVAL_GPIOCFG_S) // Disable input read registers. + +//***************************************************************************** +// +// Output options (OUTCFG) +// +//***************************************************************************** +#define AM_HAL_GPIO_OUT_DISABLE ((0x0 << 1) << CFGVAL_GPIOCFG_S) +#define AM_HAL_GPIO_OUT_PUSHPULL ((0x1 << 1) << CFGVAL_GPIOCFG_S) +#define AM_HAL_GPIO_OUT_OPENDRAIN ((0x2 << 1) << CFGVAL_GPIOCFG_S) +#define AM_HAL_GPIO_OUT_3STATE ((0x3 << 1) << CFGVAL_GPIOCFG_S) + +//***************************************************************************** +// +// Special options for IOM0 and IOM4 clocks. +// For 24MHz operation, a special enable must be selected. The 24MHZ select is +// selected via bit0 of OUTCFG (which is, in a way,an alias of OUT_PUSHPULL). +// +//***************************************************************************** +#define AM_HAL_GPIO_24MHZ_ENABLE ((0x1 << 1) << CFGVAL_GPIOCFG_S) + +//***************************************************************************** +// +// Pad configuration options. +// (Configuration value bits 7:0.) +// +//***************************************************************************** +#define AM_HAL_GPIO_HIGH_DRIVE (0x04 << CFGVAL_PADREG_S) +#define AM_HAL_GPIO_LOW_DRIVE (0x00 << CFGVAL_PADREG_S) +#define AM_HAL_GPIO_PULLUP (0x01 << CFGVAL_PADREG_S) +#define AM_HAL_GPIO_PULL1_5K ( (0x01 << CFGVAL_PADREG_S) | \ + AM_HAL_GPIO_PULLUP ) +#define AM_HAL_GPIO_PULL6K ( (0x40 << CFGVAL_PADREG_S) | \ + AM_HAL_GPIO_PULLUP ) +#define AM_HAL_GPIO_PULL12K ( (0x80 << CFGVAL_PADREG_S) | \ + AM_HAL_GPIO_PULLUP ) +#define AM_HAL_GPIO_PULL24K ( (0xC0 << CFGVAL_PADREG_S) | \ + AM_HAL_GPIO_PULLUP ) + +// POWER SWITCH is available on selected pins +#define AM_HAL_GPIO_POWERSOURCE (0x80 << CFGVAL_PADREG_S) +#define AM_HAL_GPIO_POWERSINK (0x80 << CFGVAL_PADREG_S) + +//***************************************************************************** +// +//! ALTPADREG configuration options. +//! (Configuration value bits 23:16.) +//! +//! All Apollo2 GPIO pins can be configured for 2mA or 4mA. +//! AM_HAL_GPIO_DRIVE_2MA = 2mA configuration. +//! AM_HAL_GPIO_DRIVE_4MA = 4mA configuration. +//! +//! Certain Apollo2 GPIO pins can be configured to drive up to 12mA. +//! AM_HAL_GPIO_DRIVE_8MA = 8mA configuration. +//! AM_HAL_GPIO_DRIVE_12MA = 12mA configuration. +//! +//! Notes: +//! - Always consult the Apollo2 data sheet for the latest details. +//! - The higher drive GPIOxx pads generally include: +//! 0-2,5,7-8,10,12-13,22-23,26-29,38-39,42,44-48. +//! - GPIOxx pads that do not support the higher drive: +//! 3-4,6,9,11,14-21,24-25,30-37,40-41,43,49. +//! - User is responsible for ensuring that the selected pin actually supports +//! the higher drive (8mA or 12mA) capabilities. See the Apollo2 data sheet. +//! - Attempting to set the higher drive (8mA or 12mA) configuration on a +//! non-supporting pad will actually set the pad for 4mA drive strength, +//! regardless of the lower bit setting. +// +//***************************************************************************** +#define AM_HAL_GPIO_DRIVE_2MA ( 0 ) +#define AM_HAL_GPIO_DRIVE_4MA AM_HAL_GPIO_HIGH_DRIVE +#define AM_HAL_GPIO_DRIVE_8MA ( 0x01 << CFGVAL_ALTPAD_S ) +#define AM_HAL_GPIO_DRIVE_12MA ( (0x01 << CFGVAL_ALTPAD_S) | \ + AM_HAL_GPIO_HIGH_DRIVE ) + +#define AM_HAL_GPIO_SLEWRATE ( 0x10 << CFGVAL_ALTPAD_S ) + +//***************************************************************************** +// +// Interrupt polarity +// These values can be used directly in the configval. +// +//***************************************************************************** +#define AM_HAL_GPIOCFGVAL_FALLING ((1 << 2) << CFGVAL_GPIOCFG_S) +#define AM_HAL_GPIOCFGVAL_RISING ((0 << 2) << CFGVAL_GPIOCFG_S) + +//***************************************************************************** +// +// Pad function select +// This macro represents the 3 bit function select field in the PADREG byte. +// +//***************************************************************************** +#define AM_HAL_GPIO_FUNC(x) ((x & 0x7) << 3) + +//***************************************************************************** +// +//! Interrupt polarity +//! +//! Important: +//! These values are to be used with am_hal_gpio_int_polarity_bit_set(). +// They are not intended to be used as part of the GPIO configval. +// +//***************************************************************************** +#define AM_HAL_GPIO_FALLING 0x00000001 +#define AM_HAL_GPIO_RISING 0x00000000 + +//***************************************************************************** +// +// A few common pin configurations. +// +//***************************************************************************** +#define AM_HAL_GPIO_DISABLE \ + (AM_HAL_GPIO_FUNC(3)) + +#define AM_HAL_GPIO_INPUT \ + (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_INPEN) + +#define AM_HAL_GPIO_OUTPUT \ + (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_PUSHPULL) + +#define AM_HAL_GPIO_OPENDRAIN \ + (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN) + +#define AM_HAL_GPIO_3STATE \ + (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_3STATE) + +//***************************************************************************** +// +// PADREG helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_PADREG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_PADREGA_O + (n & 0xFC)) + +#define AM_HAL_GPIO_PADREG_S(n) \ + (((uint32_t)(n) % 4) << 3) + +#define AM_HAL_GPIO_PADREG_M(n) \ + ((uint32_t) 0xFF << AM_HAL_GPIO_PADREG_S(n)) + +#define AM_HAL_GPIO_PADREG_FIELD(n, configval) \ + (((uint32_t)(configval) & CFGVAL_PADREG_M) << AM_HAL_GPIO_PADREG_S(n)) + +#define AM_HAL_GPIO_PADREG_W(n, configval) \ + AM_REGVAL(AM_HAL_GPIO_PADREG(n)) = \ + (AM_HAL_GPIO_PADREG_FIELD(n, configval) | \ + (AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & ~AM_HAL_GPIO_PADREG_M(n))) + +#define AM_HAL_GPIO_PADREG_R(n) \ + ((AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & AM_HAL_GPIO_PADREG_M(n)) >> \ + AM_HAL_GPIO_PADREG_S(n)) + + +//***************************************************************************** +// +// ALTPADCFG helper macros. +// The ALTPADCFG bits are located in [23:16] of the configval. +// +//***************************************************************************** +#define AM_HAL_GPIO_ALTPADREG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_ALTPADCFGA_O + (n & 0xFC)) + +#define AM_HAL_GPIO_ALTPADREG_S(n) \ + (((uint32_t)(n) % 4) << 3) + +#define AM_HAL_GPIO_ALTPADREG_M(n) \ + ((uint32_t) 0xFF << AM_HAL_GPIO_ALTPADREG_S(n)) + +#define AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) \ + (CFGVAL_ALTPAD_X(configval) << AM_HAL_GPIO_ALTPADREG_S(n)) + +#define AM_HAL_GPIO_ALTPADREG_W(n, configval) \ + AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) = \ + (AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) | \ + (AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & ~AM_HAL_GPIO_ALTPADREG_M(n))) + +#define AM_HAL_GPIO_ALTPADREG_R(n) \ + ((AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & AM_HAL_GPIO_ALTPADREG_M(n)) >> \ + AM_HAL_GPIO_ALTPADREG_S(n)) + +//***************************************************************************** +// +// CFG helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_CFG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_CFGA_O + ((n & 0xF8) >> 1)) + +#define AM_HAL_GPIO_CFG_S(n) \ + (((uint32_t)(n) % 8) << 2) + +#define AM_HAL_GPIO_CFG_M(n) \ + ((uint32_t) 0x7 << AM_HAL_GPIO_CFG_S(n)) + +#define AM_HAL_GPIO_CFG_FIELD(n, configval) \ + ((((uint32_t)(configval) & 0x700) >> 8) << AM_HAL_GPIO_CFG_S(n)) + +#define AM_HAL_GPIO_CFG_W(n, configval) \ + AM_REGVAL(AM_HAL_GPIO_CFG(n)) = \ + (AM_HAL_GPIO_CFG_FIELD(n, configval) | \ + (AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_CFG_M(n))) + +#define AM_HAL_GPIO_CFG_R(n) \ + ((AM_REGVAL(AM_HAL_GPIO_CFG(n)) & AM_HAL_GPIO_CFG_M(n)) >> \ + AM_HAL_GPIO_CFG_S(n)) + +//***************************************************************************** +// +// Polarity helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_POL_S(n) \ + ((((uint32_t)(n) % 8) << 2) + 3) + +#define AM_HAL_GPIO_POL_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_POL_S(n)) + +#define AM_HAL_GPIO_POL_FIELD(n, polarity) \ + (((uint32_t)(polarity) & 0x1) << AM_HAL_GPIO_POL_S(n)) + +#define AM_HAL_GPIO_POL_W(n, polarity) \ + AM_REGVAL(AM_HAL_GPIO_CFG(n)) = \ + (AM_HAL_GPIO_POL_FIELD(n, polarity) | \ + (AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_POL_M(n))) + +//***************************************************************************** +// +// RD helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_RD_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_RDA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_RD_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_RD_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_RD_S(n)) + +#define AM_HAL_GPIO_RD(n) \ + AM_REGVAL(AM_HAL_GPIO_RD_REG(n)) + +//***************************************************************************** +// +// WT helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_WT_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_WTA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_WT_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_WT_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_WT_S(n)) + +#define AM_HAL_GPIO_WT(n) \ + AM_REGVAL(AM_HAL_GPIO_WT_REG(n)) + +//***************************************************************************** +// +// WTS helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_WTS_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_WTSA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_WTS_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_WTS_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_WTS_S(n)) + +#define AM_HAL_GPIO_WTS(n) \ + AM_REGVAL(AM_HAL_GPIO_WTS_REG(n)) + +//***************************************************************************** +// +// WTC helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_WTC_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_WTCA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_WTC_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_WTC_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_WTC_S(n)) + +#define AM_HAL_GPIO_WTC(n) \ + AM_REGVAL(AM_HAL_GPIO_WTC_REG(n)) + +//***************************************************************************** +// +// EN helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_EN_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_ENA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_EN_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_EN_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_EN_S(n)) + +#define AM_HAL_GPIO_EN(n) \ + AM_REGVAL(AM_HAL_GPIO_EN_REG(n)) + +//***************************************************************************** +// +// ENS helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_ENS_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_ENSA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_ENS_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_ENS_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_ENS_S(n)) + +#define AM_HAL_GPIO_ENS(n) \ + AM_REGVAL(AM_HAL_GPIO_ENS_REG(n)) + +//***************************************************************************** +// +// ENC helper macros. +// +//***************************************************************************** +#define AM_HAL_GPIO_ENC_REG(n) \ + (AM_REG_GPIOn(0) + AM_REG_GPIO_ENCA_O + (((uint32_t)(n) & 0x20) >> 3)) + +#define AM_HAL_GPIO_ENC_S(n) \ + ((uint32_t)(n) % 32) + +#define AM_HAL_GPIO_ENC_M(n) \ + ((uint32_t) 0x1 << AM_HAL_GPIO_ENC_S(n)) + +#define AM_HAL_GPIO_ENC(n) \ + AM_REGVAL(AM_HAL_GPIO_ENC_REG(n)) + +//***************************************************************************** +// +//! @brief Configure the GPIO PAD MUX & GPIO PIN Configurations +//! +//! @param ui32PinNumber - GPIO pin number. +//! @param ui32Config - Configuration options. +//! +//! This function applies the settings for a single GPIO. For a list of valid +//! options please see the top of this file (am_hal_gpio.h) and am_hal_pin.h. +//! +//! Usage examples: +//! am_hal_gpio_pin_config(11, AM_HAL_GPIO_INPUT); +//! am_hal_gpio_pin_config(10, AM_HAL_GPIO_OUTPUT); +//! am_hal_gpio_pin_config(14, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_SLEWRATE); +//! am_hal_gpio_pin_config(15, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_HIGHDRIVESTR); +// +//***************************************************************************** +#define am_hal_gpio_pin_config(ui32PinNumber, ui32Config) \ + if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS ) \ + { \ + AM_CRITICAL_BEGIN \ + \ + AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \ + \ + AM_HAL_GPIO_CFG_W(ui32PinNumber, ui32Config); \ + AM_HAL_GPIO_PADREG_W(ui32PinNumber, ui32Config); \ + AM_HAL_GPIO_ALTPADREG_W(ui32PinNumber, ui32Config); \ + \ + AM_REGn(GPIO, 0, PADKEY) = 0; \ + \ + AM_CRITICAL_END \ + } + +//***************************************************************************** +// +//! @brief Set the state of one GPIO polarity bit. +//! +//! @param ui32BitNum - GPIO number. +//! @param ui32Polarity - Desired state. +//! +//! This function sets the state of one GPIO polarity bit to a supplied value. +//! The ui32Polarity parameter should be one of the following values: +//! +//! AM_HAL_GPIO_FALLING +//! AM_HAL_GPIO_RISING +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_int_polarity_bit_set(ui32BitNum, ui32Polarity) \ + if ( (uint32_t)(ui32BitNum) < AM_HAL_GPIO_MAX_PADS ) \ + { \ + AM_CRITICAL_BEGIN \ + \ + AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \ + AM_HAL_GPIO_POL_W(ui32BitNum, ui32Polarity); \ + AM_REGn(GPIO, 0, PADKEY) = 0; \ + \ + AM_CRITICAL_END \ + } + +//***************************************************************************** +// +//! @brief Get the state of one GPIO from the INPUT READ REGISTER. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function retrieves the state of one GPIO from the INPUT READ +//! REGISTER. +//! +//! @return the state for the requested GPIO. +// +//***************************************************************************** +#define am_hal_gpio_input_bit_read(ui32BitNum) \ + ((AM_HAL_GPIO_RD(ui32BitNum) & AM_HAL_GPIO_RD_M(ui32BitNum)) != 0) + +//***************************************************************************** +// +//! @brief Get the state of one GPIO in the DATA OUTPUT REGISTER +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function retrieves the state of one GPIO in the DATA OUTPUT REGISTER. +//! +//! @return the state for the requested GPIO or -1 for error. +// +//***************************************************************************** +#define am_hal_gpio_out_bit_read(ui32BitNum) \ + ((AM_HAL_GPIO_WT(ui32BitNum) & AM_HAL_GPIO_WT_M(ui32BitNum)) != 0) + +//***************************************************************************** +// +//! @brief Set the output state high for one GPIO. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function sets the output state to high for one GPIO. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_out_bit_set(ui32BitNum) \ + AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum) + +//***************************************************************************** +// +//! @brief Sets the output state to low for one GPIO. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function sets the output state to low for one GPIO. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_out_bit_clear(ui32BitNum) \ + AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum) + +//***************************************************************************** +// +//! @brief Sets the output state to ui32Value for one GPIO. +//! +//! @param ui32BitNum - GPIO number. +//! @param ui32Value - Desired output state. +//! +//! This function sets the output state to ui32Value for one GPIO. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_out_bit_replace(ui32BitNum, ui32Value) \ + if ( ui32Value ) \ + { \ + AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum); \ + } \ + else \ + { \ + AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum); \ + } + +//***************************************************************************** +// +//! @brief Toggle the output state of one GPIO. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function toggles the output state of one GPIO. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_out_bit_toggle(ui32BitNum) \ + if ( 1 ) \ + { \ + AM_CRITICAL_BEGIN \ + AM_HAL_GPIO_WT(ui32BitNum) ^= AM_HAL_GPIO_WT_M(ui32BitNum); \ + AM_CRITICAL_END \ + } + +//***************************************************************************** +// +//! @brief Sets the output enable for one GPIO. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function sets the output enable for one GPIO. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_out_enable_bit_set(ui32BitNum) \ + AM_HAL_GPIO_ENS(ui32BitNum) = AM_HAL_GPIO_ENS_M(ui32BitNum) + +//***************************************************************************** +// +//! @brief Clears the output enable for one GPIO. +//! +//! @param ui32BitNum - GPIO number. +//! +//! This function clears the output enable for one GPIO. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_gpio_out_enable_bit_clear(ui32BitNum) \ + AM_HAL_GPIO_ENC(ui32BitNum) = AM_HAL_GPIO_ENC_M(ui32BitNum) + +//***************************************************************************** +// +// Function pointer type for GPIO interrupt handlers. +// +//***************************************************************************** +typedef void (*am_hal_gpio_handler_t)(void); + +//***************************************************************************** +// +// External function prototypes +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +extern uint32_t am_hal_gpio_pin_config_read(uint32_t ui32PinNumber); +extern uint64_t am_hal_gpio_input_read(void); +extern uint64_t am_hal_gpio_out_read(void); +extern uint32_t am_hal_gpio_out_enable_bit_get(uint32_t ui32BitNum); +extern uint64_t am_hal_gpio_out_enable_get(void); +extern void am_hal_gpio_int_enable(uint64_t ui64InterruptMask); +extern uint64_t am_hal_gpio_int_enable_get(void); +extern void am_hal_gpio_int_disable(uint64_t ui64InterruptMask); +extern void am_hal_gpio_int_clear(uint64_t ui64InterruptMask); +extern void am_hal_gpio_int_set(uint64_t ui64InterruptMask); +extern uint64_t am_hal_gpio_int_status_get(bool bEnabledOnly); +extern void am_hal_gpio_int_service(uint64_t ui64Status); +extern void am_hal_gpio_int_register(uint32_t ui32GPIONumber, + am_hal_gpio_handler_t pfnHandler); + +extern bool am_hal_gpio_int_polarity_bit_get(uint32_t ui32BitNum); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_GPIO_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_i2c_bit_bang.c b/mcu/apollo2/hal/am_hal_i2c_bit_bang.c new file mode 100644 index 0000000..61136a3 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_i2c_bit_bang.c @@ -0,0 +1,756 @@ +//***************************************************************************** +// +// am_hal_i2c_bit_bang.c +//! @file +//! +//! @brief I2C bit bang module. +//! +//! These functions implement the I2C bit bang utility +//! It implements an I2C interface at close to 400 kHz +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include + +#include "am_mcu_apollo.h" +#include "am_hal_i2c_bit_bang.h" + +// Max number of clock cycles to wait for clock stretch +#define I2C_BB_MAX_CLOCK_STRETCH_WAIT 100 + +#define I2C_BB_DESIRED_FREQ_HZ 400000 + +#define I2C_BB_CYCLES_PER_DELAY_COUNT 3 +#define I2C_BB_ONE_BIT_TIME_IN_CYCLES (AM_HAL_CLKGEN_FREQ_MAX_HZ/I2C_BB_DESIRED_FREQ_HZ) +#define I2C_BB_ONE_BIT_TIME_IN_DELAY_COUNT (I2C_BB_ONE_BIT_TIME_IN_CYCLES/I2C_BB_CYCLES_PER_DELAY_COUNT) + +// Number of loops (each worth 3 cycles) needed to delay for defined time +// This is imprecise, as there is a setup time as well which is not accounted +// for +// One Bit time = 120 Cycles (400 kHz @ 48 MHz) +#define HALF_BIT_TIME (I2C_BB_ONE_BIT_TIME_IN_DELAY_COUNT/2) +#define QUARTER_BIT_TIME (I2C_BB_ONE_BIT_TIME_IN_DELAY_COUNT/4) +#define ASM_DELAY am_hal_flash_delay + +// Empirically determined adjustments to account for the fact that there is a +// variable time spent in actual processing as well, and hence we need not delay +// for the full time. This processing time is variable based on exact processing +// needed at various times, and will also vary based on compiler type and +// optimization levels +#define I2C_BB_TIMER_ADJUST 6 // Can not be more than QUARTER_BIT_TIME - 1 +#define I2C_BB_TIMER_HI_ADJUST 15 // Can not be more than HALF_BIT_TIME - 1 +#define I2C_BB_TIMER_LO_ADJUST 13 // Can not be more than HALF_BIT_TIME - 1 + +// Wait till it is time to end the SCL Hi Period +#define WAIT_I2C_CLOCK_HI_PERIOD() ASM_DELAY(HALF_BIT_TIME - I2C_BB_TIMER_HI_ADJUST) +// Wait till it is time to end the SCL Lo Period +#define WAIT_I2C_CLOCK_LOW_PERIOD() ASM_DELAY(HALF_BIT_TIME - I2C_BB_TIMER_LO_ADJUST) +// Delay for Quarter Clock +#define WAIT_FOR_QUARTER_I2C_CLOCK() ASM_DELAY(QUARTER_BIT_TIME - I2C_BB_TIMER_ADJUST) +#define WRITE_SCL_LO() \ + do { \ + AM_REGVAL(am_hal_i2c_bit_bang_priv.sck_reg_clr_addr) = (am_hal_i2c_bit_bang_priv.sck_reg_val); \ + } while(0) + +#define PULL_SCL_HI() \ + do { \ + AM_REGVAL(am_hal_i2c_bit_bang_priv.sck_reg_set_addr) = (am_hal_i2c_bit_bang_priv.sck_reg_val); \ + } while(0) + +#define GET_SCL() (AM_REGVAL(am_hal_i2c_bit_bang_priv.sck_reg_read_addr) & (am_hal_i2c_bit_bang_priv.sck_reg_val)) +#define GET_SDA() (AM_REGVAL(am_hal_i2c_bit_bang_priv.sda_reg_read_addr) & (am_hal_i2c_bit_bang_priv.sda_reg_val)) + +#define WRITE_SDA_LO() \ + do { \ + AM_REGVAL(am_hal_i2c_bit_bang_priv.sda_reg_clr_addr) = (am_hal_i2c_bit_bang_priv.sda_reg_val); \ + } while(0) + +#define PULL_SDA_HI() \ + do { \ + AM_REGVAL(am_hal_i2c_bit_bang_priv.sda_reg_set_addr) = (am_hal_i2c_bit_bang_priv.sda_reg_val); \ + } while(0) + + +//***************************************************************************** +// +// I2C Bit Bang Private Data Structure +// +//***************************************************************************** +typedef struct am_util_bit_bang_priv +{ + bool start_flag; + uint32_t sck_gpio_number; + uint32_t sda_gpio_number; + uint32_t sck_reg_set_addr; + uint32_t sck_reg_clr_addr; + uint32_t sck_reg_read_addr; + uint32_t sck_reg_val; + uint32_t sda_reg_set_addr; + uint32_t sda_reg_clr_addr; + uint32_t sda_reg_read_addr; + uint32_t sda_reg_val; +} am_hal_i2c_bit_bang_priv_t; +static am_hal_i2c_bit_bang_priv_t am_hal_i2c_bit_bang_priv; + +// +// Wait for any stretched clock to go high +// If it times out - return failure +// +static inline bool +i2c_pull_and_wait_scl_hi(void) +{ + // Maximum time to wait for clock stretching + uint32_t maxLoop = 4*I2C_BB_MAX_CLOCK_STRETCH_WAIT + 1; + // Pull SCL High + PULL_SCL_HI(); + // Poll for SCL to check for clock stretching + while (!GET_SCL()) + { + if (--maxLoop == 0) + { + // timeout! + return true; + } + WAIT_FOR_QUARTER_I2C_CLOCK(); + } + return false; +} + +//***************************************************************************** +// +//! @brief Initialize i2c bit bang private data structure +//! +//! @param sck_gpio_number is the GPIO # for the I2C SCK clock pin +//! @param sda_gpio_number is the GPIO # for the I2C SDA data pin +//! +//! This function initializes the I2C bit bang utility's internal data struct. +//! +//! returns None. +// +//***************************************************************************** +am_hal_i2c_bit_bang_enum_e +am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, + uint32_t sda_gpio_number) +{ + int i; + // + // remember GPIO pin assignments for I2C bus signals + // + am_hal_i2c_bit_bang_priv.sck_gpio_number = sck_gpio_number; + am_hal_i2c_bit_bang_priv.sda_gpio_number = sda_gpio_number; + + am_hal_i2c_bit_bang_priv.sck_reg_set_addr = AM_HAL_GPIO_WTS_REG(sck_gpio_number); + am_hal_i2c_bit_bang_priv.sck_reg_clr_addr = AM_HAL_GPIO_WTC_REG(sck_gpio_number); + am_hal_i2c_bit_bang_priv.sck_reg_read_addr = AM_HAL_GPIO_RD_REG(sck_gpio_number); + am_hal_i2c_bit_bang_priv.sck_reg_val = AM_HAL_GPIO_WTC_M(sck_gpio_number); + am_hal_i2c_bit_bang_priv.sda_reg_set_addr = AM_HAL_GPIO_WTS_REG(sda_gpio_number); + am_hal_i2c_bit_bang_priv.sda_reg_clr_addr = AM_HAL_GPIO_WTC_REG(sda_gpio_number); + am_hal_i2c_bit_bang_priv.sda_reg_read_addr = AM_HAL_GPIO_RD_REG(sda_gpio_number); + am_hal_i2c_bit_bang_priv.sda_reg_val = AM_HAL_GPIO_WTC_M(sda_gpio_number); + + // + // Set SCK GPIO data bit high so we aren't pulling down the clock + // + am_hal_gpio_out_bit_set(sck_gpio_number); + // + // Set up SCK GPIO configuration bi-direction, input + // + am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN); + + // + // Set SDA GPIO data bit high so we aren't pulling down the data line + // + am_hal_gpio_out_bit_set(sda_gpio_number); + // + // Set up SDA GPIO configuration bi-direction, input + // + am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN); + + // Now make sure we have control of the clock line + // + // Wait for any stretched clock to go high. Return if still not high + // + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + if (!GET_SDA()) + { + // If previous transaction did not finish - SDA may be pulled low for a Read. + // If so - need to flush out the data (max 8 bits) & NACK + for (i = 0; i < 9; i++) + { + // + // Pull down on clock line + // + WRITE_SCL_LO(); + // + // Delay for 1/2 bit cell time to start the clock and let peer write on SDA + // + WAIT_I2C_CLOCK_LOW_PERIOD(); + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + if (GET_SDA()) + { + // Send START/STOP to clear the bus + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + WRITE_SDA_LO(); + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + // + // Pull down on clock line + // + WRITE_SCL_LO(); + // + // Delay for 1/2 bit cell time to start the clock and let peer write on SDA + // + WAIT_I2C_CLOCK_LOW_PERIOD(); + // + // Release the clock line + // + PULL_SCL_HI(); + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + PULL_SDA_HI(); + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + break; + } + } + if (i == 9) + { + // It is it still stuck after 9 clocks - something is wrong. Need to bail out + return AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT; + } + } + return AM_HAL_I2C_BIT_BANG_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Receive one data byte from an I2C device +//! +//! This function handles sending one byte to a slave device +//! bNack defines if we should send an ACK or NACK +//! +//! returns the byte received +// +//***************************************************************************** +static inline am_hal_i2c_bit_bang_enum_e +i2c_receive_byte(uint8_t *pRxByte, bool bNack) +{ + int i; + uint8_t data_byte = 0; + + // + // Loop through receiving 8 bits + // + for (i = 0; i < 8; i++) + { + // + // Pull down on clock line + // + WRITE_SCL_LO(); + + // + // release the data line from from the previous ACK + // + PULL_SDA_HI(); + + // + // Delay for 1/2 bit cell time to start the clock and let peer write on SDA + // + WAIT_I2C_CLOCK_LOW_PERIOD(); + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // grab the data bit here + // + if ( GET_SDA() ) + { + // + // set the bit in the data byte to be returned + // + data_byte |= (0x80 >> i); + } + + // + // Delay for 1/2 bit cell time while clock is high + // + WAIT_I2C_CLOCK_HI_PERIOD(); + } + + *pRxByte = data_byte; + // + // Pull down on clock line + // + WRITE_SCL_LO(); + + // + // pull the data line down so we can ACK/NAK the byte we just received + // + if (bNack) + { + // + // Pull up on data line with clock low to indicate NAK + // + PULL_SDA_HI(); + } + else + { + // + // Pull down on data line with clock low to indicate ACK + // + WRITE_SDA_LO(); + } + // + // Delay for 1/2 bit cell time before sending ACK to device + // + WAIT_I2C_CLOCK_LOW_PERIOD(); + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // Delay for 1/2 bit cell time while clock is high to le peer sample the ACK/NAK + // + WAIT_I2C_CLOCK_HI_PERIOD(); + // + // Give the received data byte back to them + // + return AM_HAL_I2C_BIT_BANG_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Send one data bytes to an I2C device +//! +//! @param one_byte the byte to send, could be address could be data +//! +//! This function handles sending one byte to a slave device +//! Starts with 0 clock and runs till full cycle +//! +//! returns I2C BB ENUM +//! { +//! AM_HAL_I2C_BIT_BANG_SUCCESS, +//! AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED +//! } +// +//***************************************************************************** +static inline am_hal_i2c_bit_bang_enum_e +i2c_send_byte(uint8_t one_byte) +{ + int i; + bool data_naked = false; + + // + // Loop through sending 8 bits + // + for (i = 0; i < 8; i++) + { + // + // Pull down on clock line + // + WRITE_SCL_LO(); + + // + // output the next data bit + // + if ( one_byte & (0x80 >> i) ) + { + PULL_SDA_HI(); + } + else + { + WRITE_SDA_LO(); + } + + // + // Delay for 1/2 bit cell time to start the clock + // + WAIT_I2C_CLOCK_LOW_PERIOD(); + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // Delay for 1/2 bit cell time while clock is high + // + WAIT_I2C_CLOCK_HI_PERIOD(); + } + + // + // Pull down on clock line + // + WRITE_SCL_LO(); + + // + // Delay for 1/2 bit cell time to start the clock + // + WAIT_I2C_CLOCK_LOW_PERIOD(); + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // Grab the state of the ACK bit and return it + // + data_naked = GET_SDA(); + // + // Delay for 1/2 bit cell time to complete the high period + // + WAIT_I2C_CLOCK_HI_PERIOD(); + if ( data_naked ) + { + return AM_HAL_I2C_BIT_BANG_DATA_NAKED; + } + else + { + return AM_HAL_I2C_BIT_BANG_SUCCESS; + } +} + +//***************************************************************************** +// +//! @brief Receive a string of data bytes from an I2C device +//! +//! @param address (only 8 bit I2C addresses are supported) +//! LSB is I2C R/W +//! @param number_of_bytes to transfer (# payload bytes) +//! @param pData pointer to data buffer to receive payload +//! +//! This function handles receiving a payload from a slave device +//! +//! returns ENUM{AM_HAL_I2C_BIT_BANG_SUCCESS,AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED} +// +//***************************************************************************** +am_hal_i2c_bit_bang_enum_e +am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, + uint8_t *pData, uint8_t ui8Offset, + bool bUseOffset, bool bNoStop) +{ + uint32_t ui32I; + am_hal_i2c_bit_bang_enum_e status = AM_HAL_I2C_BIT_BANG_SUCCESS; + + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // Pull down on data line with clock high --> START CONDITION + // + WRITE_SDA_LO(); + + // + // Delay for 1/2 bit cell time to start the clock + // + WAIT_I2C_CLOCK_HI_PERIOD(); + + // + // send the address byte and wait for the ACK/NAK + // + status = i2c_send_byte(address); + if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS ) + { + if ( status == AM_HAL_I2C_BIT_BANG_DATA_NAKED) + { + return AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED; + } + return status; + } + + if ( bUseOffset ) + { + status = i2c_send_byte(ui8Offset); + if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS ) + { + return status; + } + } + + // + // receive the requested number of data bytes + // + for (ui32I = 0; ui32I < number_of_bytes - 1; ui32I++) + { + // + // receive the data bytes and send ACK for each one + // + status = i2c_receive_byte(pData, false); + if (status != AM_HAL_I2C_BIT_BANG_SUCCESS) + { + return status; + } + pData++; + } + // Send NAK for the last byte + status = i2c_receive_byte(pData, true); + if (status != AM_HAL_I2C_BIT_BANG_SUCCESS) + { + return status; + } + + //******************** + // Send stop condition + //******************** + // + // Pull down on clock line + // + WRITE_SCL_LO(); + + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + + + if (!bNoStop) + { + // + // Pull down on data line with clock low + // + WRITE_SDA_LO(); + } + else + { + // + // Release data line with clock low itself, as we are not sending STOP + // + PULL_SDA_HI(); + } + // + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // Delay for 1/2 bit cell time while clock is high + // + WAIT_I2C_CLOCK_HI_PERIOD(); + + if (!bNoStop) + { + // + // release data line with clock high --> STOP CONDITION + // + PULL_SDA_HI(); + } + + // + // message successfully received (how could we fail???) + // + return AM_HAL_I2C_BIT_BANG_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Send a string of data bytes to an I2C device +//! +//! @param address (only 8 bit I2C addresses are supported) +//! LSB is I2C R/W +//! @param number_of_bytes to transfer (# payload bytes) +//! @param pData pointer to data buffer containing payload +//! +//! This function handles sending a payload to a slave device +//! +//! returns ENUM {AM_HAL_I2C_BIT_BANG_SUCCESS, AM_HAL_I2C_BIT_BANG_DATA_NAKED, +//! AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED} +// +//***************************************************************************** +am_hal_i2c_bit_bang_enum_e +am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes, + uint8_t *pData, uint8_t ui8Offset, + bool bUseOffset, bool bNoStop) +{ + uint32_t ui32I; + am_hal_i2c_bit_bang_enum_e status; + bool data_naked = false; + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + // + // Pull down on data line with clock high --> START CONDITION + // + WRITE_SDA_LO(); + + // + // Delay for 1/2 bit cell time to start the clock + // + WAIT_I2C_CLOCK_HI_PERIOD(); + + // + // send the address byte and wait for the ACK/NAK + // + status = i2c_send_byte(address); + if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS ) + { + if ( status == AM_HAL_I2C_BIT_BANG_DATA_NAKED) + { + return AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED; + } + return status; + } + + if ( bUseOffset ) + { + status = i2c_send_byte(ui8Offset); + if ( status != AM_HAL_I2C_BIT_BANG_SUCCESS ) + { + return status; + } + } + + // + // send the requested number of data bytes + // + for (ui32I = 0; ui32I < number_of_bytes; ui32I++) + { + // + // send out the data bytes while watching for premature NAK + // + status = i2c_send_byte(*pData++); + if (status != AM_HAL_I2C_BIT_BANG_SUCCESS) + { + if (status == AM_HAL_I2C_BIT_BANG_DATA_NAKED) + { + if (ui32I != (number_of_bytes-1)) + { + data_naked = true; + // TODO - should we be sending the STOP bit in this case regardless of bNoStop? + break; + } + else + { + status = AM_HAL_I2C_BIT_BANG_SUCCESS; + } + } + else + { + return status; + } + } + } + + //******************** + // Send stop condition + //******************** + + // + // Pull down on clock line + // + WRITE_SCL_LO(); + + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + + + if (!bNoStop) + { + // + // Pull down on data line with clock low + // + WRITE_SDA_LO(); + } + else + { + // + // Release data line with clock low itself, as we are not sending STOP + // + PULL_SDA_HI(); + } + + // + // Delay for 1/4 bit cell time + // + WAIT_FOR_QUARTER_I2C_CLOCK(); + + if (i2c_pull_and_wait_scl_hi()) + { + return AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT; + } + if (!bNoStop) + { + // + // release data line with clock high --> STOP CONDITION + // + PULL_SDA_HI(); + } + + // + // Delay for 1/2 bit cell time while clock is high + // + WAIT_I2C_CLOCK_HI_PERIOD(); + + if ( data_naked ) + { + return AM_HAL_I2C_BIT_BANG_DATA_NAKED; // if it happens early + } + + // + // message successfully sent + // + return AM_HAL_I2C_BIT_BANG_SUCCESS; +} diff --git a/mcu/apollo2/hal/am_hal_i2c_bit_bang.h b/mcu/apollo2/hal/am_hal_i2c_bit_bang.h new file mode 100644 index 0000000..0422fb7 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_i2c_bit_bang.h @@ -0,0 +1,101 @@ +//***************************************************************************** +// +// am_hal_i2c_bit_bang.h +//! @file +//! +//! @brief I2C bit bang module. +//! +//! These functions implement the I2C bit bang utility +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_I2C_BIT_BANG_H +#define AM_HAL_I2C_BIT_BANG_H + +//***************************************************************************** +// +// Enumerated return constants +// +//***************************************************************************** +typedef enum +{ + AM_HAL_I2C_BIT_BANG_SUCCESS = 0, + AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED, + AM_HAL_I2C_BIT_BANG_DATA_NAKED, + AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT, + AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT, + AM_HAL_I2C_BIT_BANG_STATUS_MAX, +}am_hal_i2c_bit_bang_enum_e; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, + uint32_t sda_gpio_number); + +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_send(uint8_t address, + uint32_t number_of_bytes, + uint8_t *pData, + uint8_t ui8Offset, + bool bUseOffset, + bool bNoStop); + +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_receive(uint8_t address, + uint32_t number_of_bytes, + uint8_t *pData, + uint8_t ui8Offset, + bool bUseOffset, + bool bNoStop); +#ifdef __cplusplus +} +#endif + +#endif //AM_HAL_I2C_BIT_BANG_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_interrupt.c b/mcu/apollo2/hal/am_hal_interrupt.c new file mode 100644 index 0000000..9c28f23 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_interrupt.c @@ -0,0 +1,434 @@ +//***************************************************************************** +// +// am_hal_interrupt.c +//! @file +//! +//! @brief Helper functions supporting interrupts and NVIC operation. +//! +//! These functions may be used for NVIC-level interrupt configuration. +//! +//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Enable an interrupt. +//! +//! @param ui32Interrupt The ISR number of the interrupt to be enabled. +//! +//! This function enables an interrupt signal to the NVIC based on the provided +//! ISR number. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_interrupt_enable(uint32_t ui32Interrupt) +{ + // + // Check to see what type of interrupt this is. + // + if ( ui32Interrupt > 15 ) + { + // + // If this ISR number corresponds to a "normal" peripheral interrupt, + // enable it using the NVIC register. + // + AM_REG(NVIC, ISER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); + } + else + { + // + // If this is an ARM internal interrupt number, route it to the + // appropriate enable register. + // + switch(ui32Interrupt) + { + case AM_HAL_INTERRUPT_BUSFAULT: + AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 1); + break; + + case AM_HAL_INTERRUPT_USAGEFAULT: + AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 1); + break; + + case AM_HAL_INTERRUPT_MPUFAULT: + AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 1); + break; + } + } +} + +//***************************************************************************** +// +//! @brief Disable an interrupt. +//! +//! @param ui32Interrupt The ISR number of the interrupt to be disabled. +//! +//! This function disables an interrupt signal to the NVIC based on the +//! provided ISR number. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_interrupt_disable(uint32_t ui32Interrupt) +{ + // + // Check to see what type of interrupt this is. + // + if ( ui32Interrupt > 15 ) + { + // + // If this ISR number corresponds to a "normal" peripheral interrupt, + // disable it using the NVIC register. + // + AM_REG(NVIC, ICER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); + } + else + { + // + // If this is an ARM internal interrupt number, route it to the + // appropriate enable register. + // + switch(ui32Interrupt) + { + case AM_HAL_INTERRUPT_BUSFAULT: + AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 0); + break; + + case AM_HAL_INTERRUPT_USAGEFAULT: + AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 0); + break; + + case AM_HAL_INTERRUPT_MPUFAULT: + AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 0); + break; + } + } +} + +//***************************************************************************** +// +//! @brief Set the priority of an interrupt vector. +//! +//! @param ui32Interrupt is the ISR number of the interrupt to change. +//! @param ui32Priority is the new ISR priority value. +//! +//! This function changes the priority value in the NVIC for the given +//! interrupt vector number. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority) +{ + volatile uint32_t *pui32PriorityReg; + volatile uint32_t ui32OldPriority; + uint32_t ui32Shift; + + // + // Find the correct priority register. + // + pui32PriorityReg = (volatile uint32_t *) AM_REG_NVIC_IPR0_O; + pui32PriorityReg += ((ui32Interrupt - 16) >> 2); + + // + // Find the correct shift value. + // + ui32Shift = (((ui32Interrupt - 16) & 0x3) * 8); + + // + // Mask out the old priority. + // + ui32OldPriority = *pui32PriorityReg; + ui32OldPriority &= ~(0xFF << ui32Shift); + + // + // OR in the new priority. + // + *pui32PriorityReg = ui32OldPriority | (ui32Priority << ui32Shift); +} + +//***************************************************************************** +// +//! @brief Set a pending interrupt bit in the NVIC (Software Interrupt) +//! +//! @param ui32Interrupt is the ISR number of the interrupt to change. +//! +//! This function sets the specified bit in the Interrupt Set Pending (ISPR0) +//! register. For future MCUs there may be more than one ISPR. +//! +//! @return None +// +//***************************************************************************** +void am_hal_interrupt_pend_set(uint32_t ui32Interrupt) +{ + // + // Check to see if the specified interrupt is valid for this MCU + // + if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX ) + { + return; + } + + // + // Check to see what type of interrupt this is. + // + if ( ui32Interrupt > 15 ) + { + // + // If this ISR number corresponds to a "normal" peripheral interrupt, + // disable it using the NVIC register. + // + AM_REG(NVIC, ISPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); + } +} + +//***************************************************************************** +// +//! @brief Clear a pending interrupt bit in the NVIC without servicing it +//! +//! @param ui32Interrupt is the ISR number of the interrupt to change. +//! +//! This function clears the specified bit in the Interrupt Clear Pending +//! (ICPR0) register. For future MCUs there may be more than one ICPR. This +//! function is useful immediately following a WFI before interrupts are +//! re-enabled. +//! +//! @return None +// +//***************************************************************************** +void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt) +{ + // + // Check to see if the specified interrupt is valid for this MCU + // + if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX ) + { + return; + } + + // + // Check to see what type of interrupt this is. + // + if ( ui32Interrupt > 15 ) + { + // + // If this ISR number corresponds to a "normal" peripheral interrupt, + // disable it using the NVIC register. + // + AM_REG(NVIC, ICPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F); + } +} + +//***************************************************************************** +// +//! @brief Globally enable interrupt service routines +//! +//! This function allows interrupt signals from the NVIC to trigger ISR entry +//! in the CPU. This function must be called if interrupts are to be serviced +//! in software. +//! +//! @return 1 if interrupts were previously disabled, 0 otherwise. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm uint32_t +am_hal_interrupt_master_enable(void) +{ + mrs r0, PRIMASK + cpsie i + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless uint32_t +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Globally disable interrupt service routines +//! +//! This function prevents interrupt signals from the NVIC from triggering ISR +//! entry in the CPU. This will effectively stop incoming interrupt sources +//! from triggering their corresponding ISRs. +//! +//! @note Any external interrupt signal that occurs while the master interrupt +//! disable is active will still reach the "pending" state in the NVIC, but it +//! will not be allowed to reach the "active" state or trigger the +//! corresponding ISR. Instead, these interrupts are essentially "queued" until +//! the next time the master interrupt enable instruction is executed. At that +//! time, the interrupt handlers will be executed in order of decreasing +//! priority. +//! +//! @return 1 if interrupts were previously disabled, 0 otherwise. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm uint32_t +am_hal_interrupt_master_disable(void) +{ + mrs r0, PRIMASK + cpsid i + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless uint32_t +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Sets the master interrupt state based on the input. +//! +//! @param ui32InterruptState - Desired PRIMASK value. +//! +//! This function directly writes the PRIMASK register in the ARM core. A value +//! of 1 will disable interrupts, while a value of zero will enable them. +//! +//! This function may be used along with am_hal_interrupt_master_disable() to +//! implement a nesting critical section. To do this, call +//! am_hal_interrupt_master_disable() to start the critical section, and save +//! its return value. To complete the critical section, call +//! am_hal_interrupt_master_set() using the saved return value as \e +//! ui32InterruptState. This will safely restore PRIMASK to the value it +//! contained just before the start of the critical section. +//! +//! @return None. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + msr PRIMASK, r0 + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void __attribute__((naked)) +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +void __attribute__((naked)) +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless void +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#endif + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_interrupt.h b/mcu/apollo2/hal/am_hal_interrupt.h new file mode 100644 index 0000000..35d244d --- /dev/null +++ b/mcu/apollo2/hal/am_hal_interrupt.h @@ -0,0 +1,160 @@ +//***************************************************************************** +// +// am_hal_interrupt.h +//! @file +//! +//! @brief Helper functions supporting interrupts and NVIC operation. +//! +//! These functions may be used for NVIC-level interrupt configuration. +//! +//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_INTERRUPT_H +#define AM_HAL_INTERRUPT_H + +//***************************************************************************** +// +//! @name ISR number macros. +//! @brief ISR macros. +//! +//! These macros are used for all ui32Interrupt arguments in this module. +//! @{ +// +//***************************************************************************** +// +// Hardware interrupts +// +#define AM_HAL_INTERRUPT_MAX (47) //AM_HAL_INTERRUPT_SOFTWARE3 +#define AM_HAL_INTERRUPT_RESET 1 +#define AM_HAL_INTERRUPT_NMI 2 +#define AM_HAL_INTERRUPT_HARDFAULT 3 +#define AM_HAL_INTERRUPT_MPUFAULT 4 +#define AM_HAL_INTERRUPT_BUSFAULT 5 +#define AM_HAL_INTERRUPT_USAGEFAULT 6 + +#define AM_HAL_INTERRUPT_SVCALL 11 +#define AM_HAL_INTERRUPT_DEBUGMON 12 +#define AM_HAL_INTERRUPT_PENDSV 14 +#define AM_HAL_INTERRUPT_SYSTICK 15 + +// +// Begin IRQs +// +#define AM_HAL_INTERRUPT_BROWNOUT 16 +#define AM_HAL_INTERRUPT_WATCHDOG 17 +#define AM_HAL_INTERRUPT_CLKGEN 18 +#define AM_HAL_INTERRUPT_VCOMP 19 +#define AM_HAL_INTERRUPT_IOSLAVE 20 +#define AM_HAL_INTERRUPT_IOSACC 21 +#define AM_HAL_INTERRUPT_IOMASTER0 22 +#define AM_HAL_INTERRUPT_IOMASTER1 23 +#define AM_HAL_INTERRUPT_IOMASTER2 24 +#define AM_HAL_INTERRUPT_IOMASTER3 25 +#define AM_HAL_INTERRUPT_IOMASTER4 26 +#define AM_HAL_INTERRUPT_IOMASTER5 27 +#define AM_HAL_INTERRUPT_GPIO 28 +#define AM_HAL_INTERRUPT_CTIMER 29 +#define AM_HAL_INTERRUPT_UART0 30 +#define AM_HAL_INTERRUPT_UART1 31 +#define AM_HAL_INTERRUPT_UART (AM_HAL_INTERRUPT_UART0) +#define AM_HAL_INTERRUPT_ADC 32 +#define AM_HAL_INTERRUPT_PDM 33 +#define AM_HAL_INTERRUPT_STIMER 34 +#define AM_HAL_INTERRUPT_STIMER_CMPR0 35 +#define AM_HAL_INTERRUPT_STIMER_CMPR1 36 +#define AM_HAL_INTERRUPT_STIMER_CMPR2 37 +#define AM_HAL_INTERRUPT_STIMER_CMPR3 38 +#define AM_HAL_INTERRUPT_STIMER_CMPR4 39 +#define AM_HAL_INTERRUPT_STIMER_CMPR5 40 +#define AM_HAL_INTERRUPT_STIMER_CMPR6 41 +#define AM_HAL_INTERRUPT_STIMER_CMPR7 42 +#define AM_HAL_INTERRUPT_FLASH 43 + +#define AM_HAL_INTERRUPT_SOFTWARE0 44 +#define AM_HAL_INTERRUPT_SOFTWARE1 45 +#define AM_HAL_INTERRUPT_SOFTWARE2 46 +#define AM_HAL_INTERRUPT_SOFTWARE3 47 +//! @} + +//***************************************************************************** +// +//! @brief Interrupt priority +//! +//! This macro is made to be used with the \e am_hal_interrupt_priority_set() +//! function. It converts a priority number to the format used by the ARM +//! standard priority register, where only the top 3 bits are used. +//! +//! For example, AM_HAL_INTERRUPT_PRIORITY(1) yields a value of 0x20. +// +//***************************************************************************** +#define AM_HAL_INTERRUPT_PRIORITY(n) (((uint32_t)(n) & 0x7) << 5) + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_interrupt_enable(uint32_t ui32Interrupt); +extern void am_hal_interrupt_disable(uint32_t ui32Interrupt); +extern void am_hal_interrupt_pend_set(uint32_t ui32Interrupt); +extern void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt); +extern void am_hal_interrupt_priority_set(uint32_t ui32Interrupt, + uint32_t ui32Priority); +extern uint32_t am_hal_interrupt_master_disable(void); +extern uint32_t am_hal_interrupt_master_enable(void); +extern void am_hal_interrupt_master_set(uint32_t ui32InterruptState); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_INTERRUPT_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_iom.c b/mcu/apollo2/hal/am_hal_iom.c new file mode 100644 index 0000000..a6241a3 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_iom.c @@ -0,0 +1,5302 @@ +//***************************************************************************** +// +// am_hal_iom.c +//! @file +//! +//! @brief Functions for interfacing with the IO Master module +//! +//! @addtogroup iom2 IO Master (SPI/I2C) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __IAR_SYSTEMS_ICC__ +#define AM_INSTR_CLZ(n) __CLZ(n) +#else +#define AM_INSTR_CLZ(n) __builtin_clz(n) +#endif + +//! ASSERT(1) or Correct(0) invalid IOM R/W Thresholds. +#ifndef AM_ASSERT_INVALID_THRESHOLD +#define AM_ASSERT_INVALID_THRESHOLD (1) +#endif + +//***************************************************************************** +// +// Forward declarations. +// +//***************************************************************************** +static void iom_workaround_loop(uint32_t ui32PadRegVal, + volatile uint32_t *pui32PadReg, + bool bRising); +static uint32_t +internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation, + uint32_t ui32ChipSelect, + uint32_t ui32NumBytes, + uint32_t ui32Options); +static am_hal_iom_status_e +internal_iom_wait_i2c_scl_hi(uint32_t ui32Module); + +//***************************************************************************** +// +// IOM Buffer states. +// +//***************************************************************************** +#define BUFFER_IDLE 0x0 +#define BUFFER_SENDING 0x1 +#define BUFFER_RECEIVING 0x2 + +//***************************************************************************** +// +// Global state variables +// +//***************************************************************************** +// +// Define a structure to map CE for IOM4 only. +// +typedef struct +{ + uint8_t channel; // CE channel for SPI + uint8_t pad; // GPIO Pad + uint8_t funcsel; // FNCSEL value +} IOMPad_t; + +// Define the mapping between SPI CEn, Pads, and FNCSEL values for all IOMs. +const IOMPad_t g_IOMPads[] = +{ + {0, 29, 6}, {0, 34, 6}, {1, 18, 4}, {1, 37, 5}, {2, 41, 6}, + {3, 17, 4}, {3, 45, 4}, {4, 10, 6}, {4, 46, 6}, {5, 9, 4}, + {5, 47, 6}, {6, 35, 4}, {7, 38, 6} +}; + +typedef struct +{ + uint8_t module; // IOM module + uint8_t pad; // GPIO Pad + uint8_t funcsel; // FNCSEL value +} I2CPad_t; + +// Define the mapping between I2C SCL Pads, and FNCSEL values for all IOMs. +const I2CPad_t g_I2CPads[] = +{ + {0, 5, 0}, + {1, 8, 0}, + {2, 0, 7}, + {3, 42, 4}, + {4, 39, 4}, + {5, 48, 4}, + {2, 27, 4}, +}; + +// Defines for IOM 4 Workaround +#define WORKAROUND_IOM 4 +#define WORKAROUND_IOM_MOSI_PIN 44 +#define WORKAROUND_IOM_MOSI_CFG AM_HAL_PIN_44_M4MOSI + +#define MAX_IOM_BITS 9 +#define IOM_OVERHEAD_FACTOR 2 + +//***************************************************************************** +// +// Non-blocking buffer and buffer-management variables. +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32State; + uint32_t *pui32Data; + uint32_t ui32BytesLeft; + uint32_t ui32Options; + void (*pfnCallback)(void); +} +am_hal_iom_nb_buffer; + +// +// Global State to keep track if there is an ongoing transaction +// +volatile bool g_bIomBusy[AM_REG_IOMSTR_NUM_MODULES + 1] = {0}; + +am_hal_iom_nb_buffer g_psIOMBuffers[AM_REG_IOMSTR_NUM_MODULES]; + +// +// Save error status from non-blocking calls +// +static am_hal_iom_status_e g_iom_error_status[AM_REG_IOMSTR_NUM_MODULES + 1]; + +//***************************************************************************** +// +// Computed timeout. +// +// The IOM may not always respond to events (e.g., CMDCMP). This is a +// timeout value in cycles to be used when waiting on status changes. +//***************************************************************************** +uint32_t ui32StatusTimeout[AM_REG_IOMSTR_NUM_MODULES]; + +//***************************************************************************** +// +// Queue management variables. +// +//***************************************************************************** +am_hal_queue_t g_psIOMQueue[AM_REG_IOMSTR_NUM_MODULES]; + +//***************************************************************************** +// +// Default queue flush function +// +//***************************************************************************** +am_hal_iom_queue_flush_t am_hal_iom_queue_flush = am_hal_iom_sleeping_queue_flush; + +//***************************************************************************** +// +// Power management structure. +// +//***************************************************************************** +am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; + +//***************************************************************************** +// +// I2C BitBang to IOM error mapping +// +//***************************************************************************** +const am_hal_iom_status_e i2c_bb_errmap[AM_HAL_I2C_BIT_BANG_STATUS_MAX] = + { + AM_HAL_IOM_SUCCESS, // AM_HAL_I2C_BIT_BANG_SUCCESS, + AM_HAL_IOM_ERR_I2C_NAK, // AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED, + AM_HAL_IOM_ERR_I2C_NAK, // AM_HAL_I2C_BIT_BANG_DATA_NAKED, + AM_HAL_IOM_ERR_TIMEOUT, // AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT, + AM_HAL_IOM_ERR_TIMEOUT, // AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT, + }; + +//***************************************************************************** +// +// Static helper functions +// +//***************************************************************************** + +//***************************************************************************** +// +// Get the error interrupt staus +// +//***************************************************************************** +// +//! @brief Returns the error status based on interrupt bits +//! +//! @param ui32Module - IOM module +//! ui32Status - Currently accumulated error status +//! +//! The function looks at the supplied interrupt error status bits and the +//! the current INTSTAT and maps the same to the enum am_hal_iom_status_e. +//! +//! @return Returns the appropriate error status in the form of am_hal_iom_status_e +//! +//***************************************************************************** +static am_hal_iom_status_e +internal_iom_get_int_err(uint32_t ui32Module, uint32_t ui32IntStatus) +{ + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + // + // Let's accumulate the errors + // + ui32IntStatus |= am_hal_iom_int_status_get(ui32Module, false); + + if (ui32IntStatus & AM_HAL_IOM_INT_SWERR) + { + // Error in hardware command issued or illegal access by SW + ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_I2CARBERR) + { + // Loss of I2C multi-master arbitration + ui32Status = AM_HAL_IOM_ERR_I2C_ARB; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_NAK) + { + // I2C NAK + ui32Status = AM_HAL_IOM_ERR_I2C_NAK; + } + return ui32Status; +} + +//***************************************************************************** +// onebit() +//***************************************************************************** +// +// A power of 2? +// Return true if ui32Value has exactly 1 bit set, otherwise false. +// +static bool onebit(uint32_t ui32Value) +{ + return ui32Value && !(ui32Value & (ui32Value - 1)); +} + +//***************************************************************************** +// compute_freq() +//***************************************************************************** +// +// Compute the interface frequency based on the given parameters +// +static uint32_t compute_freq(uint32_t ui32HFRCfreqHz, + uint32_t ui32Fsel, uint32_t ui32Div3, + uint32_t ui32DivEn, uint32_t ui32TotPer) +{ + uint32_t ui32Denomfinal, ui32ClkFreq; + + ui32Denomfinal = ((1 << (ui32Fsel - 1)) * (1 + ui32Div3 * 2) * (1 + ui32DivEn * (ui32TotPer))); + ui32ClkFreq = (ui32HFRCfreqHz) / ui32Denomfinal; // Compute the set frequency value + ui32ClkFreq += (((ui32HFRCfreqHz) % ui32Denomfinal) > (ui32Denomfinal / 2)) ? 1 : 0; + + return ui32ClkFreq; +} + +//***************************************************************************** +// iom_calc_gpio() +// +// Calculate the IOM4 GPIO to assert. +// +//***************************************************************************** +static uint32_t iom_calc_gpio(uint32_t ui32ChipSelect) +{ + uint32_t index; + uint8_t ui8PadRegVal, ui8FncSelVal; + + // + // Figure out which GPIO we are using for the IOM + // + for ( index = 0; index < (sizeof(g_IOMPads) / sizeof(IOMPad_t)); index++ ) + { + // + // Is this one of the CEn that we are using? + // + if ( g_IOMPads[index].channel == ui32ChipSelect ) + { + // + // Get the PAD register value + // + ui8PadRegVal = ((AM_REGVAL(AM_HAL_GPIO_PADREG(g_IOMPads[index].pad))) & + AM_HAL_GPIO_PADREG_M(g_IOMPads[index].pad)) >> + AM_HAL_GPIO_PADREG_S(g_IOMPads[index].pad); + + // + // Get the FNCSEL field value + // + ui8FncSelVal = (ui8PadRegVal & 0x38) >> 3; + + // + // Is the FNCSEL filed for this pad set to the expected value? + // + if ( ui8FncSelVal == g_IOMPads[index].funcsel ) + { + // This is the GPIO we need to use. + return g_IOMPads[index].pad; + } + } + } + return 0xDEADBEEF; +} + +//***************************************************************************** +// +// Checks to see if this processor is a Rev B0 device. +// +// This is needed for the B0 IOM workaround. +// +//***************************************************************************** +bool +isRevB0(void) +{ + // + // Check to make sure the major rev is B and the minor rev is zero. + // + if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// +// Checks to see if this processor is a Rev B2 device. +// +// This is needed for the B2 I2C workaround. +// +//***************************************************************************** +static bool +isRevB2(void) +{ + // + // Check to make sure the major rev is B and the minor rev is zero. + // + if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == + (AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2) ) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// +// Checks and waits for the SCL line to be high +// This is to ensure clock hi time specs are not violated in case slave did +// clock stretching in previous transaction +// +//***************************************************************************** +static am_hal_iom_status_e +internal_iom_wait_i2c_scl_hi(uint32_t ui32Module) +{ + uint32_t ui32IOMGPIO = 0xDEADBEEF; + volatile uint32_t *pui32SCLPadreg; + uint32_t ui32SCLPadregVal; + uint32_t index; + uint8_t ui8PadRegVal; + uint8_t ui8FncSelVal; + uint32_t waitStatus; + + // Need to change the SCL pin as a GPIO and poll till it is set to hi + // For all the IOM's except for IOM2, there is a single designated pin for SCL + // IOM2 has two choices and we need to determine which one + + // + // Figure out which GPIO we are using for the SCL + // + for ( index = 0; index < (sizeof(g_I2CPads) / sizeof(I2CPad_t)); index++ ) + { + // + // Is this for the IOM that we are using? + // + if ( g_I2CPads[index].module == ui32Module ) + { + // + // Get the PAD register value + // + ui8PadRegVal = ((AM_REGVAL(AM_HAL_GPIO_PADREG(g_I2CPads[index].pad))) & + AM_HAL_GPIO_PADREG_M(g_I2CPads[index].pad)) >> + AM_HAL_GPIO_PADREG_S(g_I2CPads[index].pad); + + // + // Get the FNCSEL field value + // + ui8FncSelVal = (ui8PadRegVal & 0x38) >> 3; + + // + // Is the FNCSEL filed for this pad set to the expected value? + // + if ( ui8FncSelVal == g_I2CPads[index].funcsel ) + { + // This is the GPIO we need to use. + ui32IOMGPIO = g_I2CPads[index].pad; + break; + } + } + } + if (0xDEADBEEF == ui32IOMGPIO) + { + // SCL has not been configured + return AM_HAL_IOM_ERR_INVALID_CFG; + } + + // + // Save the locations and values of the SCL pin configuration + // information. + // + pui32SCLPadreg = (volatile uint32_t *)AM_HAL_GPIO_PADREG(ui32IOMGPIO); + ui32SCLPadregVal = *pui32SCLPadreg; + // + // Temporarily configure the override pin as an input. + // + am_hal_gpio_pin_config(ui32IOMGPIO, AM_HAL_PIN_INPUT); + + // + // Make sure SCL is high within standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_HAL_GPIO_RD_REG(ui32IOMGPIO), AM_HAL_GPIO_RD_M(ui32IOMGPIO), + AM_HAL_GPIO_RD_M(ui32IOMGPIO)); + + // + // Write the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; + // Revert back the original settings + *pui32SCLPadreg = ui32SCLPadregVal; + // + // Re-lock the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = 0; + + if (waitStatus != 1) + { + return AM_HAL_IOM_ERR_TIMEOUT; + } + + return AM_HAL_IOM_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Returns the proper settings for the CLKCFG register. +//! +//! @param ui32FreqHz - The desired interface frequency in Hz. +//! ui32Phase - SPI phase (0 or 1). Can affect duty cycle. +//! +//! Given a desired serial interface clock frequency, this function computes +//! the appropriate settings for the various fields in the CLKCFG register +//! and returns the 32-bit value that should be written to that register. +//! The actual interface frequency may be slightly lower than the specified +//! frequency, but the actual frequency is also returned. +//! +//! @note A couple of criteria that this algorithm follow are: +//! 1. For power savings, choose the highest FSEL possible. +//! 2. For best duty cycle, use DIV3 when possible rather than DIVEN. +//! +//! An example of #1 is that both of the following CLKCFGs would result +//! in a frequency of 428,571 Hz: 0x0E071400 and 0x1C0E1300. +//! The former is chosen by the algorithm because it results in FSEL=4 +//! while the latter is FSEL=3. +//! +//! An example of #2 is that both of the following CLKCFGs would result +//! in a frequency of 2,000,000 Hz: 0x02011400 and 0x00000C00. +//! The latter is chosen by the algorithm because it results in use of DIV3 +//! rather than DIVEN. +//! +//! @return An unsigned 64-bit value. +//! The lower 32-bits represent the value to use to set CLKCFG. +//! The upper 32-bits represent the actual frequency (in Hz) that will result +//! from setting CLKCFG with the lower 32-bits. +//! +//! 0 (64 bits) = error. Note that the caller must check the entire 64 bits. +//! It is not an error if only the low 32-bits are 0 (this is a valid value). +//! But the entire 64 bits returning 0 is an error. +//! +//***************************************************************************** + +static +uint64_t iom_get_interface_clock_cfg(uint32_t ui32FreqHz, uint32_t ui32Phase ) +{ + uint32_t ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer, ui32LowPer; + uint32_t ui32Denom, ui32v1, ui32Denomfinal, ui32ClkFreq, ui32ClkCfg; + uint32_t ui32HFRCfreqHz; + int32_t i32Div, i32N; + + if ( ui32FreqHz == 0 ) + { + return 0; + } + + // + // Set the HFRC clock frequency. + // + ui32HFRCfreqHz = AM_HAL_CLKGEN_FREQ_MAX_HZ; + + // + // Compute various parameters used for computing the optimal CLKCFG setting. + // + i32Div = (ui32HFRCfreqHz / ui32FreqHz) + ((ui32HFRCfreqHz % ui32FreqHz) ? 1 : 0); // Round up (ceiling) + + // + // Compute N (count the number of LS zeros of Div) = ctz(Div) = log2(Div & (-Div)) + // + i32N = 31 - AM_INSTR_CLZ((i32Div & (-i32Div))); + + if ( i32N > 6 ) + { + i32N = 6; + } + + ui32Div3 = ( (ui32FreqHz < (ui32HFRCfreqHz / 16384)) || + ( ((ui32FreqHz >= (ui32HFRCfreqHz / 3)) && + (ui32FreqHz <= ((ui32HFRCfreqHz / 2) - 1)) ) ) ) ? 1 : 0; + ui32Denom = ( 1 << i32N ) * ( 1 + (ui32Div3 * 2) ); + ui32TotPer = i32Div / ui32Denom; + ui32TotPer += (i32Div % ui32Denom) ? 1 : 0; + ui32v1 = 31 - AM_INSTR_CLZ(ui32TotPer); // v1 = log2(TotPer) + ui32Fsel = (ui32v1 > 7) ? ui32v1 + i32N - 7 : i32N; + ui32Fsel++; + + if ( ui32Fsel > 7 ) + { + // + // This is an error, can't go that low. + // + return 0; + } + + if ( ui32v1 > 7 ) + { + ui32DivEn = ui32TotPer; // Save TotPer for the round up calculation + ui32TotPer = ui32TotPer>>(ui32v1-7); + ui32TotPer += ((ui32DivEn) % (1 << (ui32v1 - 7))) ? 1 : 0; + } + + ui32DivEn = ( (ui32FreqHz >= (ui32HFRCfreqHz / 4)) || + ((1 << (ui32Fsel - 1)) == i32Div) ) ? 0 : 1; + + if (ui32Phase == 1) + { + ui32LowPer = (ui32TotPer - 2) / 2; // Longer high phase + } + else + { + ui32LowPer = (ui32TotPer - 1) / 2; // Longer low phase + } + + ui32ClkCfg = AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel) | + AM_REG_IOMSTR_CLKCFG_DIV3(ui32Div3) | + AM_REG_IOMSTR_CLKCFG_DIVEN(ui32DivEn) | + AM_REG_IOMSTR_CLKCFG_LOWPER(ui32LowPer) | + AM_REG_IOMSTR_CLKCFG_TOTPER(ui32TotPer - 1); + + + // + // Now, compute the actual frequency, which will be returned. + // + ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer - 1); + + // + // Determine if the actual frequency is a power of 2 (MHz). + // + if ( (ui32ClkFreq % 250000) == 0 ) + { + // + // If the actual clock frequency is a power of 2 ranging from 250KHz up, + // we can simplify the CLKCFG value using DIV3 (which also results in a + // better duty cycle). + // + ui32Denomfinal = ui32ClkFreq / (uint32_t)250000; + + if ( onebit(ui32Denomfinal) ) + { + // + // These configurations can be simplified by using DIV3. Configs + // using DIV3 have a 50% duty cycle, while those from DIVEN will + // have a 66/33 duty cycle. + // + ui32TotPer = ui32LowPer = ui32DivEn = 0; + ui32Div3 = 1; + + // + // Now, compute the return values. + // + ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer); + + ui32ClkCfg = AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel) | + AM_REG_IOMSTR_CLKCFG_DIV3(1) | + AM_REG_IOMSTR_CLKCFG_DIVEN(0) | + AM_REG_IOMSTR_CLKCFG_LOWPER(0) | + AM_REG_IOMSTR_CLKCFG_TOTPER(0); + } + } + + return ( ((uint64_t)ui32ClkFreq) << 32) | (uint64_t)ui32ClkCfg; + +} //iom_get_interface_clock_cfg() + + +//***************************************************************************** +// +//! @brief Clock setting for the I2C Clock Stretch Workaround +//! +//! This restricts the frequencies that can be used for I2C devices on +//! +//! @param ui32FreqHz - The desired interface frequency in Hz. +//! +//! @return None. +// +//***************************************************************************** +static +uint64_t iom_get_i2c_workaround_clock_cfg(uint32_t ui32FreqHz) +{ + uint32_t ui32Fsel; + + // Only allow certain SCL frequencies for clock stretching devices. + if (ui32FreqHz == AM_HAL_IOM_800KHZ) + { + ui32Fsel = 2; + } + else if (ui32FreqHz == AM_HAL_IOM_400KHZ) + { + ui32Fsel = 3; + } + else if (ui32FreqHz == AM_HAL_IOM_200KHZ) + { + ui32Fsel = 4; + } + else if (ui32FreqHz == AM_HAL_IOM_100KHZ) + { + ui32Fsel = 5; + } + else // Default is 100KHz. + { + ui32Fsel = 5; + } + + // Return the resulting CLKCFG register settings. + return (AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel) | + AM_REG_IOMSTR_CLKCFG_DIV3(0) | + AM_REG_IOMSTR_CLKCFG_DIVEN(1) | + AM_REG_IOMSTR_CLKCFG_LOWPER(14) | + AM_REG_IOMSTR_CLKCFG_TOTPER(29)); + +} // iom_get_i2c_workaround_clock_cfg + +//***************************************************************************** +// +//! @brief Enable the IOM in the power control block. +//! +//! This function enables the desigated IOM module in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_pwrctrl_enable(uint32_t ui32Module) +{ + am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, + "Trying to enable an IOM module that doesn't exist."); + + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOM0 << ui32Module); +} + +//***************************************************************************** +// +//! @brief Disable the IOM in the power control block. +//! +//! This function disables the desigated IOM module in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_pwrctrl_disable(uint32_t ui32Module) +{ + am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, + "Trying to disable an IOM module that doesn't exist."); + + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_IOM0 << ui32Module); +} + +//***************************************************************************** +// +//! @brief Enables the IOM module +//! +//! @param ui32Module - The number of the IOM module to be enabled. +//! +//! This function enables the IOM module using the IFCEN bitfield in the +//! IOMSTR_CFG register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_enable(uint32_t ui32Module) +{ + if ( ui32Module < AM_REG_IOMSTR_NUM_MODULES ) + { + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_IFCEN(1); + g_bIomBusy[ui32Module] = false; + } +} + +//***************************************************************************** +// +//! @brief Disables the IOM module. +//! +//! @param ui32Module - The number of the IOM module to be disabled. +//! +//! This function disables the IOM module using the IFCEN bitfield in the +//! IOMSTR_CFG register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_disable(uint32_t ui32Module) +{ + if ( ui32Module < AM_REG_IOMSTR_NUM_MODULES ) + { + // + // Wait until the bus is idle. + // + am_hal_iom_poll_complete(ui32Module); + + // + // Disable the interface. + // + AM_REGn(IOMSTR, ui32Module, CFG) &= ~(AM_REG_IOMSTR_CFG_IFCEN(1)); + } +} + +//***************************************************************************** +// +//! @brief Enable power to the selected IOM module. +//! +//! @param ui32Module - Module number for the IOM to be turned on. +//! +//! This function enables the power gate to the selected IOM module. It is +//! intended to be used along with am_hal_iom_power_off_save(). Used together, +//! these functions allow the caller to power IOM modules off to save +//! additional power without losing important configuration information. +//! +//! The am_hal_iom_power_off_save() function will save IOM configuration +//! register information to SRAM before powering off the selected IOM module. +//! This function will re-enable the IOM module, and restore those +//! configuration settings from SRAM. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_power_on_restore(uint32_t ui32Module) +{ + am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, + "Trying to enable an IOM module that doesn't exist."); + if (ui32Module >= AM_REG_IOMSTR_NUM_MODULES) // Guarantee index is in range (no overrun) + { + return; + } + // + // Make sure this restore is a companion to a previous save call. + // + if ( am_hal_iom_pwrsave[ui32Module].bValid == 0 ) + { + return; + } + + // + // Enable power to the selected IOM. + // + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOM0 << ui32Module); + + // + // Restore the IOM configuration registers from the structure in SRAM. + // + AM_REGn(IOMSTR, ui32Module, FIFOTHR) = am_hal_iom_pwrsave[ui32Module].FIFOTHR; + AM_REGn(IOMSTR, ui32Module, CLKCFG) = am_hal_iom_pwrsave[ui32Module].CLKCFG; + AM_REGn(IOMSTR, ui32Module, CFG) = am_hal_iom_pwrsave[ui32Module].CFG; + AM_REGn(IOMSTR, ui32Module, INTEN) = am_hal_iom_pwrsave[ui32Module].INTEN; + + // + // Indicates we have restored the configuration. + // + am_hal_iom_pwrsave[ui32Module].bValid = 0; +} + +//***************************************************************************** +// +//! @brief Disable power to the selected IOM module. +//! +//! @param ui32Module - Module number for the IOM to be turned off. +//! +//! This function disables the power gate to the selected IOM module. It is +//! intended to be used along with am_hal_iom_power_on_restore(). Used together, +//! these functions allow the caller to power IOM modules off to save +//! additional power without losing important configuration information. +//! +//! The am_hal_iom_power_off_save() function will save IOM configuration +//! register information to SRAM before powering off the selected IOM module. +//! The am_hal_iom_power_on_restore() function will re-enable the IOM module +//! and restore those configuration settings from SRAM. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_power_off_save(uint32_t ui32Module) +{ + am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, + "Trying to disable an IOM module that doesn't exist."); + + // + // Save the IOM configuration registers to the structure in SRAM. + // + am_hal_iom_pwrsave[ui32Module].FIFOTHR = AM_REGn(IOMSTR, ui32Module, FIFOTHR); + am_hal_iom_pwrsave[ui32Module].CLKCFG = AM_REGn(IOMSTR, ui32Module, CLKCFG); + am_hal_iom_pwrsave[ui32Module].CFG = AM_REGn(IOMSTR, ui32Module, CFG); + am_hal_iom_pwrsave[ui32Module].INTEN = AM_REGn(IOMSTR, ui32Module, INTEN); + + // + // Indicates we have a valid saved configuration. + // + am_hal_iom_pwrsave[ui32Module].bValid = 1; + + // + // Disable power to the selected IOM. + // + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_IOM0 << ui32Module); +} + +// +//! Check and correct the IOM FIFO threshold. +// +#define MAX_RW_THRESHOLD (AM_HAL_IOM_MAX_FIFO_SIZE - 4) +#define MIN_RW_THRESHOLD (4) +#if (AM_ASSERT_INVALID_THRESHOLD == 0) +static uint8_t check_iom_threshold(const uint8_t iom_threshold) +{ + uint8_t corrected_threshold = iom_threshold; + + if ( corrected_threshold < MIN_RW_THRESHOLD ) + { + corrected_threshold = MIN_RW_THRESHOLD; + } + + if ( corrected_threshold > MAX_RW_THRESHOLD ) + { + corrected_threshold = MAX_RW_THRESHOLD; + } + + return corrected_threshold; +} +#endif + +//***************************************************************************** +// +//! @brief Sets module-wide configuration options for the IOM module. +//! +//! @param ui32Module - The instance number for the module to be configured +//! (zero or one) +//! +//! @param psConfig - Pointer to an IOM configuration structure. +//! +//! This function is used to set the interface mode (SPI or I2C), clock +//! frequency, SPI format (when relevant), and FIFO read/write interrupt +//! thresholds for the IO master. For more information on specific +//! configuration options, please see the documentation for the configuration +//! structure. +//! +//! @note The IOM module should be disabled before configuring or +//! re-configuring. This function will not re-enable the module when it +//! completes. Call the am_hal_iom_enable function when the module is +//! configured and ready to use. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_config(uint32_t ui32Module, const am_hal_iom_config_t *psConfig) +{ + uint32_t ui32Config, ui32ClkCfg; + uint32_t ui32HFRC; + + // + // Start by checking the interface mode (I2C or SPI), and writing it to the + // configuration word. + // + ui32Config = psConfig->ui32InterfaceMode; + + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + // + // Check the SPI format, and OR in the bits for SPHA (clock phase) and SPOL + // (polarity). These shouldn't have any effect in I2C mode, so it should be + // ok to write them without checking exactly which mode we're in. + // + if ( psConfig->bSPHA ) + { + ui32Config |= AM_REG_IOMSTR_CFG_SPHA(1); + } + + if ( psConfig->bSPOL ) + { + ui32Config |= AM_REG_IOMSTR_CFG_SPOL(1); + } + + // Set the STARTRD based on the interface speed + // For all I2C frequencies and SPI frequencies below 16 MHz, the STARTRD + // field should be set to 0 to minimize the potential of the IO transfer + // holding off a bus access to the FIFO. For SPI frequencies of 16 MHz + // or 24 MHz, the STARTRD field must be set to a value of 2 to insure + // enough time for the IO preread. + if ( psConfig->ui32ClockFrequency >= 16000000UL) + { + ui32Config |= AM_REG_IOMSTR_CFG_STARTRD(2); + } + + // + // Write the resulting configuration word to the IO master CFG register for + // the module number we were provided. + // + AM_REGn(IOMSTR, ui32Module, CFG) = ui32Config; + + // + // Write the FIFO write and read thresholds to the appropriate registers. + // +#if (AM_ASSERT_INVALID_THRESHOLD == 1) + am_hal_debug_assert_msg( + (psConfig->ui8WriteThreshold <= MAX_RW_THRESHOLD), "IOM write threshold too big."); + am_hal_debug_assert_msg( + (psConfig->ui8ReadThreshold <= MAX_RW_THRESHOLD), "IOM read threshold too big."); + am_hal_debug_assert_msg( + (psConfig->ui8WriteThreshold >= MIN_RW_THRESHOLD), "IOM write threshold too small."); + am_hal_debug_assert_msg( + (psConfig->ui8ReadThreshold >= MIN_RW_THRESHOLD), "IOM read threshold too small."); + + AM_REGn(IOMSTR, ui32Module, FIFOTHR) = + (AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(psConfig->ui8WriteThreshold) | + AM_REG_IOMSTR_FIFOTHR_FIFORTHR(psConfig->ui8ReadThreshold)); +#elif (AM_ASSERT_INVALID_THRESHOLD == 0) + AM_REGn(IOMSTR, ui32Module, FIFOTHR) = + (AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(check_iom_threshold(psConfig->ui8WriteThreshold)) | + AM_REG_IOMSTR_FIFOTHR_FIFORTHR(check_iom_threshold(psConfig->ui8ReadThreshold))); +#else +#error AM_ASSERT_INVALID_THRESHOLD must be 0 or 1. +#endif + + // + // Apply I2C clock stretching workaround if B2 silicon and IOM 1,2,3, or 5 + // Note: Only I2C clock speeds of AM_HAL_IOM_800KHZ, AM_HAL_IOM_400KHZ, + // AM_HAL_IOM_200KHZ, and AM_HAL_IOM_100KHZ are allowed. Other values will + // result in the default of AM_HAL_IOM_100KHZ. + // + if ((0 != ui32Module) && (4 != ui32Module) && (6 != ui32Module) && + isRevB2() && (AM_HAL_IOM_I2CMODE == psConfig->ui32InterfaceMode)) + { + // Set SPHA field to 1 on B2 silicon to enable the feature; + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_SPHA_M; + ui32ClkCfg = iom_get_i2c_workaround_clock_cfg(psConfig->ui32ClockFrequency); + } + else + { + // + // An exception occurs in the LOWPER computation when setting an interface + // frequency (such as a divide by 5 frequency) which results in a 60/40 + // duty cycle. The 60% cycle must occur in the appropriate half-period, + // as only one of the half-periods is active, depending on which phase + // is being selected. + // If SPHA=0 the low period must be 60%. If SPHA=1 high period must be 60%. + // Note that the predetermined frequency parameters use the formula + // lowper = (totper-1)/2, which results in a 60% low period. + // + ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency, + psConfig->bSPHA ); + } + + if ( ui32ClkCfg ) + { + AM_REGn(IOMSTR, ui32Module, CLKCFG) = (uint32_t)ui32ClkCfg; + } + + // + // Compute the status timeout value. + // + ui32HFRC = am_hal_clkgen_sysclk_get(); + ui32StatusTimeout[ui32Module] = MAX_IOM_BITS * AM_HAL_IOM_MAX_FIFO_SIZE * + IOM_OVERHEAD_FACTOR * (ui32HFRC / psConfig->ui32ClockFrequency); +} + +//***************************************************************************** +// +//! @brief Returns the actual currently configured interface frequency in Hz. +// +//***************************************************************************** +uint32_t +am_hal_iom_frequency_get(uint32_t ui32ClkCfg) +{ + uint32_t ui32Freq; + + ui32Freq = compute_freq(AM_HAL_CLKGEN_FREQ_MAX_HZ, + (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_FSEL_M) >> AM_REG_IOMSTR_CLKCFG_FSEL_S, + (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_DIV3_M) >> AM_REG_IOMSTR_CLKCFG_DIV3_S, + (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_DIVEN_M) >> AM_REG_IOMSTR_CLKCFG_DIVEN_S, + (ui32ClkCfg & AM_REG_IOMSTR_CLKCFG_TOTPER_M)>> AM_REG_IOMSTR_CLKCFG_TOTPER_S); + + return ui32Freq; +} + +//***************************************************************************** +// +// Helper function for the B0 workaround. +// +//***************************************************************************** +static uint32_t +iom_get_workaround_fsel(uint32_t maxFreq) +{ + uint32_t ui32Freq, ui32Fsel; + uint32_t ui32ClkCfg = AM_REGn(IOMSTR, 4, CLKCFG); + + // + // Starting with the current clock configuration parameters, find a value + // of FSEL that will bring our total frequency down to or below maxFreq. + // + for ( ui32Fsel = 1; ui32Fsel < 8; ui32Fsel++ ) + { + ui32Freq = compute_freq(AM_HAL_CLKGEN_FREQ_MAX_HZ, ui32Fsel, + AM_BFX(IOMSTR, CLKCFG, DIV3, ui32ClkCfg), + AM_BFX(IOMSTR, CLKCFG, DIVEN, ui32ClkCfg), + AM_BFX(IOMSTR, CLKCFG, TOTPER, ui32ClkCfg)); + + if ( ui32Freq <= maxFreq && ui32Freq != 0 ) + { + // + // Return the new FSEL + // + return ui32Fsel; + } + } + + // + // Couldn't find an appropriate frequency. This should be impossible + // because there should always be a value of FSEL that brings the final IOM + // frequency below 500 KHz. + // + am_hal_debug_assert_msg(false, "Could find a valid frequency. Should never get here."); + return maxFreq; +} + +// Separating this piece of code in separate function to keep the impact of +// rest of the code to mimimal because of stack usage +static void +internal_iom_workaround_critical(uint32_t ui32Command, + volatile uint32_t *pui32CSPadreg, + uint32_t ui32CSPadregVal, + uint32_t ui32DelayTime, + uint32_t ui32ClkCfg, + uint32_t ui32LowClkCfg, + bool bRising) +{ + uint32_t ui32Critical = 0; + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Start the write on the bus. + // + AM_REGn(IOMSTR, WORKAROUND_IOM, CMD) = ui32Command; + + // + // Slow down the clock, and run the workaround loop. The workaround + // loop runs an edge-detector on MOSI, and triggers a falling edge on + // chip-enable on the first bit of our real data. + // + ((void (*)(uint32_t)) 0x0800009d)(ui32DelayTime); + // Switch to Low Freq + AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG) = ui32LowClkCfg; + iom_workaround_loop(ui32CSPadregVal, pui32CSPadreg, bRising); + // + // Restore the clock frequency and the normal MOSI pin function. + // + AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG) = ui32ClkCfg; + am_hal_gpio_pin_config(WORKAROUND_IOM_MOSI_PIN, WORKAROUND_IOM_MOSI_CFG); + + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); +} + + +//***************************************************************************** +// +//! @brief Workaround for an Apollo2 Rev B0 issue. +//! +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! Some Apollo2 Rev B0 devices have an issue where the first byte of a SPI +//! write transaction can have some of its bits changed from ones to zeroes. In +//! order to get around this issue, we artificially pad the SPI write data with +//! additional bytes, and manually control the CS pin for the beginning of the +//! SPI frame so that the receiving device will ignore the bytes of padding +//! that we added. +//! +//! This function acts as a helper function to higher-level spi APIs. It +//! performs the functions of am_hal_iom_fifo_write() and +//! am_hal_iom_spi_cmd_run() to get a SPI write started on the bus, including +//! all of the necessary workaround behavior. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_workaround_word_write(uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32TransferSize; + uint32_t ui32IOMGPIO = 0xDEADBEEF; + volatile uint32_t *pui32CSPadreg = 0; + uint32_t ui32CSPadregVal = 0; + uint32_t ui32ClkCfg = 0; + uint32_t ui32HiClkCfg, ui32LowClkCfg; + bool bRising = 0; + uint32_t ui32HiFreq = 0, ui32NormalFreq = 0; + uint32_t ui32DelayTime = 0; + uint32_t ui32LowFsel = 0; + uint32_t ui32HiFsel = 0; + uint32_t ui32FirstWord = 0; + uint32_t ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, WORKAROUND_IOM, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + uint32_t ui32Command; + // + // Make sure the transfer isn't too long for the hardware to support. + // + // Note: This is a little shorter than usual, since the workaround + // consumes an extra byte at the beginning of the transfer. + // + am_hal_debug_assert_msg(ui32NumBytes <= 4091, "SPI transfer too big."); + + // + // Create a "dummy" word to add on to the beginning of the transfer + // that will guarantee a transition between the first word and the + // second on the bus. + // + // For raw transactions, this is straightforward. For transactions + // preceded by an offset, we'll add the offset in to the "dummy" word + // to preserve data alignment later. + // + // The workaround uses a critical section for precision + // To minimize the time in critical section, we raise the SPI frequency + // to the max possible for the initial preamble to be clocked out + // then we switch to a 'reasonably' slow frequency to be able to reliably + // catch the rising or falling edge by polling. Then we switch back to + // configured frequency + // + + // We want to slow down the clock to help us count edges more + // accurately. Save it first, then slow it down. Also, we will + // pre-calculate a delay for when we need to restore the SPI settings. + // + ui32ClkCfg = AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG); + // Get the largest speed we can configure within our rated speed of 16MHz + ui32HiFsel = iom_get_workaround_fsel(16000000); + ui32HiClkCfg = ((ui32ClkCfg & (~AM_REG_IOMSTR_CLKCFG_FSEL_M)) | + AM_BFV(IOMSTR, CLKCFG, FSEL, ui32HiFsel)); + // Switch to Hi Freq + // Need to make sure we wait long enough for the hi clock to be effective + // Delay 2 cycles based on previous frequency + ui32NormalFreq = am_hal_iom_frequency_get(ui32ClkCfg); + AM_REGn(IOMSTR, WORKAROUND_IOM, CLKCFG) = ui32HiClkCfg; + ui32DelayTime = ((2 * AM_HAL_CLKGEN_FREQ_MAX_HZ) / (ui32NormalFreq * 3)); + ((void (*)(uint32_t)) 0x0800009d)(ui32DelayTime); + // + // Remember what frequency we'll be running at.during Hi Phase + // + ui32HiFreq = am_hal_iom_frequency_get(ui32HiClkCfg); + + // + // Validate return value to prevent DIVBY0 errors. + // + am_hal_debug_assert_msg(ui32HiFreq > 0, "Invalid Hi Frequency for IOM."); + if (0 == ui32HiFreq) + { + return; // Prevent DIV0 error below. + } + + // Get a reasonably slow speed (~1MHz) we can safely poll for the transition + ui32LowFsel = iom_get_workaround_fsel(1000000); + ui32LowClkCfg = ((ui32ClkCfg & (~AM_REG_IOMSTR_CLKCFG_FSEL_M)) | + AM_BFV(IOMSTR, CLKCFG, FSEL, ui32LowFsel)); + + if ( ui32Options & AM_HAL_IOM_RAW ) + { + // + // The transition we care for is on 33rd bit. + // Prepare to delay 27 bits past the start of the transaction + // before getting into polling - to leave some + // margin for compiler related variations + // + ui32DelayTime = ((27 * AM_HAL_CLKGEN_FREQ_MAX_HZ) / (ui32HiFreq * 3)); + + if ( pui32Data[0] & 0x80 ) + { + ui32FirstWord = 0x00000000; + bRising = true; + } + else + { + ui32FirstWord = 0xFFFFFF00; + bRising = false; + } + } + else + { + // + // The transition we care for is on 25th bit. + // Prepare to delay 19 bits past the start of the transaction + // before getting into polling - to leave some + // margin for compiler related variations + // + ui32DelayTime = ((19 * AM_HAL_CLKGEN_FREQ_MAX_HZ) / (ui32HiFreq * 3)); + ui32FirstWord = ((ui32Options & 0xFF00) << 16); + if ( ui32FirstWord & 0x80000000 ) + { + bRising = true; + } + else + { + ui32FirstWord |= 0x00FFFF00; + bRising = false; + } + } + + // + // Now that weve taken care of the offset byte, we can run the + // transaction in RAW mode. + // + ui32Options |= AM_HAL_IOM_RAW; + + ui32NumBytes += 4; + + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + + am_hal_iom_fifo_write(WORKAROUND_IOM, &ui32FirstWord, 4); + + am_hal_iom_fifo_write(WORKAROUND_IOM, pui32Data, ui32TransferSize - 4); + + // + // Calculate the GPIO to be controlled until the initial shift is + // complete. Make sure we get a valid value. + // + ui32IOMGPIO = iom_calc_gpio(ui32ChipSelect); + am_hal_debug_assert(0xDEADBEEF != ui32IOMGPIO); + + // + // Save the locations and values of the CS pin configuration + // information. + // + pui32CSPadreg = (volatile uint32_t *)AM_HAL_GPIO_PADREG(ui32IOMGPIO); + ui32CSPadregVal = *pui32CSPadreg; + + // + // Switch CS to a GPIO. + // + am_hal_gpio_out_bit_set(ui32IOMGPIO); + am_hal_gpio_pin_config(ui32IOMGPIO, AM_HAL_GPIO_OUTPUT); + + // + // Enable the input buffer on MOSI. + // + am_hal_gpio_pin_config(WORKAROUND_IOM_MOSI_PIN, WORKAROUND_IOM_MOSI_CFG | AM_HAL_PIN_DIR_INPUT); + + // + // Write the GPIO PADKEY register to allow the workaround loop to + // reconfigure chip enable. + // + AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; + // Preconstruct the command - to save on calculations inside critical section + ui32Command = internal_am_hal_iom_spi_cmd_construct(AM_HAL_IOM_WRITE, + ui32ChipSelect, ui32NumBytes, ui32Options); + internal_iom_workaround_critical(ui32Command, + pui32CSPadreg, ui32CSPadregVal, + ui32DelayTime, ui32ClkCfg, + ui32LowClkCfg, bRising); + // + // Re-lock the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = 0; + + // + // Update the pointer and data counter. + // + ui32NumBytes -= ui32TransferSize; + pui32Data += (ui32TransferSize - 4) >> 2; +} + +//***************************************************************************** +// +//! @brief Implement an iterative spin loop. +//! +//! @param ui32Iterations - Number of iterations to delay. +//! +//! Use this function to implement a CPU busy waiting spin. For Apollo, this +//! delay can be used for timing purposes since for Apollo, each iteration will +//! take 3 cycles. +//! +//! @return None. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm static void +iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, + bool bRising) +{ + // + // Check to see if this is a "rising edge" or "falling edge" detector. + // + cbz r2, falling_edge + + // + // Read GPIO pin 44, and loop until it's HIGH. + // +rising_edge + ldr r2, =0x40010084 +rising_check_mosi + ldr r3, [r2] + ands r3, r3, #0x1000 + beq rising_check_mosi + + // + // Write the PADREG Value to the PADREG register. + // + str r0, [r1] + bx lr + + // + // Read GPIO pin 44, and loop until it's LOW. + // +falling_edge + ldr r2, =0x40010084 +falling_check_mosi + ldr r3, [r2] + ands r3, r3, #0x1000 + bne falling_check_mosi + + // + // Write the PADREG Value to the PADREG register. + // + str r0, [r1] + bx lr + nop +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +static void +iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, + bool bRising) +{ + // + // Check to see if this is a "rising edge" or "falling edge" detector. + // + __asm( + " cbz %[bRising], falling_edge\n" + // + // Read GPIO pin 44, and loop until it's HIGH. + // + "rising_edge:\n" + " ldr r2, =0x40010084\n" + "rising_check_mosi:\n" + " ldr r3, [r2]\n" + " ands r3, r3, #0x1000\n" + " beq rising_check_mosi\n" + + // + // Write the PADREG Value to the PADREG register. + // + " str %[ui32PadRegVal], [%[pui32PadReg]]\n" + " bx lr\n" + + // + // Read GPIO pin 44, and loop until it's LOW. + // + "falling_edge:\n" + " ldr r2, =0x40010084\n" + "falling_check_mosi:\n" + " ldr r3, [r2]\n" + " ands r3, r3, #0x1000\n" + " bne falling_check_mosi\n" + + // + // Write the PADREG Value to the PADREG register. + // + " str %[ui32PadRegVal], [%[pui32PadReg]]\n" + " bx lr\n" + : + : [ui32PadRegVal] "r" (ui32PadRegVal), + [pui32PadReg] "r" (&pui32PadReg[0]), + [bRising] "r" (bRising) + : "r0", "r1", "r2", "r3", "r5", "r7" + ); +} +#elif defined(__GNUC_STDC_INLINE__) +static void __attribute__((naked)) +iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, + bool bRising) +{ + // + // Check to see if this is a "rising edge" or "falling edge" detector. + // + __asm(" cbz r2, falling_edge"); + + // + // Read GPIO pin 44, and loop until it's HIGH. + // + __asm("rising_edge:"); + __asm(" ldr r2, =0x40010084"); + __asm("rising_check_mosi:"); + __asm(" ldr r3, [r2]"); + __asm(" ands r3, r3, #0x1000"); + __asm(" beq rising_check_mosi"); + + // + // Write the PADREG Value to the PADREG register. + // + __asm(" str r0, [r1]"); + __asm(" bx lr"); + + // + // Read GPIO pin 44, and loop until it's LOW. + // + __asm("falling_edge:"); + __asm(" ldr r2, =0x40010084"); + __asm("falling_check_mosi:"); + __asm(" ldr r3, [r2]"); + __asm(" ands r3, r3, #0x1000"); + __asm(" bne falling_check_mosi"); + + // + // Write the PADREG Value to the PADREG register. + // + __asm(" str r0, [r1]"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +static void +iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, + bool bRising) +{ + // + // Check to see if this is a "rising edge" or "falling edge" detector. + // + __asm( + " cbz r2, falling_edge\n" + + // + // Read GPIO pin 44, and loop until it's HIGH. + // + "rising_edge:\n" + " mov32 r2, #0x40010084\n" + "rising_check_mosi:\n" + " ldr r3, [r2]\n" + " ands r3, r3, #0x1000\n" + " beq rising_check_mosi\n" + + // + // Write the PADREG Value to the PADREG register. + // + " str r0, [r1]\n" + " bx lr\n" + + // + // Read GPIO pin 44, and loop until it's LOW. + // + "falling_edge:\n" + " mov32 r2, #0x40010084\n" + "falling_check_mosi:\n" + " ldr r3, [r2]\n" + " ands r3, r3, #0x1000\n" + " bne falling_check_mosi\n" + + // + // Write the PADREG Value to the PADREG register. + // + " str r0, [r1]\n" + " bx lr" + ); +} +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Perform a simple write to the SPI interface. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI writes to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { + // + // Otherwise, we'll just do a polled transaction. + // + ui32Status = am_hal_iom_spi_write_nq(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options); + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform simple SPI read operations. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs simple SPI read operations. The caller is +//! responsible for ensuring that the receive buffer is large enough to hold +//! the requested amount of data. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_spi_read(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { + // + // Otherwise, just perform a polled transaction. + // + ui32Status = am_hal_iom_spi_read_nq(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options); + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex transaction to the SPI interface. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32TxData - Pointer to the bytes that will be sent. +//! @param pui32RxData - Pointer to the bytes that will be received. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Full-Duplex operation is only supported for Apollo2 B2 Silicon. + // + if (!isRevB2()) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // +#if 0 + + // To be implemented!!! + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { +#endif + // + // Otherwise, we'll just do a polled transaction. + // + ui32Status = am_hal_iom_spi_fullduplex_nq(ui32Module, ui32ChipSelect, + pui32TxData, pui32RxData, + ui32NumBytes, ui32Options); +#if 0 + } +#endif + + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a simple write to the SPI interface (without queuing) +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI writes to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32TransferSize; + uint32_t ui32SpaceInFifo; + uint32_t ui32IntConfig; + uint32_t ui32MaxFifoSize; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // If we're on a B0 part, and we're using IOM4, our first byte coule be + // corrupted, so we need to send a dummy word with chip-select held high to + // get that first byte out of the way. + // + // That operation is tricky and detailed, so we'll call a function to do it + // for us. + // + if ( WORKAROUND_IOM == ui32Module && isRevB0() ) + { + am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options); + // + // The workaround function is going to a partial transfer for us, but + // we have to keep our own data-tracking variables updated. Here, we're + // subtracting 4 bytes from the effective transfer size to account for + // the 4 bytes of "dummy" word that we sent instead of the actual data. + // + ui32TransferSize = (ui32NumBytes <= (ui32MaxFifoSize - 4) ? ui32NumBytes : + (ui32MaxFifoSize - 4)); + } + else + { + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + // + // write our first word to the fifo. + // + + am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize); + + // + // Start the write on the bus. + // + am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + } + + // + // Update the pointer and data counter. + // + ui32NumBytes -= ui32TransferSize; + pui32Data += ui32TransferSize >> 2; + + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while ( ui32NumBytes && !AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP) ) + { + // + // This will always return a multiple of four. + // + ui32SpaceInFifo = am_hal_iom_fifo_empty_slots(ui32Module); + + if ( ui32NumBytes <= ui32SpaceInFifo ) + { + // + // If the entire message will fit in the fifo, prepare to copy + // everything. + // + ui32TransferSize = ui32NumBytes; + } + else + { + // + // If only a portion of the message will fit in the fifo, prepare + // to copy the largest number of 4-byte blocks possible. + // + ui32TransferSize = ui32SpaceInFifo & ~(0x3); + } + + // + // Write this chunk to the fifo. + // + am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize); + + // + // Update the data pointer and bytes-left count. + // + ui32NumBytes -= ui32TransferSize; + pui32Data += ui32TransferSize >> 2; + } + + // + // Make sure CMDCMP was raised with standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform simple SPI read operations (without queuing). +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs simple SPI read operations. The caller is +//! responsible for ensuring that the receive buffer is large enough to hold +//! the requested amount of data. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32BytesInFifo; + uint32_t ui32IntConfig; + uint32_t bCmdCmp = false; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + + // + // Disable IOM interrupts as we'll be polling + // + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // If we're on a B0 part, and we're using IOM4, our first byte coule be + // corrupted, so we need to send a dummy word with chip-select held high to + // get that first byte out of the way. This is only true for spi reads with + // OFFSET values. + // + // That operation is tricky and detailed, so we'll call a function to do it + // for us. + // + if ( (WORKAROUND_IOM == ui32Module) && !(ui32Options & AM_HAL_IOM_RAW) && + isRevB0() ) + { + am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data, 0, + ui32Options | AM_HAL_IOM_CS_LOW); + + // + // The workaround will send our offset for us, so we can run a RAW + // command after. + // + ui32Options |= AM_HAL_IOM_RAW; + // + // Wait for the dummy word to go out over the bus. + // + // Make sure the command complete has also been raised + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + + // Clear CMDCMP status + AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + } + + am_hal_iom_spi_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + + // + // Start a loop to catch the Rx data. + // + while ( ui32NumBytes ) + { + ui32BytesInFifo = am_hal_iom_fifo_full_slots(ui32Module); + + if ( ui32BytesInFifo >= ui32NumBytes ) + { + // + // If the fifo contains our entire message, just copy the whole + // thing out. + // + am_hal_iom_fifo_read(ui32Module, pui32Data, ui32NumBytes); + ui32NumBytes = 0; + } + else if ( ui32BytesInFifo >= 4 ) + { + // + // If the fifo has at least one 32-bit word in it, copy whole + // words out. + // + am_hal_iom_fifo_read(ui32Module, pui32Data, ui32BytesInFifo & ~0x3); + ui32NumBytes -= ui32BytesInFifo & ~0x3; + pui32Data += ui32BytesInFifo >> 2; + } + if ( bCmdCmp == true ) + { + // + // No more data expected. Get out of the loop + // + break; + } + + bCmdCmp = AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP); + } + + // + // Make sure CMDCMP was raised, + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + + // + // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + + return ui32Status; + +} + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex operation to the SPI interface (without queuing) +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param pui32Data - Pointer to the bytes that will be received. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options) +{ +// volatile uint32_t ui32MaxFifoSize; + uint32_t ui32IntConfig; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Full-Duplex operation is only supported for Apollo2 B2 Silicon. + // + if (!isRevB2()) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + return ui32Status; + } + + // + // Put the IOM into Full-Duplex mode. + // + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP; + +// ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? +// AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // Set up a few tracking variables. + // + uint32_t ui32WriteSize = 0; + uint32_t ui32ReadSize = 0; + uint32_t ui32DataWritten = 0; + uint32_t ui32DataRead = 0; + + // + // Start with the largest FIFO write possible, write the command word, and + // update our tracking variable. + // + ui32WriteSize = ui32NumBytes > 64 ? 64 : ui32NumBytes; + + am_hal_iom_fifo_write(ui32Module, pui32TxData, ui32WriteSize); + + am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + + ui32DataWritten += ui32WriteSize; + pui32TxData += ui32WriteSize >> 2; + + + // + // Now we'll loop until we've written everything we have. + // + while (ui32DataWritten < ui32NumBytes) + { + // + // First, figure out if there's anything we can read. The available + // read data will always lag behind the data written a little. + // + uint32_t ui32DataSent = ui32DataWritten - am_hal_iom_fifo_full_slots(ui32Module); + ui32ReadSize = (ui32DataSent - ui32DataRead) & (~0x3); + if (ui32ReadSize <= 4) + { + ui32ReadSize = 0; + } + else + { + ui32ReadSize -= 4; + am_hal_iom_fifo_read(ui32Module, pui32RxData, ui32ReadSize); + } + + // + // Update our tracking variables. + // + ui32DataRead += ui32ReadSize; + pui32RxData += ui32ReadSize >> 2; + + // + // Next, figure out how much we can write without overflowing our read fifo. + // + uint32_t ui32WritesRemaining = ui32NumBytes - ui32DataWritten; + uint32_t ui32FifoSpace = 64 - am_hal_iom_fifo_full_slots(ui32Module); + uint32_t ui32ReadWriteDelta = ui32DataWritten - ui32DataRead; + + if (ui32ReadWriteDelta > 64) + { + // while(1); + return AM_HAL_IOM_ERR_RESOURCE_ERR; + } + + uint32_t ui32ReadFifoSpace = 64 - ui32ReadWriteDelta; + + if ((ui32WritesRemaining <= ui32ReadFifoSpace) && + (ui32WritesRemaining <= ui32FifoSpace)) + { + ui32WriteSize = ui32WritesRemaining; + } + else if (ui32FifoSpace <= ui32ReadFifoSpace) + { + ui32WriteSize = ui32FifoSpace & (~0x3); + } + else + { + ui32WriteSize = ui32ReadFifoSpace & (~0x3); + } + + am_hal_iom_fifo_write(ui32Module, pui32TxData, ui32WriteSize); + ui32DataWritten += ui32WriteSize; + pui32TxData += ui32WriteSize >> 2; + } + + // + // Make sure CMDCMP was raised with standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + + // + // One final read should catch the rest of the data. + // + while (am_hal_iom_fifo_full_slots(ui32Module)); + ui32ReadSize = ui32NumBytes - ui32DataRead; + am_hal_iom_fifo_read(ui32Module, pui32RxData, ui32ReadSize); + + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + + // + // Take the IOM out of Full-Duplex mode. + // + AM_REGn(IOMSTR, ui32Module, CFG) &= ~AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP; + + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a non-blocking write to the SPI interface. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! @param pfnCallback - Function to call when the transaction completes. +//! +//! This function performs SPI writes to the selected SPI device. +//! +//! This function call is a non-blocking implementation. It will write as much +//! data to the FIFO as possible immediately, store a pointer to the remaining +//! data, start the transfer on the bus, and then immediately return. The +//! caller will need to make sure that \e am_hal_iom_int_service() is called +//! for IOM FIFO interrupt events and "command complete" interrupt events. The +//! \e am_hal_iom_int_service() function will refill the FIFO as necessary and +//! call the \e pfnCallback function when the transaction is finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback) +{ + am_hal_iom_status_e ui32Status; + uint32_t ui32TransferSize; + uint32_t ui32MaxFifoSize; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status for non-blocking transfer + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + + // + // Need to mark IOM busy to avoid another transaction to be scheduled. + // This is to take care of a race condition in Queue mode, where the IDLE + // set is not a guarantee that the CMDCMP has been received + // + g_bIomBusy[ui32Module] = true; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // Check to see if we need to do the workaround. + // + if ( WORKAROUND_IOM == ui32Module && isRevB0() ) + { + // + // Figure out how many bytes we can write to the FIFO immediately, + // accounting for the extra word from the workaround. + // + ui32TransferSize = (ui32NumBytes <= (ui32MaxFifoSize - 4) ? ui32NumBytes : + (ui32MaxFifoSize - 4)); + + // + // Prepare the global IOM buffer structure. + // + g_psIOMBuffers[ui32Module].ui32State = BUFFER_SENDING; + g_psIOMBuffers[ui32Module].pui32Data = pui32Data + (ui32TransferSize / 4); + g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes - ui32TransferSize; + g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback; + g_psIOMBuffers[ui32Module].ui32Options = ui32Options; + + // + // Start the write on the bus using the workaround. This includes both + // the command write and the first fifo write, so we won't need to do + // either of those things manually. + // + am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options); + } + else + { + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + + if ( am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize) > 0 ) + { + // + // Prepare the global IOM buffer structure. + // + g_psIOMBuffers[ui32Module].ui32State = BUFFER_SENDING; + g_psIOMBuffers[ui32Module].pui32Data = pui32Data; + g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes; + g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback; + g_psIOMBuffers[ui32Module].ui32Options = ui32Options; + + // + // Update the pointer and the byte counter based on the portion of + // the transfer we just sent to the fifo. + // + g_psIOMBuffers[ui32Module].ui32BytesLeft -= ui32TransferSize; + g_psIOMBuffers[ui32Module].pui32Data += (ui32TransferSize / 4); + + // + // Start the write on the bus. + // + am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + } + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a non-blocking SPI read. +//! +//! @param ui32Module - Module number for the IOM. +//! @param ui32ChipSelect - Chip select number of the target device. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional SPI transfer options. +//! @param pfnCallback - Function to call when the transaction completes. +//! +//! This function performs SPI reads to a selected SPI device. +//! +//! This function call is a non-blocking implementation. It will start the SPI +//! transaction on the bus and store a pointer for the destination for the read +//! data, but it will not wait for the SPI transaction to finish. The caller +//! will need to make sure that \e am_hal_iom_int_service() is called for IOM +//! FIFO interrupt events and "command complete" interrupt events. The \e +//! am_hal_iom_int_service() function will empty the FIFO as necessary, +//! transfer the data to the \e pui32Data buffer, and call the \e pfnCallback +//! function when the transaction is finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback) +{ + am_hal_iom_status_e ui32Status; + uint32_t ui32IntConfig; + uint32_t waitStatus; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + + // + // Need to mark IOM busy to avoid another transaction to be scheduled. + // This is to take care of a race condition in Queue mode, where the IDLE + // set is not a guarantee that the CMDCMP has been received + // + g_bIomBusy[ui32Module] = true; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // If we're on a B0 part, and we're using IOM4, our first byte could be + // corrupted, so we need to send a dummy word with chip-select held high to + // get that first byte out of the way. This is only true for spi reads with + // OFFSET values. + // + // That operation is tricky and detailed, so we'll call a function to do it + // for us. + // + if ( (WORKAROUND_IOM == ui32Module) && !(ui32Options & AM_HAL_IOM_RAW) && + isRevB0() ) + { + // + // We might mess up the interrupt handler behavior if we allow this + // polled transaction to complete with interrupts enabled. We'll + // briefly turn them off here. + // + ui32IntConfig = AM_REGn(IOMSTR, 4, INTEN); + AM_REGn(IOMSTR, 4, INTEN) = 0; + + am_hal_iom_workaround_word_write(ui32ChipSelect, pui32Data, + 0, ui32Options | AM_HAL_IOM_CS_LOW); + + // + // The workaround will send our offset for us, so we can run a RAW + // command after. + // + ui32Options |= AM_HAL_IOM_RAW; + + // + // Wait for the dummy word to go out over the bus. + // + // Make sure the command complete has also been raised + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + return ui32Status; + } + + // + // Re-mark IOM as busy + // + + g_bIomBusy[ui32Module] = true; + + // + // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, 4, INTEN) = ui32IntConfig; + } + + // + // Prepare the global IOM buffer structure. + // + g_psIOMBuffers[ui32Module].ui32State = BUFFER_RECEIVING; + g_psIOMBuffers[ui32Module].pui32Data = pui32Data; + g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes; + g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback; + g_psIOMBuffers[ui32Module].ui32Options = ui32Options; + + // + // Start the read transaction on the bus. + // + am_hal_iom_spi_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + + return ui32Status; +} + +static uint32_t +internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation, + uint32_t ui32ChipSelect, + uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32Command; + // + // Start building the command from the operation parameter. + // + ui32Command = ui32Operation; + + // + // Set the transfer length (the length field is split, so this requires + // some swizzling). + // + ui32Command |= ((ui32NumBytes & 0xF00) << 15); + ui32Command |= (ui32NumBytes & 0xFF); + + // + // Set the chip select number. + // + ui32Command |= ((ui32ChipSelect << 16) & 0x00070000); + + // + // Finally, OR in the rest of the options. This mask should make sure that + // erroneous option values won't interfere with the other transfer + // parameters. + // + ui32Command |= ui32Options & 0x5C00FF00; + return ui32Command; +} +//***************************************************************************** +// +//! @brief Runs a SPI "command" through the IO master. +//! +//! @param ui32Operation - SPI action to be performed. +//! +//! @param psDevice - Structure containing information about the slave device. +//! +//! @param ui32NumBytes - Number of bytes to move (transmit or receive) with +//! this command. +//! +//! @param ui32Options - Additional SPI options to apply to this command. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_spi_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, + uint32_t ui32ChipSelect, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32Command; + + am_hal_debug_assert_msg(ui32NumBytes > 0, + "Trying to do a 0 byte transaction"); + ui32Command = internal_am_hal_iom_spi_cmd_construct(ui32Operation, + ui32ChipSelect, ui32NumBytes, ui32Options); + + + // + // Write the complete command word to the IOM command register. + // + AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command; +} + +//***************************************************************************** +// +//! @brief Perform a simple write to the I2C interface (without queuing) +//! +//! @param ui32Module - Module number for the IOM. +//! @param ui32BusAddress - I2C address of the target device. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional I2C transfer options. +//! +//! This function performs I2C writes to a selected I2C device. +//! +//! This function call is a blocking implementation. It will write as much +//! data to the FIFO as possible immediately, and then refill the FIFO as data +//! is transmiitted. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32Data array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32TransferSize; + uint32_t ui32SpaceInFifo; + uint32_t ui32IntConfig; + uint32_t ui32MaxFifoSize; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; + + // + // Validate parameters + // + if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until any earlier transactions have completed. + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Redirect to the bit-bang interface if the module number matches the + // software I2C module. + // + if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) + { + if ( ui32Options & AM_HAL_IOM_RAW ) + { + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + (uint8_t *)pui32Data, 0, false, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + else + { + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + (uint8_t *)pui32Data, + ((ui32Options & 0xFF00) >> 8), + true, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + + // + // Return. convert BB retCode to proper retCode here + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + + am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize); + + // + // Start the write on the bus. + // + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, + ui32NumBytes, ui32Options); + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status = ui32Status; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + // + // Update the pointer and data counter. + // + ui32NumBytes -= ui32TransferSize; + pui32Data += ui32TransferSize >> 2; + + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while ( ui32NumBytes && !AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP) ) + { + // + // This will always return a multiple of four. + // + ui32SpaceInFifo = am_hal_iom_fifo_empty_slots(ui32Module); + + if ( ui32NumBytes <= ui32SpaceInFifo ) + { + // + // If the entire message will fit in the fifo, prepare to copy + // everything. + // + ui32TransferSize = ui32NumBytes; + } + else + { + // + // If only a portion of the message will fit in the fifo, prepare + // to copy the largest number of 4-byte blocks possible. + // + ui32TransferSize = ui32SpaceInFifo; + } + + // + // Write this chunk to the fifo. + // + am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize); + + // + // Update the data pointer and bytes-left count. + // + ui32NumBytes -= ui32TransferSize; + pui32Data += ui32TransferSize >> 2; + } + + // + // Make sure CMDCMP was raised, + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform simple I2C read operations (without queuing). +//! +//! @param ui32Module - Module number for the IOM. +//! @param ui32BusAddress - I2C address of the target device. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional I2C transfer options. +//! +//! This function performs an I2C read to a selected I2C device. +//! +//! This function call is a blocking implementation. It will read as much +//! data from the FIFO as possible immediately, and then re-read the FIFO as more +//! data is available. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32BytesInFifo; + uint32_t ui32IntConfig; + uint32_t bCmdCmp = false; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; + + // + // Validate parameters + // + if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Redirect to the bit-bang interface if the module number matches the + // software I2C module. + // + if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) + { + if ( ui32Options & AM_HAL_IOM_RAW ) + { + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + (uint8_t *)pui32Data, 0, false, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + else + { + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + (uint8_t *)pui32Data, + ((ui32Options & 0xFF00) >> 8), + true, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, + ui32NumBytes, ui32Options); + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status = ui32Status; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + + // + // Start a loop to catch the Rx data. + // + while ( ui32NumBytes ) + { + ui32BytesInFifo = am_hal_iom_fifo_full_slots(ui32Module); + + if ( ui32BytesInFifo >= ui32NumBytes ) + { + // + // If the fifo contains our entire message, just copy the whole + // thing out. + // + am_hal_iom_fifo_read(ui32Module, pui32Data, ui32NumBytes); + ui32NumBytes = 0; + } + else if ( ui32BytesInFifo >= 4 ) + { + // + // If the fifo has at least one 32-bit word in it, copy whole + // words out. + // + am_hal_iom_fifo_read(ui32Module, pui32Data, ui32BytesInFifo & ~0x3); + + ui32NumBytes -= ui32BytesInFifo & ~0x3; + pui32Data += ui32BytesInFifo >> 2; + } + + if ( bCmdCmp == true ) + { + // No more data expected - exit out of loop + break; + } + + bCmdCmp = AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP); + } + + // + // Make sure CMDCMP was raised, + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a simple write to the I2C interface. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32BusAddress - I2C bus address for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional options +//! +//! Performs a write to the I2C interface using the provided parameters. +//! +//! See the "Command Options" section for parameters that may be ORed together +//! and used in the \b ui32Options parameter. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; + // + // Validate parameters + // + if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Redirect to the bit-bang interface if the module number matches the + // software I2C module. + // + if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) + { + if ( ui32Options & AM_HAL_IOM_RAW ) + { + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + (uint8_t *)pui32Data, 0, false, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + else + { + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + (uint8_t *)pui32Data, + ((ui32Options & 0xFF00) >> 8), + true, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_i2c_write(ui32Module, ui32BusAddress, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { + // + // Otherwise, we'll just do a polled transaction. + // + ui32Status = am_hal_iom_i2c_write_nq(ui32Module, ui32BusAddress, pui32Data, + ui32NumBytes, ui32Options); + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform simple I2C read operations. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32BusAddress - I2C bus address for this transaction. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional I2C transfer options. +//! +//! This function performs simple I2C read operations. The caller is +//! responsible for ensuring that the receive buffer is large enough to hold +//! the requested amount of data. If \e bPolled is true, this function will +//! block until all of the requested data has been received and placed in the +//! user-supplied buffer. Otherwise, the function will execute the I2C read +//! command and return immediately. The user-supplied buffer will be filled +//! with the received I2C data as it comes in over the physical interface, and +//! the "command complete" interrupt bit will become active once the entire +//! message is available. +//! +//! See the "Command Options" section for parameters that may be ORed together +//! and used in the \b ui32Options parameter. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; + // + // Validate parameters + // + if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Redirect to the bit-bang interface if the module number matches the + // software I2C module. + // + if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) + { + if ( ui32Options & AM_HAL_IOM_RAW ) + { + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + (uint8_t *)pui32Data, 0, false, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + else + { + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + (uint8_t *)pui32Data, + ((ui32Options & 0xFF00) >> 8), + true, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_i2c_read(ui32Module, ui32BusAddress, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { + // + // Otherwise, just perform a polled transaction. + // + ui32Status = am_hal_iom_i2c_read_nq(ui32Module, ui32BusAddress, pui32Data, + ui32NumBytes, ui32Options); + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a non-blocking write to the I2C interface. +//! +//! @param ui32Module - Module number for the IOM. +//! @param ui32BusAddress - I2C address of the target device. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional I2C transfer options. +//! @param pfnCallback - Function to call when the transaction completes. +//! +//! This function performs I2C writes to a selected I2C device. +//! +//! This function call is a non-blocking implementation. It will write as much +//! data to the FIFO as possible immediately, store a pointer to the remaining +//! data, start the transfer on the bus, and then immediately return. The +//! caller will need to make sure that \e am_hal_iom_int_service() is called +//! for IOM FIFO interrupt events and "command complete" interrupt events. The +//! \e am_hal_iom_int_service() function will refill the FIFO as necessary and +//! call the \e pfnCallback function when the transaction is finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32Data array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback) +{ + am_hal_iom_status_e ui32Status; + uint32_t ui32TransferSize; + uint32_t ui32MaxFifoSize; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; + + // + // Validate parameters + // + if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Redirect to the bit-bang interface if the module number matches the + // software I2C module. + // + if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) + { + // Reset the error status for non-blocking transfer + g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32Options & AM_HAL_IOM_RAW ) + { + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + (uint8_t *)pui32Data, 0, false, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + else + { + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + (uint8_t *)pui32Data, + ((ui32Options & 0xFF00) >> 8), + true, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + // + // The I2C bit-bang interface is actually a blocking transfer, and it + // doesn't trigger the interrupt handler, so we have to call the + // callback function manually. + // + if ( pfnCallback ) + { + pfnCallback(); + } + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + + // Need to mark IOM busy to avoid another transaction to be scheduled. + // This is to take care of a race condition in Queue mode, where the IDLE + // set is not a guarantee that the CMDCMP has been received + g_bIomBusy[ui32Module] = true; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + if ( am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize) > 0 ) + { + // + // Prepare the global IOM buffer structure. + // + g_psIOMBuffers[ui32Module].ui32State = BUFFER_SENDING; + g_psIOMBuffers[ui32Module].pui32Data = pui32Data; + g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes; + g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback; + + // + // Update the pointer and the byte counter based on the portion of the + // transfer we just sent to the fifo. + // + g_psIOMBuffers[ui32Module].ui32BytesLeft -= ui32TransferSize; + g_psIOMBuffers[ui32Module].pui32Data += (ui32TransferSize / 4); + + // + // Start the write on the bus. + // + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, + ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a non-blocking I2C read. +//! +//! @param ui32Module - Module number for the IOM. +//! @param ui32ChipSelect - I2C address of the target device. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional I2C transfer options. +//! @param pfnCallback - Function to call when the transaction completes. +//! +//! This function performs an I2C read to a selected I2C device. +//! +//! This function call is a non-blocking implementation. It will start the I2C +//! transaction on the bus and store a pointer for the destination for the read +//! data, but it will not wait for the I2C transaction to finish. The caller +//! will need to make sure that \e am_hal_iom_int_service() is called for IOM +//! FIFO interrupt events and "command complete" interrupt events. The \e +//! am_hal_iom_int_service() function will empty the FIFO as necessary, +//! transfer the data to the \e pui32Data buffer, and call the \e pfnCallback +//! function when the transaction is finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback) +{ + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; + // + // Validate parameters + // + if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Redirect to the bit-bang interface if the module number matches the + // software I2C module. + // + if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) + { + // Reset the error status for non-blocking transfer + g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32Options & AM_HAL_IOM_RAW ) + { + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + (uint8_t *)pui32Data, 0, false, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + else + { + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + (uint8_t *)pui32Data, + ((ui32Options & 0xFF00) >> 8), + true, + (ui32Options & AM_HAL_IOM_NO_STOP)); + } + + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + // + // The I2C bit-bang interface is actually a blocking transfer, and it + // doesn't trigger the interrupt handler, so we have to call the + // callback function manually. + // + if ( pfnCallback ) + { + pfnCallback(); + } + + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // Need to mark IOM busy to avoid another transaction to be scheduled. + // This is to take care of a race condition in Queue mode, where the IDLE + // set is not a guarantee that the CMDCMP has been received + // + g_bIomBusy[ui32Module] = true; + + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // Prepare the global IOM buffer structure. + // + g_psIOMBuffers[ui32Module].ui32State = BUFFER_RECEIVING; + g_psIOMBuffers[ui32Module].pui32Data = pui32Data; + g_psIOMBuffers[ui32Module].ui32BytesLeft = ui32NumBytes; + g_psIOMBuffers[ui32Module].pfnCallback = pfnCallback; + + // + // Start the read transaction on the bus. + // + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, + ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Runs a I2C "command" through the IO master. +//! +//! @param ui32Operation - I2C action to be performed. This should either be +//! AM_HAL_IOM_WRITE or AM_HAL_IOM_READ. +//! @param ui32Module - Module number for the IOM. +//! @param ui32BusAddress - I2C address of the target device. +//! @param ui32NumBytes - Number of bytes to move (transmit or receive) with +//! this command. +//! @param ui32Options - Additional I2C options to apply to this command. +//! +//! This function may be used along with am_hal_iom_fifo_write and +//! am_hal_iom_fifo_read to perform more complex I2C reads and writes. +//! This function has additional logic to make sure SCL is high before a new +//! transaction is initiated. +//! +//! @return 0 on success +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, + uint32_t ui32BusAddress, uint32_t ui32NumBytes, + uint32_t ui32Options) +{ + uint32_t ui32Command; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + if (ui32NumBytes == 0) + { + return AM_HAL_IOM_ERR_INVALID_PARAM; + } + + // + // Start building the command from the operation parameter. + // + ui32Command = ui32Operation; + + // + // Set the transfer length. + // + ui32Command |= (ui32NumBytes & 0xFF); + + // + // Set the chip select number. + // + ui32Command |= ((ui32BusAddress << 16) & 0x03FF0000); + + // + // Finally, OR in the rest of the options. This mask should make sure that + // erroneous option values won't interfere with the other transfer + // parameters. + // + ui32Command |= (ui32Options & 0x5C00FF00); + + // + // Wait for SCL to be high before initiating a new transaction + // This is to ensure clock hi time specs are not violated in case slave did + // clock stretching in previous transaction + // + ui32Status = internal_iom_wait_i2c_scl_hi(ui32Module); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Write the complete command word to the IOM command register. + // + AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command; + } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Sets the repeat count for the next IOM command. +//! +//! @param ui32Module is the IOM module number. +//! @param ui32CmdCount is the number of times the next command should be +//! executed. +//! +//! @note This function is not compatible with the am_hal_iom_spi_read/write() +//! or am_hal_iom_i2c_read/write() functions. Instead, you will need to use the +//! am_hal_iom_fifo_read/write() functions and the am_hal_iom_spi/i2c_cmd_run() +//! functions. +//! +//! Example usage: +//! @code +//! +//! // +//! // Create a buffer and add 3 bytes of data to it. +//! // +//! am_hal_iom_buffer(3) psBuffer; +//! psBuffer.bytes[0] = 's'; +//! psBuffer.bytes[1] = 'p'; +//! psBuffer.bytes[2] = 'i'; +//! +//! // +//! // Send three different bytes to the same SPI register on a remote device. +//! // +//! am_hal_iom_fifo_write(ui32Module, psBuffer.words, 3); +//! +//! am_hal_command_repeat_set(ui32Module, 3); +//! +//! am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, psDevice, 1, +//! AM_HAL_IOM_OFFSET(0x5)); +//! +//! // +//! // The sequence "0x5, 's', 0x5, 'p', 0x5, 'i'" should be written to the SPI +//! // bus. +//! // +//! +//! @endcode +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_command_repeat_set(uint32_t ui32Module, uint32_t ui32CmdCount) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + AM_REGn(IOMSTR, ui32Module, CMDRPT) = ui32CmdCount; +} + +//***************************************************************************** +// +//! @brief Writes data to the IOM FIFO. +//! +//! @param ui32Module - Selects the IOM module to use (zero or one). +//! @param pui32Data - Pointer to an array of the data to be written. +//! @param ui32NumBytes - Number of BYTES to copy into the FIFO. +//! +//! This function copies data from the array \e pui32Data into the IOM FIFO. +//! This prepares the data to eventually be sent as SPI or I2C data by an IOM +//! "command". +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +//! +//! @note This function may be used to write partial or complete SPI or I2C +//! messages into the IOM FIFO. When writing partial messages to the FIFO, make +//! sure that the number of bytes written is a multiple of four. Only the last +//! 'part' of a message may consist of a number of bytes that is not a multiple +//! of four. If this rule is not followed, the IOM will not be able to send +//! these bytes correctly. +//! +//! @return Number of bytes actually written to the FIFO. +// +//***************************************************************************** +uint32_t +am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes) +{ + uint32_t ui32Index; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + // + // Make sure we check the number of bytes we're writing to the FIFO. + // + am_hal_debug_assert_msg((am_hal_iom_fifo_empty_slots(ui32Module) >= ui32NumBytes), + "The fifo couldn't fit the requested number of bytes"); + + // + // Loop over the words in the array until we have the correct number of + // bytes. + // + for ( ui32Index = 0; (4 * ui32Index) < ui32NumBytes; ui32Index++ ) + { + // + // Write the word to the FIFO. + // + AM_REGn(IOMSTR, ui32Module, FIFO) = pui32Data[ui32Index]; + } + + return ui32NumBytes; +} + +//***************************************************************************** +// +//! @brief Reads data from the IOM FIFO. +//! +//! @param ui32Module - Selects the IOM module to use (zero or one). +//! @param pui32Data - Pointer to an array where the FIFO data will be copied. +//! @param ui32NumBytes - Number of bytes to copy into array. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This function will pack the individual bytes from the physical interface +//! into 32-bit words, which are then placed into the \e pui32Data array. Only +//! the first \e ui32NumBytes bytes in this array will contain valid data. +//! +//! @return Number of bytes read from the fifo. +// +//***************************************************************************** +uint32_t +am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes) +{ + am_hal_iom_buffer(4) sTempBuffer; + uint32_t i, j, ui32NumWords, ui32Leftovers; + uint8_t *pui8Data; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + // + // Make sure we check the number of bytes we're reading from the FIFO. + // This doesn't make sense for Full-Duplex operations. + // + if ( AM_REG_IOMSTR_CFG_FULLDUP_NORMAL == (AM_REGn(IOMSTR, ui32Module, CFG) & AM_REG_IOMSTR_CFG_FULLDUP_M) ) + { + am_hal_debug_assert_msg((am_hal_iom_fifo_full_slots(ui32Module) >= ui32NumBytes), + "The fifo doesn't contain the requested number of bytes."); + } + + // + // Figure out how many whole words we're reading from the fifo, and how + // many bytes will be left over when we're done. + // + ui32NumWords = ui32NumBytes / 4; + ui32Leftovers = ui32NumBytes - (ui32NumWords * 4); + + // + // Copy out as many full words as we can. + // + for ( i = 0; i < ui32NumWords; i++ ) + { + // + // Copy data out of the FIFO, one word at a time. + // + pui32Data[i] = AM_REGn(IOMSTR, ui32Module, FIFO); + } + + // + // If there were leftovers, we'll copy them carefully. Pull the last word + // from the fifo (there should only be one) into a temporary buffer. Also, + // create an 8-bit pointer to help us copy the remaining bytes one at a + // time. + // + // Note: If the data buffer we were given was truly a word pointer like the + // definition requests, we wouldn't need to do this. It's possible to call + // this function with a re-cast or packed pointer instead though. If that + // happens, we want to be careful not to overwrite any data that might be + // sitting just past the end of the destination array. + // + if ( ui32Leftovers ) + { + sTempBuffer.words[0] = AM_REGn(IOMSTR, ui32Module, FIFO); + pui8Data = (uint8_t *) (&pui32Data[i]); + + // + // If we had leftover bytes, copy them out one byte at a time. + // + for ( j = 0; j < ui32Leftovers; j++ ) + { + pui8Data[j] = sTempBuffer.bytes[j]; + } + } + + return ui32NumBytes; +} + +//***************************************************************************** +// +//! @brief Check amount of empty space in the IOM fifo. +//! +//! @param ui32Module - Module number of the IOM whose fifo should be checked. +//! +//! Returns the number of bytes that could be written to the IOM fifo without +//! causing an overflow. +//! +//! @return Amount of space available in the fifo (in bytes). +// +//***************************************************************************** +uint8_t +am_hal_iom_fifo_empty_slots(uint32_t ui32Module) +{ + uint32_t ui32MaxFifoSize; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + + // + // Calculate the FIFO Remaining from the FIFO size. This will be different + // depending on whether the IOM is configured for half-duplex or + // full-duplex. + // + return (ui32MaxFifoSize - AM_BFRn(IOMSTR, ui32Module, FIFOPTR, FIFOSIZ)) & (~0x3); +} + +//***************************************************************************** +// +//! @brief Check to see how much data is in the IOM fifo. +//! +//! @param ui32Module - Module number of the IOM whose fifo should be checked. +//! +//! Returns the number of bytes of data that are currently in the IOM fifo. +//! +//! @return Number of bytes in the fifo. +// +//***************************************************************************** +uint8_t +am_hal_iom_fifo_full_slots(uint32_t ui32Module) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + return AM_BFRn(IOMSTR, ui32Module, FIFOPTR, FIFOSIZ); +} + +//***************************************************************************** +// +//! @brief Wait for the current IOM command to complete. +//! +//! @param ui32Module - The module number of the IOM to use. +//! +//! This function polls until the IOM bus becomes idle. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_poll_complete(uint32_t ui32Module) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + // + // Poll on the IDLE bit in the status register. + // + while ( g_bIomBusy[ui32Module] ); +} + +//***************************************************************************** +// +//! @brief Returns the contents of the IOM status register. +//! +//! @param ui32Module IOM instance to check the status of. +//! +//! This function is just a wrapper around the IOM status register. +//! +//! @return 32-bit contents of IOM status register. +// +//***************************************************************************** +uint32_t +am_hal_iom_status_get(uint32_t ui32Module) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + return AM_REGn(IOMSTR, ui32Module, STATUS); +} + +//***************************************************************************** +// +//! @brief Returns current error state of the IOM. +//! +//! @param ui32Module IOM instance to check the status of. +//! +//! This function returns status indicating whether the IOM has incurred any +//! errors or not for previous operation. +//! This function can be called when the callback is invoked to determine the +//! status of the transaction just completed. +//! This function can also be called after a blocking call, though it would +//! return the same status as returned from the call itself +//! This function should not be called for an ongoing transaction, and the +//! result of such operation is indeterministic +//! +//! @return AM_HAL_IOM_SUCCESS if all is well. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_error_status_get(uint32_t ui32Module) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + // + // AM_HAL_IOM_ERR_INVALID_MODULE is defined as an unused interrupt bit. + // + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + + return (g_iom_error_status[ui32Module]); +} + +//***************************************************************************** +// +//! @brief Service interrupts from the IOM. +//! +//! @param ui32Status is the IOM interrupt status as returned from +//! am_hal_iom_int_status_get() +//! +//! This function performs the necessary operations to facilitate non-blocking +//! IOM writes and reads. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status) +{ + am_hal_iom_nb_buffer *psBuffer; + uint32_t ui32NumBytes; + uint32_t ui32SpaceInFifo; + uint32_t thresh; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + // + // Find the buffer information for the chosen IOM module. + // + psBuffer = &g_psIOMBuffers[ui32Module]; + + // Keep accumulating any error indications + // This is to account for the case if the error indication comes before CMDCMP + g_iom_error_status[ui32Module] |= ui32Status; + // + // Figure out what type of interrupt this was. + // + if ( ui32Status & AM_HAL_IOM_INT_CMDCMP ) + { + // + // Need to mark IOM Free + // + g_bIomBusy[ui32Module] = false; + + // + // If we're not in the middle of a non-blocking call right now, there's + // nothing for this routine to do. + // + if ( psBuffer->ui32State == BUFFER_IDLE ) + { + return; + } + + // + // If a command just completed, we need to transfer all available data. + // + if ( psBuffer->ui32State == BUFFER_RECEIVING ) + { + // + // If we were receiving, we need to copy any remaining data out of + // the IOM FIFO before calling the callback. + // + ui32NumBytes = am_hal_iom_fifo_full_slots(ui32Module); + am_hal_iom_fifo_read(ui32Module, psBuffer->pui32Data, ui32NumBytes); + } + + // + // A command complete event also means that we've already transferred + // all of the data we need, so we can mark the data buffer as IDLE. + // + psBuffer->ui32State = BUFFER_IDLE; + + g_iom_error_status[ui32Module] = internal_iom_get_int_err(ui32Module, g_iom_error_status[ui32Module]); + // + // If we have a callback, call it now. + // + if ( psBuffer->pfnCallback ) + { + psBuffer->pfnCallback(); + } + } + else if ( ui32Status & AM_HAL_IOM_INT_THR ) + { + // + // If we're not in the middle of a non-blocking call right now, there's + // nothing for this routine to do. + // + if ( psBuffer->ui32State == BUFFER_IDLE ) + { + return; + } + // + // If we received a threshold event in the middle of a command, we need + // to transfer data. + // + if ( psBuffer->ui32State == BUFFER_SENDING ) + { + thresh = AM_BFRn(IOMSTR, ui32Module, FIFOTHR, FIFOWTHR); + do + { + ui32SpaceInFifo = am_hal_iom_fifo_empty_slots(ui32Module); + + // + // Figure out how much data we can send. + // + if ( psBuffer->ui32BytesLeft <= ui32SpaceInFifo ) + { + // + // If the whole transfer will fit in the fifo, send it all. + // + ui32NumBytes = psBuffer->ui32BytesLeft; + } + else + { + // + // If the transfer won't fit in the fifo completely, send as + // much as we can (rounded down to a multiple of four bytes). + // + ui32NumBytes = ui32SpaceInFifo; + } + + // + // Perform the transfer. + // + am_hal_iom_fifo_write(ui32Module, psBuffer->pui32Data, ui32NumBytes); + + // Clear any spurious THR interrupt that might have got raised + // while we were adding data to FIFO + AM_BFWn(IOMSTR, ui32Module, INTCLR, THR, 1); + // + // Update the pointer and the byte counter. + // + psBuffer->ui32BytesLeft -= ui32NumBytes; + psBuffer->pui32Data += (ui32NumBytes / 4); + + if ( 0 == psBuffer->ui32BytesLeft ) + { + // + // Done with this transaction + // + break; + } + } while ( am_hal_iom_fifo_full_slots(ui32Module) <= thresh ); + } + else + { + thresh = AM_BFRn(IOMSTR, ui32Module, FIFOTHR, FIFORTHR); + while ( (ui32NumBytes = am_hal_iom_fifo_full_slots(ui32Module)) >= thresh ) + { + // + // If we get here, we're in the middle of a read. Transfer as much + // data as possible out of the FIFO and into our buffer. + // + if ( ui32NumBytes == psBuffer->ui32BytesLeft ) + { + // + // If the fifo contains our entire message, just copy the whole + // thing out. + // + am_hal_iom_fifo_read(ui32Module, psBuffer->pui32Data, + psBuffer->ui32BytesLeft); + + break; + } + else if ( ui32NumBytes >= 4 ) + { + // + // If the fifo has at least one 32-bit word in it, copy out the + // biggest block we can. + // + ui32NumBytes = (ui32NumBytes & (~0x3)); + + am_hal_iom_fifo_read(ui32Module, psBuffer->pui32Data, ui32NumBytes); + + // + // Update the pointer and the byte counter. + // + psBuffer->ui32BytesLeft -= ui32NumBytes; + psBuffer->pui32Data += (ui32NumBytes / 4); + + // Clear any spurious THR interrupt that might have got raised + // while we were reading the data from FIFO + AM_BFWn(IOMSTR, ui32Module, INTCLR, THR, 1); + } + } + } + } +} + +//***************************************************************************** +// +//! @brief Initialize the IOM queue system. +//! +//! @param ui32Module - IOM module to be initialized for queue transfers. +//! @param psQueueMemory - Memory to be used for queueing IOM transfers. +//! @param ui32QueueMemSize - Size of the queue memory. +//! +//! This function prepares the selected IOM interface for use with the IOM +//! queue system. The IOM queue system allows the caller to start multiple IOM +//! transfers in a non-blocking way. In order to do this, the HAL requires some +//! amount of memory dedicated to keeping track of IOM transactions before they +//! can be sent to the hardware registers. This function tells the HAL what +//! memory it should use for this purpose. For more information on the IOM +//! queue interface, please see the documentation for +//! am_hal_iom_queue_spi_write(). +//! +//! @note This function only needs to be called once (per module), but it must +//! be called before any other am_hal_iom_queue function. +//! +//! @note Each IOM module will need its own working space. If you intend to use +//! the queueing mechanism with more than one IOM module, you will need to +//! provide separate queue memory for each module. +//! +//! Example usage: +//! +//! @code +//! +//! // +//! // Declare an array to be used for IOM queue transactions. This array will +//! // be big enough to handle 32 IOM transactions. +//! // +//! am_hal_iom_queue_entry_t g_psQueueMemory[32]; +//! +//! // +//! // Attach the IOM0 queue system to the memory we just allocated. +//! // +//! am_hal_iom_queue_init(0, g_psQueueMemory, sizeof(g_psQueueMemory)); +//! +//! @endcode +// +//***************************************************************************** +void +am_hal_iom_queue_init(uint32_t ui32Module, am_hal_iom_queue_entry_t *psQueueMemory, + uint32_t ui32QueueMemSize) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + am_hal_queue_init(&g_psIOMQueue[ui32Module], psQueueMemory, + sizeof(am_hal_iom_queue_entry_t), ui32QueueMemSize); +} + +//***************************************************************************** +// +//! @brief Check to see how many transactions are in the queue. +//! +//! @param ui32Module Module number for the queue to check +//! +//! This function will check to see how many transactions are in the IOM queue +//! for the selected IOM module. +//! +//! @return Number of transactions in the queue. +// +//***************************************************************************** +uint32_t +am_hal_iom_queue_length_get(uint32_t ui32Module) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + return am_hal_queue_data_left(&g_psIOMQueue[ui32Module]); +} + +//***************************************************************************** +// +//! @brief Executes the next operation in the IOM queue. +//! +//! @param ui32ModuleNum - Module number for the IOM to use. +//! +//! This function checks the IOM queue to see if there are any remaining +//! transactions. If so, it will start the next available transaction in a +//! non-blocking way. +//! +//! @note This function is called automatically by am_hal_iom_queue_service(). +//! You should not call this function standalone in a normal application. +// +//***************************************************************************** +void +am_hal_iom_queue_start_next_msg(uint32_t ui32Module) +{ + am_hal_iom_queue_entry_t sIOMTransaction = {0}; + + uint32_t ui32ChipSelect; + uint32_t *pui32Data; + uint32_t ui32NumBytes; + uint32_t ui32Options; + am_hal_iom_callback_t pfnCallback; + + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + uint32_t ui32Critical; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Try to get the next IOM operation from the queue. + // + if ( am_hal_queue_item_get(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) ) + { + // + // Read the operation parameters + // + ui32ChipSelect = sIOMTransaction.ui32ChipSelect; + pui32Data = sIOMTransaction.pui32Data; + ui32NumBytes = sIOMTransaction.ui32NumBytes; + ui32Options = sIOMTransaction.ui32Options; + pfnCallback = sIOMTransaction.pfnCallback; + + // + // Figure out if this was a SPI or I2C write or read, and call the + // appropriate non-blocking function. + // + switch ( sIOMTransaction.ui32Operation ) + { + case AM_HAL_IOM_QUEUE_SPI_WRITE: + ui32Status = am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + break; + + case AM_HAL_IOM_QUEUE_SPI_READ: + ui32Status = am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + break; + + case AM_HAL_IOM_QUEUE_I2C_WRITE: + ui32Status = am_hal_iom_i2c_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + break; + + case AM_HAL_IOM_QUEUE_I2C_READ: + ui32Status = am_hal_iom_i2c_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + break; + } + } + + // + // Exit the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + // Preserve the error + g_iom_error_status[ui32Module] = ui32Status; + // Call the respective callback + pfnCallback(); + } +} + +//***************************************************************************** +// +//! @brief Send a SPI frame using the IOM queue. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI writes to a selected SPI device. +//! +//! This function call is a queued implementation. It will write as much +//! data to the FIFO as possible immediately, store a pointer to the remaining +//! data, start the transfer on the bus, and then immediately return. If the +//! FIFO is already in use, this function will save its arguments to the IOM +//! queue and execute the transaction when the FIFO becomes available. +//! +//! The caller will need to make sure that \e am_hal_iom_queue_service() is +//! called for IOM FIFO interrupt events and "command complete" interrupt +//! events. The \e am_hal_iom_queue_service() function will refill the FIFO as +//! necessary and call the \e pfnCallback function when the transaction is +//! finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) +{ + uint32_t ui32Critical; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Check to see if we need to use the queue. If the IOM is idle, and + // there's nothing in the queue already, we can go ahead and start the + // transaction in the physical IOM. Need to check for the g_bIomBusy to + // avoid a race condition where IDLE is set - but the command complete + // for previous transaction has not been processed yet + // + if ( (g_bIomBusy[ui32Module] == false) && + am_hal_queue_empty(&g_psIOMQueue[ui32Module]) ) + { + // + // Send the packet. + // + ui32Status = am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + } + else + { + // + // Otherwise, we'll build a transaction structure and add it to the queue. + // + am_hal_iom_queue_entry_t sIOMTransaction; + + sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_SPI_WRITE; + sIOMTransaction.ui32Module = ui32Module; + sIOMTransaction.ui32ChipSelect = ui32ChipSelect; + sIOMTransaction.pui32Data = pui32Data; + sIOMTransaction.ui32NumBytes = ui32NumBytes; + sIOMTransaction.ui32Options = ui32Options; + sIOMTransaction.pfnCallback = pfnCallback; + + // + // Make sure the item actually makes it into the queue + // + if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false ) + { + // + // Didn't have enough memory. + // + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; + } + } + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + // + // Exit the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Read a SPI frame using the IOM queue. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip select number for this transaction. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI reads to a selected SPI device. +//! +//! This function call is a queued implementation. It will write as much +//! data to the FIFO as possible immediately, store a pointer to the remaining +//! data, start the transfer on the bus, and then immediately return. If the +//! FIFO is already in use, this function will save its arguments to the IOM +//! queue and execute the transaction when the FIFO becomes available. +//! +//! The caller will need to make sure that \e am_hal_iom_queue_service() is +//! called for IOM FIFO interrupt events and "command complete" interrupt +//! events. The \e am_hal_iom_queue_service() function will empty the FIFO as +//! necessary and call the \e pfnCallback function when the transaction is +//! finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) +{ + uint32_t ui32Critical; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Check to see if we need to use the queue. If the IOM is idle, and + // there's nothing in the queue already, we can go ahead and start the + // transaction in the physical IOM. Need to check for the g_bIomBusy to + // avoid a race condition where IDLE is set - but the command complete + // for previous transaction has not been processed yet + // + if ( (g_bIomBusy[ui32Module] == false) && + am_hal_queue_empty(&g_psIOMQueue[ui32Module]) ) + { + // + // Send the packet. + // + ui32Status = am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + } + else + { + // + // Otherwise, we'll build a transaction structure and add it to the queue. + // + am_hal_iom_queue_entry_t sIOMTransaction; + + sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_SPI_READ; + sIOMTransaction.ui32Module = ui32Module; + sIOMTransaction.ui32ChipSelect = ui32ChipSelect; + sIOMTransaction.pui32Data = pui32Data; + sIOMTransaction.ui32NumBytes = ui32NumBytes; + sIOMTransaction.ui32Options = ui32Options; + sIOMTransaction.pfnCallback = pfnCallback; + + // + // Make sure the item actually makes it into the queue + // + if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false ) + { + // + // Didn't have enough memory. + // + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; + } + } + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + // + // Exit the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Send an I2C frame using the IOM queue. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32BusAddress - I2C address of the target device. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional I2C transfer options. +//! +//! This function performs I2C writes to a selected I2C device. +//! +//! This function call is a queued implementation. It will write as much +//! data to the FIFO as possible immediately, store a pointer to the remaining +//! data, start the transfer on the bus, and then immediately return. If the +//! FIFO is already in use, this function will save its arguments to the IOM +//! queue and execute the transaction when the FIFO becomes available. +//! +//! The caller will need to make sure that \e am_hal_iom_queue_service() is +//! called for IOM FIFO interrupt events and "command complete" interrupt +//! events. The \e am_hal_iom_queue_service() function will refill the FIFO as +//! necessary and call the \e pfnCallback function when the transaction is +//! finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) +{ + am_hal_iom_status_e ui32Status; + uint32_t ui32Critical; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Check to see if we need to use the queue. If the IOM is idle, and + // there's nothing in the queue already, we can go ahead and start the + // transaction in the physical IOM. Need to check for the g_bIomBusy to + // avoid a race condition where IDLE is set - but the command complete + // for previous transaction has not been processed yet + // + if ( (g_bIomBusy[ui32Module] == false) && + am_hal_queue_empty(&g_psIOMQueue[ui32Module]) ) + { + // + // Send the packet. + // + ui32Status = am_hal_iom_i2c_write_nb(ui32Module, ui32BusAddress, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + } + else + { + // + // Otherwise, we'll build a transaction structure and add it to the queue. + // + am_hal_iom_queue_entry_t sIOMTransaction; + + sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_I2C_WRITE; + sIOMTransaction.ui32Module = ui32Module; + sIOMTransaction.ui32ChipSelect = ui32BusAddress; + sIOMTransaction.pui32Data = pui32Data; + sIOMTransaction.ui32NumBytes = ui32NumBytes; + sIOMTransaction.ui32Options = ui32Options; + sIOMTransaction.pfnCallback = pfnCallback; + + // + // Make sure the item actually makes it into the queue + // + if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false ) + { + // + // Didn't have enough memory. + // + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; + } + } + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + // + // Exit the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Read a I2C frame using the IOM queue. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32BusAddress - I2C address of the target device. +//! @param pui32Data - Pointer to the array where received bytes should go. +//! @param ui32NumBytes - Number of bytes to read. +//! @param ui32Options - Additional I2C transfer options. +//! +//! This function performs I2C reads to a selected I2C device. +//! +//! This function call is a queued implementation. It will write as much +//! data to the FIFO as possible immediately, store a pointer to the remaining +//! data, start the transfer on the bus, and then immediately return. If the +//! FIFO is already in use, this function will save its arguments to the IOM +//! queue and execute the transaction when the FIFO becomes available. +//! +//! The caller will need to make sure that \e am_hal_iom_queue_service() is +//! called for IOM FIFO interrupt events and "command complete" interrupt +//! events. The \e am_hal_iom_queue_service() function will empty the FIFO as +//! necessary and call the \e pfnCallback function when the transaction is +//! finished. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32Data array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui8Data array. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) +{ + uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Check to see if we need to use the queue. If the IOM is idle, and + // there's nothing in the queue already, we can go ahead and start the + // transaction in the physical IOM. Need to check for the g_bIomBusy to + // avoid a race condition where IDLE is set - but the command complete + // for previous transaction has not been processed yet + // + if ( (g_bIomBusy[ui32Module] == false) && + am_hal_queue_empty(&g_psIOMQueue[ui32Module]) ) + { + // + // Send the packet. + // + ui32Status = am_hal_iom_i2c_read_nb(ui32Module, ui32BusAddress, pui32Data, + ui32NumBytes, ui32Options, pfnCallback); + } + else + { + // + // Otherwise, we'll build a transaction structure and add it to the queue. + // + am_hal_iom_queue_entry_t sIOMTransaction; + + sIOMTransaction.ui32Operation = AM_HAL_IOM_QUEUE_I2C_READ; + sIOMTransaction.ui32Module = ui32Module; + sIOMTransaction.ui32ChipSelect = ui32BusAddress; + sIOMTransaction.pui32Data = pui32Data; + sIOMTransaction.ui32NumBytes = ui32NumBytes; + sIOMTransaction.ui32Options = ui32Options; + sIOMTransaction.pfnCallback = pfnCallback; + + // + // Make sure the item actually makes it into the queue + // + if ( am_hal_queue_item_add(&g_psIOMQueue[ui32Module], &sIOMTransaction, 1) == false ) + { + // + // Didn't have enough memory. + // + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; + } + } + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + // + // Exit the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + return ui32Status; +} + +//***************************************************************************** +// +//! @brief "Block" until the queue of IOM transactions is over. +//! +//! @param ui32Module - Module number for the IOM. +//! +//! This function will sleep the core block until the queue for the selected +//! IOM is empty. This is mainly useful for non-RTOS applications where the +//! caller needs to know that a certain IOM transaction is complete before +//! continuing with the main program flow. +//! +//! @note This function will put the core to sleep while it waits for the +//! queued IOM transactions to complete. This will save power, in most +//! situations, but it may not be the best option in all cases. \e Do \e not +//! call this function from interrupt context (the core may not wake up again). +//! \e Be \e careful using this function from an RTOS task (many RTOS +//! implementations use hardware interrupts to switch contexts, and most RTOS +//! implementations expect to control sleep behavior). +// +//***************************************************************************** +void +am_hal_iom_sleeping_queue_flush(uint32_t ui32Module) +{ + bool bWaiting = true; + uint32_t ui32Critical; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + // + // Loop forever waiting for the IOM to be idle and the queue to be empty. + // + while ( bWaiting ) + { + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Check the queue and the IOM itself. + // + if ( (g_bIomBusy[ui32Module] == false) && + am_hal_queue_empty(&g_psIOMQueue[ui32Module]) ) + { + // + // If the queue is empty and the IOM is idle, we can go ahead and + // return. + // + bWaiting = false; + } + else + { + // + // Otherwise, we should sleep until the interface is actually free. + // + am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_NORMAL); + } + + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + } +} + +//***************************************************************************** +// +//! @brief Service IOM transaction queue. +//! +//! @param ui32Module - Module number for the IOM to be used. +//! @param ui32Status - Interrupt status bits for the IOM module being used. +//! +//! This function handles the operation of FIFOs and the IOM queue during +//! queued IOM transactions. If you are using \e am_hal_iom_queue_spi_write() +//! or similar functions, you will need to call this function in your interrupt +//! handler. +//! +//! @note This interrupt service routine relies on the user to enable the IOM +//! interrupts for FIFO threshold and CMD complete. +//! +//! Example: +//! +//! @code +//! void +//! am_iomaster0_isr(void) +//! { +//! uint32_t ui32Status; +//! +//! // +//! // Check to see which interrupt caused us to enter the ISR. +//! // +//! ui32Status = am_hal_iom_int_status(0, true); +//! +//! // +//! // Clear the interrupts. This should be done before calling service routine +//! // as otherwise we may lose re-triggered interrupts +//! // +//! am_hal_iom_int_clear(ui32Status); +//! +//! // +//! // Fill or empty the FIFO, and either continue the current operation or +//! // start the next one in the queue. If there was a callback, it will be +//! // called here. +//! // +//! am_hal_iom_queue_service(0, ui32Status); +//! } +//! @endcode +//! +//! @return +// +//***************************************************************************** +void +am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Status) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + // + // Service the FIFOs in case this was a threshold interrupt. + // + am_hal_iom_int_service(ui32Module, ui32Status); + + // + // If the last interrupt was a "command complete", then the IOM should be + // idle already or very soon. Make absolutely sure that the IOM is not in + // use, and then start the next transaction in the queue. + // + if ( ui32Status & AM_HAL_IOM_INT_CMDCMP ) + { + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + am_hal_iom_queue_start_next_msg(ui32Module); + } + } +} + +//***************************************************************************** +// +//! @brief Enable selected IOM Interrupts. +//! +//! @param ui32Module - Module number. +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h +//! +//! Use this function to enable the IOM interrupts. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_iom_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + AM_REGn(IOMSTR, ui32Module, INTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled IOM Interrupts. +//! +//! @param ui32Module - Module number. +//! +//! Use this function to return all enabled IOM interrupts. +//! +//! @return all enabled IOM interrupts. +// +//***************************************************************************** +uint32_t +am_hal_iom_int_enable_get(uint32_t ui32Module) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + return AM_REGn(IOMSTR, ui32Module, INTEN); +} + +//***************************************************************************** +// +//! @brief Disable selected IOM Interrupts. +//! +//! @param ui32Module - Module number. +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h +//! +//! Use this function to disable the IOM interrupts. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_iom_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + AM_REGn(IOMSTR, ui32Module, INTEN) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clear selected IOM Interrupts. +//! +//! @param ui32Module - Module number. +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h +//! +//! Use this function to clear the IOM interrupts. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_iom_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + AM_REGn(IOMSTR, ui32Module, INTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Set selected IOM Interrupts. +//! +//! @param ui32Module - Module number. +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_iom.h +//! +//! Use this function to set the IOM interrupts. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_iom_int_set(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return; + } + + AM_REGn(IOMSTR, ui32Module, INTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the IOM Interrupt status. +//! +//! @param ui32Module - Module number. +//! @param bEnabledOnly - return only the enabled interrupts. +//! +//! Use this function to get the IOM interrupt status. +//! +//! @return interrupt status +// +//***************************************************************************** +uint32_t +am_hal_iom_int_status_get(uint32_t ui32Module, bool bEnabledOnly) +{ + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return 0; + } + + if ( bEnabledOnly ) + { + uint32_t u32RetVal = AM_REGn(IOMSTR, ui32Module, INTSTAT); + return u32RetVal & AM_REGn(IOMSTR, ui32Module, INTEN); + } + else + { + return AM_REGn(IOMSTR, ui32Module, INTSTAT); + } +} + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_iom.h b/mcu/apollo2/hal/am_hal_iom.h new file mode 100644 index 0000000..09ab0f9 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_iom.h @@ -0,0 +1,611 @@ +//***************************************************************************** +// +// am_hal_iom.h +//! @file +//! +//! @brief Functions for accessing and configuring the IO Master module +//! +//! @addtogroup iom2 IO Master (SPI/I2C) +//! @ingroup apollo2hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_HAL_IOM_H +#define AM_HAL_IOM_H + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @name IOM Clock Frequencies +//! @brief Macro definitions for common SPI and I2C clock frequencies. +//! +//! These macros may be used with the ui32ClockFrequency member of the +//! am_hal_iom_config_t structure to set the clock frequency of the serial +//! interfaces. +//! +//! This list of frequencies is not exhaustive by any means. If your desired +//! frequency is not in this list, simply set ui32ClockFrequency to the +//! desired frequency (in Hz) when calling am_hal_iom_config(). +// +//***************************************************************************** +#define AM_HAL_IOM_24MHZ 24000000 +#define AM_HAL_IOM_16MHZ 16000000 +#define AM_HAL_IOM_12MHZ 12000000 +#define AM_HAL_IOM_8MHZ 8000000 +#define AM_HAL_IOM_6MHZ 6000000 +#define AM_HAL_IOM_4MHZ 4000000 +#define AM_HAL_IOM_3MHZ 3000000 +#define AM_HAL_IOM_2MHZ 2000000 +#define AM_HAL_IOM_1_5MHZ 1500000 +#define AM_HAL_IOM_1MHZ 1000000 +#define AM_HAL_IOM_800KHZ 800000 +#define AM_HAL_IOM_750KHZ 750000 +#define AM_HAL_IOM_500KHZ 500000 +#define AM_HAL_IOM_400KHZ 400000 +#define AM_HAL_IOM_375KHZ 375000 +#define AM_HAL_IOM_250KHZ 250000 +#define AM_HAL_IOM_200KHZ 200000 +#define AM_HAL_IOM_125KHZ 125000 +#define AM_HAL_IOM_100KHZ 100000 +#define AM_HAL_IOM_50KHZ 50000 +#define AM_HAL_IOM_10KHZ 10000 + +// Hardware FIFO Size +#define AM_HAL_IOM_MAX_FIFO_SIZE 128 + +//***************************************************************************** +// +//! @name IOM Physical Protocols +//! @brief Macro Definitions for general IOM configuration. +//! +//! These macros may be used with the am_hal_iom_config_t structure to set the +//! operating parameters of each serial IO master module. Choose SPIMODE to +//! select the SPI interface, or I2CMODE to select the I2C interface. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOM_SPIMODE AM_REG_IOMSTR_CFG_IFCSEL(1) +#define AM_HAL_IOM_I2CMODE AM_REG_IOMSTR_CFG_IFCSEL(0) +//! @} + +//***************************************************************************** +// +//! @name IOM Operations +//! @brief Macro definitions used for ui32Operation parameters. +//! +//! These macros may be used to specify which action an IOM command will +//! execute. The 'OFFSET' operations will cause the IOM hardware to transmit the +//! provided 1-byte 'offset' before executing the rest of the command. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOM_WRITE 0x00000000 +#define AM_HAL_IOM_READ 0x80000000 +//! @} + +//***************************************************************************** +// +//! @name Command Options +//! @brief Macro definitions used for ui32Options parameters. +//! +//! These macros are all related to SPI or I2C command words. They can be used +//! to set specific options on a per-transaction basis. +//! +//! - CS_LOW - Do not raise the CS signal at the end of this SPI command. +//! - NO_STOP - Do not release the I2C bus with a STOP bit after this command. +//! - LSB_FIRST - Reverse the payload bits of this command. +//! - 10BIT_ADDRESS - (I2C only) use a 10-bit I2C address protocol. +//! - RAW - Don't use an offset byte. +//! - OFFSET() - Send this 1-byte offset as the first byte of the transaction. +//! This can be used to access "registers" in external I2C devices, or add a +//! 1-byte write to the beginning of a SPI write or read command. See +//! "normal mode" operation in the I2C/SPI Master section of the datasheet +//! for more information on this parameter. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOM_CS_LOW 0x10000000 +#define AM_HAL_IOM_NO_STOP 0x10000000 +#define AM_HAL_IOM_LSB_FIRST 0x08000000 +#define AM_HAL_IOM_10BIT_ADDRESS 0x04000000 +#define AM_HAL_IOM_RAW 0x40000000 +#define AM_HAL_IOM_OFFSET(n) (((n) << 8) & 0x0000FF00) +//! @} + +//***************************************************************************** +// +//! @name IOM Interrupts +//! @brief Macro definitions for IOM interrupt status bits. +//! +//! These macros correspond to the bits in the IOM interrupt status register. +//! They may be used with any of the \e am_hal_iom_int_x() functions. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOM_INT_ARB AM_REG_IOMSTR_INTEN_ARB_M +#define AM_HAL_IOM_INT_STOP AM_REG_IOMSTR_INTEN_STOP_M +#define AM_HAL_IOM_INT_START AM_REG_IOMSTR_INTEN_START_M +#define AM_HAL_IOM_INT_ICMD AM_REG_IOMSTR_INTEN_ICMD_M +#define AM_HAL_IOM_INT_IACC AM_REG_IOMSTR_INTEN_IACC_M +#define AM_HAL_IOM_INT_WTLEN AM_REG_IOMSTR_INTEN_WTLEN_M +#define AM_HAL_IOM_INT_NAK AM_REG_IOMSTR_INTEN_NAK_M +#define AM_HAL_IOM_INT_FOVFL AM_REG_IOMSTR_INTEN_FOVFL_M +#define AM_HAL_IOM_INT_FUNDFL AM_REG_IOMSTR_INTEN_FUNDFL_M +#define AM_HAL_IOM_INT_THR AM_REG_IOMSTR_INTEN_THR_M +#define AM_HAL_IOM_INT_CMDCMP AM_REG_IOMSTR_INTEN_CMDCMP_M + +#define AM_HAL_IOM_INT_ALL ( \ + AM_HAL_IOM_INT_ARB | \ + AM_HAL_IOM_INT_STOP | \ + AM_HAL_IOM_INT_START | \ + AM_HAL_IOM_INT_ICMD | \ + AM_HAL_IOM_INT_IACC | \ + AM_HAL_IOM_INT_WTLEN | \ + AM_HAL_IOM_INT_NAK | \ + AM_HAL_IOM_INT_FOVFL | \ + AM_HAL_IOM_INT_FUNDFL | \ + AM_HAL_IOM_INT_THR | \ + AM_HAL_IOM_INT_CMDCMP) + +#define AM_HAL_IOM_INT_SWERR ( \ + AM_HAL_IOM_INT_ICMD | \ + AM_HAL_IOM_INT_FOVFL | \ + AM_HAL_IOM_INT_FUNDFL | \ + AM_HAL_IOM_INT_IACC) + +#define AM_HAL_IOM_INT_I2CARBERR ( \ + AM_HAL_IOM_INT_ARB | \ + AM_HAL_IOM_INT_START | \ + AM_HAL_IOM_INT_STOP) +//! @} + +//***************************************************************************** +// +//! @name Software IOM modules +//! @brief Macro definitions for using the software I2C interface. +//! +//! Use this macro as the module number for standard IOM functions to emulate +//! them using the bit-banged i2c interface. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOM_I2CBB_MODULE AM_REG_IOMSTR_NUM_MODULES +//! @} + +//***************************************************************************** +// +//! @name IOM Return Codes +//! @brief Enum definitions for defining return values for IOM APIs +//! +//! This enum defines possible values for non-void IOM APIs +//! +//! @{ +// +//***************************************************************************** +typedef enum +{ + AM_HAL_IOM_SUCCESS = 0, + AM_HAL_IOM_ERR_TIMEOUT, + AM_HAL_IOM_ERR_INVALID_MODULE, + AM_HAL_IOM_ERR_INVALID_PARAM, + AM_HAL_IOM_ERR_INVALID_CFG, + AM_HAL_IOM_ERR_INVALID_OPER, + AM_HAL_IOM_ERR_I2C_NAK, + AM_HAL_IOM_ERR_I2C_ARB, + AM_HAL_IOM_ERR_RESOURCE_ERR, +} am_hal_iom_status_e ; + +//! @} + +//***************************************************************************** +// +//! @brief Union type for a word-aligned, byte-addressable array. +//! +//! This is a convenience macro that may be used to define byte-addressable +//! arrays with 32-bit alignment. This allows the programmer to define SPI or +//! I2C transactions as a series of 8-bit values, but also write them to the +//! IOM FIFO efficiently as a series of 32-bit values. +//! +//! Example usage: +//! +//! @code +//! // +//! // Declare a buffer array with at least 3-bytes worth of space. +//! // +//! am_hal_iom_buffer(3) sBuffer; +//! +//! // +//! // Populate the buffer with a 3-byte command. +//! // +//! sBuffer.bytes[0] = 's'; +//! sBuffer.bytes[1] = 'p'; +//! sBuffer.bytes[2] = 'i'; +//! +//! // +//! // Send the buffer over the spi interface. +//! // +//! am_hal_iom_spi_write(psDevice, sBuffer.words, 3, 0); +//! +//! @endcode +// +//***************************************************************************** +#define am_hal_iom_buffer(A) \ + union \ + { \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ + } + +//***************************************************************************** +// +//! @brief Configuration structure for the IO master module. +// +//***************************************************************************** +typedef struct +{ + // + //! @brief Selects the physical protocol for the IO master module. Choose + //! either AM_HAL_IOM_SPIMODE or AM_HAL_IOM_I2CMODE. + // + uint32_t ui32InterfaceMode; + + // + //! @brief Selects the output clock frequency for SPI or I2C mode. Choose + //! one of the AM_HAL_IOM_nMHZ or AM_HAL_IOM_nKHZ macros. + // + uint32_t ui32ClockFrequency; + + // + //! Select the SPI clock phase (unused in I2C mode). + // + bool bSPHA; + + // + //! Select the SPI clock polarity (unused in I2C mode). + // + bool bSPOL; + + // + //! @brief Select the FIFO write threshold. + //! + //! The IOM controller will generate a processor interrupt when the number + //! of entries in the FIFO goes *below* this number. + // + uint8_t ui8WriteThreshold; + + // + //! @brief Select the FIFO read threshold. + //! + //! The IOM controller will generate a processor interrupt when the number + //! of entries in the FIFO grows *larger* than this number. + // + uint8_t ui8ReadThreshold; + +} +am_hal_iom_config_t; + +//***************************************************************************** +// +//! Configuration structure for an individual SPI device. +// +//***************************************************************************** +typedef struct +{ + // + //! IOM module to use for communicating with this device. + // + uint32_t ui32Module; + + // + //! Chip select signal that should be used for this device. + // + uint32_t ui32ChipSelect; + + // + //! Additional options that will ALWAYS be ORed into the command word. + // + uint32_t ui32Options; +} +am_hal_iom_spi_device_t; + +//***************************************************************************** +// +//! Configuration structure for an individual I2C device. +// +//***************************************************************************** +typedef struct +{ + // + //! IOM module to use for communicating with this device. + // + uint32_t ui32Module; + + // + //! I2C address associated with this device. + // + uint32_t ui32BusAddress; + + // + //! Additional options that will ALWAYS be ORed into the command word. + // + uint32_t ui32Options; +} +am_hal_iom_i2c_device_t; + +//***************************************************************************** +// +// Typedef for non-blocking function callbacks. +// +//***************************************************************************** +typedef void (*am_hal_iom_callback_t)(void); + +//***************************************************************************** +// +// Typedef for a function that waits until the IOM queue is empty. +// +//***************************************************************************** +typedef void (*am_hal_iom_queue_flush_t)(uint32_t); + +extern am_hal_iom_queue_flush_t am_hal_iom_queue_flush; + + +//***************************************************************************** +// +// Operations +// +//***************************************************************************** +#define AM_HAL_IOM_QUEUE_SPI_WRITE 0 +#define AM_HAL_IOM_QUEUE_SPI_READ 1 +#define AM_HAL_IOM_QUEUE_I2C_WRITE 2 +#define AM_HAL_IOM_QUEUE_I2C_READ 3 + +//***************************************************************************** +// +// Structure to hold IOM operations. +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32Operation; + uint32_t ui32Module; + uint32_t ui32ChipSelect; + uint32_t *pui32Data; + uint32_t ui32NumBytes; + uint32_t ui32Options; + am_hal_iom_callback_t pfnCallback; +} +am_hal_iom_queue_entry_t; + +//***************************************************************************** +// +// Structure to hold IOM configuration during module power-down. +// +//***************************************************************************** +typedef struct +{ + uint32_t FIFOTHR; + uint32_t CLKCFG; + uint32_t CFG; + uint32_t INTEN; + uint32_t bValid; +} +am_hal_iom_pwrsave_t; + +//***************************************************************************** +// +// Global variables +// +//***************************************************************************** +extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_iom_pwrctrl_enable(uint32_t ui32Module); +extern void am_hal_iom_pwrctrl_disable(uint32_t ui32Module); +extern void am_hal_iom_power_on_restore(uint32_t ui32Module); +extern void am_hal_iom_power_off_save(uint32_t ui32Module); +extern void am_hal_iom_config(uint32_t ui32Module, + const am_hal_iom_config_t *psConfig); +extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module); +extern void am_hal_iom_enable(uint32_t ui32Module); +extern void am_hal_iom_disable(uint32_t ui32Module); +extern am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options); + +extern am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern void am_hal_iom_spi_cmd_run(uint32_t ui32Operation, + uint32_t ui32Module, + uint32_t ui32ChipSelect, + uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, + uint32_t ui32Module, + uint32_t ui32BusAddress, + uint32_t ui32NumBytes, + uint32_t ui32Options); +extern void am_hal_iom_command_repeat_set(uint32_t ui32Module, + uint32_t ui32CmdCount); +extern uint32_t am_hal_iom_status_get(uint32_t ui32Module); +extern am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module); +extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes); +extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes); +extern uint8_t am_hal_iom_fifo_empty_slots(uint32_t ui32Module); +extern uint8_t am_hal_iom_fifo_full_slots(uint32_t ui32Module); +extern void am_hal_iom_poll_complete(uint32_t ui32Module); +extern void am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status); +extern void am_hal_iom_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt); +extern uint32_t am_hal_iom_int_enable_get(uint32_t ui32Module); +extern void am_hal_iom_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt); +extern void am_hal_iom_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt); +extern void am_hal_iom_int_set(uint32_t ui32Module, uint32_t ui32Interrupt); +extern uint32_t am_hal_iom_int_status_get(uint32_t ui32Module, bool bEnabledOnly); +extern void am_hal_iom_queue_init(uint32_t ui32ModuleNum, + am_hal_iom_queue_entry_t *psQueueMemory, + uint32_t ui32QueueMemSize); +extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module); +extern void am_hal_iom_sleeping_queue_flush(uint32_t ui32Module); +extern am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, + uint32_t *pui32Data, uint32_t ui32NumBytes, + uint32_t ui32Options, + am_hal_iom_callback_t pfnCallback); +extern void am_hal_iom_queue_start_next_msg(uint32_t ui32Module); +extern void am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Status); + +//***************************************************************************** +// +// Helper functions. +// +//***************************************************************************** +#define AM_IOMASTER_ISR_QUEUE(x) \ +void am_iomaster##x##_isr(void) \ +{ \ + uint32_t ui32IntStatus; \ + ui32IntStatus = am_hal_iom_int_status_get(x, false); \ + am_hal_iom_int_clear(x, ui32IntStatus); \ + am_hal_iom_queue_service(x, ui32IntStatus); \ +} + +#define AM_IOMASTER_ISR_NB(x) \ +void am_iomaster##x##_isr(void) \ +{ \ + uint32_t ui32IntStatus; \ + ui32IntStatus = am_hal_iom_int_status_get(x, false); \ + am_hal_iom_int_clear(x, ui32IntStatus); \ + am_hal_iom_int_service(x, ui32IntStatus); \ +} + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_IOM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_ios.c b/mcu/apollo2/hal/am_hal_ios.c new file mode 100644 index 0000000..d9b7c45 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_ios.c @@ -0,0 +1,1362 @@ +//***************************************************************************** +// +// am_hal_ios.c +//! @file +//! +//! @brief Functions for interfacing with the IO Slave module +//! +//! @addtogroup ios2 IO Slave (SPI/I2C) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// SRAM Buffer structure +// +//***************************************************************************** +typedef struct +{ + uint8_t *pui8Data; + volatile uint32_t ui32WriteIndex; + volatile uint32_t ui32ReadIndex; + volatile uint32_t ui32Length; + uint32_t ui32FifoInc; + uint32_t ui32Capacity; +} +am_hal_ios_buffer_t; + +am_hal_ios_buffer_t g_sSRAMBuffer; + +//***************************************************************************** +// +// Forward declarations of static funcitons. +// +//***************************************************************************** +static void am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, + void *pvArray, uint32_t ui32Bytes); + +static void fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes); + +//***************************************************************************** +// +// Function-like macros. +// +//***************************************************************************** +#define am_hal_ios_buffer_empty(psBuffer) \ + ((psBuffer)->ui32Length == 0) + +#define am_hal_ios_buffer_full(psBuffer) \ + ((psBuffer)->ui32Length == (psBuffer)->ui32Capacity) + +#define am_hal_ios_buffer_data_left(psBuffer) \ + ((psBuffer)->ui32Length) + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +volatile uint8_t * const am_hal_ios_pui8LRAM = (uint8_t *)REG_IOSLAVE_BASEADDR; +uint8_t *g_pui8FIFOBase = (uint8_t *) REG_IOSLAVE_BASEADDR; +uint8_t *g_pui8FIFOEnd = (uint8_t *) REG_IOSLAVE_BASEADDR; +uint8_t *g_pui8FIFOPtr = (uint8_t *) REG_IOSLAVE_BASEADDR; +uint8_t g_ui32HwFifoSize = 0; +uint32_t g_ui32FifoBaseOffset = 0; + +//***************************************************************************** +// +// Checks to see if this processor is a Rev B2 device. +// +// This is needed to disable SHELBY-1654 workaround. +// +//***************************************************************************** +bool +isRevB2(void) +{ + // + // Check to make sure the major rev is B and the minor rev is 2. + // + return ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == \ + (AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | (AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 + 2)) ); +} + +//***************************************************************************** +// +//! @brief Enable the IOS in the power control block. +//! +//! This function enables the IOS module in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_pwrctrl_enable(void) +{ + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOS); +} + +//***************************************************************************** +// +//! @brief Disable the IOS in the power control block. +//! +//! This function disables the IOS module in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_pwrctrl_disable(void) +{ + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_IOS); +} + +//***************************************************************************** +// +//! @brief Enables the IOS module +//! +//! This function enables the IOSLAVE module using the IFCEN bitfield in the +//! IOSLAVE_CFG register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_enable(uint32_t ui32Module) +{ + AM_REGn(IOSLAVE, ui32Module, CFG) |= AM_REG_IOSLAVE_CFG_IFCEN(1); +} + +//***************************************************************************** +// +//! @brief Disables the IOSLAVE module. +//! +//! This function disables the IOSLAVE module using the IFCEN bitfield in the +//! IOSLAVE_CFG register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_disable(uint32_t ui32Module) +{ + AM_REGn(IOSLAVE, ui32Module, CFG) &= ~(AM_REG_IOSLAVE_CFG_IFCEN(1)); +} + +//***************************************************************************** +// +//! @brief Configure the IOS module. +//! +//! This function reads the an \e am_hal_ios_config_t structure and uses it to +//! set up the IO Slave module. Please see the information on the configuration +//! structure for more information on the parameters that may be set by this +//! function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_config(am_hal_ios_config_t *psConfig) +{ + uint32_t ui32LRAMConfig; + + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_IOS); + + // + // Record the FIFO parameters for later use. + // + g_pui8FIFOBase = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32FIFOBase); + g_pui8FIFOEnd = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32RAMBase); + g_ui32HwFifoSize = g_pui8FIFOEnd - g_pui8FIFOBase; + g_ui32FifoBaseOffset = psConfig->ui32FIFOBase; + + // + // Calculate the value for the IO Slave FIFO configuration register. + // + ui32LRAMConfig = AM_REG_IOSLAVE_FIFOCFG_ROBASE(psConfig->ui32ROBase >> 3); + ui32LRAMConfig |= AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(psConfig->ui32FIFOBase >> 3); + ui32LRAMConfig |= AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(psConfig->ui32RAMBase >> 3); + + // + // Just in case, disable the IOS + // + am_hal_ios_disable(0); + + // + // Write the configuration register with the user's selected interface + // characteristics. + // + AM_REG(IOSLAVE, CFG) = psConfig->ui32InterfaceSelect; + + // + // Write the FIFO configuration register to set the memory map for the LRAM. + // + AM_REG(IOSLAVE, FIFOCFG) = ui32LRAMConfig; + + // + // Enable the IOS. The following configuration options can't be set while + // the IOS is disabled. + // + am_hal_ios_enable(0); + + // + // Initialize the FIFO pointer to the beginning of the FIFO section. + // + am_hal_ios_fifo_ptr_set(psConfig->ui32FIFOBase); + + // + // Write the FIFO threshold register. + // + AM_REG(IOSLAVE, FIFOTHR) = psConfig->ui32FIFOThreshold; +} + +//***************************************************************************** +// +//! @brief Set bits in the HOST side IOINTCTL register. +//! +//! This function may be used to set an interrupt bit to the host. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_host_int_set(uint32_t ui32Interrupt) +{ + // + // Set a bit that will cause an interrupt to the host. + // + AM_REG(IOSLAVE, IOINTCTL) = AM_REG_IOSLAVE_IOINTCTL_IOINTSET(ui32Interrupt); +} + +//***************************************************************************** +// +//! @brief Clear bits in the HOST side IOINTCTL register. +//! +//! This function may be used to clear an interrupt bit to the host. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_host_int_clear(uint32_t ui32Interrupt) +{ + // + // Clear bits that will cause an interrupt to the host. + // + AM_REG(IOSLAVE, IOINTCTL) = AM_REG_IOSLAVE_IOINTCTL_IOINTCLR(ui32Interrupt); +} + +//***************************************************************************** +// +//! @brief Get the bits in the HOST side IOINTCTL register. +//! +//! This function may be used to read the host side interrupt bits. +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_ios_host_int_get(void) +{ + // + // return the value of the bits that will cause an interrupt to the host. + // + return AM_BFR(IOSLAVE, IOINTCTL, IOINT); +} + +//***************************************************************************** +// +//! @brief Get the enable bits in the HOST side IOINTCTL register. +//! +//! This function may be used to read the host side interrupt bits. +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_ios_host_int_enable_get(void) +{ + // + // return the value of the bits that will cause an interrupt to the host. + // + return AM_BFR(IOSLAVE, IOINTCTL, IOINTEN); +} + +//***************************************************************************** +// +//! @brief Enable an IOS Access Interrupt. +//! +//! This function may be used to enable an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_access_int_enable(uint32_t ui32Interrupt) +{ + // + // OR the desired interrupt into the enable register. + // + AM_REG(IOSLAVE, REGACCINTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return all enabled IOS Access Interrupts. +//! +//! This function may be used to return all enabled IOS Access interrupts. +//! +//! @return the enabled interrrupts. +// +//***************************************************************************** +uint32_t +am_hal_ios_access_int_enable_get(void) +{ + // + // Return the enabled interrupts. + // + return AM_REG(IOSLAVE, REGACCINTEN); +} + +//***************************************************************************** +// +//! @brief Disable an IOS Access Interrupt. +//! +//! This function may be used to disable an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_access_int_disable(uint32_t ui32Interrupt) +{ + // + // Clear the desired bit from the interrupt enable register. + // + AM_REG(IOSLAVE, REGACCINTEN) &= ~(ui32Interrupt); +} + +//***************************************************************************** +// +//! @brief Clear an IOS Access Interrupt. +//! +//! This function may be used to clear an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_access_int_clear(uint32_t ui32Interrupt) +{ + // + // Use the interrupt clear register to deactivate the chosen interrupt. + // + AM_REG(IOSLAVE, REGACCINTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Set an IOS Access Interrupt. +//! +//! This function may be used to set an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_access_int_set(uint32_t ui32Interrupt) +{ + // + // Use the interrupt set register to activate the chosen interrupt. + // + AM_REG(IOSLAVE, REGACCINTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Check the status of an IOS Access Interrupt. +//! +//! @param bEnabledOnly - return only the enabled interrupt status. +//! +//! This function may be used to return the enabled interrupt status. +//! +//! @return the enabled interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_ios_access_int_status_get(bool bEnabledOnly) +{ + if ( bEnabledOnly ) + { + uint32_t u32RetVal = AM_REG(IOSLAVE, REGACCINTSTAT); + return u32RetVal & AM_REG(IOSLAVE, REGACCINTEN); + + } + else + { + return AM_REG(IOSLAVE, REGACCINTSTAT); + } +} + +//***************************************************************************** +// +//! @brief Enable an IOS Interrupt. +//! +//! @param ui32Interrupt - desired interrupts. +//! +//! This function may be used to enable an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_int_enable(uint32_t ui32Interrupt) +{ + // + // OR the desired interrupt into the enable register. + // + AM_REG(IOSLAVE, INTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return all enabled IOS Interrupts. +//! +//! This function may be used to return all enabled IOS interrupts. +//! +//! @return the enabled interrrupts. +// +//***************************************************************************** +uint32_t +am_hal_ios_int_enable_get(void) +{ + // + // Return the enabled interrupts. + // + return AM_REG(IOSLAVE, INTEN); +} + +//***************************************************************************** +// +//! @brief Disable an IOS Interrupt. +//! +//! @param ui32Interrupt - desired interrupts. +//! +//! This function may be used to disable an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_int_disable(uint32_t ui32Interrupt) +{ + // + // Clear the desired bit from the interrupt enable register. + // + AM_REG(IOSLAVE, INTEN) &= ~(ui32Interrupt); +} + +//***************************************************************************** +// +//! @brief Clear an IOS Interrupt. +//! +//! @param ui32Interrupt - desired interrupts. +//! +//! This function may be used to clear an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_int_clear(uint32_t ui32Interrupt) +{ + // + // Use the interrupt clear register to deactivate the chosen interrupt. + // + AM_REG(IOSLAVE, INTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Set an IOS Interrupt. +//! +//! @param ui32Interrupt - desired interrupts. +//! +//! This function may be used to set an interrupt to the NVIC. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_int_set(uint32_t ui32Interrupt) +{ + // + // Use the interrupt clear register to deactivate the chosen interrupt. + // + AM_REG(IOSLAVE, INTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Write to the LRAM. +//! +//! @param ui32Offset - offset into the LRAM to write. +//! @param ui8Value - value to be written. +//! +//! This function writes ui8Value to offset ui32Offset inside the LRAM. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_lram_write(uint32_t ui32Offset, uint8_t ui8Value) +{ + // + // Write the LRAM. + // + am_hal_ios_pui8LRAM[ui32Offset] = ui8Value; +} + +//***************************************************************************** +// +//! @brief Read from the LRAM. +//! +//! @param ui32Offset - offset into the LRAM to read. +//! +//! This function read from offset ui32Offset inside the LRAM. +//! +//! @return the value at ui32Offset. +// +//***************************************************************************** +uint8_t +am_hal_ios_lram_read(uint32_t ui32Offset) +{ + // + // Read the LRAM. + // + return am_hal_ios_pui8LRAM[ui32Offset]; +} + +//***************************************************************************** +// +//! @brief Check the status of an IOS Interrupt. +//! +//! @param bEnabledOnly - return only the enabled interrupt status. +//! +//! This function may be used to return the enabled interrupt status. +//! +//! @return the enabled interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_ios_int_status_get(bool bEnabledOnly) +{ + if ( bEnabledOnly ) + { + uint32_t u32RetVal = AM_REG(IOSLAVE, INTSTAT); + return u32RetVal & AM_REG(IOSLAVE, INTEN); + + } + else + { + return AM_REG(IOSLAVE, INTSTAT); + } +} + +//***************************************************************************** +// +//! @brief Check the amount of space used in the FIFO +//! +//! This function returns the available data in the overall FIFO yet to be +//! read by the host. This takes into account the SRAM buffer and hardware FIFO +//! +//! @return Bytes used in the Overall FIFO. +// +//***************************************************************************** +uint32_t +am_hal_ios_fifo_space_used(void) +{ + uint32_t ui32Val; + uint32_t ui32Primask; + // + // Start a critical section for thread safety. + // + ui32Primask = am_hal_interrupt_master_disable(); + ui32Val = g_sSRAMBuffer.ui32Length; + ui32Val += AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ); + // + // End the critical section + // + am_hal_interrupt_master_set(ui32Primask); + return ui32Val; +} + + + +//***************************************************************************** +// +//! @brief Check the amount of space left in the FIFO +//! +//! This function returns the available space in the overall FIFO to accept +//! new data. This takes into account the SRAM buffer and hardware FIFO +//! +//! @return Bytes left in the Overall FIFO. +// +//***************************************************************************** +uint32_t +am_hal_ios_fifo_space_left(void) +{ + uint32_t ui32Val; + uint32_t ui32Primask; + // + // Start a critical section for thread safety. + // + ui32Primask = am_hal_interrupt_master_disable(); + // + // We waste one byte in HW FIFO + // + ui32Val = g_sSRAMBuffer.ui32Capacity + g_ui32HwFifoSize - 1; + ui32Val -= g_sSRAMBuffer.ui32Length; + ui32Val -= AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ); + // + // End the critical section + // + am_hal_interrupt_master_set(ui32Primask); + return ui32Val; +} + +//***************************************************************************** +// +//! @brief Check the amount of space left in the hardware FIFO +//! +//! This function reads the IOSLAVE FIFOPTR register and determines the amount +//! of space left in the IOS LRAM FIFO. +//! +//! @return Bytes left in the IOS FIFO. +// +//***************************************************************************** +static uint32_t +fifo_space_left(void) +{ + // + // We waste one byte in HW FIFO + // + return ((uint32_t)g_ui32HwFifoSize- AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ) - 1); +} + +//***************************************************************************** +// +// Helper function for managing IOS FIFO writes. +// +//***************************************************************************** +static void +fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) +{ + uint8_t *pFifoPtr = g_pui8FIFOPtr; + uint8_t *pFifoBase = g_pui8FIFOBase; + uint8_t *pFifoEnd = g_pui8FIFOEnd; + while ( ui32NumBytes ) + { + // + // Write the data to the FIFO + // + *pFifoPtr++ = *pui8Data++; + ui32NumBytes--; + + // + // Make sure to wrap the FIFO pointer if necessary. + // + if ( pFifoPtr == pFifoEnd ) + { + pFifoPtr = pFifoBase; + } + } + g_pui8FIFOPtr = pFifoPtr; +} + +// +// Assembly code below assumes 8bit FIFOSIZ field aligned at a byte boundary +// +#if (((AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M >> AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S) != 0xFF) \ + || (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S & 0x3)) +#error "FIFOSIZ not 8bit value aligned at byte offset" +#endif + +// +// Byte offset of FIFOSIZ field in FIFOPTR register +// +#define BYTEOFFSET_FIFOSIZE (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S >> 3) + +//***************************************************************************** +// +// Helper function in assembly for implementing the ReSync +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm static void +internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr) +{ + push {r3, r4} // Save r3, r4 - used by this function +internal_resync_fifoSize_loop + ldr r4, [r2] // Load FIFOPTR register in r4 + ubfx r3, r4, #AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S, #8 // Extract hwFifoSize to r3 + uxtb r4, r4 // Extract rdOffset in r4 + subs r4, r0, r4 // fifoSize in r4 = wrOffset - rdOffset + it cc // if (wrOffset < rdOffset), + addcc r4, r4, r1 // fifoSize = maxFifoSize - (rdOffset - wrOffset) + cmp r3, r4 // (hwFifoSize != fifoSize) + beq internal_resync_fifosize_done + strb r4, [r2, #1] // Overwrite FIFOSIZ value with fifoSize + b internal_resync_fifoSize_loop // Repeat the check +internal_resync_fifosize_done + pop {r3, r4} // Restore registers + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#if (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S != 8) +#error "AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S not 8" +#endif +__attribute__((naked)) +static void +internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr) +{ + __asm + ( + " push {r3,r4}\n\t" // Save r3, r4 - used by this function + "__internal_resync_fifoSize_loop:\n\t" + " ldr r4, [r2]\n\t" // Load FIFOPTR register in r4 + " ubfx r3, r4, #8, #8\n\t" // Extract hwFifoSize to r3 + " uxtb r4, r4\n\t" // Extract rdOffset in r4 + " subs r4, r0, r4\n\t" // fifoSize in r4 = wrOffset - rdOffset + " it cc\n\t" // if (wrOffset < rdOffset) + " addcc r4, r4, r1\n\t" // fifoSize = maxFifoSize - (rdOffset - wrOffset) + " cmp r3, r4\n\t" // (hwFifoSize != fifoSize) + " beq __internal_resync_fifosize_done\n\t" + " strb r4, [r2, #1]\n\t" // Overwrite FIFOSIZ value with fifoSize + " b __internal_resync_fifoSize_loop\n\t" // Repeat the check + "__internal_resync_fifosize_done:\n\t" + " pop {r3,r4}\n\t" // Restore registers + " bx lr\n\t" + ); +} +#elif defined(__GNUC_STDC_INLINE__) +#if (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S != 8) +#error "AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S not 8" +#endif +__attribute__((naked)) +static void +internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr) +{ + __asm + ( + " push {r3,r4}\n\t" // Save r3, r4 - used by this function + "__internal_resync_fifoSize_loop:\n\t" + " ldr r4, [r2]\n\t" // Load FIFOPTR register in r4 + " ubfx r3, r4, #8, #8\n\t" // Extract hwFifoSize to r3 + " uxtb r4, r4\n\t" // Extract rdOffset in r4 + " subs r4, r0, r4\n\t" // fifoSize in r4 = wrOffset - rdOffset + " it cc\n\t" // if (wrOffset < rdOffset) + " addcc r4, r4, r1\n\t" // fifoSize = maxFifoSize - (rdOffset - wrOffset) + " cmp r3, r4\n\t" // (hwFifoSize != fifoSize) + " beq __internal_resync_fifosize_done\n\t" + " strb r4, [r2, #1]\n\t" // Overwrite FIFOSIZ value with fifoSize + " b __internal_resync_fifoSize_loop\n\t" // Repeat the check + "__internal_resync_fifosize_done:\n\t" + " pop {r3,r4}\n\t" // Restore registers + " bx lr\n\t" + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#if (AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S != 8) +#error "AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S not 8" +#endif +__stackless static void +internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr) +{ + __asm volatile ( + " push {r3,r4}\n" // Save r3, r4 - used by this function + "__internal_resync_fifoSize_loop:\n" + " ldr r4, [r2]\n" // Load FIFOPTR register in r4 + " ubfx r3, r4, #8, #8\n" // Extract hwFifoSize to r3 + " uxtb r4, r4\n" // Extract rdOffset in r4 + " subs r4, r0, r4\n" // fifoSize in r4 = wrOffset - rdOffset + " it cc\n" + " addcc r4, r4, r1\n" // fifoSize = maxFifoSize - (rdOffset - wrOffset) + " cmp r3, r4\n" // (fifoSize != hwFifoSize) + " beq __internal_resync_fifosize_done\n" + " strb r4, [r2, #1]\n" // Overwrite FIFOSIZ value with fifoSize + " b __internal_resync_fifoSize_loop\n" // Repeat the check + "__internal_resync_fifosize_done:\n" + " pop {r3,r4}\n" // Restore registers + " bx lr\n" + ); +} + +#else +static void +internal_resync_fifoSize(uint32_t wrOffset, uint32_t maxFifoSize, uint32_t hwFifoPtrRegAddr) +{ + uint32_t fifoSize; + uint32_t hwFifoPtrReg; + uint32_t rdOffset; + uint32_t hwFifoSize; + + hwFifoPtrReg = AM_REGVAL(hwFifoPtrRegAddr); + rdOffset = ((hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S); + hwFifoSize = (hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S; + // By wasting one byte in hardware FIFO, we're guaranteed that fifoSize does not need special handling for FULL FIFO case + fifoSize = ((wrOffset >= rdOffset) ? (wrOffset - rdOffset) : (maxFifoSize - (rdOffset - wrOffset))); + while ( fifoSize != hwFifoSize ) + { + // Overwite correct FIFOSIZ + // Need to do a Byte Write to make sure the FIFOPTR is not overwritten + *((uint8_t *)(hwFifoPtrRegAddr + BYTEOFFSET_FIFOSIZE)) = fifoSize; + // Read back the register and check for consistency + hwFifoPtrReg = AM_REGVAL(hwFifoPtrRegAddr); + rdOffset = ((hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S); + hwFifoSize = (hwFifoPtrReg & AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M) >> AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S; + // By wasting one byte in hardware FIFO, we're guaranteed that fifoSize does not need special handling for FULL FIFO case + fifoSize = ((wrOffset >= rdOffset) ? (wrOffset - rdOffset) : (hwFifoSize - (rdOffset - wrOffset))); + } +} +#endif + +// +// Address of the FIFOPTR register +// +#define AM_REG_IOS_FIFOPTR (REG_IOSLAVE_BASEADDR + AM_REG_IOSLAVE_FIFOPTR_O) + +// When the FIFO is being replenished by the SW, at the same time as host is +// reading from it, there is a possible race condition, where the hardware decrement +// of FIFOSIZ as a result of read gets overwritten by hardware increment due to +// write. +// This function re-sync's the FIFOSIZ to ensure such errors do not accumulate +void +resync_fifoSize(void) +{ + uint32_t ui32Primask; + uint32_t wrOffset = (uint32_t)g_pui8FIFOPtr - (uint32_t)am_hal_ios_pui8LRAM; + // + // Start a critical section for thread safety. + // + ui32Primask = am_hal_interrupt_master_disable(); + internal_resync_fifoSize(wrOffset, g_ui32HwFifoSize, AM_REG_IOS_FIFOPTR); + // Clear interrupts for IOS which could be spuriously triggered + AM_REG(IOSLAVE, REGACCINTCLR) = (AM_HAL_IOS_INT_FSIZE | AM_HAL_IOS_INT_FOVFL | AM_HAL_IOS_INT_FUNDFL); + // + // End the critical section + // + am_hal_interrupt_master_set(ui32Primask); + return; +} + +//***************************************************************************** +// +//! @brief Transfer any available data from the IOS SRAM buffer to the FIFO. +//! +//! This function is meant to be called from an interrupt handler for the +//! ioslave module. It checks the IOS FIFO interrupt status for a threshold +//! event, and transfers data from an SRAM buffer into the IOS FIFO. +//! +//! @param ui32Status should be set to the ios interrupt status at the time of +//! ISR entry. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_fifo_service(uint32_t ui32Status) +{ + uint32_t thresh; + uint32_t freeSpace, usedSpace, chunk1, chunk2, ui32WriteIndex; + + // + // Check for FIFO size interrupts. + // + if ( ui32Status & AM_HAL_IOS_INT_FSIZE ) + { + thresh = AM_BFR(IOSLAVE, FIFOTHR, FIFOTHR); + + // + // While the FIFO is at or below threshold Add more data + // If Fifo level is above threshold, we're guaranteed an FSIZ interrupt + // + while ( g_sSRAMBuffer.ui32Length && + ((usedSpace = AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ)) <= thresh) ) + { + // + // So, we do have some data in SRAM which needs to be moved to FIFO. + // A chunk of data is a continguous set of bytes in SRAM that can be + // written to FIFO. Determine the chunks of data from SRAM that can + // be written. Up to two chunks possible + // + ui32WriteIndex = g_sSRAMBuffer.ui32WriteIndex; + chunk1 = ((ui32WriteIndex > (uint32_t)g_sSRAMBuffer.ui32ReadIndex) ? \ + (ui32WriteIndex - (uint32_t)g_sSRAMBuffer.ui32ReadIndex) : \ + (g_sSRAMBuffer.ui32Capacity - (uint32_t)g_sSRAMBuffer.ui32ReadIndex)); + chunk2 = g_sSRAMBuffer.ui32Length - chunk1; + // We waste one byte in HW FIFO + freeSpace = g_ui32HwFifoSize - usedSpace - 1; + // Write data in chunks + // Determine the chunks of data from SRAM that can be written + if ( chunk1 > freeSpace ) + { + fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace); + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += freeSpace; + // No need to check for wrap as we wrote less than chunk1 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= freeSpace; + } + else + { + fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk1); + + // + // Update the read index - wrapping as needed + // + g_sSRAMBuffer.ui32ReadIndex += chunk1; + g_sSRAMBuffer.ui32ReadIndex %= g_sSRAMBuffer.ui32Capacity; + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= chunk1; + freeSpace -= chunk1; + + if ( freeSpace && chunk2 ) + { + if ( chunk2 > freeSpace ) + { + fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace); + + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += freeSpace; + + // No need to check for wrap in chunk2 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= freeSpace; + } + else + { + fifo_write((uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk2); + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += chunk2; + + // No need to check for wrap in chunk2 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= chunk2; + } + } + } + if (!isRevB2()) + { + resync_fifoSize(); + } + + // + // Need to retake the FIFO space, after Threshold interrupt has been reenabled + // Clear any spurious FSIZE interrupt that might have got raised + // + AM_BFW(IOSLAVE, INTCLR, FSIZE, 1); + } + } +} + +//***************************************************************************** +// +//! @brief Writes the specified number of bytes to the IOS fifo. +//! +//! @param pui8Data is a pointer to the data to be written to the fifo. +//! @param ui32NumBytes is the number of bytes to send. +//! +//! This function will write data from the caller-provided array to the IOS +//! LRAM FIFO. If there is no space in the LRAM FIFO, the data will be copied +//! to a temporary SRAM buffer instead. +//! +//! The maximum message size for the IO Slave is 1023 bytes. +//! +//! @note In order for SRAM copy operations in the function to work correctly, +//! the \e am_hal_ios_buffer_service() function must be called in the ISR for +//! the ioslave module. +//! +//! @return Number of bytes written (could be less than ui32NumBytes, if not enough space) +// +//***************************************************************************** +uint32_t +am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) +{ + uint32_t ui32FIFOSpace; + uint32_t ui32SRAMSpace; + uint32_t ui32SRAMLength; + uint32_t ui32Primask; + uint32_t totalBytes = ui32NumBytes; + + // + // This operation will only work properly if an SRAM buffer has been + // allocated. Make sure that am_hal_ios_fifo_buffer_init() has been called, + // and the buffer pointer looks valid. + // + am_hal_debug_assert(g_sSRAMBuffer.pui8Data != 0); + + if ( ui32NumBytes == 0 ) + { + return 0; + } + + // + // Start a critical section for thread safety. + // + ui32Primask = am_hal_interrupt_master_disable(); + + ui32SRAMLength = g_sSRAMBuffer.ui32Length; + // + // End the critical section + // + am_hal_interrupt_master_set(ui32Primask); + + // + // If the SRAM buffer is empty, we should just write directly to the FIFO. + // + if ( ui32SRAMLength == 0 ) + { + ui32FIFOSpace = fifo_space_left(); + + // + // If the whole message fits, send it now. + // + if ( ui32NumBytes <= ui32FIFOSpace ) + { + fifo_write(pui8Data, ui32NumBytes); + ui32NumBytes = 0; + } + else + { + fifo_write(pui8Data, ui32FIFOSpace); + ui32NumBytes -= ui32FIFOSpace; + pui8Data += ui32FIFOSpace; + }; + if (!isRevB2()) + { + resync_fifoSize(); + } + } + + // + // If there's still data, write it to the SRAM buffer. + // + if ( ui32NumBytes ) + { + uint32_t idx, writeIdx, capacity, fifoSize; + ui32SRAMSpace = g_sSRAMBuffer.ui32Capacity - ui32SRAMLength; + + writeIdx = g_sSRAMBuffer.ui32WriteIndex; + capacity = g_sSRAMBuffer.ui32Capacity; + // + // Make sure that the data will fit inside the SRAM buffer. + // + if ( ui32SRAMSpace > ui32NumBytes ) + { + ui32SRAMSpace = ui32NumBytes; + } + + // + // If the data will fit, write it to the SRAM buffer. + // + for ( idx = 0; idx < ui32SRAMSpace; idx++ ) + { + g_sSRAMBuffer.pui8Data[(idx + writeIdx) % capacity] = pui8Data[idx]; + } + + ui32NumBytes -= idx; + // + // Start a critical section for thread safety before updating length & wrIdx. + // + ui32Primask = am_hal_interrupt_master_disable(); + // + // Advance the write index, making sure to wrap if necessary. + // + g_sSRAMBuffer.ui32WriteIndex = (idx + writeIdx) % capacity; + + // + // Update the length value appropriately. + // + g_sSRAMBuffer.ui32Length += idx; + // + // End the critical section + // + am_hal_interrupt_master_set(ui32Primask); + + // It is possible that there is a race condition that the FIFO level has + // gone below the threshold by the time we set the wrIdx above, and hence + // we may never get the threshold interrupt to serve the SRAM data we + // just wrote + + // If that is the case, explicitly generate the FSIZE interrupt from here + fifoSize = AM_BFR(IOSLAVE, FIFOPTR, FIFOSIZ); + if ( fifoSize <= AM_BFR(IOSLAVE, FIFOTHR, FIFOTHR) ) + { + AM_BFW(IOSLAVE, INTSET, FSIZE, 1); + } + } + + // Number of bytes written + g_sSRAMBuffer.ui32FifoInc += totalBytes - ui32NumBytes; + return (totalBytes - ui32NumBytes); +} + +//***************************************************************************** +// +//! @brief Writes the specified number of bytes to the IOS fifo simply. +//! +//! @param pui8Data is a pointer to the data to be written to the fifo. +//! @param ui32NumBytes is the number of bytes to send. +//! +//! This function will write data from the caller-provided array to the IOS +//! LRAM FIFO. This simple routine does not use SRAM buffering for large +//! messages. This function also updates the FIFOCTR. +//! +//! The maximum message size for the IO Slave is 128 bytes. +//! +//! @note Do note call the \e am_hal_ios_buffer_service() function in the ISR for +//! the ioslave module. +//! +//! @return +// +//***************************************************************************** +void +am_hal_ios_fifo_write_simple(uint8_t *pui8Data, uint32_t ui32NumBytes) +{ + uint32_t ui32FIFOSpace; + + // + // Check the FIFO and the SRAM buffer to see where we have space. + // + ui32FIFOSpace = fifo_space_left(); + + // + // If the whole message fits, send it now. + // + if ( ui32NumBytes <= ui32FIFOSpace ) + { + fifo_write(pui8Data, ui32NumBytes); + // Write FIFOINC + AM_BFW(IOSLAVE, FIFOINC, FIFOINC, ui32NumBytes); + } + else + { + // + // The message didn't fit. Try using am_hal_ios_fifo_write() instead. + // + am_hal_debug_assert_msg(0, "The requested IOS transfer didn't fit in" + "the LRAM FIFO. Try using am_hal_ios_fifo_write()."); + } +} + +//***************************************************************************** +// +//! @brief Sets the IOS FIFO pointer to the specified LRAM offset. +//! +//! @param ui32Offset is LRAM offset to set the FIFO pointer to. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_fifo_ptr_set(uint32_t ui32Offset) +{ + uint32_t ui32Primask; + + // + // Start a critical section for thread safety. + // + ui32Primask = am_hal_interrupt_master_disable(); + + // + // Set the FIFO Update bit. + // + AM_REG(IOSLAVE, FUPD) = 0x1; + + // + // Change the FIFO offset. + // + AM_REG(IOSLAVE, FIFOPTR) = ui32Offset; + + // + // Clear the FIFO update bit. + // + AM_REG(IOSLAVE, FUPD) = 0x0; + + // + // Set the global FIFO-pointer tracking variable. + // + g_pui8FIFOPtr = (uint8_t *) (REG_IOSLAVE_BASEADDR + ui32Offset); + + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Primask); +} + +//***************************************************************************** +// +// Initialize an SRAM buffer for use with the IO Slave. +// +//***************************************************************************** +static void +am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray, + uint32_t ui32Bytes) +{ + psBuffer->ui32WriteIndex = 0; + psBuffer->ui32ReadIndex = 0; + psBuffer->ui32Length = 0; + psBuffer->ui32Capacity = ui32Bytes; + psBuffer->ui32FifoInc = 0; + psBuffer->pui8Data = (uint8_t *)pvArray; +} + +//***************************************************************************** +// +//! @brief Poll for all host side read activity to complete. +//! +//! Poll for all host side read activity to complete. Use this before +//! calling am_hal_ios_fifo_write_simple(). +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_read_poll_complete(void) +{ + while ( AM_REG(IOSLAVE, FUPD) & AM_REG_IOSLAVE_FUPD_IOREAD_M ); +} + +//***************************************************************************** +// +//! @brief Initializes an SRAM buffer for the IOS FIFO. +//! +//! @param pui8Buffer is the SRAM buffer that will be used for IOS fifo data. +//! @param ui32BufferSize is the size of the SRAM buffer. +//! +//! This function provides the IOS HAL functions with working memory for +//! managing outgoing IOS FIFO transactions. It needs to be called at least +//! once before am_hal_ios_fifo_write() may be used. +//! +//! The recommended buffer size for the IOS FIFO is 1024 bytes. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes) +{ + // + // Initialize the global SRAM buffer + // Total size, which is SRAM Buffer plus the hardware FIFO needs to be + // limited to 1023 + // + if ( ui32NumBytes > (1023 - g_ui32HwFifoSize + 1) ) + { + ui32NumBytes = (1023 - g_ui32HwFifoSize + 1); + } + + am_hal_ios_buffer_init(&g_sSRAMBuffer, pui8Buffer, ui32NumBytes); + + // + // Clear the FIFO State + // + AM_BFW(IOSLAVE, FIFOCTR, FIFOCTR, 0x0); + AM_BFW(IOSLAVE, FIFOPTR, FIFOSIZ, 0x0); + + am_hal_ios_fifo_ptr_set(g_ui32FifoBaseOffset); +} + +//***************************************************************************** +// +//! @brief Update the FIFOCTR to inform host of available data to read. +//! +//! This function allows the application to indicate to HAL when it is safe to +//! update the FIFOCTR. This function needs to be used in conjunction with +//! am_hal_ios_fifo_write(), which itself does not update the FIFOCTR +//! +//! CAUTION: +//! Application needs to implement some sort of +//! synchronization with the host to make sure host is not reading FIFOCTR while +//! it is being updated by the MCU, since the FIFOCTR read over +//! IO is not an atomic operation. Otherwise, some other logic could be implemented +//! by the host to detect and disregard transient values of FIFOCTR (e.g. multiple +//! reads till it gets a stable value). +//! For Pre-B2 parts, it is necessary to have this synchronization guarantee that +//! Host is not doing any READ operation - be it for FIFOCTR or FIFO itself when +//! this call is made, as otherwise the FIFOCTR value may get corrupted. +//! +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ios_update_fifoctr(void) +{ + // Write FIFOINC + AM_BFW(IOSLAVE, FIFOINC, FIFOINC, g_sSRAMBuffer.ui32FifoInc); + g_sSRAMBuffer.ui32FifoInc = 0; + return; +} + +//***************************************************************************** +// +// End the doxygen group +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_ios.h b/mcu/apollo2/hal/am_hal_ios.h new file mode 100644 index 0000000..bafc25b --- /dev/null +++ b/mcu/apollo2/hal/am_hal_ios.h @@ -0,0 +1,362 @@ +//***************************************************************************** +// +// am_hal_ios.h +//! @file +//! +//! @brief Functions for interfacing with the IO Slave module +//! +//! @addtogroup ios2 IO Slave (SPI/I2C) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_IOS_H +#define AM_HAL_IOS_H + + +//***************************************************************************** +// +//! @name Interface Configuration +//! @brief Macro definitions for configuring the physical interface of the IO +//! Slave +//! +//! These macros may be used with the am_hal_ios_config_t structure to set the +//! physical parameters of the SPI/I2C slave module. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_USE_SPI AM_REG_IOSLAVE_CFG_IFCSEL_SPI +#define AM_HAL_IOS_SPIMODE_0 AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3 +#define AM_HAL_IOS_SPIMODE_1 AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2 +#define AM_HAL_IOS_SPIMODE_2 AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2 +#define AM_HAL_IOS_SPIMODE_3 AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3 + +#define AM_HAL_IOS_USE_I2C AM_REG_IOSLAVE_CFG_IFCSEL_I2C +#define AM_HAL_IOS_I2C_ADDRESS(n) AM_REG_IOSLAVE_CFG_I2CADDR(n) + +#define AM_HAL_IOS_LSB_FIRST AM_REG_IOSLAVE_CFG_LSB(1) +//! @} + +//***************************************************************************** +// +//! @name Register Access Interrupts +//! @brief Macro definitions for register access interrupts. +//! +//! These macros may be used with any of the +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_ACCESS_INT_00 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 31) +#define AM_HAL_IOS_ACCESS_INT_01 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 30) +#define AM_HAL_IOS_ACCESS_INT_02 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 29) +#define AM_HAL_IOS_ACCESS_INT_03 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 28) +#define AM_HAL_IOS_ACCESS_INT_04 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 27) +#define AM_HAL_IOS_ACCESS_INT_05 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 26) +#define AM_HAL_IOS_ACCESS_INT_06 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 25) +#define AM_HAL_IOS_ACCESS_INT_07 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 24) +#define AM_HAL_IOS_ACCESS_INT_08 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 23) +#define AM_HAL_IOS_ACCESS_INT_09 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 22) +#define AM_HAL_IOS_ACCESS_INT_0A AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 21) +#define AM_HAL_IOS_ACCESS_INT_0B AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 20) +#define AM_HAL_IOS_ACCESS_INT_0C AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 19) +#define AM_HAL_IOS_ACCESS_INT_0D AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 18) +#define AM_HAL_IOS_ACCESS_INT_0E AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 17) +#define AM_HAL_IOS_ACCESS_INT_0F AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 16) +#define AM_HAL_IOS_ACCESS_INT_13 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 15) +#define AM_HAL_IOS_ACCESS_INT_17 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 14) +#define AM_HAL_IOS_ACCESS_INT_1B AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 13) +#define AM_HAL_IOS_ACCESS_INT_1F AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 12) +#define AM_HAL_IOS_ACCESS_INT_23 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 11) +#define AM_HAL_IOS_ACCESS_INT_27 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 10) +#define AM_HAL_IOS_ACCESS_INT_2B AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 9) +#define AM_HAL_IOS_ACCESS_INT_2F AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 8) +#define AM_HAL_IOS_ACCESS_INT_33 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 7) +#define AM_HAL_IOS_ACCESS_INT_37 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 6) +#define AM_HAL_IOS_ACCESS_INT_3B AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 5) +#define AM_HAL_IOS_ACCESS_INT_3F AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 4) +#define AM_HAL_IOS_ACCESS_INT_43 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 3) +#define AM_HAL_IOS_ACCESS_INT_47 AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 2) +#define AM_HAL_IOS_ACCESS_INT_4B AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 1) +#define AM_HAL_IOS_ACCESS_INT_4F AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 0) +#define AM_HAL_IOS_ACCESS_INT_ALL 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! @name I/O Slave Interrupts +//! @brief Macro definitions for I/O slave (IOS) interrupts. +//! +//! These macros may be used with any of the +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_INT_FSIZE AM_REG_IOSLAVE_INTEN_FSIZE_M +#define AM_HAL_IOS_INT_FOVFL AM_REG_IOSLAVE_INTEN_FOVFL_M +#define AM_HAL_IOS_INT_FUNDFL AM_REG_IOSLAVE_INTEN_FUNDFL_M +#define AM_HAL_IOS_INT_FRDERR AM_REG_IOSLAVE_INTEN_FRDERR_M +#define AM_HAL_IOS_INT_GENAD AM_REG_IOSLAVE_INTEN_GENAD_M +#define AM_HAL_IOS_INT_IOINTW AM_REG_IOSLAVE_INTEN_IOINTW_M +#define AM_HAL_IOS_INT_XCMPWR AM_REG_IOSLAVE_INTEN_XCMPWR_M +#define AM_HAL_IOS_INT_XCMPWF AM_REG_IOSLAVE_INTEN_XCMPWF_M +#define AM_HAL_IOS_INT_XCMPRR AM_REG_IOSLAVE_INTEN_XCMPRR_M +#define AM_HAL_IOS_INT_XCMPRF AM_REG_IOSLAVE_INTEN_XCMPRF_M +#define AM_HAL_IOS_INT_ALL 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! @name I/O Slave Interrupts triggers +//! @brief Macro definitions for I/O slave (IOS) interrupts. +//! +//! These macros may be used with am_hal_ios_int_set and am_hal_ios_int_clear +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_IOINTCTL_INT0 (0x01) +#define AM_HAL_IOS_IOINTCTL_INT1 (0x02) +#define AM_HAL_IOS_IOINTCTL_INT2 (0x04) +#define AM_HAL_IOS_IOINTCTL_INT3 (0x08) +#define AM_HAL_IOS_IOINTCTL_INT4 (0x10) +#define AM_HAL_IOS_IOINTCTL_INT5 (0x20) +//! @} + +//***************************************************************************** +// +// External variable definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief LRAM pointer +//! +//! Pointer to the base of the IO Slave LRAM. +// +//***************************************************************************** +extern volatile uint8_t * const am_hal_ios_pui8LRAM; + +//***************************************************************************** +// +//! @brief Configuration structure for the IO slave module. +//! +//! This structure may be used along with the am_hal_ios_config() function to +//! select key parameters of the IO Slave module. See the descriptions of each +//! parameter within this structure for more information on what they control. +// +//***************************************************************************** +typedef struct +{ + // + //! Interface Selection + //! + //! This word selects the physical behavior of the IO Slave port. For SPI + //! mode, this word should be the logical OR of one or more of the + //! following: + //! + //! AM_HAL_IOS_USE_SPI + //! AM_HAL_IOS_SPIMODE_0 + //! AM_HAL_IOS_SPIMODE_1 + //! AM_HAL_IOS_SPIMODE_2 + //! AM_HAL_IOS_SPIMODE_3 + //! + //! For I2C mode, use the logical OR of one or more of these values instead + //! (where n is the 7 or 10-bit I2C address to use): + //! + //! AM_HAL_IOS_USE_I2C + //! AM_HAL_IOS_I2C_ADDRESS(n) + //! + //! Also, in any mode, you may OR in this value to reverse the order of + //! incoming data bits. + //! + //! AM_HAL_IOS_LSB_FIRST + // + uint32_t ui32InterfaceSelect; + + // + //! Read-Only section + //! + //! The IO Slave LRAM is split into three main sections. The first section + //! is a "Direct Write" section, which may be accessed for reads or write + //! either directly through the Apollo CPU, or over the SPI/I2C bus. The + //! "Direct Write" section always begins at LRAM offset 0x0. At the end of + //! the normal "Direct Write" space, there is a "Read Only" space, which is + //! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI + //! Bus. This word selects the base address of this "Read Only" space. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x78, + //! inclusive. For the configuration to be valid, \e ui32ROBase must also + //! be less than or equal to \e ui32FIFOBase + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "Read Only" space may only be set in 8-byte increments, this + //! value must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32ROBase; + + // + //! FIFO section + //! + //! After the "Direct Access" and "Read Only" sections is a section of LRAM + //! allocated to a FIFO. This section is accessible by the Apollo CPU + //! through the FIFO control registers, and accessible on the SPI/I2C bus + //! through the 0x7F address. This word selects the base address of the + //! FIFO space. The FIFO will extend from the address specified here to the + //! address specified in \e ui32RAMBase. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x78, + //! inclusive. For the configuration to be valid, \e ui32FIFOBase must also + //! be greater than or equal to \e ui32ROBase. + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "FIFO" space may only be set in 8-byte increments, this value + //! must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32FIFOBase; + + // + //! RAM section + //! + //! At the end of the IOS LRAM, the user may allocate a "RAM" space that + //! can only be accessed by the Apollo CPU. This space will not interact + //! with the SPI/I2C bus at all, and may be used as general-purpose memory. + //! Unlike normal SRAM, this section of LRAM will retain its state through + //! Deep Sleep, so it may be used as a data retention space for + //! ultra-low-power applications. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x100, + //! inclusive. For the configuration to be valid, \e ui32RAMBase must also + //! be greater than or equal to \e ui32FIFOBase. + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "FIFO" space may only be set in 8-byte increments, this value + //! must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32RAMBase; + + // + //! FIFO threshold + //! + //! The IO Slave module will trigger an interrupt when the number of + //! entries in the FIFO drops below this number of bytes. + // + uint32_t ui32FIFOThreshold; + + // + // Pointer to an SRAM + // + uint8_t *pui8SRAMBuffer; +} +am_hal_ios_config_t; + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_ios_enable(uint32_t ui32Module); +extern void am_hal_ios_disable(uint32_t ui32Module); + +// these interrupts drive the HOST side IOS interrupt pins +extern void am_hal_ios_host_int_set(uint32_t ui32Interrupt); +extern void am_hal_ios_host_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_ios_host_int_get(void); +extern uint32_t am_hal_ios_host_int_enable_get(void); + +extern void am_hal_ios_lram_write(uint32_t ui32Offset, uint8_t ui8Value); +extern uint8_t am_hal_ios_lram_read(uint32_t ui32Offset); + +// the following interrupts go back to the NVIC +extern void am_hal_ios_config(am_hal_ios_config_t *psConfig); +extern void am_hal_ios_access_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_ios_access_int_enable_get(void); +extern void am_hal_ios_access_int_disable(uint32_t ui32Interrupt); +extern void am_hal_ios_access_int_clear(uint32_t ui32Interrupt); +extern void am_hal_ios_access_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_ios_access_int_status_get(bool bEnabledOnly); +extern void am_hal_ios_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_ios_int_enable_get(void); +extern void am_hal_ios_int_disable(uint32_t ui32Interrupt); +extern void am_hal_ios_int_clear(uint32_t ui32Interrupt); +extern void am_hal_ios_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_ios_int_status_get(bool bEnabledOnly); + +extern void am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes); +extern uint32_t am_hal_ios_fifo_space_left(void); +extern uint32_t am_hal_ios_fifo_space_used(void); +extern void am_hal_ios_fifo_service(uint32_t ui32Status); +// Returns the number of bytes actually written +extern uint32_t am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes); +extern void am_hal_ios_fifo_write_simple(uint8_t *pui8Data, + uint32_t ui32NumBytes); +extern void am_hal_ios_fifo_ptr_set(uint32_t ui32Offset); +extern void am_hal_ios_update_fifoctr(void); + +extern void am_hal_ios_read_poll_complete(void); +extern void am_hal_ios_pwrctrl_enable(void); +extern void am_hal_ios_pwrctrl_disable(void); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_IOS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_itm.c b/mcu/apollo2/hal/am_hal_itm.c new file mode 100644 index 0000000..9f473d3 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_itm.c @@ -0,0 +1,430 @@ +//***************************************************************************** +// +// am_hal_itm.c +//! @file +//! +//! @brief Functions for operating the instrumentation trace macrocell +//! +//! @addtogroup itm2 Instrumentation Trace Macrocell (ITM) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Enables the ITM +//! +//! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_enable(void) +{ + if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M) + { + return; + } + + // + // To be able to access ITM registers, set the Trace Enable bit + // in the Debug Exception and Monitor Control Register (DEMCR). + // + AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1); + while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) ); + + // + // Write the key to the ITM Lock Access register to unlock the ITM_TCR. + // + AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL; + + // + // Set the enable bits in the ITM trace enable register, and the ITM + // control registers to enable trace data output. + // + AM_REGVAL(AM_REG_ITM_TPR_O) = 0x0000000f; + AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff; + + // + // Write to the ITM control and status register. + // + AM_REGVAL(AM_REG_ITM_TCR_O) = + AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15) | + AM_WRITE_SM(AM_REG_ITM_TCR_TS_FREQ, 1) | + AM_WRITE_SM(AM_REG_ITM_TCR_TS_PRESCALE, 1) | + AM_WRITE_SM(AM_REG_ITM_TCR_SWV_ENABLE, 1) | + AM_WRITE_SM(AM_REG_ITM_TCR_DWT_ENABLE, 0) | + AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0) | + AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0) | + AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1); + +} + +//***************************************************************************** +// +//! @brief Disables the ITM +//! +//! This function completely disables the ARM ITM by resetting the TRCENA bit +//! in the DEMCR register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_disable(void) +{ + + if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M) + { + return; + } + + // + // Make sure the ITM_TCR is unlocked. + // + AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL; + + // + // Make sure the ITM/TPIU is not busy. + // + while ( AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1) ); + + // + // Disable the ITM. + // + for (int ix = 0; ix < 100; ix++) + { + AM_REG(ITM, TCR) &= ~AM_REG_ITM_TCR_ITM_ENABLE(1); + while ( AM_REG(ITM, TCR) & (AM_REG_ITM_TCR_ITM_ENABLE(1) | AM_REG_ITM_TCR_BUSY(1)) ); + } + + // + // Reset the TRCENA bit in the DEMCR register, which should disable the ITM + // for operation. + // + AM_REG(SYSCTRL, DEMCR) &= ~AM_REG_SYSCTRL_DEMCR_TRCENA(1); + + // + // Disable the TPIU clock source in MCU control. + // + AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz | + AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS; +} + +//***************************************************************************** +// +//! @brief Checks if itm is busy and provides a delay to flush the fifo +//! +//! This function disables the ARM ITM by resetting the TRCENA bit in the DEMCR +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_not_busy(void) +{ + // + // Make sure the ITM/TPIU is not busy. + // + while (AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1)); + + // + // wait for 50us for the data to flush out + // + am_hal_flash_delay(FLASH_CYCLES_US(50)); +} + +//***************************************************************************** +// +//! @brief Enables tracing on a given set of ITM ports +//! +//! @param ui8portNum - Set ports to be enabled +//! +//! Enables tracing on the ports referred to by \e ui8portNum by writing the +//! associated bit in the Trace Privilege Register in the ITM. The value for +//! ui8portNum should be the logical OR one or more of the following values: +//! +//! \e ITM_PRIVMASK_0_7 - enable ports 0 through 7 +//! \e ITM_PRIVMASK_8_15 - enable ports 8 through 15 +//! \e ITM_PRIVMASK_16_23 - enable ports 16 through 23 +//! \e ITM_PRIVMASK_24_31 - enable ports 24 through 31 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_trace_port_enable(uint8_t ui8portNum) +{ + AM_REGVAL(AM_REG_ITM_TPR_O) |= (0x00000001 << (ui8portNum>>3)); +} + +//***************************************************************************** +// +//! @brief Disable tracing on the given ITM stimulus port. +//! +//! @param ui8portNum +//! +//! Disables tracing on the ports referred to by \e ui8portNum by writing the +//! associated bit in the Trace Privilege Register in the ITM. The value for +//! ui8portNum should be the logical OR one or more of the following values: +//! +//! \e ITM_PRIVMASK_0_7 - disable ports 0 through 7 +//! \e ITM_PRIVMASK_8_15 - disable ports 8 through 15 +//! \e ITM_PRIVMASK_16_23 - disable ports 16 through 23 +//! \e ITM_PRIVMASK_24_31 - disable ports 24 through 31 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_trace_port_disable(uint8_t ui8portNum) +{ + AM_REGVAL(AM_REG_ITM_TPR_O) &= ~(0x00000001 << (ui8portNum >> 3)); +} + +//***************************************************************************** +// +//! @brief Poll the given ITM stimulus register until not busy. +//! +//! @param ui32StimReg - stimulus register +//! +//! @return true if not busy, false if busy (timed out or other error). +// +//***************************************************************************** +bool +am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg) +{ + uint32_t ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg)); + + // + // Busy waiting until it is available, non-zero means ready. + // + while (!AM_REGVAL(ui32StimAddr)); + + return true; +} + +//***************************************************************************** +// +//! @brief Writes a 32-bit value to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui32Value - value to be written. +//! +//! Write a word to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, uint32_t ui32Value) +{ + uint32_t ui32StimAddr; + + ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg)); + + // + // Busy waiting until it is available, non-zero means ready + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + AM_REGVAL(ui32StimAddr) = ui32Value; +} + +//***************************************************************************** +// +//! @brief Writes a short to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui16Value - short to be written. +//! +//! Write a short to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, uint16_t ui16Value) +{ + uint32_t ui32StimAddr; + + ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg)); + + // + // Busy waiting until it is available non-zero means ready + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + *((volatile uint16_t *) ui32StimAddr) = ui16Value; +} + +//***************************************************************************** +// +//! @brief Writes a byte to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui8Value - byte to be written. +//! +//! Write a byte to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, uint8_t ui8Value) +{ + uint32_t ui32StimAddr; + + ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg)); + + // + // Busy waiting until it is available (non-zero means ready) + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + *((volatile uint8_t *) ui32StimAddr) = ui8Value; +} + +//***************************************************************************** +// +//! @brief Sends a Sync Packet. +//! +//! Sends a sync packet. This can be useful for external software should it +//! become out of sync with the ITM stream. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_sync_send(void) +{ + // + // Write the register. + // + am_hal_itm_stimulus_reg_word_write(AM_HAL_ITM_SYNC_REG, + AM_HAL_ITM_SYNC_VAL); +} + +//***************************************************************************** +// +//! @brief Poll the print stimulus registers until not busy. +//! +//! @return true if not busy, false if busy (timed out or other error). +// +//***************************************************************************** +bool +am_hal_itm_print_not_busy(void) +{ + // + // Poll stimulus register allocated for printing. + // + am_hal_itm_stimulus_not_busy(0); + + + return true; +} + +//***************************************************************************** +// +//! @brief Prints a char string out of the ITM. +//! +//! @param pcString pointer to the character sting +//! +//! This function prints a sting out of the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_print(char *pcString) +{ + uint32_t ui32Length = 0; + + // + // Determine the length of the string. + // + while (*(pcString + ui32Length)) + { + ui32Length++; + } + + // + // If there is no longer a word left, empty out the remaining characters. + // + while (ui32Length) + { + // + // Print string out the ITM. + // + am_hal_itm_stimulus_reg_byte_write(0, (uint8_t)*pcString++); + + // + // Subtract from length. + // + ui32Length--; + } +} +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_itm.h b/mcu/apollo2/hal/am_hal_itm.h new file mode 100644 index 0000000..6215016 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_itm.h @@ -0,0 +1,106 @@ +//***************************************************************************** +// +// am_hal_itm.h +//! @file +//! +//! @brief Functions for accessing and configuring the ARM ITM. +//! +//! @addtogroup itm2 Instrumentation Trace Macrocell (ITM) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_HAL_ITM_H +#define AM_HAL_ITM_H + +//***************************************************************************** +// +// Sync Packet Defines +// +//***************************************************************************** +#define AM_HAL_ITM_SYNC_REG 23 +#define AM_HAL_ITM_SYNC_VAL 0xF8F8F8F8 + +//***************************************************************************** +// +// PrintF Setup +// +//***************************************************************************** +#define AM_HAL_ITM_PRINT_NUM_BYTES 1 +#define AM_HAL_ITM_PRINT_NUM_REGS 1 +extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS]; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_itm_enable(void); +extern void am_hal_itm_disable(void); +extern void am_hal_itm_not_busy(void); +extern void am_hal_itm_sync_send(void); +extern void am_hal_itm_trace_port_enable(uint8_t ui8portNum); +extern void am_hal_itm_trace_port_disable(uint8_t ui8portNum); +extern bool am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg); +extern void am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, + uint32_t ui32Value); +extern void am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, + uint16_t ui16Value); +extern void am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, + uint8_t ui8Value); +extern bool am_hal_itm_print_not_busy(void); +extern void am_hal_itm_print(char *pcString); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_ITM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_mcuctrl.c b/mcu/apollo2/hal/am_hal_mcuctrl.c new file mode 100644 index 0000000..df0303a --- /dev/null +++ b/mcu/apollo2/hal/am_hal_mcuctrl.c @@ -0,0 +1,265 @@ +//***************************************************************************** +// +// am_hal_mcuctrl.c +//! @file +//! +//! @brief Functions for interfacing with the MCUCTRL. +//! +//! @addtogroup mcuctrl2 MCU Control (MCUCTRL) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +#define LDO_TRIM_REG_ADDR (0x50023004) +#define BUCK_TRIM_REG_ADDR (0x50023000) + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +// +// Define the flash sizes from CHIP_INFO. +// +const uint32_t +g_am_hal_mcuctrl_flash_size[AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_N] = +{ + 16 * 1024, /* 0x0 0x00004000 16 KB */ + 32 * 1024, /* 0x1 0x00008000 32 KB */ + 64 * 1024, /* 0x2 0x00010000 64 KB */ + 128 * 1024, /* 0x3 0x00020000 128 KB */ + 256 * 1024, /* 0x4 0x00040000 256 KB */ + 512 * 1024, /* 0x5 0x00080000 512 KB */ + 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */ + 2 * 1024 * 1024, /* 0x7 0x00200000 2 MB */ +}; + +// +// Define the SRAM sizes from CHIP_INFO. +// For Apollo2, the SRAM sizes are defined exactly the same as the flash sizes. +// +#define g_am_hal_mcuctrl_sram_size g_am_hal_mcuctrl_flash_size + +//***************************************************************************** +// +//! @brief Gets all relevant device information. +//! +//! @param psDevice is a pointer to a structure that will be used to store all +//! device info. +//! +//! This function gets the device part number, chip IDs, and revision and +//! stores them in the passed structure. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice) +{ + // + // Read the Part Number. + // + psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO); + + // + // Read the Chip ID0. + // + psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0); + + // + // Read the Chip ID1. + // + psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1); + + // + // Read the Chip Revision. + // + psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV); + + // + // Read the Chip VENDOR ID. + // + psDevice->ui32VendorID = AM_REG(MCUCTRL, VENDORID); + + // + // Qualified from Part Number. + // + psDevice->ui32Qualified = + (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_QUAL_M) >> + AM_HAL_MCUCTRL_CHIP_INFO_QUAL_S; + + // + // Flash size from Part Number. + // + psDevice->ui32FlashSize = + g_am_hal_mcuctrl_flash_size[ + (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M) >> + AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S]; + + // + // SRAM size from Part Number. + // + psDevice->ui32SRAMSize = + g_am_hal_mcuctrl_sram_size[ + (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M) >> + AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S]; + + // + // Now, let's look at the JEDEC info. + // The full partnumber is 12 bits total, but is scattered across 2 registers. + // Bits [11:8] are 0xE. + // Bits [7:4] are 0xE for Apollo, 0xD for Apollo2. + // Bits [3:0] are defined differently for Apollo and Apollo2. + // For Apollo, the low nibble is 0x0. + // For Apollo2, the low nibble indicates flash and SRAM size. + // + psDevice->ui32JedecPN = (AM_BFR(JEDEC, PID0, PNL8) << 0); + psDevice->ui32JedecPN |= (AM_BFR(JEDEC, PID1, PNH4) << 8); + + // + // JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as + // 0x1B, with parity bit is 0x9B. It is 8 bits located across 2 registers. + // + psDevice->ui32JedecJEPID = (AM_BFR(JEDEC, PID1, JEPIDL) << 0); + psDevice->ui32JedecJEPID |= (AM_BFR(JEDEC, PID2, JEPIDH) << 4); + + // + // CHIPREV is 8 bits located across 2 registers. + // + psDevice->ui32JedecCHIPREV = (AM_BFR(JEDEC, PID2, CHIPREVH4) << 4); + psDevice->ui32JedecCHIPREV |= (AM_BFR(JEDEC, PID3, CHIPREVL4) << 0); + + // + // Let's get the Coresight ID (32-bits across 4 registers) + // For Apollo and Apollo2, it's expected to be 0xB105100D. + // + psDevice->ui32JedecCID = (AM_BFR(JEDEC, CID3, CID) << 24); + psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID2, CID) << 16); + psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID1, CID) << 8); + psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID0, CID) << 0); +} + +//***************************************************************************** +// +//! @brief Enables the fault capture registers. +//! +//! This function enables the DCODEFAULTADDR and ICODEFAULTADDR registers. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_mcuctrl_fault_capture_enable(void) +{ + // + // Enable the Fault Capture registers. + // + AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 1); +} + +//***************************************************************************** +// +//! @brief Disables the fault capture registers. +//! +//! This function disables the DCODEFAULTADDR and ICODEFAULTADDR registers. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_mcuctrl_fault_capture_disable(void) +{ + // + // Disable the Fault Capture registers. + // + AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 0); +} + +//***************************************************************************** +// +//! @brief Gets the fault status and capture registers. +//! +//! @param psFault is a pointer to a structure that will be used to store all +//! fault info. +//! +//! This function gets the status of the ICODE, DCODE, and SYS bus faults and +//! the addresses associated with the fault. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault) +{ + uint32_t ui32FaultStat; + + // + // Read the Fault Status Register. + // + ui32FaultStat = AM_REG(MCUCTRL, FAULTSTATUS); + psFault->bICODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M); + psFault->bDCODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M); + psFault->bSYS = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_SYS_M); + + // + // Read the DCODE fault capture address register. + // + psFault->ui32DCODE = AM_REG(MCUCTRL, DCODEFAULTADDR); + + // + // Read the ICODE fault capture address register. + // + psFault->ui32ICODE |= AM_REG(MCUCTRL, ICODEFAULTADDR); + + // + // Read the ICODE fault capture address register. + // + psFault->ui32SYS |= AM_REG(MCUCTRL, SYSFAULTADDR); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_mcuctrl.h b/mcu/apollo2/hal/am_hal_mcuctrl.h new file mode 100644 index 0000000..2ef3e7b --- /dev/null +++ b/mcu/apollo2/hal/am_hal_mcuctrl.h @@ -0,0 +1,216 @@ +//***************************************************************************** +// +// am_hal_mcuctrl.h +//! @file +//! +//! @brief Functions for accessing and configuring the MCUCTRL. +//! +//! @addtogroup mcuctrl2 MCU Control (MCUCTRL) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_MCUCTRL_H +#define AM_HAL_MCUCTRL_H + +// +// Deprecate the am_hal_mcuctrl_bucks_enable() and disable() functions. +// This functionality is now handled in pwrctrl. +// +#if 0 +#define am_hal_mcuctrl_bucks_enable am_hal_pwrctrl_bucks_enable +#define am_hal_mcuctrl_bucks_disable am_hal_pwrctrl_bucks_disable +#endif + + +//***************************************************************************** +// +// Define CHIP_INFO fields, which for Apollo2 are not defined in the register +// definitions. +// +//***************************************************************************** +#define AM_HAL_MCUCTRL_CHIP_INFO_CLASS_M 0xFF000000 +#define AM_HAL_MCUCTRL_CHIP_INFO_CLASS_S 24 +#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M 0x00F00000 +#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S 20 +#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_N ((AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M >> AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S) + 1) +#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M 0x000F0000 +#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S 16 +#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_N ((AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M >> AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S) + 1) +#define AM_HAL_MCUCTRL_CHIP_INFO_REV_M 0x0000FF00 +#define AM_HAL_MCUCTRL_CHIP_INFO_REV_S 8 +#define AM_HAL_MCUCTRL_CHIP_INFO_PKG_M 0x000000C0 +#define AM_HAL_MCUCTRL_CHIP_INFO_PKG_S 6 +#define AM_HAL_MCUCTRL_CHIP_INFO_PINS_M 0x00000038 +#define AM_HAL_MCUCTRL_CHIP_INFO_PINS_S 3 +#define AM_HAL_MCUCTRL_CHIP_INFO_TEMP_M 0x00000006 +#define AM_HAL_MCUCTRL_CHIP_INFO_TEMP_S 1 +#define AM_HAL_MCUCTRL_CHIP_INFO_QUAL_M 0x00000001 +#define AM_HAL_MCUCTRL_CHIP_INFO_QUAL_S 0 + +//***************************************************************************** +// +// Apollo Number Decode. +// +//***************************************************************************** +extern const uint32_t g_am_hal_mcuctrl_flash_size[]; +extern const uint32_t g_am_hal_mcuctrl_sram_size[]; + +//***************************************************************************** +// +//! MCUCTRL device structure +// +//***************************************************************************** +typedef struct +{ + // + //! Device part number. (BCD format) + // + uint32_t ui32ChipPN; + + // + //! Unique Chip ID 0. + // + uint32_t ui32ChipID0; + + // + //! Unique Chip ID 1. + // + uint32_t ui32ChipID1; + + // + //! Chip Revision. + // + uint32_t ui32ChipRev; + + // + //! Vendor ID. + // + uint32_t ui32VendorID; + + // + //! Qualified chip. + // + uint32_t ui32Qualified; + + // + //! Flash Size. + // + uint32_t ui32FlashSize; + + // + //! SRAM Size. + // + uint32_t ui32SRAMSize; + + // + // JEDEC chip info + // + uint32_t ui32JedecPN; + uint32_t ui32JedecJEPID; + uint32_t ui32JedecCHIPREV; + uint32_t ui32JedecCID; +} +am_hal_mcuctrl_device_t; + +//***************************************************************************** +// +//! MCUCTRL fault structure +// +//***************************************************************************** +typedef struct +{ + // + //! ICODE bus fault occurred. + // + bool bICODE; + + // + //! ICODE bus fault address. + // + uint32_t ui32ICODE; + + // + //! DCODE bus fault occurred. + // + bool bDCODE; + + // + //! DCODE bus fault address. + // + uint32_t ui32DCODE; + + // + //! SYS bus fault occurred. + // + bool bSYS; + + // + //! SYS bus fault address. + // + uint32_t ui32SYS; +} +am_hal_mcuctrl_fault_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice); +extern void am_hal_mcuctrl_fault_capture_enable(void); +extern void am_hal_mcuctrl_fault_capture_disable(void); +extern void am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_MCUCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_otp.c b/mcu/apollo2/hal/am_hal_otp.c new file mode 100644 index 0000000..8c6391d --- /dev/null +++ b/mcu/apollo2/hal/am_hal_otp.c @@ -0,0 +1,173 @@ +//***************************************************************************** +// +// am_hal_otp.c +//! @file +//! +//! @brief Functions for handling the OTP interface. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#include "am_mcu_apollo.h" +#include "am_hal_flash.h" + +//***************************************************************************** +// +//! THIS FUNCTION IS DEPRECATED! +//! Use the respective HAL flash function instead. +//! +// @brief Check if debugger is currently locked out. +// +// @param None. +// +// Determine if the debugger is already locked out. +// +// @return non-zero if debugger is currently locked out. +// Specifically: +// 0 = debugger is not locked out. +// 1 = debugger is locked out. +// +//***************************************************************************** +int +am_hal_otp_is_debugger_lockedout(void) +{ + return am_hal_flash_debugger_disable_check(); +} + +//***************************************************************************** +// +//! THIS FUNCTION IS DEPRECATED! +//! Use the respective HAL flash function instead. +//! +// @brief Lock out debugger access. +// +// @param None. +// +// This function locks out access by a debugger. +// +// @return 0 if lockout was successful or if lockout was already enabled. +// +//***************************************************************************** +int +am_hal_otp_debugger_lockout(void) +{ + return am_hal_flash_debugger_disable(); +} + +//***************************************************************************** +// +//! THIS FUNCTION IS DEPRECATED! +//! Use the respective HAL flash function instead. +//! +// @brief Lock out SRAM access. +// +// @param None. +// +// This function locks out access by a debugger to SRAM. +// +// @return 0 if lockout was successful or if lockout was already enabled. +// Low byte=0xff, byte 1 contains current value of lockout. +// Else, return value from HAL programming function. +// +//***************************************************************************** +int +am_hal_otp_sram_lockout(void) +{ + return am_hal_flash_wipe_sram_enable(); +} + +//***************************************************************************** +// +//! THIS FUNCTION IS DEPRECATED! +//! Use the respective HAL flash function instead. +//! +// @brief Set copy (read) protection. +// +// @param @u32BegAddr The beginning address to be copy protected. +// @u32EndAddr The ending address to be copy protected. +// +// @note For Apollo, the u32BegAddr parameter should be on a 16KB boundary, and +// the u32EndAddr parameter should be on a (16KB-1) boundary. Otherwise +// both parameters will be truncated/expanded to do so. +// For example, if u32BegAddr=0x1000 and u32EndAddr=0xC200, the actual +// range that protected is: 0x0 - 0xFFFF. +// +// This function enables copy protection on a given flash address range. +// +// @return 0 if copy protection was successfully enabled. +// +//***************************************************************************** +int +am_hal_otp_set_copy_protection(uint32_t u32BegAddr, uint32_t u32EndAddr) +{ + return am_hal_flash_copy_protect_set((uint32_t*)u32BegAddr, + (uint32_t*)u32EndAddr); +} + +//***************************************************************************** +// +//! THIS FUNCTION IS DEPRECATED! +//! Use the respective HAL flash function instead. +//! +// @brief Set write protection. +// +// @param @u32BegAddr The beginning address to be write protected. +// @u32EndAddr The ending address to be write protected. +// +// @note For Apollo, the u32BegAddr parameter should be on a 16KB boundary, and +// the u32EndAddr parameter should be on a (16KB-1) boundary. Otherwise +// both parameters will be truncated/expanded to do so. +// For example, if u32BegAddr=0x1000 and u32EndAddr=0xC200, the actual +// range that protected is: 0x0 - 0xFFFF. +// +// This function enables write protection on a given flash address range. +// +// @return 0 if write protection was successfully enabled. +// +//***************************************************************************** +int +am_hal_otp_set_write_protection(uint32_t u32BegAddr, uint32_t u32EndAddr) +{ + return am_hal_flash_write_protect_set((uint32_t*)u32BegAddr, + (uint32_t*)u32EndAddr); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_otp.h b/mcu/apollo2/hal/am_hal_otp.h new file mode 100644 index 0000000..2c23448 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_otp.h @@ -0,0 +1,108 @@ +//***************************************************************************** +// +// am_hal_otp.h +//! @file +//! +//! @brief Functions for handling the OTP interface. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_OTP_H +#define AM_HAL_OTP_H + +//***************************************************************************** +// +// Define some OTP values and macros. +// +//***************************************************************************** +#define AM_HAL_OTP_SIG0 0x00 +#define AM_HAL_OTP_SIG1 0x04 +#define AM_HAL_OTP_SIG2 0x08 +#define AM_HAL_OTP_SIG3 0x0C + +#define AM_HAL_OTP_DBGR_O 0x10 +#define AM_HAL_OTP_WRITPROT0_O 0x20 +#define AM_HAL_OTP_WRITPROT1_O 0x24 +#define AM_HAL_OTP_COPYPROT0_O 0x30 +#define AM_HAL_OTP_COPYPROT1_O 0x34 + +#define AM_HAL_OTP_ADDR 0x50020000 +#define AM_HAL_OTP_DBGRPROT_ADDR (AM_HAL_OTP_ADDR + AM_HAL_OTP_DBGR_O) +#define AM_HAL_OTP_WRITPROT_ADDR (AM_HAL_OTP_ADDR + AM_HAL_OTP_WRITPROT0_O) +#define AM_HAL_OTP_COPYPROT_ADDR (AM_HAL_OTP_ADDR + AM_HAL_OTP_COPYPROT0_O) + +#define AM_HAL_OTP_CHUNKSIZE (16*1024) + +// +// Debugger port lockout macros. +// +#define AM_OTP_DBGR_LOCKOUT_S (0) +#define AM_OTP_DBGR_LOCKOUT_M (0x1 << AM_OTP_DBGR_LOCKOUT_S) +#define AM_OTP_STRM_LOCKOUT_S (1) +#define AM_OTP_STRM_LOCKOUT_M (0x1 << AM_OTP_STRM_LOCKOUT_S) +#define AM_OTP_SRAM_LOCKOUT_S (2) +#define AM_OTP_SRAM_LOCKOUT_M (0x1 << AM_OTP_SRAM_LOCKOUT_S) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +extern int am_hal_otp_is_debugger_lockedout(void); +extern int am_hal_otp_debugger_lockout(void); +extern int am_hal_otp_sram_lockout(void); +extern int am_hal_otp_set_copy_protection(uint32_t u32BegAddr, uint32_t u32EndAddr); +extern int am_hal_otp_set_write_protection(uint32_t u32BegAddr, uint32_t u32EndAddr); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_OTP_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/mcu/apollo2/hal/am_hal_pdm.c b/mcu/apollo2/hal/am_hal_pdm.c new file mode 100644 index 0000000..07f72d6 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_pdm.c @@ -0,0 +1,158 @@ +//***************************************************************************** +// +// am_hal_pdm.c +//! @file +//! +//! @brief Functions for interfacing with Pulse Density Modulation (PDM). +//! +//! @addtogroup pdm2 DMEMS Microphon3 (PDM) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Configure the PDM module. +//! +//! This function reads the an \e am_hal_pdm_config_t structure and uses it to +//! set up the PDM module. +//! +//! Please see the information on the am_hal_pdm_config_t configuration +//! structure, found in am_hal_pdm.h, for more information on the parameters +//! that may be set by this function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_pdm_config(am_hal_pdm_config_t *psConfig) +{ + // + // setup the PDM PCFG register + // + AM_REG(PDM, PCFG) = psConfig->ui32PDMConfigReg; + + // + // setup the PDM VCFG register + // + AM_REG(PDM, VCFG) = psConfig->ui32VoiceConfigReg; + + // + // setup the PDM FIFO Threshold register + // + AM_REG(PDM, FTHR) = psConfig->ui32FIFOThreshold; + + // + // Flush the FIFO for good measure. + // + am_hal_pdm_fifo_flush(); +} + +//***************************************************************************** +// +//! @brief Enable the PDM module. +//! +//! This function enables the PDM module in the mode previously defined by +//! am_hal_pdm_config(). +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_pdm_enable(void) +{ + AM_REG(PDM, PCFG) |= AM_REG_PDM_PCFG_PDMCORE_EN; + AM_REG(PDM, VCFG) |= ( AM_REG_PDM_VCFG_IOCLKEN_EN | + AM_REG_PDM_VCFG_PDMCLK_EN | + AM_REG_PDM_VCFG_RSTB_NORM ); +} + +//***************************************************************************** +// +//! @brief Disable the PDM module. +//! +//! This function disables the PDM module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_pdm_disable(void) +{ + AM_REG(PDM, PCFG) &= ~ AM_REG_PDM_PCFG_PDMCORE_EN; + AM_REG(PDM, VCFG) &= ~ ( AM_REG_PDM_VCFG_IOCLKEN_EN | + AM_REG_PDM_VCFG_PDMCLK_EN | + AM_REG_PDM_VCFG_RSTB_NORM ); +} + +//***************************************************************************** +// +//! @brief Return the PDM Interrupt status. +//! +//! @param bEnabledOnly - return only the enabled interrupts. +//! +//! Use this function to get the PDM interrupt status. +//! +//! @return intrrupt status +// +//***************************************************************************** +uint32_t +am_hal_pdm_int_status_get(bool bEnabledOnly) +{ + if ( bEnabledOnly ) + { + uint32_t u32RetVal = AM_REG(PDM, INTSTAT); + return u32RetVal & AM_REG(PDM, INTEN); + } + else + { + return AM_REG(PDM, INTSTAT); + } +} + +//***************************************************************************** +// +// End the doxygen group +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_pdm.h b/mcu/apollo2/hal/am_hal_pdm.h new file mode 100644 index 0000000..7421988 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_pdm.h @@ -0,0 +1,674 @@ +//***************************************************************************** +// +// am_hal_pdm.h +//! @file +//! +//! @brief Functions for accessing and configuring the PDM module +//! +//! @addtogroup pdm2 Pulse Density Modulation (PDM) Input Module. +//! @ingroup apollo2hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_HAL_PDM_H +#define AM_HAL_PDM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @name PDM Left Right Swap Control +//! @brief Macro definitions for the PDM LRSWAP bit field +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! left right swap bit. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_LRSWAP_ENABLE \ + AM_REG_PDM_PCFG_LRSWAP_EN +#define AM_HAL_PDM_PCFG_LRSWAP_DISABLE \ + AM_REG_PDM_PCFG_LRSWAP_NOSWAP +//! @} + +//***************************************************************************** +// +//! @name PDM Right Gain Setting +//! @brief Macro definitions for the PDM Right Gain Setting. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! right gain value. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M15DB AM_REG_PDM_PCFG_PGARIGHT_M15DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M300DB AM_REG_PDM_PCFG_PGARIGHT_M300DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M45DB AM_REG_PDM_PCFG_PGARIGHT_M45DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M60DB AM_REG_PDM_PCFG_PGARIGHT_M60DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M75DB AM_REG_PDM_PCFG_PGARIGHT_M75DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M90DB AM_REG_PDM_PCFG_PGARIGHT_M90DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M105DB AM_REG_PDM_PCFG_PGARIGHT_M105DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_M120DB AM_REG_PDM_PCFG_PGARIGHT_M120DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P105DB AM_REG_PDM_PCFG_PGARIGHT_P105DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P90DB AM_REG_PDM_PCFG_PGARIGHT_P90DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P75DB AM_REG_PDM_PCFG_PGARIGHT_P75DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P60DB AM_REG_PDM_PCFG_PGARIGHT_P60DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P45DB AM_REG_PDM_PCFG_PGARIGHT_P45DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P300DB AM_REG_PDM_PCFG_PGARIGHT_P300DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_P15DB AM_REG_PDM_PCFG_PGARIGHT_P15DB +#define AM_HAL_PDM_PCFG_RIGHT_PGA_0DB AM_REG_PDM_PCFG_PGARIGHT_0DB +//! @} + +//***************************************************************************** +// +//! @name PDM Left Gain Setting +//! @brief Macro definitions for the PDM Left Gain Setting. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! left gain value. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_LEFT_PGA_M15DB AM_REG_PDM_PCFG_PGALEFT_M15DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M300DB AM_REG_PDM_PCFG_PGALEFT_M300DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M45DB AM_REG_PDM_PCFG_PGALEFT_M45DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M60DB AM_REG_PDM_PCFG_PGALEFT_M60DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M75DB AM_REG_PDM_PCFG_PGALEFT_M75DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M90DB AM_REG_PDM_PCFG_PGALEFT_M90DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M105DB AM_REG_PDM_PCFG_PGALEFT_M105DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_M120DB AM_REG_PDM_PCFG_PGALEFT_M120DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P105DB AM_REG_PDM_PCFG_PGALEFT_P105DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P90DB AM_REG_PDM_PCFG_PGALEFT_P90DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P75DB AM_REG_PDM_PCFG_PGALEFT_P75DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P60DB AM_REG_PDM_PCFG_PGALEFT_P60DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P45DB AM_REG_PDM_PCFG_PGALEFT_P45DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P300DB AM_REG_PDM_PCFG_PGALEFT_P300DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_P15DB AM_REG_PDM_PCFG_PGALEFT_P15DB +#define AM_HAL_PDM_PCFG_LEFT_PGA_0DB AM_REG_PDM_PCFG_PGALEFT_0DB +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration MCLK Divider +//! @brief Macro definitions for the PDM MCLK Divider +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! sinc decimation rate relative to the PDM sample clock (OSR). +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_MCLKDIV_DIV1 AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1 +#define AM_HAL_PDM_PCFG_MCLKDIV_DIV2 AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2 +#define AM_HAL_PDM_PCFG_MCLKDIV_DIV3 AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3 +#define AM_HAL_PDM_PCFG_MCLKDIV_DIV4 AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4 + +#define AM_HAL_PDM_PCFG_MCLKDIV(DIV) AM_REG_PDM_PCFG_MCLKDIV(DIV) +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration SINC Decimation Rate +//! @brief Macro definitions for the PDM SINC decimation rate +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! sinc decimation rate relative to the PDM sample clock (OSR). +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_SINC_RATE(OSR) \ + AM_REG_PDM_PCFG_SINCRATE(OSR) +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration High Pass Filter Enable +//! @brief Macro definitions for the PDM ADCHPD +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! the high pass filter. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_ADCHPD_ENABLE AM_REG_PDM_PCFG_ADCHPD_EN +#define AM_HAL_PDM_PCFG_ADCHPD_DISABLE AM_REG_PDM_PCFG_ADCHPD_DIS +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration HPCUTOFF +//! @brief Macro definitions for the PDM High Pass Filter Cutoff Selector. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! high pass filter cutoff frequency. Valid range is 0 to 7. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_HPCUTOFF(HPSEL) \ + AM_REG_PDM_PCFG_HPCUTOFF(HPSEL) +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration Gain Set Change Clock Delay +//! @brief Macro definitions for the PDM clock delay for gain set changes. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! number of clocks for spreading gain setting changes. Valid range is 0 to 7. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_CYCLES(CLOCKS) \ + AM_REG_PDM_PCFG_CYCLES(CLOCKS) +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration SOFTMUTE enable/disable. +//! @brief Macro definitions for the PDM PCFG register mute controls. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the SOFTMUTE option. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_SOFTMUTE_ENABLE AM_REG_PDM_PCFG_SOFTMUTE_EN +#define AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE AM_REG_PDM_PCFG_SOFTMUTE_DIS +//! @} + +//***************************************************************************** +// +//! @name PDM Configuration PDM Core enable/disable. +//! @brief Macro definitions for the PDM PCFG register filter engine enable. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the PDM filter engine core. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_PCFG_PDMCORE_ENABLE AM_REG_PDM_PCFG_PDMCORE_EN +#define AM_HAL_PDM_PCFG_PDMCORE_DISABLE AM_REG_PDM_PCFG_PDMCORE_DIS +//! @} + +//***************************************************************************** +// +//! @name PDM Clock Frequencies +//! @brief Macro definitions for the PDM clock (from clkgen) frequencies. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! source clock frequency of the PDM interface. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_IOCLK_12MHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_12MHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +#define AM_HAL_PDM_IOCLK_6MHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_6MHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +#define AM_HAL_PDM_IOCLK_3MHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_3MHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +#define AM_HAL_PDM_IOCLK_1_5MHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +#define AM_HAL_PDM_IOCLK_750KHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_750KHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +#define AM_HAL_PDM_IOCLK_375KHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_375KHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +#define AM_HAL_PDM_IOCLK_187KHZ \ + (AM_REG_PDM_VCFG_PDMCLKSEL_187KHz | AM_REG_PDM_VCFG_IOCLKEN_EN) +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration RSTB +//! @brief Reset the IP core. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_RSTB_RESET AM_REG_PDM_VCFG_RSTB_RESET +#define AM_HAL_PDM_VCFG_RSTB_NORMAL AM_REG_PDM_VCFG_RSTB_NORM +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration PDM Clock Enable/Disable +//! @brief Macro definitions for the PDM VCFG register PDMCLKEN. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the PDM clock output to the pad mux and from there to the world. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_PDMCLK_ENABLE AM_REG_PDM_VCFG_PDMCLK_EN +#define AM_HAL_PDM_VCFG_PDMCLK_DISABLE AM_REG_PDM_VCFG_PDMCLK_DIS +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration I2S Mode Enable/Disable +//! @brief Macro definitions for the PDM VCFG register I2SMODE. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the PDM clock output to the pad mux and from there to the world. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_I2SMODE_ENABLE AM_REG_PDM_VCFG_I2SMODE_EN +#define AM_HAL_PDM_VCFG_I2SMODE_DISABLE AM_REG_PDM_VCFG_I2SMODE_DIS +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration BCLK Inversion Enable/Disable +//! @brief Macro definitions for the PDM VCFG register BCLKINV. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the PDM clock output to the pad mux and from there to the world. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_BCLKINV_ENABLE AM_REG_PDM_VCFG_BCLKINV_INV +#define AM_HAL_PDM_VCFG_BCLKINV_DISABLE AM_REG_PDM_VCFG_BCLKINV_NORM +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration DMICDEL Enable/Disable +//! @brief Macro definitions for the PDM VCFG register Digital Mic Delay. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the PDM digital microphone clock delay. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_DMICDEL_1CYC AM_REG_PDM_VCFG_DMICKDEL_1CYC +#define AM_HAL_PDM_VCFG_DMICDEL_0CYC AM_REG_PDM_VCFG_DMICKDEL_0CYC +#define AM_HAL_PDM_VCFG_DMICDEL_ENABLE AM_REG_PDM_VCFG_DMICKDEL_1CYC +#define AM_HAL_PDM_VCFG_DMICDEL_DISABLE AM_REG_PDM_VCFG_DMICKDEL_0CYC +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration Select Apps Processor (AP) versus Internal +//! @brief Macro definitions for the PDM VCFG register Digital Mic Delay. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to select +//! the Application Processor (I2S slave) mode or the Internal FIFO interface +//! to the Apollo Cortex M4. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_SELAP_I2S AM_REG_PDM_VCFG_SELAP_I2S +#define AM_HAL_PDM_VCFG_SELAP_INTERNAL AM_REG_PDM_VCFG_SELAP_INTERNAL +#define AM_HAL_PDM_VCFG_SELAP_AP_I2S AM_REG_PDM_VCFG_SELAP_I2S +#define AM_HAL_PDM_VCFG_SELAP_CM4_FIFO AM_REG_PDM_VCFG_SELAP_INTERNAL +//! @} + +//***************************************************************************** +// +//! @name PDM Voice Configuration PACK Enable/Disable +//! @brief Macro definitions for the PDM VCFG register sample packing mode. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to enable +//! or disable the PDM sample packing mode. This mode puts two 16-bit samples +//! per 32-bit FIFO word. The following packed modes are available: +//! +//! mono left: LEFT_NEW, LEFT_OLD +//! mono right: RIGHT_NEW,RIGHT_OLD +//! stereo right: LEFT, RIGHT +//! stereo right(LRSWAP): RIGHT, LEFT +//! +//! +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_PACK_ENABLE AM_REG_PDM_VCFG_PCMPACK_EN +#define AM_HAL_PDM_VCFG_PACK_DISABLE AM_REG_PDM_VCFG_PCMPACK_DIS +//! @} + +//***************************************************************************** +// +//! @name PDM Channel Selects +//! @brief Macro definitions for the PDM Channel Selection. +//! +//! These macros may be used with the am_hal_pdm_config_t structure to set the +//! channel selection for the PDM interface. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_VCFG_CHANNEL_LEFT AM_REG_PDM_VCFG_CHSET_LEFT +#define AM_HAL_PDM_VCFG_CHANNEL_RIGHT AM_REG_PDM_VCFG_CHSET_RIGHT +#define AM_HAL_PDM_VCFG_CHANNEL_STEREO AM_REG_PDM_VCFG_CHSET_STEREO +//! @} + +//***************************************************************************** +// +//! @name PDM Interrupts +//! @brief Macro definitions for the PDM interrupt status bits. +//! +//! These macros correspond to the bits in the PDM interrupt status register. +//! They may be used for any of the am_hal_pdm_int_x() functions. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_PDM_INT_UNDFL AM_REG_PDM_INTEN_UNDFL_M +#define AM_HAL_PDM_INT_OVF AM_REG_PDM_INTEN_OVF_M +#define AM_HAL_PDM_INT_FIFO AM_REG_PDM_INTEN_THR_M +//! @} + +//***************************************************************************** +// +//! @brief Configuration structure for the PDM module. +// +//***************************************************************************** +typedef struct +{ + // + //! @brief Set the PDM configuration reg with the values in this member. + //! Choose from AM_HAL_PDM_PCFG macros. + //! AM_HAL_PDM_PCFG_LRSWAP_xxx + //! AM_HAL_PDM_PCFG_RIGHT_PGA_xxx + //! AM_HAL_PDM_PCFG_LEFT_PGA_xxx + //! AM_HAL_PDM_PCFG_MCLKDIV_xxx + //! AM_HAL_PDM_PCFG_SINC_RATE() + //! AM_HAL_PDM_PCFG_ADCHPD_xxx + //! AM_HAL_PDM_PCFG_HPCUTOFF() + //! AM_HAL_PDM_PCFG_CYCLES() + //! AM_HAL_PDM_PCFG_SOFTMUTE_xxx + //! * AM_HAL_PDM_PCFG_PDMCORE_EN + //! AM_HAL_PDM_PCFG_PDMCORE_DISABLE + // + uint32_t ui32PDMConfigReg; + + // + //! @brief Set the Voice Configuration reg with the values in this member. + //! Choose from AM_HAL_PDM_VCFG macros. + //! AM_HAL_PDM_IOCLK_xxx (also sets AM_REG_PDM_VCFG_IOCLKEN_EN) + //! * AM_REG_PDM_VCFG_IOCLKEN_EN + //! * AM_HAL_PDM_VCFG_RSTB_RESET + //! AM_HAL_PDM_VCFG_RSTB_NORMAL + //! * AM_HAL_PDM_VCFG_PDMCLK_EN + //! AM_HAL_PDM_VCFG_PDMCLK_DIS + //! AM_HAL_PDM_VCFG_I2SMODE_xxx + //! AM_HAL_PDM_VCFG_BCLKINV_xxx + //! AM_HAL_PDM_VCFG_DMICDEL_xxx + //! AM_HAL_PDM_VCFG_SELAP_xxx + //! AM_HAL_PDM_VCFG_PACK_xxx + //! AM_HAL_PDM_VCFG_CHANNEL_xxx + //! + //! * = These bits are set or cleared by the HAL PDM functions + //! am_hal_pdm_enable() or am_hal_pdm_disable(). + // + uint32_t ui32VoiceConfigReg; + + // + //! @brief Select the FIFO PCM sample threshold. + //! + //! The PDM controller will generate a processor interrupt when the number + //! of entries in the FIFO goes *above* this number. + // + uint32_t ui32FIFOThreshold; +} am_hal_pdm_config_t; + +//***************************************************************************** +// +// Define function-like macros. +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Read the FIFO depth information as an in-line macro +// +//***************************************************************************** +#define am_hal_pdm_fifo_depth_read() (AM_REG(PDM, FR)) + +//***************************************************************************** +// +//! @brief Read the FIFO READ DATA as an in-line macro +// +//***************************************************************************** +#define am_hal_pdm_fifo_data_read() (AM_REG(PDM, FRD)) + +//***************************************************************************** +// +//! @brief Flush the FIFO as an in-line macro +// +//***************************************************************************** +#define am_hal_pdm_fifo_flush() (AM_REG(PDM, FLUSH) = 0) + +//***************************************************************************** +// +//! @brief Set the PDM Configuration (PCFG) Register +//! +//! This function sets the PDM configuration register +// +//***************************************************************************** +#define am_hal_pdm_pcfg_set(Value) (AM_REG(PDM, PCFG) = Value) + +//***************************************************************************** +// +//! @brief Get the PCFG register value from PDM module. +// +//***************************************************************************** +#define am_hal_pdm_pcfg_get() (AM_REG(PDM, PCFG)) + +//***************************************************************************** +// +//! @brief Set the Voice Configuration (VCFG) Register +// +//***************************************************************************** +#define am_hal_pdm_vcfg_set(Value) (AM_REG(PDM, VCFG) = Value) + +//***************************************************************************** +// +//! @brief Get the VCFG register value from PDM module. +// +//***************************************************************************** +#define am_hal_pdm_vcfg_get() (AM_REG(PDM, VCFG)) + +//***************************************************************************** +// +//! @brief Set the FIFO Threshold +// +//***************************************************************************** +#define am_hal_pdm_thresh_set(thresh) (AM_REG(PDM, FTHR) = thresh) + +//***************************************************************************** +// +//! @brief Get the FIFO Threshold register value from PDM module. +// +//***************************************************************************** +#define am_hal_pdm_thresh_get() (AM_REG(PDM, FTHR)) + +//***************************************************************************** +// +//! @brief Set the left microphone PGA gain. +//! +//***************************************************************************** +#define am_hal_pdm_left_gain_set(gain) (AM_BFW(PDM, PCFG, PGALEFT, gain)) + +//***************************************************************************** +// +//! @brief Set the right microphone PGA gain. +// +//***************************************************************************** +#define am_hal_pdm_right_gain_set(gain) (AM_BFW(PDM, PCFG, PGARIGHT, gain)) + +//***************************************************************************** +// +//! @brief Get the left microphone PGA gain value. +// +//***************************************************************************** +#define am_hal_pdm_left_gain_get() (AM_BFR(PDM, PCFG, PGALEFT)) + +//***************************************************************************** +// +//! @brief Get the right microphone PGA gain value. +// +//***************************************************************************** +#define am_hal_pdm_right_gain_get() (AM_BFR(PDM, PCFG, PGARIGHT)) + +//***************************************************************************** +// +//! @brief Enable the Soft Mute functionality. +// +//***************************************************************************** +#define am_hal_pdm_soft_mute_enable() (AM_BFWe(PDM, PCFG, SOFTMUTE, EN)) + +//***************************************************************************** +// +//! @brief Disable the Soft Mute functionality. +// +//***************************************************************************** +#define am_hal_pdm_soft_mute_disable() (AM_BFWe(PDM, PCFG, SOFTMUTE, DIS)) + +//***************************************************************************** +// +//! @brief Enable selected PDM Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n +//! AM_HAL_PDM_INT_UNDFL\n +//! AM_HAL_PDM_INT_OVF\n +//! AM_HAL_PDM_INT_FIFO\n +// +//***************************************************************************** +#define am_hal_pdm_int_enable(intrpt) (AM_REG(PDM, INTEN) |= intrpt) + +//***************************************************************************** +// +//! @brief Return the enabled PDM Interrupts. +//! +//! Use this function to return all enabled PDM interrupts. +//! +//! @return all enabled PDM interrupts as a mask.\n +//! AM_HAL_PDM_INT_UNDFL\n +//! AM_HAL_PDM_INT_OVF\n +//! AM_HAL_PDM_INT_FIFO\n +// +//***************************************************************************** +#define am_hal_pdm_int_enable_get() (AM_REG(PDM, INTEN)) + +//***************************************************************************** +// +//! @brief Disable selected PDM Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n +//! AM_HAL_PDM_INT_UNDFL\n +//! AM_HAL_PDM_INT_OVF\n +//! AM_HAL_PDM_INT_FIFO\n +// +//***************************************************************************** +#define am_hal_pdm_int_disable(intrpt) (AM_REG(PDM, INTEN) &= ~intrpt) + +//***************************************************************************** +// +//! @brief Clear selected PDM Interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n +//! AM_HAL_PDM_INT_UNDFL\n +//! AM_HAL_PDM_INT_OVF\n +//! AM_HAL_PDM_INT_FIFO\n +// +//***************************************************************************** +#define am_hal_pdm_int_clear(intrpt) (AM_REG(PDM, INTCLR) = intrpt) + +//***************************************************************************** +// +//! @brief Set selected PDM Interrupts. +//! +//! Use this function to set the PDM interrupts. +//! +//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_pdm.h\n +//! AM_HAL_PDM_INT_UNDFL\n +//! AM_HAL_PDM_INT_OVF\n +//! AM_HAL_PDM_INT_FIFO\n +// +//***************************************************************************** +#define am_hal_pdm_int_set(intrpt) (AM_REG(PDM, INTSET) = intrpt) + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_pdm_config(am_hal_pdm_config_t * cfg); +extern void am_hal_pdm_enable(void); +extern void am_hal_pdm_disable(void); + +extern uint32_t am_hal_pdm_int_status_get(bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_PDM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_pin.h b/mcu/apollo2/hal/am_hal_pin.h new file mode 100644 index 0000000..249de7b --- /dev/null +++ b/mcu/apollo2/hal/am_hal_pin.h @@ -0,0 +1,548 @@ +//***************************************************************************** +// +// am_hal_pin.h +//! @file +//! @brief Macros for configuring specific pins. +//! +//! @addtogroup pin2 PIN definitions for Apollo2. +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_HAL_PIN_H +#define AM_HAL_PIN_H + +//***************************************************************************** +// +// Pin definition helper macros. +// +//***************************************************************************** +#define AM_HAL_PIN_DIR_INPUT (AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_DIR_OUTPUT (AM_HAL_GPIO_OUT_PUSHPULL) +#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN) +#define AM_HAL_PIN_DIR_3STATE (AM_HAL_GPIO_OUT_3STATE) + +//***************************************************************************** +// +// Pin definition helper macros. +// +//***************************************************************************** +#define AM_HAL_PIN_DISABLE (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_INPUT (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_OUTPUT (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT) +#define AM_HAL_PIN_OPENDRAIN (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_3STATE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_3STATE) + +//***************************************************************************** +// +// Pin definition macros. +// +//***************************************************************************** +#define AM_HAL_PIN_0_SLSCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_0_SLSCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_0_CLKOUT (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_0_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_0_MxSCKLB (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_0_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_0_MxSCLLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) + +#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_1_SLMISO (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_1_UART0TX (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_1_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_1_MxMISOLB (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_1_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_1_MxSDALB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) + +#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_2_SLMOSI (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_2_UART0RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_2_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_2_MxMOSILB (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_2_M2MOSI (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_2_MxWIR3LB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_GPIO_INPEN) + +#define AM_HAL_PIN_3_UART0RTS (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_3_SLnCE (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_3_M1nCE4 (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_3_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_3_MxnCELB (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_3_M2nCE0 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_3_TRIG1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_3_I2S_WCLK (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_4_UART0CTS (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_4_SLINT (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_4_M0nCE5 (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_4_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_4_SLINTGP (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_4_M2nCE5 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_4_CLKOUT (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_4_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) +// PSINK usage: GPIOWT=0 to activate the power switch, GPIOWT=1 to disable +#define AM_HAL_PIN_4_PSINK (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_POWERSINK) + +#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_5_M0SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_5_UART0RTS (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_5_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_5_M0SCKLB (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_5_M0SCLLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_5_M1nCE2 (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_6_M0MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_6_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_6_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_6_SLMISOLB (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_6_M1nCE0 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_6_SLSDALB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_6_I2S_DAT (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_7_M0MOSI (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_7_CLKOUT (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_7_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_7_TRIG0 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_7_UART0TX (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_7_SLWIR3LB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_7_M1nCE1 (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_8_M1SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_8_M0nCE4 (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_8_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_8_M2nCE4 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_8_M1SCKLB (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_8_UART1TX (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_8_M1SCLLB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_9_M1MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_9_M0nCE5 (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_9_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_9_M4nCE5 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_9_SLMISOLB (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_9_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_9_SLSDALB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_10_M1MOSI (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_10_M0nCE6 (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_10_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_10_M2nCE6 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_10_UART1RTS (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_10_M4nCE4 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_10_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_11_ADCSE2 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_11_M0nCE0 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_11_CLKOUT (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_11_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_11_M2nCE7 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_11_UART1CTS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_11_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_11_PDM_DATA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) + +#define AM_HAL_PIN_12_ADCD0NSE9 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_12_M1nCE0 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_12_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_12_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_12_CLKOUT (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_12_PDM_CLK (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_12_UART0CTS (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_12_UART1TX (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_13_ADCD0PSE8 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_13_M1nCE1 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_13_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_13_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_13_M2nCE3 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_13_UART0RTS (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_13_UART1RX (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) + +#define AM_HAL_PIN_14_ADCD1P (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_14_M1nCE2 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_14_UART1TX (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_14_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_14_M2nCE1 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_14_SWDCK (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_14_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_15_ADCD1N (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_15_M1nCE3 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_15_UART1RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_15_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_15_M2nCE2 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_15_SWDIO (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_15_SWO (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_16_ADCSE0 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_16_M0nCE4 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_16_TRIG0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_16_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_16_M2nCE3 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_16_CMPIN0 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_16_UART0TX (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_16_UART1RTS (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_17_CMPRF1 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_17_M0nCE1 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_17_TRIG1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_17_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_17_M4nCE3 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_17_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_17_UART1CTS (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) + +#define AM_HAL_PIN_18_CMPIN1 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_18_M0nCE2 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_18_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_18_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_18_M4nCE1 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_18_UART1TX (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_18_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_19_CMPRF0 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_19_M0nCE3 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_19_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_19_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_19_TCTA1 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_19_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_19_I2S_BCLK (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_20_SWDCK (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_20_M1nCE5 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_20_TCTA2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_20_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_20_UART0TX (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_20_UART1TX (AM_HAL_GPIO_FUNC(5)) + +#define AM_HAL_PIN_21_SWDIO (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_21_M1nCE6 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_21_TCTB2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_21_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_21_UART0RX (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_21_UART1RX (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) + +#define AM_HAL_PIN_22_UART0TX (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_22_M1nCE7 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_22_TCTA3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_22_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_22_PDM_CLK (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_22_TCTB1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_22_SWO (AM_HAL_GPIO_FUNC(7)) +// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable +#define AM_HAL_PIN_22_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWERSOURCE) + +#define AM_HAL_PIN_23_UART0RX (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_23_M0nCE0 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_23_TCTB3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_23_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_23_PDM_DATA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_23_CMPOUT (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_23_TCTB1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_24_M2nCE1 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_24_M0nCE1 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_24_CLKOUT (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_24_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_24_M5nCE0 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_24_TCTA1 (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_24_I2S_BCLK (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_24_SWO (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_25_M0nCE2 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_25_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_25_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_25_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_25_SLMISOLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_25_SLSDALB (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_26_M0nCE3 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_26_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_26_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_26_M2nCE0 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_26_TCTA1 (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_26_M5nCE1 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_26_M3nCE0 (AM_HAL_GPIO_FUNC(7)) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_27_M1nCE4 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_27_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_27_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_27_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_27_M2SCKLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_27_M2SCLLB (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_28_I2S_WCLK (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_28_M1nCE5 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_28_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_28_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_28_M2MOSI (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_28_M5nCE3 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_28_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_29_ADCSE1 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_29_M1nCE6 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_29_TCTA2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_29_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_29_UART0CTS (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_29_UART1CTS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_29_M4nCE0 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_29_PDM_DATA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_30_M1nCE7 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_30_TCTB2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_30_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_30_UART0TX (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_30_UART1RTS (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_30_I2S_DAT (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_31_ADCSE3 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_31_M0nCE4 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_31_TCTA3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_31_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_31_UART0RX (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_31_TCTB1 (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_32_ADCSE4 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_32_M0nCE5 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_32_TCTB3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_32_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_32_TCTB1 (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_33_ADCSE5 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_33_M0nCE6 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_33_32KHZ_XT (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_33_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_33_M3nCE7 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_33_TCTB1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_33_SWO (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_34_ADCSE6 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_34_M0nCE7 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_34_M2nCE3 (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_34_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_34_CMPRF2 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_34_M3nCE1 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_34_M4nCE0 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_34_M5nCE2 (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_35_ADCSE7 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_35_M1nCE0 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_35_UART1TX (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_35_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_35_M4nCE6 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_35_TCTA1 (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_35_UART0RTS (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_35_M3nCE2 (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_36_TRIG1 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_36_M1nCE1 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_36_UART1RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_36_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_36_32KHZ_XT (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_36_M2nCE0 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_36_UART0CTS (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_36_M3nCE3 (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_37_TRIG2 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_37_M1nCE2 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_37_UART0RTS (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_37_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_37_M3nCE4 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_37_M4nCE1 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_37_PDM_CLK (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_37_TCTA1 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_38_TRIG3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_38_M1nCE3 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_38_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_38_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_38_M3MOSI (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_38_M4nCE7 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_38_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_39_UART0TX (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_39_UART1TX (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_39_CLKOUT (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_39_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_39_M4SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_39_M4SCKLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_39_M4SCLLB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_40_UART0RX (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_40_UART1RX (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_40_TRIG0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_40_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_40_M4MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_40_SLMISOLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_40_SLSDALB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_41_M2nCE1 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_41_CLKOUT (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_41_SWO (AM_HAL_GPIO_FUNC(2)) +#define AM_HAL_PIN_41_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_41_M3nCE5 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_41_M5nCE7 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_41_M4nCE2 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_41_UART0RTS (AM_HAL_GPIO_FUNC(7)) +// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable +#define AM_HAL_PIN_41_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWERSOURCE) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_42_M2nCE2 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_42_M0nCE0 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_42_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_42_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_42_M3SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_42_M3SCKLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_42_M3SCLLB (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_43_M2nCE4 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_43_M0nCE1 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_43_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_43_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_43_M3MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_43_SLMISOLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_43_SLSDALB (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_44_UART1RTS (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_44_M0nCE2 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_44_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_44_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_44_M4MOSI (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_44_M5nCE6 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_44_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_45_UART1CTS (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_45_M0nCE3 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_45_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_45_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_45_M4nCE3 (AM_HAL_GPIO_FUNC(4)) +#define AM_HAL_PIN_45_M3nCE6 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_45_M5nCE5 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_45_SWO (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_46_32KHZ_XT (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_46_M0nCE4 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_46_TCTA2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_46_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_46_TCTA1 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_46_M5nCE4 (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_46_M4nCE4 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_46_SWO (AM_HAL_GPIO_FUNC(7)) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_47_M2nCE5 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_47_M0nCE5 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_47_TCTB2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_47_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_47_M5MOSI (AM_HAL_GPIO_FUNC(5)) +#define AM_HAL_PIN_47_M4nCE5 (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_47_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_48_M2nCE6 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_48_M0nCE6 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_48_TCTA3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_48_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_48_M5SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_48_M5SCKLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_48_M5SCLLB (AM_HAL_GPIO_FUNC(7)) + +#define AM_HAL_PIN_49_M2nCE7 (AM_HAL_GPIO_FUNC(0)) +#define AM_HAL_PIN_49_M0nCE7 (AM_HAL_GPIO_FUNC(1)) +#define AM_HAL_PIN_49_TCTB3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_49_GPIO (AM_HAL_GPIO_FUNC(3)) +#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_49_M5MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_49_SLMISOLB (AM_HAL_GPIO_FUNC(6)) +#define AM_HAL_PIN_49_SLSDALB (AM_HAL_GPIO_FUNC(7)) + +#endif // AM_HAL_PIN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_pwrctrl.c b/mcu/apollo2/hal/am_hal_pwrctrl.c new file mode 100644 index 0000000..9290a34 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_pwrctrl.c @@ -0,0 +1,558 @@ +//***************************************************************************** +// +// am_hal_pwrctrl.c +//! @file +//! +//! @brief Functions for enabling and disabling power domains. +//! +//! @addtogroup pwrctrl2 Power Control +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// ONE_BIT - true iff value has exactly 1 bit set. +// +//***************************************************************************** +#define ONE_BIT(ui32Value) (ui32Value && !(ui32Value & (ui32Value - 1))) + +//***************************************************************************** +// +// Determine if this is an Apollo2 revision that requires additional handling +// of the BUCK to LDO transition when only the ADC is in use and going to +// deepsleep. +// +//***************************************************************************** +static bool +isRev_ADC(void) +{ + return AM_BFM(MCUCTRL, CHIPREV, REVMAJ) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ? + true : false; +} + +//***************************************************************************** +// +//! @brief Enable power for a peripheral. +//! +//! @param ui32Peripheral - The peripheral to enable +//! +//! This function directly enables or disables power for the chosen peripheral. +//! +//! @note Unpowered peripherals may lose their configuration information. This +//! function does not save or restore peripheral configuration registers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral) +{ + + am_hal_debug_assert_msg(ONE_BIT(ui32Peripheral), + "Cannot enable more than one peripheral at a time."); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable power control for the given device. + // + AM_REG(PWRCTRL, DEVICEEN) |= ui32Peripheral; + + // + // End Critical Section. + // + AM_CRITICAL_END + + // + // Wait for the power to stablize. Using a simple delay loop is more + // power efficient than a polling loop. + // + am_hal_flash_delay(AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES / 3); + + // + // Quick check to guarantee we're good (should never be more than 1 read). + // + POLL_PWRSTATUS(ui32Peripheral); +} + +//***************************************************************************** +// +//! @brief Disable power for a peripheral. +//! +//! @param ui32Peripheral - The peripheral to disable +//! +//! This function directly disables or disables power for the chosen peripheral. +//! +//! @note Unpowered peripherals may lose their configuration information. This +//! function does not save or restore peripheral configuration registers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral) +{ + + am_hal_debug_assert_msg(ONE_BIT(ui32Peripheral), + "Cannot enable more than one peripheral at a time."); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable power control for the given device. + // + AM_REG(PWRCTRL, DEVICEEN) &= ~ui32Peripheral; + + // + // End critical section. + // + AM_CRITICAL_END + + // + // Wait for the power to stablize + // + am_hal_flash_delay(AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES / 3); +} + +//***************************************************************************** +// +//! @brief Enable and disable power for memory devices (SRAM, flash, cache). +//! +//! @param ui32MemEn - The memory and amount to be enabled. +//! Must be one of the following: +//! AM_HAL_PWRCTRL_MEMEN_CACHE +//! AM_HAL_PWRCTRL_MEMEN_CACHE_DIS +//! AM_HAL_PWRCTRL_MEMEN_FLASH512K +//! AM_HAL_PWRCTRL_MEMEN_FLASH1M +//! AM_HAL_PWRCTRL_MEMEN_SRAM8K +//! AM_HAL_PWRCTRL_MEMEN_SRAM16K +//! AM_HAL_PWRCTRL_MEMEN_SRAM24K +//! AM_HAL_PWRCTRL_MEMEN_SRAM32K +//! AM_HAL_PWRCTRL_MEMEN_SRAM64K +//! AM_HAL_PWRCTRL_MEMEN_SRAM96K +//! AM_HAL_PWRCTRL_MEMEN_SRAM128K +//! AM_HAL_PWRCTRL_MEMEN_SRAM160K +//! AM_HAL_PWRCTRL_MEMEN_SRAM192K +//! AM_HAL_PWRCTRL_MEMEN_SRAM224K +//! AM_HAL_PWRCTRL_MEMEN_SRAM256K +//! AM_HAL_PWRCTRL_MEMEN_ALL (the default, power-up state) +//! +//! This function enables/disables power to provide only the given amount of +//! the type of memory specified. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! Settings for zero SRAM or FLASH are not provided as device behavior under +//! either of those conditions is undefined. +//! +//! @note Unpowered memory devices may lose their configuration information. +//! This function does not save or restore peripheral configuration registers. +//! +//! @return None. +// +//***************************************************************************** +bool +am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn) +{ + uint32_t ui32MemEnMask, ui32MemDisMask; + uint32_t ui32PwrStatEnMask, ui32PwrStatDisMask; + int32_t i32TOcnt; + + if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_FLASH512K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_FLASH0_EN; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_FLASH1_EN; + ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M; + ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_FLASH1M ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_FLASH0_EN | + AM_REG_PWRCTRL_MEMEN_FLASH1_EN; + ui32MemDisMask = 0; + ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M | + AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M; + ui32PwrStatDisMask = 0; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM8K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM16K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM24K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 | + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 | + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~(AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 | + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 | + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2); + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM32K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM64K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM96K ) + { + ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM96K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_HAL_PWRCTRL_MEMEN_SRAM96K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM128K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM160K ) + { + ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM160K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_HAL_PWRCTRL_MEMEN_SRAM160K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM192K ) + { + ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM192K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_HAL_PWRCTRL_MEMEN_SRAM192K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM224K ) + { + ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM224K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_HAL_PWRCTRL_MEMEN_SRAM224K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM256K ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL & + ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K; + ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL & + ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_CACHE ) + { + ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | + AM_REG_PWRCTRL_MEMEN_CACHEB2_EN; + ui32MemDisMask = 0; + ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M | + AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M; + ui32PwrStatDisMask = 0; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_CACHE_DIS ) + { + ui32MemEnMask = 0; + ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | + AM_REG_PWRCTRL_MEMEN_CACHEB2_EN; + ui32PwrStatEnMask = 0; + ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M | + AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M; + } + else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_ALL ) + { + ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_ALL; + ui32MemDisMask = 0; + ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL; + ui32PwrStatDisMask = 0; + } + else + { + return false; + } + + // + // Disable unneeded memory. If nothing to be disabled, skip to save time. + // + // Note that a deliberate disable step using a disable mask is taken here + // for 2 reasons: 1) To only affect the specified type of memory, and 2) + // To avoid inadvertently disabling any memory currently being depended on. + // + if ( ui32MemDisMask != 0 ) + { + AM_REG(PWRCTRL, MEMEN) &= ~ui32MemDisMask; + } + + // + // Enable the required memory. + // + if ( ui32MemEnMask != 0 ) + { + AM_REG(PWRCTRL, MEMEN) |= ui32MemEnMask; + } + + // + // Wait for the power to be turned on. + // Apollo2 note - these loops typically end up taking 1 iteration. + // + i32TOcnt = 200; + if ( ui32PwrStatDisMask ) + { + while ( --i32TOcnt && + ( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatDisMask ) ); + } + + if ( i32TOcnt <= 0 ) + { + return false; + } + + i32TOcnt = 200; + if ( ui32PwrStatEnMask ) + { + while ( --i32TOcnt && + (( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatEnMask ) + != ui32PwrStatEnMask) ); + } + if ( i32TOcnt <= 0 ) + { + return false; + } + + return true; +} + +//***************************************************************************** +// +//! @brief Initialize the core and memory buck converters. +//! +//! This function is intended to be used for first time core and memory buck +//! converters initialization. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_pwrctrl_bucks_init(void) +{ + am_hal_pwrctrl_bucks_enable(); + + while ( ( AM_REG(PWRCTRL, POWERSTATUS) & + ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M | + AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) ) != + ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M | + AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) ); + + // + // Additional delay to make sure BUCKs are initialized. + // + am_hal_flash_delay(200 / 3); +} + +//***************************************************************************** +// +//! @brief Enable the core and memory buck converters. +//! +//! This function enables the core and memory buck converters. +//! +//! @return None +// +//***************************************************************************** +#define LDO_TRIM_REG_ADDR (0x50023004) +#define BUCK_TRIM_REG_ADDR (0x50023000) + +void +am_hal_pwrctrl_bucks_enable(void) +{ + // + // Check to see if the bucks are already on. If so, we can just return. + // + if ( AM_BFR(PWRCTRL, POWERSTATUS, COREBUCKON) && + AM_BFR(PWRCTRL, POWERSTATUS, MEMBUCKON) ) + { + return; + } + + // + // Enable BUCK power up + // + AM_BFW(PWRCTRL, SUPPLYSRC, COREBUCKEN, 1); + AM_BFW(PWRCTRL, SUPPLYSRC, MEMBUCKEN, 1); + + // + // Make sure bucks are ready. + // + while ( ( AM_REG(PWRCTRL, POWERSTATUS) & + ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M | + AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) ) != + ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M | + AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) ); +} + +//***************************************************************************** +// +//! @brief Disable the core and memory buck converters. +//! +//! This function disables the core and memory buck converters. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_pwrctrl_bucks_disable(void) +{ + // + // Check to see if the bucks are already off. If so, we can just return. + // + if ( AM_BFR(PWRCTRL, POWERSTATUS, COREBUCKON) == 0 && + AM_BFR(PWRCTRL, POWERSTATUS, MEMBUCKON) == 0) + { + return; + } + + // + // Handle the special case if only the ADC is powered. + // + if ( isRev_ADC() && + (AM_REG(PWRCTRL, DEVICEEN) == AM_REG_PWRCTRL_DEVICEEN_PWRADC_EN) ) + { + // + // Set SUPPLYSRC to handle this case + // + AM_REG(PWRCTRL, SUPPLYSRC) &= + (AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN | + AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN); + } + else + { + // + // Power them down + // + AM_BFW(PWRCTRL, SUPPLYSRC, COREBUCKEN, 0); + AM_BFW(PWRCTRL, SUPPLYSRC, MEMBUCKEN, 0); + } + + // + // Wait until BUCKs are disabled. + // + am_hal_flash_delay(AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES / 3); +} + +//***************************************************************************** +// +//! @brief Misc low power initializations. +//! +//! This function performs low power initializations that aren't specifically +//! handled elsewhere. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_pwrctrl_low_power_init(void) +{ + // + // For lowest power, we enable clock gating for all SRAM configuration. + // + AM_REG(PWRCTRL, SRAMCTRL) |= + AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN | + AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN | + AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS; + + // + // For lowest deep sleep power, make sure we stay in BUCK mode. + // + AM_REG(PWRCTRL, SUPPLYSRC) &= + ~AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_pwrctrl.h b/mcu/apollo2/hal/am_hal_pwrctrl.h new file mode 100644 index 0000000..65983a4 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_pwrctrl.h @@ -0,0 +1,351 @@ +//***************************************************************************** +// +// am_hal_pwrctrl.h +//! @file +//! +//! @brief Functions for enabling and disabling power domains. +//! +//! @addtogroup pwrctrl2 Power Control +//! @ingroup apollo2hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_HAL_PWRCTRL_H +#define AM_HAL_PWRCTRL_H + +//***************************************************************************** +// +// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable() +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_ADC AM_REG_PWRCTRL_DEVICEEN_PWRADC_EN +#define AM_HAL_PWRCTRL_IOM0 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN +#define AM_HAL_PWRCTRL_IOM1 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN +#define AM_HAL_PWRCTRL_IOM2 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN +#define AM_HAL_PWRCTRL_IOM3 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN +#define AM_HAL_PWRCTRL_IOM4 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN +#define AM_HAL_PWRCTRL_IOM5 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN +#define AM_HAL_PWRCTRL_IOS AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN +#define AM_HAL_PWRCTRL_PDM AM_REG_PWRCTRL_DEVICEEN_PWRPDM_EN +#define AM_HAL_PWRCTRL_UART0 AM_REG_PWRCTRL_DEVICEEN_PWRUART0_EN +#define AM_HAL_PWRCTRL_UART1 AM_REG_PWRCTRL_DEVICEEN_PWRUART1_EN + +//***************************************************************************** +// +// Macro to set the appropriate IOM peripheral when using +// am_hal_pwrctrl_periph_enable()/disable(). +// For Apollo2, the module argument must resolve to be a value from 0-5. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_IOM(module) \ + (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN << module) + +//***************************************************************************** +// +// Macro to set the appropriate UART peripheral when using +// am_hal_pwrctrl_periph_enable()/disable(). +// For Apollo2, the module argument must resolve to be a value from 0-1. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_UART(module) \ + (AM_REG_PWRCTRL_DEVICEEN_PWRUART0_EN << module) + + +//***************************************************************************** +// +// Memory enable values for am_hal_pwrctrl_memory_enable() +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMEN_SRAM8K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K +#define AM_HAL_PWRCTRL_MEMEN_SRAM16K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K +#define AM_HAL_PWRCTRL_MEMEN_SRAM24K (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2) +#define AM_HAL_PWRCTRL_MEMEN_SRAM32K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K +#define AM_HAL_PWRCTRL_MEMEN_SRAM64K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K +#define AM_HAL_PWRCTRL_MEMEN_SRAM96K \ + (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2) +#define AM_HAL_PWRCTRL_MEMEN_SRAM128K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K +#define AM_HAL_PWRCTRL_MEMEN_SRAM160K \ + (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4) +#define AM_HAL_PWRCTRL_MEMEN_SRAM192K \ + (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5) +#define AM_HAL_PWRCTRL_MEMEN_SRAM224K \ + (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5 | \ + AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6) +#define AM_HAL_PWRCTRL_MEMEN_SRAM256K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K + +#define AM_HAL_PWRCTRL_MEMEN_FLASH512K AM_REG_PWRCTRL_MEMEN_FLASH0_EN +#define AM_HAL_PWRCTRL_MEMEN_FLASH1M \ + (AM_REG_PWRCTRL_MEMEN_FLASH0_EN | \ + AM_REG_PWRCTRL_MEMEN_FLASH1_EN) +#define AM_HAL_PWRCTRL_MEMEN_CACHE \ + (AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \ + AM_REG_PWRCTRL_MEMEN_CACHEB2_EN) +#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS \ + ~(AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \ + AM_REG_PWRCTRL_MEMEN_CACHEB2_EN) + +// +// Power up all available memory devices (this is the default power up state) +// +#define AM_HAL_PWRCTRL_MEMEN_ALL \ + (AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL | \ + AM_REG_PWRCTRL_MEMEN_FLASH0_EN | \ + AM_REG_PWRCTRL_MEMEN_FLASH1_EN | \ + AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \ + AM_REG_PWRCTRL_MEMEN_CACHEB2_EN) + +//***************************************************************************** +// +// Peripheral power enable and disable delays +// The delay counts are based on an internal clock that runs at half of +// HFRC. Therefore, we need to double the delay cycles. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES (22 * 2) +#define AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES (22 * 2) + +// +// Use the following only when enabling after sleep (not during initialization). +// +#define AM_HAL_PWRCTRL_BUCKEN_DELAYCYCLES (0 * 2) +#define AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES (15 * 2) + +//***************************************************************************** +// +// Peripheral PWRONSTATUS groupings. +// +//***************************************************************************** +// +// Group DEVICEEN bits (per PWRONSTATUS groupings). +// +#define AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 \ + (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN | \ + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN | \ + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN ) + +#define AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 \ + (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN | \ + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN | \ + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN ) + +#define AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS \ + (AM_REG_PWRCTRL_DEVICEEN_PWRUART0_EN | \ + AM_REG_PWRCTRL_DEVICEEN_PWRUART1_EN | \ + AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN ) + +#define AM_HAL_PWRCTRL_DEVICEEN_ADC AM_REG_PWRCTRL_DEVICEEN_PWRADC_EN +#define AM_HAL_PWRCTRL_DEVICEEN_PDM AM_REG_PWRCTRL_DEVICEEN_PWRPDM_EN + +// +// Map PWRONSTATUS bits to peripheral groupings. +// +#define AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS AM_REG_PWRCTRL_PWRONSTATUS_PDA_M +#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5 AM_REG_PWRCTRL_PWRONSTATUS_PDC_M +#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2 AM_REG_PWRCTRL_PWRONSTATUS_PDB_M +#define AM_HAL_PWRCTRL_PWRONSTATUS_ADC AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M +#define AM_HAL_PWRCTRL_PWRONSTATUS_PDM AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M + +#define POLL_PWRSTATUS(ui32Peripheral) \ + if ( 1 ) \ + { \ + uint32_t ui32PwrOnStat; \ + if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 ) \ + { \ + ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2; \ + } \ + else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 ) \ + { \ + ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5; \ + } \ + else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS ) \ + { \ + ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS; \ + } \ + else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_ADC ) \ + { \ + ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_ADC; \ + } \ + else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_PDM ) \ + { \ + ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_PDM; \ + } \ + else \ + { \ + ui32PwrOnStat = 0xFFFFFFFF; \ + } \ + \ + /* */ \ + /* Wait for the power control setting to take effect. */ \ + /* */ \ + while ( !(AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrOnStat) ); \ + } + +//***************************************************************************** +// +// Memory PWRONSTATUS enable values for am_hal_pwrctrl_memory_enable() +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \ + (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ + AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) + +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +extern void am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral); +extern void am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral); +extern bool am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn); +extern void am_hal_pwrctrl_bucks_init(void); +extern void am_hal_pwrctrl_bucks_enable(void); +extern void am_hal_pwrctrl_bucks_disable(void); +extern void am_hal_pwrctrl_low_power_init(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_PWRCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_queue.c b/mcu/apollo2/hal/am_hal_queue.c new file mode 100644 index 0000000..2d51163 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_queue.c @@ -0,0 +1,286 @@ +//***************************************************************************** +// +// am_hal_queue.c +//! @file +//! +//! @brief Functions for implementing a queue system. +//! +//! @addtogroup Miscellaneous2 Software Features (MISC) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Initializes a queue. +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvData - Pointer to a memory location to be used for data storage. +//! @param ui32ItemSize - Number of bytes per item in the queue. +//! @param ui32ArraySize - Number of bytes in the data array. +//! +//! This function initializes the members of a queue structure and attaches it +//! to an array of memory that it can use for storage. This function should be +//! called before the queue is used. +//! +//! In this example, we are creating a queue that can hold 1024 32-bit +//! integers. The integers themselves will be stored in the array named +//! pui32WorkingSpace, while information about the queue itself will be stored +//! in sDataQueue. +//! +//! @note The caller should not modify any of the members of am_hal_queue_t +//! structures. The queue API will handle these members in a thread-safe way. +//! +//! @note The queue will remember what size data is in it. Other queue API +//! functions will perform transfers in units of "items" where one "item" is +//! the number of bytes you specify in the \e ui32ItemSize argument upon +//! initialization. +//! +//! Example usage: +//! +//! @code +//! +//! // +//! // Declare a queue structure and an array of bytes we can use to store +//! // data. +//! // +//! am_hal_queue_t sDataQueue; +//! uint32_t pui32WorkingSpace[1024]; +//! +//! // +//! // Attach the queue structure to the working memory. +//! // +//! am_hal_queue_init(&sDataQueue, pui8WorkingSpace, sizeof(uint32_t) +//! sizeof(pui32WorkingSpace)); +//! +//! @endcode +//! +//! The am_hal_queue_from_array macro is a convenient shorthand for this +//! operation. The code below does the same thing as the code above. +//! +//! @code +//! +//! // +//! // Declare a queue structure and an array of bytes we can use to store +//! // data. +//! // +//! am_hal_queue_t sDataQueue; +//! uint32_t pui32WorkingSpace[1024]; +//! +//! // +//! // Attach the queue structure to the working memory. +//! // +//! am_hal_queue_from_array(&sDataQueue, pui8WorkingSpace); +//! +//! @endcode +// +//***************************************************************************** +void +am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, + uint32_t ui32ArraySize) +{ + psQueue->ui32WriteIndex = 0; + psQueue->ui32ReadIndex = 0; + psQueue->ui32Length = 0; + psQueue->ui32Capacity = ui32ArraySize; + psQueue->ui32ItemSize = ui32ItemSize; + psQueue->pui8Data = (uint8_t *) pvData; +} + +//***************************************************************************** +// +//! @brief Adds an item to the Queue +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvSource - Pointer to the data to be added. +//! @param ui32NumItems - Number of items to be added. +//! +//! This function will copy the data pointed to by pvSource into the queue. The +//! \e ui32NumItems term specifies the number of items to be copied from \e +//! pvSource. The size of an "item" depends on how the queue was initialized. +//! Please see am_hal_queue_init() for more information on this. +//! +//! @return true if the add operation was successful, or false if the queue +//! didn't have enough space. +// +//***************************************************************************** +bool +am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems) +{ + uint32_t i; + uint8_t *pui8Source; + uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize; + bool bSuccess = false; + uint32_t ui32Primask; + + pui8Source = (uint8_t *) pvSource; + + ui32Primask = am_hal_interrupt_master_disable(); + + // + // Check to make sure that the buffer isn't already full + // + if ( am_hal_queue_space_left(psQueue) >= ui32Bytes ) + { + // + // Loop over the bytes in the source array. + // + for ( i = 0; i < ui32Bytes; i++ ) + { + // + // Write the value to the buffer. + // + psQueue->pui8Data[psQueue->ui32WriteIndex] = pui8Source[i]; + + // + // Advance the write index, making sure to wrap if necessary. + // + psQueue->ui32WriteIndex = ((psQueue->ui32WriteIndex + 1) % + psQueue->ui32Capacity); + } + + // + // Update the length value appropriately. + // + psQueue->ui32Length += ui32Bytes; + + // + // Report a success. + // + bSuccess = true; + } + else + { + // + // The buffer can't fit the amount of data requested. Return a + // failure. + // + bSuccess = false; + } + + am_hal_interrupt_master_set(ui32Primask); + + return bSuccess; +} + +//***************************************************************************** +// +//! @brief Removes an item from the Queue +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvDest - Pointer to the data to be added. +//! @param ui32NumItems - Number of items to be added. +//! +//! This function will copy the data from the queue into the memory pointed to +//! by pvDest. The \e ui32NumItems term specifies the number of items to be +//! copied from the queue. The size of an "item" depends on how the queue was +//! initialized. Please see am_hal_queue_init() for more information on this. +//! +//! @return true if we were able to pull the requested number of items from the +//! queue, or false if the queue didn't have that many items to pull. +// +//***************************************************************************** +bool +am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems) +{ + uint32_t i; + uint8_t *pui8Dest; + uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize; + bool bSuccess = false; + uint32_t ui32Primask; + + pui8Dest = (uint8_t *) pvDest; + + ui32Primask = am_hal_interrupt_master_disable(); + + // + // Check to make sure that the buffer isn't empty + // + if ( am_hal_queue_data_left(psQueue) >= ui32Bytes ) + { + // + // Loop over the bytes in the destination array. + // + for ( i = 0; i < ui32Bytes; i++ ) + { + // + // Grab the next value from the buffer. + // + pui8Dest[i] = psQueue->pui8Data[psQueue->ui32ReadIndex]; + + // + // Advance the read index, wrapping if needed. + // + psQueue->ui32ReadIndex = ((psQueue->ui32ReadIndex + 1) % + psQueue->ui32Capacity); + } + + // + // Adjust the length value to reflect the change. + // + psQueue->ui32Length -= ui32Bytes; + + // + // Report a success. + // + bSuccess = true; + } + else + { + // + // If the buffer didn't have enough data, just return false. + // + bSuccess = false; + } + + am_hal_interrupt_master_set(ui32Primask); + + return bSuccess; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_queue.h b/mcu/apollo2/hal/am_hal_queue.h new file mode 100644 index 0000000..b0f1d10 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_queue.h @@ -0,0 +1,123 @@ +//***************************************************************************** +// +// am_hal_queue.h +//! @file +//! +//! @brief Functions for implementing a queue system. +//! +//! @addtogroup Miscellaneous2 Software Features (MISC) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_QUEUE_H +#define AM_HAL_QUEUE_H + +//***************************************************************************** +// +//! @brief A data structure that will operate as a queue. +//! +//! This data structure holds information necessary for operating a thread-safe +//! queue. When declaring a structure of type am_hal_queue_t, you will also need +//! to provide some working memory for the queue to use. For more information on +//! setting up and using the am_hal_queue_t structure, please see the +//! documentation for am_hal_queue_init(). +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32WriteIndex; + uint32_t ui32ReadIndex; + uint32_t ui32Length; + uint32_t ui32Capacity; + uint32_t ui32ItemSize; + uint8_t *pui8Data; +} +am_hal_queue_t; + +//***************************************************************************** +// +// Function-like macros. +// +//***************************************************************************** +#define am_hal_queue_empty(psQueue) \ + ((psQueue)->ui32Length == 0) + +#define am_hal_queue_full(psQueue) \ + ((psQueue)->ui32Length == (psQueue)->ui32Capacity) + +#define am_hal_queue_space_left(psQueue) \ + ((psQueue)->ui32Capacity - (psQueue)->ui32Length) + +#define am_hal_queue_data_left(psQueue) \ + ((psQueue)->ui32Length) + +//***************************************************************************** +// +// Use this to make sure you get the size parameters right. +// +//***************************************************************************** +#define am_hal_queue_from_array(queue, array) \ + am_hal_queue_init((queue), (array), sizeof((array)[0]), sizeof(array)) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, uint32_t ui32ArraySize); +extern bool am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems); +extern bool am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_QUEUE_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_reset.c b/mcu/apollo2/hal/am_hal_reset.c new file mode 100644 index 0000000..7298f0d --- /dev/null +++ b/mcu/apollo2/hal/am_hal_reset.c @@ -0,0 +1,160 @@ +//***************************************************************************** +// +// am_hal_reset.c +//! @file +//! +//! @brief Hardware abstraction layer for the Reset Generator module. +//! +//! @addtogroup rstgen2 Reset Generator (RSTGEN) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Configure the Reset Generator. +//! +//! @param ui32Config - Or together the supplied macros to enable +//! configurations to obtain the desired reset generator settings. +//! +//! This function will set the reset generator's configuration register based on +//! the user's desired settings listed in the supplied arugment. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_reset_init(uint32_t ui32Config) +{ + // + // Write the configuration to the reset generator + // + AM_REG(RSTGEN, CFG) = ui32Config; +} + +//***************************************************************************** +// +//! @brief Issue a POR (Apollo's last stage interrupt). +//! +//! This function will issue a POR reset. +//! The Apollo chip has numerous stages of reset. POR is the last and is also +//! the reset invoked by the chip's reset pin, the watchdog timer, the AIRCR +//! reset, and the SWD debugger requested interrupt. +//! +//! The Debug Access Port in the M4 is not cleared by this reset. +//! +//! @return None. +// +//***************************************************************************** +void am_hal_reset_por(void) +{ + // + // Write the POR key to the software POR register. + // + AM_REG(RSTGEN, SWPOR) = + AM_REG_RSTGEN_SWPOR_SWPORKEY(AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE); +} + +//***************************************************************************** +// +//! @brief Issue a POI (Apollo's second stage interrupt). +//! +//! This function will issue a POI reset. +//! The Apollo chip has numerous stages of reset. POI is the second stage. +//! A few modules are reset by POI that are not reset by POR, notably POI +//! causes the shadow registers to be reloaded from the OTP. A full power +//! cycle or POI should be used after writing new flash, debug or SRAM +//! protection bits into the OTP for these protections to take effect. +//! +//! The Debug Access Port in the M4 is not cleared by this reset. +//! +//! @return None. +// +//***************************************************************************** +void am_hal_reset_poi(void) +{ + // + // Write the POI key to the software POI register. + // + AM_REG(RSTGEN, SWPOI) = + AM_REG_RSTGEN_SWPOI_SWPOIKEY(AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE); +} + +//***************************************************************************** +// +//! @brief Retrieve the status bits from the reset generator. +//! +//! This function will get the status bits from the reset generator. +//! These bits are sticky and show the accumulation of reset types that the +//! Apollo chip has experienced since power on. One should clear these out +//! after reading them. +//! +//! @return None. +// +//***************************************************************************** +uint32_t am_hal_reset_status_get(void) +{ + // + // Retrieve the reset generator status bits + // + return AM_REG(RSTGEN, STAT); +} + +//***************************************************************************** +// +//! @brief Clear ALL of the status bits in the reset generator. +//! +//! This function will clear all status bits in the reset generator status. +//! +//! @return None. +// +//***************************************************************************** +void am_hal_reset_status_clear(void) +{ + AM_REG(RSTGEN, CLRSTAT) = AM_REG_RSTGEN_CLRSTAT_CLRSTAT(1); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_reset.h b/mcu/apollo2/hal/am_hal_reset.h new file mode 100644 index 0000000..90a2556 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_reset.h @@ -0,0 +1,119 @@ +//***************************************************************************** +// +// am_hal_reset.h +//! @file +//! +//! @brief Hardware abstraction layer for the Reset Generator module. +//! +//! @addtogroup wdt2 Watchdog Timer (RSTGEN) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_RSTGEN_H +#define AM_HAL_RSTGEN_H + +//***************************************************************************** +// +//! @name Reset Generator Configuration +//! @brief These macros may be used to set the reset generator's configuration. +//! @{ +// +//***************************************************************************** +#define AM_HAL_RESET_CFG_WDT_RESET_ENABLE (AM_REG_RSTGEN_CFG_WDREN(1)) +// Brown out high (2.1v) reset enable. +#define AM_HAL_RESET_CFG_BOD_HIGH_RESET_ENABLE (AM_REG_RSTGEN_CFG_BODHREN(1)) +//! @} + +//***************************************************************************** +// +//! @name Reset Generator Status Bit Masks +//! @brief These macros may be used to determine which type(s) of resets have +//! been seen. +//! @{ +// +//***************************************************************************** +// Reset was initiated by a Watchdog Timer Reset. +#define AM_HAL_RESET_STAT_WDT (AM_REG_RSTGEN_STAT_WDRSTAT_M) + +// Reset was a initiated by Debugger Reset. +#define AM_HAL_RESET_STAT_DEBUG (AM_REG_RSTGEN_STAT_DBGRSTAT_M) + +// Reset was a initiated by Software POI Reset. +#define AM_HAL_RESET_STAT_POI (AM_REG_RSTGEN_STAT_POIRSTAT_M) + +// Reset was a initiated by Software POR or AIRCR Reset. +#define AM_HAL_RESET_STAT_SOFTWARE (AM_REG_RSTGEN_STAT_SWRSTAT_M) + +// Reset was initiated by a Brown-Out Reset. +#define AM_HAL_RESET_STAT_BOD (AM_REG_RSTGEN_STAT_BORSTAT_M) + +// Reset was initiated by a Power Cycle +#define AM_HAL_RESET_STAT_POWER_CYCLE (AM_REG_RSTGEN_STAT_PORSTAT_M) + +// Reset was initiated by an External Reset. +#define AM_HAL_RESET_STAT_EXTERNAL (AM_REG_RSTGEN_STAT_EXRSTAT_M) +//! @} + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_reset_init(uint32_t ui32Config); +extern void am_hal_reset_por(void); +extern void am_hal_reset_poi(void); +extern uint32_t am_hal_reset_status_get(void); +extern void am_hal_reset_status_clear(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_RSTGEN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_rtc.c b/mcu/apollo2/hal/am_hal_rtc.c new file mode 100644 index 0000000..ef1af4b --- /dev/null +++ b/mcu/apollo2/hal/am_hal_rtc.c @@ -0,0 +1,682 @@ +//***************************************************************************** +// +// am_hal_rtc.c +//! @file +//! +//! @brief Functions for interfacing with the Real-Time Clock (RTC). +//! +//! @addtogroup rtc2 Real-Time Clock (RTC) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Converts a Binary Coded Decimal (BCD) byte to its Decimal form. +// +//***************************************************************************** +static uint8_t +bcd_to_dec(uint8_t ui8BCDByte) +{ + return (((ui8BCDByte & 0xF0) >> 4) * 10) + (ui8BCDByte & 0x0F); +} + +//***************************************************************************** +// +// Converts a Decimal byte to its Binary Coded Decimal (BCD) form. +// +//***************************************************************************** +static uint8_t +dec_to_bcd(uint8_t ui8DecimalByte) +{ + return (((ui8DecimalByte / 10) << 4) | (ui8DecimalByte % 10)); +} + +//***************************************************************************** +// +//! @brief Selects the clock source for the RTC. +//! +//! @param ui32OSC the clock source for the RTC. +//! +//! This function selects the clock source for the RTC. +//! +//! Valid values for ui32OSC are: +//! +//! AM_HAL_RTC_OSC_LFRC +//! AM_HAL_RTC_OSC_XT +//! +//! @return None +//! +//! @note After selection of the RTC oscillator, a 2 second delay occurs before +//! the new setting is reflected in status. Therefore the CLKGEN.STATUS.OMODE +//! bit will not reflect the new status until after the 2s wait period. +// +//***************************************************************************** +void +am_hal_rtc_osc_select(uint32_t ui32OSC) +{ + // + // Set XT if flag is set. + // Otherwise configure for LFRC. + // + if (ui32OSC) + { + AM_REG(CLKGEN, OCTRL) |= AM_REG_CLKGEN_OCTRL_OSEL_M; + } + else + { + AM_REG(CLKGEN, OCTRL) &= ~AM_REG_CLKGEN_OCTRL_OSEL_M; + } +} + +//***************************************************************************** +// +//! @brief Enable/Start the RTC oscillator. +//! +//! Starts the RTC oscillator. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_osc_enable(void) +{ + // + // Start the RTC Oscillator. + // + AM_REG(RTC, RTCCTL) &= ~AM_REG_RTC_RTCCTL_RSTOP(1); +} + +//***************************************************************************** +// +//! @brief Disable/Stop the RTC oscillator. +//! +//! Stops the RTC oscillator. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_osc_disable(void) +{ + // + // Stop the RTC Oscillator. + // + AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_RSTOP(1); +} + +//***************************************************************************** +// +//! @brief Configures the RTC for 12 or 24 hour time keeping. +//! +//! @param b12Hour - A 'true' configures the RTC for 12 hour time keeping. +//! +//! Configures the RTC for 12 (true) or 24 (false) hour time keeping. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_time_12hour(bool b12Hour) +{ + // + // Set the 12/24 hour bit. + // + AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_HR1224(b12Hour); +} + +//***************************************************************************** +// +//! @brief Enable selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Enables the RTC interrupts. +//! +//! ui32Interrupt should be an OR of the following: +//! +//! AM_HAL_RTC_INT_ALM +//! AM_HAL_RTC_INT_OF +//! AM_HAL_RTC_INT_ACC +//! AM_HAL_RTC_INT_ACF +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupts. + // + AM_REG(RTC, INTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled RTC interrupts. +//! +//! Returns the enabled RTC interrupts. +//! +//! @return enabled RTC interrupts. Return is a logical or of: +//! +//! AM_HAL_RTC_INT_ALM +//! AM_HAL_RTC_INT_OF +//! AM_HAL_RTC_INT_ACC +//! AM_HAL_RTC_INT_ACF +// +//***************************************************************************** +uint32_t +am_hal_rtc_int_enable_get(void) +{ + // + // Read the RTC interrupt enable register, and return its contents. + // + return AM_REG(RTC, INTEN); +} + +//***************************************************************************** +// +//! @brief Disable selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Disables the RTC interrupts. +//! +//! ui32Interrupt should be an OR of the following: +//! +//! AM_HAL_RTC_INT_ALM +//! AM_HAL_RTC_INT_OF +//! AM_HAL_RTC_INT_ACC +//! AM_HAL_RTC_INT_ACF +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupts. + // + AM_REG(RTC, INTEN) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Sets the selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Sets the RTC interrupts causing them to immediately trigger. +//! +//! ui32Interrupt should be an OR of the following: +//! +//! AM_HAL_RTC_INT_ALM +//! AM_HAL_RTC_INT_OF +//! AM_HAL_RTC_INT_ACC +//! AM_HAL_RTC_INT_ACF +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + AM_REG(RTC, INTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clear selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Clears the RTC interrupts. +//! +//! ui32Interrupt should be an OR of the following: +//! +//! AM_HAL_RTC_INT_ALM +//! AM_HAL_RTC_INT_OF +//! AM_HAL_RTC_INT_ACC +//! AM_HAL_RTC_INT_ACF +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_clear(uint32_t ui32Interrupt) +{ + // + // Clear the interrupts. + // + AM_REG(RTC, INTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Returns the RTC interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! Returns the RTC interrupt status. +//! +//! @return Bitwise representation of the current interrupt status. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_RTC_INT_ALM +//! AM_HAL_RTC_INT_OF +//! AM_HAL_RTC_INT_ACC +//! AM_HAL_RTC_INT_ACF +// +//***************************************************************************** +uint32_t +am_hal_rtc_int_status_get(bool bEnabledOnly) +{ + // + // Get the interrupt status. + // + if (bEnabledOnly) + { + uint32_t u32RetVal; + u32RetVal = AM_REG(RTC, INTSTAT); + u32RetVal &= AM_REG(RTC, INTEN); + return u32RetVal & + (AM_HAL_RTC_INT_ALM | AM_HAL_RTC_INT_OF | + AM_HAL_RTC_INT_ACC | AM_HAL_RTC_INT_ACF); + } + else + { + return (AM_REG(RTC, INTSTAT) & (AM_HAL_RTC_INT_ALM | + AM_HAL_RTC_INT_OF | + AM_HAL_RTC_INT_ACC | + AM_HAL_RTC_INT_ACF)); + } +} + +//***************************************************************************** +// +//! @brief Set the Real Time Clock counter registers. +//! +//! @param *pTime - A pointer to the time structure. +//! +//! Sets the RTC counter registers to the supplied values. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_time_set(am_hal_rtc_time_t *pTime) +{ + // + // Enable writing to the counters. + // + AM_REG(RTC, RTCCTL) |= AM_REG_RTC_RTCCTL_WRTC(1); + + // + // Write the RTCLOW register. + // + AM_REG(RTC, CTRLOW) = + AM_REG_RTC_CTRLOW_CTRHR(dec_to_bcd(pTime->ui32Hour)) | + AM_REG_RTC_CTRLOW_CTRMIN(dec_to_bcd(pTime->ui32Minute)) | + AM_REG_RTC_CTRLOW_CTRSEC(dec_to_bcd(pTime->ui32Second)) | + AM_REG_RTC_CTRLOW_CTR100(dec_to_bcd(pTime->ui32Hundredths)); + + // + // Write the RTCUP register. + // + AM_REG(RTC, CTRUP) = + AM_REG_RTC_CTRUP_CEB((pTime->ui32CenturyEnable)) | + AM_REG_RTC_CTRUP_CB((pTime->ui32Century)) | + AM_REG_RTC_CTRUP_CTRWKDY((pTime->ui32Weekday)) | + AM_REG_RTC_CTRUP_CTRYR(dec_to_bcd((pTime->ui32Year))) | + AM_REG_RTC_CTRUP_CTRMO(dec_to_bcd((pTime->ui32Month))) | + AM_REG_RTC_CTRUP_CTRDATE(dec_to_bcd((pTime->ui32DayOfMonth))); + + // + // Disable writing to the counters. + // + AM_REG(RTC, RTCCTL) &= ~AM_REG_RTC_RTCCTL_WRTC(1); +} + +//***************************************************************************** +// +//! @brief Get the Real Time Clock current time. +//! +//! @param *pTime - A pointer to the time structure to store the current time. +//! +//! Gets the RTC's current time +//! +//! @return 0 for success and 1 for error. +// +//***************************************************************************** +uint32_t +am_hal_rtc_time_get(am_hal_rtc_time_t *pTime) +{ + uint32_t ui32RTCLow, ui32RTCUp, ui32Value; + + // + // Read the upper and lower RTC registers. + // + ui32RTCLow = AM_REG(RTC, CTRLOW); + ui32RTCUp = AM_REG(RTC, CTRUP); + + // + // Break out the lower word. + // + ui32Value = + ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTRHR_M) >> AM_REG_RTC_CTRLOW_CTRHR_S); + pTime->ui32Hour = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTRMIN_M) >> AM_REG_RTC_CTRLOW_CTRMIN_S); + pTime->ui32Minute = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTRSEC_M) >> AM_REG_RTC_CTRLOW_CTRSEC_S); + pTime->ui32Second = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & AM_REG_RTC_CTRLOW_CTR100_M) >> AM_REG_RTC_CTRLOW_CTR100_S); + pTime->ui32Hundredths = bcd_to_dec(ui32Value); + + // + // Break out the upper word. + // + pTime->ui32ReadError = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CTERR_M) >> AM_REG_RTC_CTRUP_CTERR_S); + + pTime->ui32CenturyEnable = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CEB_M) >> AM_REG_RTC_CTRUP_CEB_S); + + pTime->ui32Century = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CB_M) >> AM_REG_RTC_CTRUP_CB_S); + + ui32Value = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRWKDY_M) >> AM_REG_RTC_CTRUP_CTRWKDY_S); + pTime->ui32Weekday = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRYR_M) >> AM_REG_RTC_CTRUP_CTRYR_S); + pTime->ui32Year = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRMO_M) >> AM_REG_RTC_CTRUP_CTRMO_S); + pTime->ui32Month = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & AM_REG_RTC_CTRUP_CTRDATE_M) >> AM_REG_RTC_CTRUP_CTRDATE_S); + pTime->ui32DayOfMonth = bcd_to_dec(ui32Value); + + // + // Was there a read error? + // + if (pTime->ui32ReadError) + { + return 1; + } + else + { + return 0; + } +} + +//***************************************************************************** +// +//! @brief Sets the alarm repeat interval. +//! +//! @param ui32RepeatInterval the desired repeat interval. +//! +//! Sets the alarm repeat interval. +//! +//! Valid values for ui32RepeatInterval: +//! +//! AM_HAL_RTC_ALM_RPT_DIS +//! AM_HAL_RTC_ALM_RPT_YR +//! AM_HAL_RTC_ALM_RPT_MTH +//! AM_HAL_RTC_ALM_RPT_WK +//! AM_HAL_RTC_ALM_RPT_DAY +//! AM_HAL_RTC_ALM_RPT_HR +//! AM_HAL_RTC_ALM_RPT_MIN +//! AM_HAL_RTC_ALM_RPT_SEC +//! AM_HAL_RTC_ALM_RPT_10TH +//! AM_HAL_RTC_ALM_RPT_100TH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval) +{ + uint32_t ui32RptInt, ui32Alm100, ui32Value; + + switch(ui32RepeatInterval) + { + // + // If repeat every 10th set RPT and ALM100 field accordinly + // + case AM_HAL_RTC_ALM_RPT_10TH: + ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC; + ui32Alm100 = AM_HAL_RTC_ALM100_10TH; + break; + // + // If repeat every 100th set RPT and ALM100 field accordinly + // + case AM_HAL_RTC_ALM_RPT_100TH: + ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC; + ui32Alm100 = AM_HAL_RTC_ALM100_100TH; + break; + // + // Otherwise set RPT as value passed. ALM100 values need to be 0xnn + // in this setting where n = 0-9. + // + default: + // + // Get the current value of the ALM100 field. + // + ui32Value = AM_BFR(RTC, ALMLOW, ALM100); + + // + // If ALM100 was previous EVERY_10TH or EVERY_100TH reset to zero + // otherwise keep previous setting. + // + ui32Alm100 = ui32Value >= 0xF0 ? 0 : ui32Value; + + // + // Set RPT value to value passed. + // + ui32RptInt = ui32RepeatInterval; + break; + } + + // + // Write the interval to the register. + // + AM_BFW(RTC, RTCCTL, RPT, ui32RptInt); + + // + // Write the Alarm 100 bits in the ALM100 register. + // + AM_BFW(RTC, ALMLOW, ALM100, ui32Alm100); +} + +//***************************************************************************** +// +//! @brief Sets the RTC's Alarm. +//! +//! @param *pTime - A pointer to the time structure. +//! @param ui32RepeatInterval - the desired alarm repeat interval. +//! +//! Set the Real Time Clock Alarm Parameters. +//! +//! Valid values for ui32RepeatInterval: +//! +//! AM_HAL_RTC_ALM_RPT_DIS +//! AM_HAL_RTC_ALM_RPT_YR +//! AM_HAL_RTC_ALM_RPT_MTH +//! AM_HAL_RTC_ALM_RPT_WK +//! AM_HAL_RTC_ALM_RPT_DAY +//! AM_HAL_RTC_ALM_RPT_HR +//! AM_HAL_RTC_ALM_RPT_MIN +//! AM_HAL_RTC_ALM_RPT_SEC +//! AM_HAL_RTC_ALM_RPT_10TH +//! AM_HAL_RTC_ALM_RPT_EVERY_100TH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, uint32_t ui32RepeatInterval) +{ + uint8_t ui8Value = 0; + + // + // Write the interval to the register. + // + AM_REG(RTC, RTCCTL) |= + AM_REG_RTC_RTCCTL_RPT(ui32RepeatInterval > 0x7 ? 0x7 : ui32RepeatInterval); + + // + // Check if the interval is 10th or every 100th and track it in ui8Value. + // + if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_10TH) + { + ui8Value = 0xF0; + } + else if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_100TH) + { + ui8Value = 0xFF; + } + + // + // Write the ALMUP register. + // + AM_REG(RTC, ALMUP) = + AM_REG_RTC_ALMUP_ALMWKDY((pTime->ui32Weekday)) | + AM_REG_RTC_ALMUP_ALMMO(dec_to_bcd((pTime->ui32Month))) | + AM_REG_RTC_ALMUP_ALMDATE(dec_to_bcd((pTime->ui32DayOfMonth))); + + // + // Write the ALMLOW register. + // + AM_REG(RTC, ALMLOW) = + AM_REG_RTC_ALMLOW_ALMHR(dec_to_bcd(pTime->ui32Hour)) | + AM_REG_RTC_ALMLOW_ALMMIN(dec_to_bcd(pTime->ui32Minute)) | + AM_REG_RTC_ALMLOW_ALMSEC(dec_to_bcd(pTime->ui32Second)) | + AM_REG_RTC_ALMLOW_ALM100(dec_to_bcd(pTime->ui32Hundredths) | ui8Value); +} + +//***************************************************************************** +// +//! @brief Get the Real Time Clock Alarm Parameters +//! +//! @param *pTime - A pointer to the time structure to store the current alarm. +//! +//! Gets the RTC's Alarm time +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime) +{ + uint32_t ui32ALMLow, ui32ALMUp, ui32Value; + + // + // Read the upper and lower RTC registers. + // + ui32ALMLow = AM_REG(RTC, ALMLOW); + ui32ALMUp = AM_REG(RTC, ALMUP); + + // + // Break out the lower word. + // + ui32Value = + ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALMHR_M) >> AM_REG_RTC_ALMLOW_ALMHR_S); + pTime->ui32Hour = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALMMIN_M) >> AM_REG_RTC_ALMLOW_ALMMIN_S); + pTime->ui32Minute = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALMSEC_M) >> AM_REG_RTC_ALMLOW_ALMSEC_S); + pTime->ui32Second = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32ALMLow & AM_REG_RTC_ALMLOW_ALM100_M) >> AM_REG_RTC_ALMLOW_ALM100_S); + pTime->ui32Hundredths = bcd_to_dec(ui32Value); + + // + // Break out the upper word. + // + pTime->ui32ReadError = 0; + pTime->ui32CenturyEnable = 0; + pTime->ui32Century = 0; + + ui32Value = + ((ui32ALMUp & AM_REG_RTC_ALMUP_ALMWKDY_M) >> AM_REG_RTC_ALMUP_ALMWKDY_S); + pTime->ui32Weekday = bcd_to_dec(ui32Value); + + pTime->ui32Year = 0; + + ui32Value = + ((ui32ALMUp & AM_REG_RTC_ALMUP_ALMMO_M) >> AM_REG_RTC_ALMUP_ALMMO_S); + pTime->ui32Month = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32ALMUp & AM_REG_RTC_ALMUP_ALMDATE_M) >> AM_REG_RTC_ALMUP_ALMDATE_S); + pTime->ui32DayOfMonth = bcd_to_dec(ui32Value); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_rtc.h b/mcu/apollo2/hal/am_hal_rtc.h new file mode 100644 index 0000000..f381849 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_rtc.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +// am_hal_rtc.h +//! @file +//! +//! @brief Functions for interfacing and accessing the Real-Time Clock (RTC). +//! +//! @addtogroup rtc2 Real-Time Clock (RTC) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_RTC_H +#define AM_HAL_RTC_H + +//***************************************************************************** +// +//! @name OSC Start and Stop +//! @brief OSC Start and Stop defines. +//! +//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x(). +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_OSC_LFRC 0x1 +#define AM_HAL_RTC_OSC_XT 0x0 +//! @} + +//***************************************************************************** +// +//! @name RTC Interrupts +//! @brief Macro definitions for RTC interrupt status bits. +//! +//! These macros correspond to the bits in the RTC interrupt status register. +//! They may be used with any of the \e am_hal_rtc_int_x() functions. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_INT_ALM AM_REG_RTC_INTEN_ALM_M +#define AM_HAL_RTC_INT_OF AM_REG_RTC_INTEN_OF_M +#define AM_HAL_RTC_INT_ACC AM_REG_RTC_INTEN_ACC_M +#define AM_HAL_RTC_INT_ACF AM_REG_RTC_INTEN_ACF_M +//! @} + +//***************************************************************************** +// +//! @name RTC Alarm Repeat Interval. +//! @brief Macro definitions for the RTC alarm repeat interval. +//! +//! These macros correspond to the RPT bits in the RTCCTL register. +//! They may be used with the \e am_hal_rtc_alarm_interval_set() function. +//! +//! Note: AM_HAL_RTC_ALM_RPT_10TH and AM_HAL_RTC_ALM_RPT_100TH do not +//! correspond to the RPT bits but are used in conjunction with setting the +//! ALM100 bits in the ALMLOW register. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_ALM_RPT_DIS 0x0 +#define AM_HAL_RTC_ALM_RPT_YR 0x1 +#define AM_HAL_RTC_ALM_RPT_MTH 0x2 +#define AM_HAL_RTC_ALM_RPT_WK 0x3 +#define AM_HAL_RTC_ALM_RPT_DAY 0x4 +#define AM_HAL_RTC_ALM_RPT_HR 0x5 +#define AM_HAL_RTC_ALM_RPT_MIN 0x6 +#define AM_HAL_RTC_ALM_RPT_SEC 0x7 +#define AM_HAL_RTC_ALM_RPT_10TH 0x8 +#define AM_HAL_RTC_ALM_RPT_100TH 0x9 +//! @} + +//***************************************************************************** +// +//! @name RTC Alarm 100 Interval. +//! @brief Macro definitions for the RTC alarm ms intervals. +//! +//! These macros are used inside the #am_hal_rtc_alarm_interval_set function +//! when 10ms and 100ms repeated alarm intervals are desired. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_ALM100_DEFAULT 0x00 +#define AM_HAL_RTC_ALM100_10TH 0xF0 +#define AM_HAL_RTC_ALM100_100TH 0xFF +//! @} + +//***************************************************************************** +// +//! @brief The basic time structure used by the HAL for RTC interaction. +//! +//! All values are positive whole numbers. The HAL routines convert back and +//! forth to BCD. +// +//***************************************************************************** +typedef struct am_hal_rtc_time_struct +{ + uint32_t ui32ReadError; + uint32_t ui32CenturyEnable; + uint32_t ui32Weekday; + uint32_t ui32Century; + uint32_t ui32Year; + uint32_t ui32Month; + uint32_t ui32DayOfMonth; + uint32_t ui32Hour; + uint32_t ui32Minute; + uint32_t ui32Second; + uint32_t ui32Hundredths; +}am_hal_rtc_time_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_rtc_osc_select(uint32_t ui32OSC); +extern void am_hal_rtc_osc_enable(void); +extern void am_hal_rtc_osc_disable(void); +extern void am_hal_rtc_time_12hour(bool b12Hour); +extern void am_hal_rtc_time_set(am_hal_rtc_time_t *pTime); +extern uint32_t am_hal_rtc_time_get(am_hal_rtc_time_t *pTime); +extern void am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval); +extern void am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, + uint32_t ui32RepeatInterval); +extern void am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime); +extern void am_hal_rtc_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_rtc_int_enable_get(void); +extern void am_hal_rtc_int_disable(uint32_t ui32Interrupt); +extern void am_hal_rtc_int_clear(uint32_t ui32Interrupt); +extern void am_hal_rtc_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_rtc_int_status_get(bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_RTC_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_stimer.c b/mcu/apollo2/hal/am_hal_stimer.c new file mode 100644 index 0000000..58e187b --- /dev/null +++ b/mcu/apollo2/hal/am_hal_stimer.c @@ -0,0 +1,574 @@ +//***************************************************************************** +// +// am_hal_stimer.c +//! @file +//! +//! @brief Functions for interfacing with the system timer (STIMER). +//! +//! @addtogroup stimer2 System Timer (STIMER) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Set up the stimer. +//! +//! @param ui32STimerConfig is the value to load into the configuration reg. +//! +//! This function should be used to perform the initial set-up of the +//! stimer. +//! +//! @return The 32-bit current config of the STimer Config register +// +//***************************************************************************** +uint32_t +am_hal_stimer_config(uint32_t ui32STimerConfig) +{ + uint32_t ui32CurrVal; + + // + // Read the current config + // + ui32CurrVal = AM_REG(CTIMER, STCFG); + + // + // Write our configuration value. + // + AM_REG(CTIMER, STCFG) = ui32STimerConfig; + + // + // If all of the clock sources are not HFRC, disable LDO when sleeping if timers are enabled. + // + if ( (AM_BFR(CTIMER, STCFG, CLKSEL) == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16) || + (AM_BFR(CTIMER, STCFG, CLKSEL) == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) ) + { + AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 0); + } + else + { + AM_BFW(PWRCTRL, MISCOPT, DIS_LDOLPMODE_TIMERS, 1); + } + return ui32CurrVal; +} + +//***************************************************************************** +// +//! @brief Get the current stimer value. +//! +//! This function can be used to read, uninvasively, the value in the stimer. +//! +//! @return The 32-bit value from the STimer counter register. +// +//***************************************************************************** +uint32_t +am_hal_stimer_counter_get(void) +{ + uint32_t ui32TmrAddr = AM_REGADDRn(CTIMER, 0, STTMR); + uint32_t ui32Values[3]; + uint32_t ui32RetVal; + + // + // Read the register into ui32Values[]. + // + am_hal_triple_read(ui32TmrAddr, ui32Values); + + // + // Now determine which of the three values is the correct value. + // If the first 2 match, then the values are both correct and we're done. + // Otherwise, the third value is taken to be the correct value. + // + if ( ui32Values[0] == ui32Values[1] ) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32RetVal = ui32Values[1]; + } + else + { + ui32RetVal = ui32Values[2]; + } + return ui32RetVal; +} + +//***************************************************************************** +// +//! @brief Clear the stimer counter. +//! +//! This function clears the STimer Counter and leaves the stimer running. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_counter_clear(void) +{ + // + // Set the clear bit + // + AM_REG(CTIMER, STCFG) |= AM_REG_CTIMER_STCFG_CLEAR_M; + + // + // Reset the clear bit + // + AM_REG(CTIMER, STCFG) &= ~AM_REG_CTIMER_STCFG_CLEAR_M; +} + +//***************************************************************************** +// +//! @brief Set the compare value. +//! +//! @param ui32CmprInstance is the compare register instance number (0-7). +//! @param ui32Delta is the value to add to the STimer counter and load into +//! the comparator register. It should be > 1 +//! +//! NOTE: There is no way to set an absolute value into a comparator register. +//! Only deltas added to the STimer counter can be written to the compare +//! registers. +//! CAUTION: The HAL implementation requires temporarily disabling the +//! comparison. To avoid the remote possibility of losing an interrupt +//! during that time, delta should always be set to a value greater than 1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta) +{ + uint32_t cfgVal; + uint32_t ui32Critical = 0; + if ( ui32CmprInstance > 7 ) + { + return; + } + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + cfgVal = AM_REG(CTIMER, STCFG); + // We need to disable the compare temporarily while setting the delta value + // That leaves a corner case where we could miss the trigger if setting a very + // small delta. To avoid this, we take critical section, and we should ensure + // that delta value is at least > 1 + + // Disable the compare if already enabled, when setting the new value + AM_REG(CTIMER, STCFG) &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance)); + AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; + // Restore Compare Enable bit + AM_REG(CTIMER, STCFG) |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance); + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); +} + +//***************************************************************************** +// +//! @brief Get the current stimer compare register value. +//! +//! @param ui32CmprInstance is the compare register instance number (0-7). +//! +//! This function can be used to read the value in an stimer compare register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_stimer_compare_get(uint32_t ui32CmprInstance) +{ + if ( ui32CmprInstance > 7 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); +} + +//***************************************************************************** +// +//! @brief Start capturing data with the specified capture register. +//! +//! @param ui32CaptureNum is the Capture Register Number to read (0-3). +//! ui32GPIONumber is the pin number. +//! bPolarity: false (0) = Capture on low to high transition. +//! true (1) = Capture on high to low transition. +//! +//! Use this function to start capturing. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_capture_start(uint32_t ui32CaptureNum, + uint32_t ui32GPIONumber, + bool bPolarity) +{ + uint32_t ui32CapCtrl; + + if ( ui32GPIONumber > (AM_HAL_GPIO_MAX_PADS-1) ) + { + return; + } + + // + // Set the polarity and pin selection in the GPIO block. + // + switch (ui32CaptureNum) + { + case 0: + AM_BFW(GPIO, STMRCAP, STPOL0, bPolarity); + AM_BFW(GPIO, STMRCAP, STSEL0, ui32GPIONumber); + ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M; + break; + case 1: + AM_BFW(GPIO, STMRCAP, STPOL1, bPolarity); + AM_BFW(GPIO, STMRCAP, STSEL1, ui32GPIONumber); + ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_M; + break; + case 2: + AM_BFW(GPIO, STMRCAP, STPOL2, bPolarity); + AM_BFW(GPIO, STMRCAP, STSEL2, ui32GPIONumber); + ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_M; + break; + case 3: + AM_BFW(GPIO, STMRCAP, STPOL3, bPolarity); + AM_BFW(GPIO, STMRCAP, STSEL3, ui32GPIONumber); + ui32CapCtrl = AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_M; + break; + default: + return; // error concealment. + } + + // + // Enable it in the CTIMER Block + // + AM_REG(CTIMER, CAPTURE_CONTROL) |= ui32CapCtrl; +} + +//***************************************************************************** +// +//! @brief Start capturing data with the specified capture register. +//! +//! @param ui32CaptureNum is the Capture Register Number to read. +//! +//! Use this function to start capturing. +//! +//! @return None. +// +//***************************************************************************** +void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum) +{ + // + // Disable it in the CTIMER block. + // + AM_REG(CTIMER, CAPTURE_CONTROL) &= + ~(AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M << + ((AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_S - + AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_S) * ui32CaptureNum)); +} + +//***************************************************************************** +// +//! @brief Get the current stimer capture register value. +//! +//! @param ui32CaptureNum is the Capture Register Number to read. +//! +//! This function can be used to read the value in an stimer capture register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum) +{ + if ( ui32CaptureNum > 7 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum)); +} + +//***************************************************************************** +// +//! @brief Enables the selected system timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will enable the selected interrupts in the STIMER interrupt +//! enable register. In order to receive an interrupt from an stimer component, +//! you will need to enable the interrupt for that component in this main +//! register, as well as in the stimer configuration register (accessible though +//! am_hal_stimer_config()), and in the NVIC. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupt at the module level. + // + AM_REGn(CTIMER, 0, STMINTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled stimer interrupts. +//! +//! This function will return all enabled interrupts in the STIMER +//! interrupt enable register. +//! +//! @return return enabled interrupts. This will be a logical or of: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return Return the enabled timer interrupts. +// +//***************************************************************************** +uint32_t +am_hal_stimer_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return AM_REGn(CTIMER, 0, STMINTEN); +} + +//***************************************************************************** +// +//! @brief Disables the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will disable the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + AM_REGn(CTIMER, 0, STMINTEN) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Sets the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will set the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + AM_REGn(CTIMER, 0, STMINTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clears the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will clear the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_clear(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + AM_REGn(CTIMER, 0, STMINTCLR) = ui32Interrupt; +} + + +//***************************************************************************** +// +//! @brief Returns either the enabled or raw stimer interrupt status. +//! +//! This function will return the stimer interrupt status. +//! +//! @bEnabledOnly if true returns the status of the enabled interrupts +//! only. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! +//! @return Returns the stimer interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_stimer_int_status_get(bool bEnabledOnly) +{ + // + // Return the desired status. + // + uint32_t ui32RetVal = AM_REGn(CTIMER, 0, STMINTSTAT); + + if ( bEnabledOnly ) + { + ui32RetVal &= AM_REGn(CTIMER, 0, STMINTEN); + } + + return ui32RetVal; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_stimer.h b/mcu/apollo2/hal/am_hal_stimer.h new file mode 100644 index 0000000..5ab0613 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_stimer.h @@ -0,0 +1,242 @@ +//***************************************************************************** +// +// am_hal_stimer.h +//! @file +//! +//! @brief Functions for accessing and configuring the STIMER. +//! +//! @addtogroup stimer2 Counter/Timer (STIMER) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_STIMER_H +#define AM_HAL_STIMER_H + +// +// Compute address of a given COMPARE or CAPTURE register. +// Note - For Apollo2, the parameter n should be 0 (as only 1 stimer module +// exists) and the parameter r should be 0-7 (compare) or 0-3 (capture). +// +#define AM_REG_STIMER_COMPARE(n, r) (AM_REG_CTIMERn(n) + \ + AM_REG_CTIMER_SCMPR0_O + (r * 4)) + +#define AM_REG_STIMER_CAPTURE(n, r) (AM_REG_CTIMERn(n) + \ + AM_REG_CTIMER_SCAPT0_O + (r * 4)) + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_INT_COMPAREA AM_REG_CTIMER_STMINTSTAT_COMPAREA_M +#define AM_HAL_STIMER_INT_COMPAREB AM_REG_CTIMER_STMINTSTAT_COMPAREB_M +#define AM_HAL_STIMER_INT_COMPAREC AM_REG_CTIMER_STMINTSTAT_COMPAREC_M +#define AM_HAL_STIMER_INT_COMPARED AM_REG_CTIMER_STMINTSTAT_COMPARED_M +#define AM_HAL_STIMER_INT_COMPAREE AM_REG_CTIMER_STMINTSTAT_COMPAREE_M +#define AM_HAL_STIMER_INT_COMPAREF AM_REG_CTIMER_STMINTSTAT_COMPAREF_M +#define AM_HAL_STIMER_INT_COMPAREG AM_REG_CTIMER_STMINTSTAT_COMPAREG_M +#define AM_HAL_STIMER_INT_COMPAREH AM_REG_CTIMER_STMINTSTAT_COMPAREH_M + +#define AM_HAL_STIMER_INT_OVERFLOW AM_REG_CTIMER_STMINTSTAT_OVERFLOW_M + +#define AM_HAL_STIMER_INT_CAPTUREA AM_REG_CTIMER_STMINTSTAT_CAPTUREA_M +#define AM_HAL_STIMER_INT_CAPTUREB AM_REG_CTIMER_STMINTSTAT_CAPTUREB_M +#define AM_HAL_STIMER_INT_CAPTUREC AM_REG_CTIMER_STMINTSTAT_CAPTUREC_M +#define AM_HAL_STIMER_INT_CAPTURED AM_REG_CTIMER_STMINTSTAT_CAPTURED_M + +//! @} + + + +//***************************************************************************** +// +//! @name STimer Configuration Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_CFG_THAW \ + AM_REG_CTIMER_STCFG_FREEZE_THAW +#define AM_HAL_STIMER_CFG_FREEZE \ + AM_REG_CTIMER_STCFG_FREEZE_FREEZE +#define AM_HAL_STIMER_CFG_RUN \ + AM_REG_CTIMER_STCFG_CLEAR_RUN +#define AM_HAL_STIMER_CFG_CLEAR \ + AM_REG_CTIMER_STCFG_CLEAR_CLEAR +#define AM_HAL_STIMER_CFG_COMPARE_A_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_A_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_B_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_B_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_C_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_C_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_D_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_D_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_E_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_E_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_F_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_F_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_G_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_G_EN_ENABLE +#define AM_HAL_STIMER_CFG_COMPARE_H_ENABLE \ + AM_REG_CTIMER_STCFG_COMPARE_H_EN_ENABLE + +//! @} + +//***************************************************************************** +// +//! @name Clock Configuration options +//! @brief STimer Configuration register options. +//! +//! These options are to be used with the am_hal_stimer_config() function. +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_NO_CLK \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_NOCLK) +#define AM_HAL_STIMER_HFRC_3MHZ \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16) +#define AM_HAL_STIMER_HFRC_187_5KHZ \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) +#define AM_HAL_STIMER_XTAL_32KHZ \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV1) +#define AM_HAL_STIMER_XTAL_16KHZ \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV2) +#define AM_HAL_STIMER_XTAL_1KHZ \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV32) +#define AM_HAL_STIMER_LFRC_1KHZ \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_LFRC_DIV1) +#define AM_HAL_STIMER_HFRC_CTIMER0A \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0A) +#define AM_HAL_STIMER_HFRC_CTIMER0B \ + AM_REG_CTIMER_STCFG_CLKSEL(AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0B) +//! @} + + + +//***************************************************************************** +// +//! @name Capture Control Register options. +//! @brief Configuration options for capture control register. +//! +//! These options are to be used with the am_hal_stimer_capture_control_set +//! function. +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_CAPTURE_A_ENABLE \ + AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_ENABLE +#define AM_HAL_STIMER_CAPTURE_B_ENABLE \ + AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_ENABLE +#define AM_HAL_STIMER_CAPTURE_C_ENABLE \ + AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_ENABLE +#define AM_HAL_STIMER_CAPTURE_D_ENABLE \ + AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_ENABLE + +//! @} + + +//***************************************************************************** +// +// +// +//***************************************************************************** + +//***************************************************************************** +// +// Stimer configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Configuration options for the STIMER + // + uint32_t ui32STimerConfig; +} +am_hal_stimer_config_t; + + + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_hal_stimer_config(uint32_t ui32STimerConfig); +extern uint32_t am_hal_stimer_counter_get(void); +extern void am_hal_stimer_counter_clear(void); +extern void am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, + uint32_t ui32Delta); +extern uint32_t am_hal_stimer_compare_get(uint32_t ui32CmprInstance); +extern void am_hal_stimer_capture_start(uint32_t ui32CaptureNum, + uint32_t ui32GPIONumber, + bool bPolarity); +extern void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum); +extern uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum); +extern void am_hal_stimer_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_stimer_int_enable_get(void); +extern void am_hal_stimer_int_disable(uint32_t ui32Interrupt); +extern void am_hal_stimer_int_set(uint32_t ui32Interrupt); +extern void am_hal_stimer_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_stimer_int_status_get(bool bEnabledOnly); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_STIMER_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_sysctrl.c b/mcu/apollo2/hal/am_hal_sysctrl.c new file mode 100644 index 0000000..bc13f30 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_sysctrl.c @@ -0,0 +1,950 @@ +//***************************************************************************** +// +// am_hal_sysctrl.c +//! @file +//! +//! @brief Functions for interfacing with the M4F system control registers +//! +//! @addtogroup sysctrl2 System Control (SYSCTRL) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Local macro constants +// +//***************************************************************************** +// +// Define ZX workaround values. +// These values are defined by the factory. +// +#define COREZXVALUE 0x07 +#define MEMZXVALUE 0x07 + +// +// Define values for g_ui32CoreBuck, which indicates which timer carries +// the signal for the CORE Buck, and which also implies that the other timer +// carries the signal for the MEM buck. +// +#define COREBUCK_TIMERA 1 // Core buck signal comes in on timer A +#define COREBUCK_TIMERB 2 // Core buck signal comes in on timer B + +// +// Define the bit values for static function g_buckZX_chk; +// +#define CHKBUCKZX_BUCKS 0x01 // The bucks are enabled +#define CHKBUCKZX_REV 0x02 // This chip rev needs the workaround +#define CHKBUCKZX_TIMER 0x04 // A valid timer has been allocated +#define CHKBUCKZX_DEVEN 0x08 // Devices are powered up and enabled + +#define TIMER_OFFSET (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O) + +//***************************************************************************** +// +// Prototypes +// +//***************************************************************************** +static void am_hal_sysctrl_buckA_ctimer_isr(void); +static void am_hal_sysctrl_buckB_ctimer_isr(void); + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +static volatile uint32_t g_ui32BuckTimer = 0; +static volatile uint32_t g_ui32BuckInputs = 0; +static volatile bool g_bBuckRestoreComplete = false; +static volatile bool g_bBuckTimed = false; +static uint32_t g_ui32SaveCoreBuckZX, g_ui32SaveMemBuckZX; +static uint32_t g_buckZX_chk = 0; +static volatile uint32_t g_ui32CoreBuck; + +//***************************************************************************** +// +// Determine if we need to do the zero cross workaround on this device. +// Four criteria are used. All four must be true. +// 1. Are the bucks enabled? +// 2. Is the chip rev appropriate for the workaround? +// 3. Has a timer been allocated to do the workaround? +// 4. Are certain peripherals powered up? +// +// Saves the bitmask to the global g_buckZX_chk. +// Bitmask bits are defined as: CHKBUCKZX_BUCKS, CHKBUCKZX_REV, CHKBUCKZX_TIMER. +// +// Returns true if all criteria are met, false otherwise. +// g_buckZX_chk can be probed to determine which criteria passed or failed. +// +//***************************************************************************** +static bool +buckZX_chk(void) +{ + uint32_t ui32SupplySrc; + + // + // Is this chip rev appropriate to do the workaround? + // + g_buckZX_chk = AM_BFM(MCUCTRL, CHIPREV, REVMAJ) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ? + CHKBUCKZX_REV : 0x0; + + // + // Has a timer been configured to handle the workaround? + // + g_buckZX_chk |= ( g_ui32BuckTimer - 1 ) <= BUCK_TIMER_MAX ? + CHKBUCKZX_TIMER : 0x0; + + // + // Are either or both of the bucks actually enabled? + // + ui32SupplySrc = AM_REG(PWRCTRL, SUPPLYSRC); + + g_buckZX_chk |= (ui32SupplySrc & + (AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M | + AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M) ) ? + CHKBUCKZX_BUCKS : 0x0; + + // + // Finally, if any peripheral (other than ADC-only) is already powered up, + // we don't need to do the ZX workaround because in this case the bucks + // remain in active mode. + // If ONLY the ADC is powered up (and no other peripherals), a case occurs + // which is complex to handle. However it can also be completely handled + // via the ZX workaround, so that case is also checked at this point. + // For more information on both issues see erratum ERR010 and ERR019. + // + ui32SupplySrc = AM_REG(PWRCTRL, DEVICEEN); + + g_buckZX_chk |= ( ui32SupplySrc & + (AM_REG_PWRCTRL_DEVICEEN_PWRPDM_M | + AM_REG_PWRCTRL_DEVICEEN_PWRUART1_M | + AM_REG_PWRCTRL_DEVICEEN_PWRUART0_M | + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M | + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M | + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M | + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M | + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M | + AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M | + AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M) ) ? + 0x0 : CHKBUCKZX_DEVEN; + + // + // If all 4 criteria were met, we're good to do the workaround. + // + return ( g_buckZX_chk == + (CHKBUCKZX_BUCKS | CHKBUCKZX_REV | + CHKBUCKZX_TIMER | CHKBUCKZX_DEVEN) ) ? true : false; +} + +//***************************************************************************** +// +// Set the buck zero cross settings to the values given. +// +// ui32Flags, one or more of the following: +// SETBUCKZX_USE_PROVIDED_SETTINGS - Use the values provided in the parameters +// to set the trim value(s). +// SETBUCKZX_USE_SAVED_SETTINGS - Use the values that were previously saved +// to set the trim value(s). +// SETBUCKZX_SAVE_CURR_SETTINGS - Save the current trim values before +// setting the new ones. +// SETBUCKZX_RESTORE_CORE_ONLY - Restore the Core trim and save the current +// value of the core buck trim iff +// SETBUCKZX_SAVE_CURR_SETTINGS is set. +// SETBUCKZX_RESTORE_MEM_ONLY - Restore the Mem trim and save the current +// value of the mem buck trim iff +// SETBUCKZX_SAVE_CURR_SETTINGS is set. +// SETBUCKZX_RESTORE_BOTH - Restore both buck trims and save the +// current value of both iff +// SETBUCKZX_SAVE_CURR_SETTINGS is set. +// +//***************************************************************************** +#define SETBUCKZX_USE_PROVIDED_SETTINGS 0x01 +#define SETBUCKZX_USE_SAVED_SETTINGS 0x02 +#define SETBUCKZX_SAVE_CURR_SETTINGS 0x04 +#define SETBUCKZX_RESTORE_CORE_ONLY 0x10 +#define SETBUCKZX_RESTORE_MEM_ONLY 0x20 +#define SETBUCKZX_RESTORE_BOTH ( SETBUCKZX_RESTORE_CORE_ONLY | \ + SETBUCKZX_RESTORE_MEM_ONLY ) +static void +setBuckZX(uint32_t ui32CoreBuckZX, uint32_t ui32MemBuckZX, uint32_t ui32Flags) +{ + uint32_t ui32SaveCore, ui32SaveMem, ui32NewCore, ui32NewMem; + bool bDoRestore = false; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Get the current zero cross trim values. + // + ui32SaveCore = AM_BFR(MCUCTRL, BUCK3, COREBUCKZXTRIM); + ui32SaveMem = AM_BFR(MCUCTRL, BUCK3, MEMBUCKZXTRIM); + + // + // Determine which values will be restored. + // + if ( ui32Flags & SETBUCKZX_USE_SAVED_SETTINGS ) + { + // + // Use saved settings + // + ui32NewCore = g_ui32SaveCoreBuckZX; + ui32NewMem = g_ui32SaveMemBuckZX; + bDoRestore = true; + } + else if ( ui32Flags & SETBUCKZX_USE_PROVIDED_SETTINGS ) + { + // + // Use settings provided in the call parameters + // + ui32NewCore = ui32CoreBuckZX; + ui32NewMem = ui32MemBuckZX; + bDoRestore = true; + } + + // + // Restore the buck Core and Mem trim registers. + // + if ( bDoRestore ) + { + if ( ui32Flags & SETBUCKZX_RESTORE_CORE_ONLY ) + { + AM_BFW(MCUCTRL, BUCK3, COREBUCKZXTRIM, ui32NewCore); + } + + if ( ui32Flags & SETBUCKZX_RESTORE_MEM_ONLY ) + { + AM_BFW(MCUCTRL, BUCK3, MEMBUCKZXTRIM, ui32NewMem); + } + } + + if ( ui32Flags & SETBUCKZX_SAVE_CURR_SETTINGS ) + { + // + // Save off the zero cross values as read on entry to the function. + // + if ( ui32Flags & SETBUCKZX_RESTORE_CORE_ONLY ) + { + g_ui32SaveCoreBuckZX = ui32SaveCore; + } + + if ( ui32Flags & SETBUCKZX_RESTORE_MEM_ONLY ) + { + g_ui32SaveMemBuckZX = ui32SaveMem; + } + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // setBuckZX() + +//***************************************************************************** +// +//! @brief Place the core into sleep or deepsleep. +//! +//! @param bSleepDeep - False for Normal or True Deep sleep. +//! +//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep. +//! +//! Valid values for bSleepDeep are: +//! +//! AM_HAL_SYSCTRL_SLEEP_NORMAL +//! AM_HAL_SYSCTRL_SLEEP_DEEP +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_sleep(bool bSleepDeep) +{ + uint32_t ui32Critical; + bool bBuckZX_chk; + volatile uint32_t ui32BuckTimer; + + // + // Disable interrupts and save the previous interrupt state. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // If the user selected DEEPSLEEP and the TPIU is off, attempt to enter + // DEEP SLEEP. + // + if ((bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) && + (AM_BFM(MCUCTRL, TPIUCTRL, ENABLE) == AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS)) + { + // + // Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit). + // + AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 1); + + // + // Check if special buck handling is needed + // + bBuckZX_chk = buckZX_chk(); + + if ( bBuckZX_chk ) + { + ui32BuckTimer = g_ui32BuckTimer - 1; + + am_hal_ctimer_int_disable((AM_HAL_CTIMER_INT_TIMERA0C0 | + AM_HAL_CTIMER_INT_TIMERB0C0 ) << + (ui32BuckTimer * 2)); + + // + // Before going to sleep, clear the buck timers. + // This will also handle the case where we're going back to + // sleep before the buck sequence has even completed. + // + am_hal_ctimer_clear(ui32BuckTimer, AM_HAL_CTIMER_BOTH); + + // + // Enable the interrupts for timers A and B + // + am_hal_ctimer_int_enable( (AM_HAL_CTIMER_INT_TIMERA0C0 | + AM_HAL_CTIMER_INT_TIMERB0C0 ) << + (ui32BuckTimer * 2) ); + + // + // Disable bucks before going to sleep. + // + am_hal_pwrctrl_bucks_disable(); + } + + // + // Before executing WFI, flush any buffered core and peripheral writes. + // + AM_ASM_DSB + + // + // Execute the sleep instruction. + // + AM_ASM_WFI; + + // + // Upon wake, execute the Instruction Sync Barrier instruction. + // + AM_ASM_ISB + + // + // Return from sleep + // + if ( bBuckZX_chk ) + { + // + // Adjust the core and mem trims + // + setBuckZX(COREZXVALUE, MEMZXVALUE, + SETBUCKZX_USE_PROVIDED_SETTINGS | + SETBUCKZX_RESTORE_BOTH ); + + // + // Delay for 2us before enabling bucks. + // + am_hal_flash_delay( FLASH_CYCLES_US(2) ); + + // + // Turn on the bucks + // + am_hal_pwrctrl_bucks_enable(); + + // + // Get the actual timer number + // + ui32BuckTimer = g_ui32BuckTimer - 1; + + // + // Initialize the complete flag + // + g_bBuckRestoreComplete = false; + + // + // Initialize the input flags + // + g_ui32BuckInputs = 0; + + // + // Delay for 5us to make sure we're receiving clean buck signals. + // + am_hal_flash_delay( FLASH_CYCLES_US(5) ); + + // + // Start timers (set the enable bit, clear the clear bit) + // + am_hal_ctimer_start(ui32BuckTimer, AM_HAL_CTIMER_BOTH); + } + else + { + // + // Since we're not doing anything, we're done, so set the done flag. + // + g_bBuckRestoreComplete = true; + } + } + else + { + // + // Prepare the core for normal sleep (write 0 to the DEEPSLEEP bit). + // + AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 0); + + // + // Before executing WFI, flush any buffered core and peripheral writes. + // + AM_ASM_DSB + + // + // Go to sleep. + // + AM_ASM_WFI; + + // + // Upon wake, execute the Instruction Sync Barrier instruction. + // + AM_ASM_ISB + } + + // + // Restore the interrupt state. + // + am_hal_interrupt_master_set(ui32Critical); + +} // am_hal_sysctrl_sleep() + +//***************************************************************************** +// +//! @brief Enable the floating point module. +//! +//! Call this function to enable the ARM hardware floating point module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_enable(void) +{ + // + // Enable access to the FPU in both privileged and user modes. + // NOTE: Write 0s to all reserved fields in this register. + // + AM_REG(SYSCTRL, CPACR) = (AM_REG_SYSCTRL_CPACR_CP11(0x3) | + AM_REG_SYSCTRL_CPACR_CP10(0x3)); + +} // am_hal_sysctrl_fpu_enable() + +//***************************************************************************** +// +//! @brief Disable the floating point module. +//! +//! Call this function to disable the ARM hardware floating point module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_disable(void) +{ + // + // Disable access to the FPU in both privileged and user modes. + // NOTE: Write 0s to all reserved fields in this register. + // + AM_REG(SYSCTRL, CPACR) = 0x00000000 & + ~(AM_REG_SYSCTRL_CPACR_CP11(0x3) | + AM_REG_SYSCTRL_CPACR_CP10(0x3)); +} // am_hal_sysctrl_fpu_disable() + +//***************************************************************************** +// +//! @brief Enable stacking of FPU registers on exception entry. +//! +//! @param bLazy - Set to "true" to enable "lazy stacking". +//! +//! This function allows the core to save floating-point information to the +//! stack on exception entry. Setting the bLazy option enables "lazy stacking" +//! for interrupt handlers. Normally, mixing floating-point code and interrupt +//! driven routines causes increased interrupt latency, because the core must +//! save extra information to the stack upon exception entry. With the lazy +//! stacking option enabled, the core will skip the saving of floating-point +//! registers when possible, reducing average interrupt latency. +//! +//! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1, +//! enabling Lazy mode by default. Therefore this function will generally +//! only have an affect when setting for full-context save (or when switching +//! from full-context to lazy mode). +//! +//! @note See also: +//! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html +//! +//! @note Three valid FPU context saving modes are possible. +//! 1. Lazy ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true) +//! and default. +//! 2. Full-context ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false) +//! 3. No FPU state ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable() +//! 4. Invalid ASPEN=0 LSPEN=1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_stacking_enable(bool bLazy) +{ +#define SYSCTRL_FPCCR_LAZY (AM_REG_SYSCTRL_FPCCR_ASPEN_M | AM_REG_SYSCTRL_FPCCR_LSPEN_M) + + uint32_t ui32fpccr; + + // + // Set the requested FPU stacking mode in ISRs. + // + AM_CRITICAL_BEGIN + ui32fpccr = AM_REG(SYSCTRL, FPCCR); + ui32fpccr &= ~(SYSCTRL_FPCCR_LAZY); + ui32fpccr |= (bLazy ? SYSCTRL_FPCCR_LAZY : AM_REG_SYSCTRL_FPCCR_ASPEN_M); + AM_REG(SYSCTRL, FPCCR) = ui32fpccr; + AM_CRITICAL_END + +} // am_hal_sysctrl_fpu_stacking_enable() + +//***************************************************************************** +// +//! @brief Disable FPU register stacking on exception entry. +//! +//! This function disables all stacking of floating point registers for +//! interrupt handlers. This mode should only be used when it is absolutely +//! known that no FPU instructions will be executed in an ISR. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_stacking_disable(void) +{ + // + // Completely disable FPU context save on entry to ISRs. + // + AM_CRITICAL_BEGIN + AM_REG(SYSCTRL, FPCCR) &= ~SYSCTRL_FPCCR_LAZY; + AM_CRITICAL_END + +} // am_hal_sysctrl_fpu_stacking_disable() + +//***************************************************************************** +// +//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl. +//! +//! This function issues a system wide reset (Apollo POR level reset). +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_aircr_reset(void) +{ + // + // Set the system reset bit in the AIRCR register + // + AM_REG(SYSCTRL, AIRCR) = AM_REG_SYSCTRL_AIRCR_VECTKEY(0x5FA) | + AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(1); + +} // am_hal_sysctrl_aircr_reset() + +//***************************************************************************** +// +//! @brief Buck CTimer ISR initializer. +//! +//! @param ui32BuckTimerNumber - Timer number to be used for handling the buck. +//! Must be 0-3. +//! +//! If called with an invalid timer (that is, not 0 - 3, or greater than +//! BUCK_TIMER_MAX), then the workaround will not be enabled. +//! +//! Instead, the bucks will be initialized with a value that will avoid the +//! issues described in the Errata (ERR019). However, this will cause a +//! less efficient energy usage condtion. +//! +//! @return 0. +// +//***************************************************************************** +uint32_t +am_hal_sysctrl_buck_ctimer_isr_init(uint32_t ui32BuckTimerNumber) +{ + uint32_t ui32RetVal = 0; + + // + // Initialize the input flags + // + g_ui32BuckInputs = 0; + + // + // Initialize operation complete flag + // + g_bBuckRestoreComplete = false; + + // + // Initialize to assume there is no valid timer. + // + g_ui32BuckTimer = 0; + + if ( ui32BuckTimerNumber > BUCK_TIMER_MAX ) + { + if ( ( ui32BuckTimerNumber & 0xFFFF0000 ) == + AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT ) + { + // + // The caller is asking for the hard option, which changes the + // settings to the more noise-immune, if less efficient, settings. + // While we're at it, go ahead and save off the current settings. + // + if ( (ui32BuckTimerNumber & 0x0000FFFF) == 0 ) + { + setBuckZX(COREZXVALUE, MEMZXVALUE, + SETBUCKZX_USE_PROVIDED_SETTINGS | + SETBUCKZX_SAVE_CURR_SETTINGS | + SETBUCKZX_RESTORE_BOTH ); + } + else + { + uint32_t ui32Core, ui32Mem; + + // + // Use the setting provided in the parameter. + // + ui32Core = (((ui32BuckTimerNumber & 0x001F) >> 0) - 1) & 0xF; + ui32Mem = (((ui32BuckTimerNumber & 0x1F00) >> 8) - 1) & 0xF; + + setBuckZX(ui32Core, ui32Mem, + SETBUCKZX_USE_PROVIDED_SETTINGS | + SETBUCKZX_SAVE_CURR_SETTINGS | + SETBUCKZX_RESTORE_BOTH ); + } + } + } + else + { + // + // Save off the current trim settings (but don't change any settings). + // + setBuckZX(0, 0, SETBUCKZX_SAVE_CURR_SETTINGS | SETBUCKZX_RESTORE_BOTH); + + // + // The timer number will be maintained as (n + 1). Therefore, a value + // of 0 saved in the global is an invalid timer. 1=timer0, 2=timer1... + // + g_ui32BuckTimer = ui32BuckTimerNumber + 1; + + // + // Register the timer ISRs + // + am_hal_ctimer_int_register( AM_HAL_CTIMER_INT_TIMERA0C0 << + (ui32BuckTimerNumber * 2), + am_hal_sysctrl_buckA_ctimer_isr ); + + am_hal_ctimer_int_register( AM_HAL_CTIMER_INT_TIMERB0C0 << + (ui32BuckTimerNumber * 2), + am_hal_sysctrl_buckB_ctimer_isr ); + + // + // Determine which timer input (A or B) is core buck and which is mem + // buck based on the timer number. + // For CTIMER 0 & 1: Timer A is mem buck, Timer B is core buck + // For CTIMER 2 & 3: Timer A is core buck, Timer B is mem buck + // + if ( (ui32BuckTimerNumber == 0) || (ui32BuckTimerNumber == 1) ) + { + // + // Indicate that TimerB is core buck. + // + g_ui32CoreBuck = COREBUCK_TIMERB; + } + else + { + // + // Indicate that TimerA is core buck + // + g_ui32CoreBuck = COREBUCK_TIMERA; + } + + // + // Clear and configure the timers + // + am_hal_ctimer_clear(ui32BuckTimerNumber, AM_HAL_CTIMER_BOTH); + + // + // Find the correct register to write based on the timer number. + // + volatile uint32_t *pui32CmprReg, *pui32ConfigReg; + pui32CmprReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CMPRA0_O + + (ui32BuckTimerNumber * TIMER_OFFSET)); + pui32ConfigReg = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CTRL0_O + + (ui32BuckTimerNumber * TIMER_OFFSET)); + // + // Configure the timer. + // + AM_REGVAL(pui32ConfigReg) = + AM_REG_CTIMER_CTRL0_TMRB0IE0(1) | // Interrupt on CMPR0 only + AM_REG_CTIMER_CTRL0_TMRB0FN(4) | // Func 4=Continuous + AM_REG_CTIMER_CTRL0_TMRB0CLK(0x10) | // Clock=BUCKB + AM_REG_CTIMER_CTRL0_TMRA0IE0(1) | // Interrupt on CMPR0 only + AM_REG_CTIMER_CTRL0_TMRA0FN(4) | // Func 4=Continuous + AM_REG_CTIMER_CTRL0_TMRA0CLK(0x10); // Clock=BUCKA + + #define TIMER_BUCK_PULSES 10 + + AM_REGVAL(pui32CmprReg) = (0 << 16) | TIMER_BUCK_PULSES; // Timer A CMPR0 + pui32CmprReg++; + AM_REGVAL(pui32CmprReg) = (0 << 16) | TIMER_BUCK_PULSES; // Timer B CMPR0 + + // + // Enable the timer interrupt in the NVIC. + // + am_hal_interrupt_enable(AM_HAL_INTERRUPT_CTIMER); + } + + return ui32RetVal; + +} // am_hal_sysctrl_buck_ctimer_isr_init() + +//***************************************************************************** +// +// Get buck update complete status. +// +//***************************************************************************** +bool +am_hal_sysctrl_buck_update_complete(void) +{ + return g_bBuckRestoreComplete; +} // am_hal_sysctrl_buck_update_complete() + + +//***************************************************************************** +// +// Perform a short delay. +// +//***************************************************************************** +static void +short_delay(volatile register uint32_t ui32iters) +{ + // + // Note: for a 1us delay, we need 48 cycles at 48MHz. + // When optimized, we would expect this function to be inlined by + // the compiler and the loop itself to end up with about 6 instructions. + // Therefore iters should be about 8 for 1us. + // 6=0.52us, 10=0.76us, 13=0.9us, 15=1us, 20=1.36us + // + while ( ui32iters-- ); +} // short_delay() + +//***************************************************************************** +// +// Buck CTIMER ISR (for handling buck switching via TimerA). +// +// Note: This handler assumes that the interrupt is cleared in am_ctimer_isr(). +// +//***************************************************************************** +static void +am_hal_sysctrl_buckA_ctimer_isr(void) +{ + uint32_t ui32CTaddr, ui32InitVal; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable Timer A interrupts + // + am_hal_ctimer_int_disable( AM_HAL_CTIMER_INT_TIMERA0C0 << + ((g_ui32BuckTimer - 1) * 2)); + + // + // Determine which buck (core or mem) needs to be updated. + // + if ( g_ui32CoreBuck == COREBUCK_TIMERA ) + { + // + // Timer A buck signal is the CORE buck. + // For the core buck, timing is critical as we cannot change the trims + // during a buck event. + // In order to assure optimal timing while the trims are changed, the + // beginning of the next pulse must be determined by polling. + // + ui32CTaddr = AM_REGADDRn(CTIMER, (g_ui32BuckTimer - 1), TMR0); + ui32InitVal = AM_REGVAL(ui32CTaddr) & AM_HAL_CTIMER_TIMERA; + + // + // We can safely assume that we're nowhere near a rollover since the + // interrupt that got us here was based on a single digit TMR value. + // Wait for the next buck pulse. + // + while ( (AM_REGVAL(ui32CTaddr) & AM_HAL_CTIMER_TIMERA) <= ui32InitVal ) {}; + + // + // The following delay ensures that we're far enough away from the + // pulse to avoid any problems. It must be inside the critical section. + // + short_delay(10); // 10 = about 750ns delay + + // + // Restore the core buck. + // + setBuckZX(0, 0, SETBUCKZX_RESTORE_CORE_ONLY | + SETBUCKZX_USE_SAVED_SETTINGS ); + } + else + { + // + // Timer A buck signal is the MEM buck. + // Restore the mem buck. + // + setBuckZX(0, 0, SETBUCKZX_RESTORE_MEM_ONLY | + SETBUCKZX_USE_SAVED_SETTINGS ); + } + + g_ui32BuckInputs |= 0x1; + + if ( g_ui32BuckInputs == 0x3 ) + { + g_bBuckRestoreComplete = true; + g_ui32BuckInputs = 0; + } + + // + // End critical section. + // + AM_CRITICAL_END + +} // am_hal_sysctrl_buckA_ctimer_isr + +//***************************************************************************** +// +// Buck CTIMER ISR (for handling buck switching via TimerB). +// +// Note: This handler assumes that the interrupt is cleared in am_ctimer_isr(). +// +//***************************************************************************** +static void +am_hal_sysctrl_buckB_ctimer_isr(void) +{ + uint32_t ui32CTaddr, ui32InitVal; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable Timer B interrupts + // + am_hal_ctimer_int_disable( AM_HAL_CTIMER_INT_TIMERB0C0 << + ((g_ui32BuckTimer - 1) * 2)); + + // + // Determine which buck (core or mem) needs to be updated. + // + if ( g_ui32CoreBuck == COREBUCK_TIMERB ) + { + // + // Timer B buck signal is the CORE buck. + // For the core buck, timing is critical as we cannot change the trims + // during a buck event. + // In order to assure optimal timing while the trims are changed, the + // beginning of the next pulse must be determined by polling. + // + ui32CTaddr = AM_REGADDRn(CTIMER, (g_ui32BuckTimer - 1), TMR0); + ui32InitVal = AM_REGVAL(ui32CTaddr) & AM_HAL_CTIMER_TIMERB; + + // + // We can safely assume that we're nowhere near a rollover since the + // interrupt that got us here was based on a single digit TMR value. + // Wait for the next buck pulse. + // + while ( (AM_REGVAL(ui32CTaddr) & AM_HAL_CTIMER_TIMERB) <= ui32InitVal ) {}; + + // + // The following delay ensures that we're far enough away from the + // pulse to avoid any problems. It must be inside the critical section. + // + short_delay(10); // 10 = about 750ns delay + + // + // Restore the core buck. + // + setBuckZX(0, 0, SETBUCKZX_RESTORE_CORE_ONLY | + SETBUCKZX_USE_SAVED_SETTINGS ); + } + else + { + // + // Timer B buck signal is the MEM buck. + // Restore the mem buck. + // + setBuckZX(0, 0, SETBUCKZX_RESTORE_MEM_ONLY | + SETBUCKZX_USE_SAVED_SETTINGS ); + } + + g_ui32BuckInputs |= 0x2; + + if ( g_ui32BuckInputs == 0x3 ) + { + g_bBuckRestoreComplete = true; + g_ui32BuckInputs = 0; + } + + // + // End critical section. + // + AM_CRITICAL_END + +} // am_hal_sysctrl_buckB_ctimer_isr + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_sysctrl.h b/mcu/apollo2/hal/am_hal_sysctrl.h new file mode 100644 index 0000000..1346afb --- /dev/null +++ b/mcu/apollo2/hal/am_hal_sysctrl.h @@ -0,0 +1,119 @@ +//***************************************************************************** +// +//! am_hal_sysctrl.h +//! @file +//! +//! @brief Functions for interfacing with the M4F system control registers +//! +//! @addtogroup sysctrl2 System Control (SYSCTRL) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_SYSCTRL_H +#define AM_HAL_SYSCTRL_H + + +//***************************************************************************** +// +// Definitions for sleep mode parameter +// +//***************************************************************************** +#define AM_HAL_SYSCTRL_SLEEP_DEEP true +#define AM_HAL_SYSCTRL_SLEEP_NORMAL false + +//***************************************************************************** +// +// Parameters for am_hal_sysctrl_buck_ctimer_isr_init() +// +//***************************************************************************** +// +// Define the maximum valid timer number +// +#define BUCK_TIMER_MAX (AM_HAL_CTIMER_TIMERS_NUM - 1) + +// +// Define the valid timer numbers +// +#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER0 0 +#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER1 1 +#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER2 2 +#define AM_HAL_SYSCTRL_BUCK_CTIMER_TIMER3 3 + +// +// The following is an invalid timer number. If used, it is the caller telling +// the HAL to use the "Hard Option", which applies a constant value to the zero +// cross. The applied value is more noise immune, if less energy efficent. +// +#define AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT 0x01000000 // No timer, apply a constant value + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_sysctrl_sleep(bool bSleepDeep); +extern void am_hal_sysctrl_fpu_enable(void); +extern void am_hal_sysctrl_fpu_disable(void); +extern void am_hal_sysctrl_fpu_stacking_enable(bool bLazy); +extern void am_hal_sysctrl_fpu_stacking_disable(void); +extern void am_hal_sysctrl_aircr_reset(void); + +// +// Apollo2 zero-cross buck/ctimer related functions +// +extern uint32_t am_hal_sysctrl_buck_ctimer_isr_init(uint32_t ui32BuckTimerNumber); +extern bool am_hal_sysctrl_buck_update_complete(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SYSCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/mcu/apollo2/hal/am_hal_systick.c b/mcu/apollo2/hal/am_hal_systick.c new file mode 100644 index 0000000..e86986a --- /dev/null +++ b/mcu/apollo2/hal/am_hal_systick.c @@ -0,0 +1,346 @@ +//***************************************************************************** +// +// am_hal_systick.c +//! @file +//! +//! @brief Functions for interfacing with the SYSTICK +//! +//! @addtogroup systick2 System Timer (SYSTICK) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** +#define SYSTICK_MAX_TICKS ((1 << 24)-1) +#define MAX_U32 (0xffffffff) + +//***************************************************************************** +// +//! @brief Start the SYSTICK. +//! +//! This function starts the systick timer. +//! +//! @note This timer does not run in deep-sleep mode as it runs from the core +//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use +//! one of the ctimers instead. Also to note is this timer will consume higher +//! power than the ctimers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_start(void) +{ + // + // Start the systick timer. + // + AM_REG(SYSTICK, SYSTCSR) |= AM_REG_SYSTICK_SYSTCSR_ENABLE_M; +} + +//***************************************************************************** +// +//! @brief Stop the SYSTICK. +//! +//! This function stops the systick timer. +//! +//! @note This timer does not run in deep-sleep mode as it runs from the core +//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use +//! one of the ctimers instead. Also to note is this timer will consume higher +//! power than the ctimers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_stop(void) +{ + // + // Stop the systick timer. + // + AM_REG(SYSTICK, SYSTCSR) &= ~AM_REG_SYSTICK_SYSTCSR_ENABLE_M; +} + +//***************************************************************************** +// +//! @brief Enable the interrupt in the SYSTICK. +//! +//! This function enables the interupt in the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_int_enable(void) +{ + // + // Enable the systick timer interrupt. + // + AM_REG(SYSTICK, SYSTCSR) |= AM_REG_SYSTICK_SYSTCSR_TICKINT_M; +} + +//***************************************************************************** +// +//! @brief Disable the interrupt in the SYSTICK. +//! +//! This function disables the interupt in the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_int_disable(void) +{ + // + // Disable the systick timer interrupt. + // + AM_REG(SYSTICK, SYSTCSR) &= ~AM_REG_SYSTICK_SYSTCSR_TICKINT_M; +} + +//***************************************************************************** +// +//! @brief Reads the interrupt status. +//! +//! This function reads the interrupt status in the systick timer. +//! +//! @return the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_systick_int_status_get(void) +{ + // + // Return the systick timer interrupt status. + // + return AM_REG(SYSTICK, SYSTCSR) & AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M; +} + +//***************************************************************************** +// +//! @brief Reset the interrupt in the SYSTICK. +//! +//! This function resets the systick timer by clearing out the configuration +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_reset(void) +{ + // + // Reset the systick timer interrupt. + // + AM_REG(SYSTICK, SYSTCSR) = 0x0; +} + +//***************************************************************************** +// +//! @brief Load the value into the SYSTICK. +//! +//! @param ui32LoadVal the desired load value for the systick. Maximum value is +//! 0x00FF.FFFF. +//! +//! This function loads the desired value into the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_load(uint32_t ui32LoadVal) +{ + // + // The proper SysTick initialization sequence is: (p 4-36 of the M4 UG). + // 1. Program reload value + // 2. Clear current value + // 3. Program CSR + // Write the given value to the reload register. + // Write the Current Value Register to clear it to 0. + // + AM_REG(SYSTICK, SYSTRVR) = ui32LoadVal; + AM_REG(SYSTICK, SYSTCVR) = 0; +} + +//***************************************************************************** +// +//! @brief Get the current count value in the SYSTICK. +//! +//! This function gets the current count value in the systick timer. +//! +//! @return Current count value. +// +//***************************************************************************** +uint32_t +am_hal_systick_count(void) +{ + // + // Return the current systick timer count value. + // + return AM_REG(SYSTICK, SYSTCVR); +} + +//***************************************************************************** +// +//! @brief Wait the specified number of ticks. +//! +//! This function delays for the given number of SysTick ticks. +//! +//! @note If the SysTick timer is being used elsewhere, it will be corrupted +//! by calling this function. +//! +//! @return 0 if successful. +// +//***************************************************************************** +uint32_t +am_hal_systick_wait_ticks(uint32_t ui32Ticks) +{ + + if ( ui32Ticks == 0 ) + { + ui32Ticks++; // Make sure we get the COUNTFLAG + } + + // + // The proper SysTick initialization sequence is: (p 4-36 of the M4 UG). + // 1. Program reload value + // 2. Clear current value + // 3. Program CSR + // + // Set the reload value to the required number of ticks. + // + AM_REG(SYSTICK, SYSTRVR) = ui32Ticks; + + // + // Clear the current count. + // + AM_REG(SYSTICK, SYSTCVR) = 0x0; + + // + // Set to use the processor clock, but don't cause an exception (we'll poll). + // + AM_REG(SYSTICK, SYSTCSR) = AM_REG_SYSTICK_SYSTCSR_ENABLE_M; + + // + // Poll till done + // + while ( !(AM_REG(SYSTICK, SYSTCSR) & AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M) ); + + // + // And disable systick before exiting. + // + AM_REG(SYSTICK, SYSTCSR) = 0; + + return 0; +} + +//***************************************************************************** +// +//! @brief Delay the specified number of microseconds. +//! +//! This function will use the SysTick timer to delay until the specified +//! number of microseconds have elapsed. It uses the processor clocks and +//! takes into account the current CORESEL setting. +//! +//! @note If the SysTick timer is being used elsewhere, it will be corrupted +//! by calling this function. +//! +//! @return Total number of SysTick ticks delayed. +// +//***************************************************************************** +uint32_t +am_hal_systick_delay_us(uint32_t ui32NumUs) +{ + uint32_t ui32nLoops, ui32Ticks, uRet; + uint32_t ui32ClkFreq, ui32TicksPerMHz; + uint32_t ui32CoreSel = AM_BFR(CLKGEN, CCTRL, CORESEL); + + ui32nLoops = 0; + if ( (ui32CoreSel <= AM_HAL_CLKGEN_CORESEL_MAXDIV) && (ui32NumUs >= 2) ) + { + // + // Determine clock freq, then whether we need more than 1 iteration. + // + ui32ClkFreq = AM_HAL_CLKGEN_FREQ_MAX_MHZ >> ui32CoreSel; + + ui32TicksPerMHz = SYSTICK_MAX_TICKS / ui32ClkFreq; + if ( ui32NumUs > ui32TicksPerMHz ) + { + // + // Get number of required loops, as well as additional ticks. + // + ui32nLoops = ui32NumUs / ui32TicksPerMHz; + ui32NumUs = ui32NumUs % ui32TicksPerMHz; + } + + // + // Compute the number of ticks required. + // Allow for about 2us of call overhead. + // + ui32Ticks = (ui32NumUs - 2) * ui32ClkFreq; + } + else + { + ui32Ticks = 1; + } + + uRet = (ui32nLoops * SYSTICK_MAX_TICKS) + ui32Ticks; + while ( ui32nLoops ) + { + am_hal_systick_wait_ticks(SYSTICK_MAX_TICKS); + ui32nLoops--; + } + am_hal_systick_wait_ticks(ui32Ticks); + + return uRet; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_systick.h b/mcu/apollo2/hal/am_hal_systick.h new file mode 100644 index 0000000..eebed78 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_systick.h @@ -0,0 +1,83 @@ +//***************************************************************************** +// +// am_hal_systick.h +//! @file +//! +//! @brief Functions for accessing and configuring the SYSTICK. +//! +//! @addtogroup systick2 System Timer (SYSTICK) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_SYSTICK_H +#define AM_HAL_SYSTICK_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_systick_start(void); +extern void am_hal_systick_stop(void); +extern void am_hal_systick_int_enable(void); +extern void am_hal_systick_int_disable(void); +extern uint32_t am_hal_systick_int_status_get(void); +extern void am_hal_systick_reset(void); +extern void am_hal_systick_load(uint32_t ui32LoadVal); +extern uint32_t am_hal_systick_count(void); +extern uint32_t am_hal_systick_wait_ticks(uint32_t u32Ticks); +extern uint32_t am_hal_systick_delay_us(uint32_t u32NumUs); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SYSTICK_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_tpiu.c b/mcu/apollo2/hal/am_hal_tpiu.c new file mode 100644 index 0000000..2fc8774 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_tpiu.c @@ -0,0 +1,387 @@ +//***************************************************************************** +// +// am_hal_tpiu.c +//! @file +//! +//! @brief Support functions for the ARM TPIU module +//! +//! Provides support functions for configuring the ARM TPIU module +//! +//! @addtogroup tpiu2 Trace Port Interface Unit (TPIU) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Enable the clock to the TPIU module. +//! +//! This function enables the clock to the TPIU module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_clock_enable(void) +{ + // + // Enable the TPIU clock + // + AM_REG(MCUCTRL, TPIUCTRL) |= AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M; +} + +//***************************************************************************** +// +//! @brief Disable the clock to the TPIU module. +//! +//! This function disables the clock to the TPIU module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_clock_disable(void) +{ + // + // Disable the TPIU clock + // + AM_REG(MCUCTRL, TPIUCTRL) &= ~AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M; +} + +//***************************************************************************** +// +//! @brief Set the output port width of the TPIU +//! +//! @param ui32PortWidth - The desired port width (in bits) +//! +//! This function uses the TPIU_CSPSR register to set the desired output port +//! width of the TPIU. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_port_width_set(uint32_t ui32PortWidth) +{ + AM_REG(TPIU, CSPSR) = 1 << (ui32PortWidth - 1); +} + +//***************************************************************************** +// +//! @brief Read the supported_output port width of the TPIU +//! +//! This function uses the \e TPIU_SSPSR register to set the supported output +//! port widths of the TPIU. +//! +//! @return Current width of the TPIU output port +// +//***************************************************************************** +uint32_t +am_hal_tpiu_supported_port_width_get(void) +{ + uint32_t i, ui32WidthValue; + + // + // Read the supported width register. + // + ui32WidthValue = AM_REG(TPIU, SSPSR); + + // + // The register value is encoded in a one-hot format, so the position of + // the single set bit determines the actual width of the port. + // + for (i = 1; i < 32; i++) + { + // + // Check each bit for a '1'. When we find it, our current loop index + // will be equal to the port width. + // + if (ui32WidthValue == (0x1 << (i - 1))) + { + return i; + } + } + + // + // We should never get here, but if we do, just return the smallest + // possible value for a supported trace port width. + // + return 1; +} + +//***************************************************************************** +// +//! @brief Read the output port width of the TPIU +//! +//! This function uses the \e TPIU_CSPSR register to set the desired output +//! port width of the TPIU. +//! +//! @return Current width of the TPIU output port +// +//***************************************************************************** +uint32_t +am_hal_tpiu_port_width_get(void) +{ + uint32_t ui32Temp; + uint32_t ui32Width; + + ui32Width = 1; + ui32Temp = AM_REG(TPIU, CSPSR); + + while ( !(ui32Temp & 1) ) + { + ui32Temp = ui32Temp >> 1; + ui32Width++; + + if (ui32Width > 32) + { + ui32Width = 0; + break; + } + } + + // + // Current width of the TPIU output port. + // + return ui32Width; +} + +//***************************************************************************** +// +//! @brief Configure the TPIU based on the values in the configuration struct. +//! +//! @param psConfig - pointer to an am_hal_tpiu_config_t structure containing +//! the desired configuration information. +//! +//! This function reads the provided configuration structure, and sets the +//! relevant TPIU registers to achieve the desired configuration. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig) +{ + // + // Set the clock freq in the MCUCTRL register. + // + AM_REG(MCUCTRL, TPIUCTRL) |= psConfig->ui32TraceClkIn; + + // + // Set the desired protocol. + // + AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol; + + // + // Set the parallel port width. This may be redundant if the user has + // selected a serial protocol, but we'll set it anyway. + // + AM_REG(TPIU, CSPSR) = (1 << (psConfig->ui32ParallelPortSize - 1)); + + // + // Set the clock prescaler. + // + AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler; +} + +//***************************************************************************** +// +//! @brief Enables the TPIU +//! +//! This function enables the ARM TPIU by setting the TPIU registers and then +//! enabling the TPIU clock source in MCU control register. +//! +//! @param psConfig - structure for configuration. +//! If ui32SetItmBaud, the other structure members are used to set the +//! TPIU configuration. +//! But for simplicity, ui32SetItmBaud can be set to one of the +//! following, in which case all other structure members are ignored. +//! In this case, the given BAUD rate is based on a div-by-8 HFRC clock. +//! AM_HAL_TPIU_BAUD_57600 +//! AM_HAL_TPIU_BAUD_115200 +//! AM_HAL_TPIU_BAUD_230400 +//! AM_HAL_TPIU_BAUD_460800 +//! AM_HAL_TPIU_BAUD_500000 +//! AM_HAL_TPIU_BAUD_1M +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) +{ + uint32_t ui32HFRC, ui32SWOscaler, ui32ITMbitrate; + + ui32ITMbitrate = psConfig->ui32SetItmBaud; + + // + // TPIU formatter & flush control register. + // + AM_REG(TPIU, FFCR) = 0; + + if ( ui32ITMbitrate ) + { + // + // Set the Current Parallel Port Size (note - only 1 bit can be set). + // + AM_REG(TPIU, CSPSR) = AM_REG_TPIU_CSPSR_CWIDTH_1BIT; + + // + // Use some default assumptions to set the ITM frequency. + // + if ( (ui32ITMbitrate < AM_HAL_TPIU_BAUD_57600 ) || + (ui32ITMbitrate > AM_HAL_TPIU_BAUD_2M ) ) + { + ui32ITMbitrate = AM_HAL_TPIU_BAUD_DEFAULT; + } + + // + // Get the current HFRC frequency. + // + ui32HFRC = am_hal_clkgen_sysclk_get(); + + // + // Compute the SWO scaler value. + // + if ( ui32HFRC != 0xFFFFFFFF ) + { + ui32SWOscaler = ((ui32HFRC / 8) / ui32ITMbitrate) - 1; + } + else + { + ui32SWOscaler = ( (AM_HAL_CLKGEN_FREQ_MAX_HZ / 8) / + AM_HAL_TPIU_BAUD_DEFAULT ) - 1; + } + + // + // Set the scaler value. + // + AM_REG(TPIU, ACPR) = AM_REG_TPIU_ACPR_SWOSCALER(ui32SWOscaler); + + // + // Set for UART mode + // + AM_REG(TPIU, SPPR) = AM_REG_TPIU_SPPR_TXMODE_UART; + + // + // Make sure we are not in test mode (important for proper deep sleep + // operation). + // + AM_REG(TPIU, ITCTRL) = AM_REG_TPIU_ITCTRL_MODE_NORMAL; + + // + // Enable the TPIU clock source in MCU control. + // Set TPIU clock for HFRC/8 (6 or 3 MHz) operation. + // + AM_REGn(MCUCTRL, 0, TPIUCTRL) = + AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_8 | + AM_REG_MCUCTRL_TPIUCTRL_ENABLE_EN; + } + else + { + // + // Set the configuration according to the structure values. + // + + // + // Set the Asynchronous Clock Prescaler Register. + // + AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler; + + // + // Set the Selected Pin Protocol Register. + // e.g. AM_REG_TPIU_SPPR_TXMODE_UART + // + AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol; + + // + // Set the Current Parallel Port Size (note - only 1 bit can be set). + // This may be redundant if the user has selected a serial protocol, + // but we'll set it anyway. + // + AM_REG(TPIU, CSPSR) = (1 << (psConfig->ui32ParallelPortSize - 1)); + + // + // Make sure we are not in test mode (important for proper deep sleep + // operation). + // + AM_REG(TPIU, ITCTRL) = AM_REG_TPIU_ITCTRL_MODE_NORMAL; + + // + // Set the clock freq and enable fields in the MCUCTRL register. + // + AM_REG(MCUCTRL, TPIUCTRL) = psConfig->ui32TraceClkIn; + } + + // + // Wait for 50us for the data to flush out. + // + am_hal_flash_delay(FLASH_CYCLES_US(50)); +} + +//***************************************************************************** +// +//! @brief Disables the TPIU +//! +//! This function disables the ARM TPIU by disabling the TPIU clock source +//! in MCU control register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_disable(void) +{ + // + // Disable the TPIU clock source in MCU control. + // + AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz | + AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_tpiu.h b/mcu/apollo2/hal/am_hal_tpiu.h new file mode 100644 index 0000000..fe11a09 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_tpiu.h @@ -0,0 +1,193 @@ +//***************************************************************************** +// +// am_hal_tpiu.h +//! @file +//! +//! @brief Definitions and structures for working with the TPIU. +//! +//! @addtogroup tpiu2 Trace Port Interface Unit (TPIU) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_TPIU_H +#define AM_HAL_TPIU_H + +#include + +//***************************************************************************** +// +// TPIU bit rate defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_BAUD_57600 (115200 / 2) +#define AM_HAL_TPIU_BAUD_115200 (115200 * 1) +#define AM_HAL_TPIU_BAUD_230400 (115200 * 2) +#define AM_HAL_TPIU_BAUD_460800 (115200 * 4) +#define AM_HAL_TPIU_BAUD_500000 (1000000 / 2) +#define AM_HAL_TPIU_BAUD_1M (1000000 * 1) +#define AM_HAL_TPIU_BAUD_2M (1000000 * 2) +#define AM_HAL_TPIU_BAUD_DEFAULT (AM_HAL_TPIU_BAUD_1M) + +//***************************************************************************** +// +// TPIU register defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_SSPSR 0xE0040000 //! Supported Parallel Port Sizes +#define AM_HAL_TPIU_CSPSR 0xE0040004 //! Current Parallel Port Size +#define AM_HAL_TPIU_ACPR 0xE0040010 //! Asynchronous Clock Prescaler +#define AM_HAL_TPIU_SPPR 0xE00400F0 //! Selected Pin Protocol +#define AM_HAL_TPIU_TYPE 0xE0040FC8 //! TPIU Type + +//***************************************************************************** +// +// TPIU ACPR defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_ACPR_SWOSCALER_M 0x0000FFFF //! SWO baud rate prescalar + +//***************************************************************************** +// +// TPIU_SPPR TXMODE defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_SPPR_PARALLEL 0x00000000 +#define AM_HAL_TPIU_SPPR_MANCHESTER 0x00000001 +#define AM_HAL_TPIU_SPPR_NRZ 0x00000002 + +//***************************************************************************** +// +// TPIU Type defines +// +//***************************************************************************** +#define AM_HAL_TPIU_TYPE_NRZVALID 0x00000800 +#define AM_HAL_TPIU_TYPE_MANCVALID 0x00000400 +#define AM_HAL_TPIU_TYPE_PTINVALID 0x00000200 +#define AM_HAL_TPIU_TYPE_FIFOSZ_M 0x000001C0 + +//***************************************************************************** +// +// TPIU Clock defines +// +//***************************************************************************** +#define AM_HAL_TPIU_TRACECLKIN_6MHZ AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(0) +#define AM_HAL_TPIU_TRACECLKIN_3MHZ AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(1) +#define AM_HAL_TPIU_TRACECLKIN_1_5MHZ AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(2) +#define AM_HAL_TPIU_TRACECLKIN_750KHZ AM_REG_MCUCTRL_TPIUCTRL_TPIUCLKSEL(3) + +//***************************************************************************** +// +//! @brief Structure used for configuring the TPIU +// +//***************************************************************************** +typedef struct +{ + // + // If ui32SetItmBaud is non-zero, the ITM frequency is set to the given + // frequency, and is based on a divide-by-8 HFRC TPIU clock. + // If zero, other structure members are used to set the TPIU configuration. + // + uint32_t ui32SetItmBaud; + + // + //! MCU Control TRACECLKIN clock freq. + //! + //! Valid values for ui32TraceClkIn are: + //! + //! AM_HAL_TPIU_TRACECLKIN_6MHZ + //! AM_HAL_TPIU_TRACECLKIN_3MHZ + //! AM_HAL_TPIU_TRACECLKIN_1_5MHZ + //! AM_HAL_TPIU_TRACECLKIN_750KHZ + // + uint32_t ui32TraceClkIn; + + // + //! Protocol to use for the TPIU + //! + //! Valid values for ui32PinProtocol are: + //! + //! AM_HAL_TPIU_SPPR_PARALLEL + //! AM_HAL_TPIU_SPPR_MANCHESTER + //! AM_HAL_TPIU_SPPR_NRZ + // + uint32_t ui32PinProtocol; + + // + //! Desired width of the TPIU parallel port + // + uint32_t ui32ParallelPortSize; + + // + //! Desired Clock prescaler value + // + uint32_t ui32ClockPrescaler; +} +am_hal_tpiu_config_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_tpiu_clock_enable(void); +extern void am_hal_tpiu_clock_disable(void); +extern void am_hal_tpiu_port_width_set(uint32_t ui32PortWidth); +extern uint32_t am_hal_tpiu_supported_port_width_get(void); +extern uint32_t am_hal_tpiu_port_width_get(void); +extern void am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig); +extern void am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig); +extern void am_hal_tpiu_disable(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_TPIU_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_ttp.c b/mcu/apollo2/hal/am_hal_ttp.c new file mode 100644 index 0000000..ffff0e9 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_ttp.c @@ -0,0 +1,205 @@ +//***************************************************************************** +// +// am_hal_ttp.c +//! @file +//! +//! @brief Functions for handling the "two time program" interface. +//! +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#include "am_mcu_apollo.h" +#include "am_hal_ttp.h" + +//***************************************************************************** +// +// Local constants +// +//***************************************************************************** +#define TTP_ADDR 0x50020000 + +//***************************************************************************** +// +// Local prototypes +// +//***************************************************************************** +#if !defined(__GNUC__) +void __breakpoint(int val); +#endif + +//***************************************************************************** +// +// A function to verify that the TTP was saved and/or restored properly. +// +//***************************************************************************** +int +verifyTTPSaved(uint32_t *pSaveArray, int iNumWords) +{ + int ix, iErrCnt = 0; + uint32_t *pDataSpace = (uint32_t*)TTP_ADDR; + + for (ix = 0; ix +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Transmit and receive queue pointers for each UART module. +// +//***************************************************************************** +am_hal_queue_t g_psTxQueue[AM_REG_UART_NUM_MODULES]; +am_hal_queue_t g_psRxQueue[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// Power tracking structure +// +//***************************************************************************** +am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// Set Baud Rate based on the UART clock frequency. +// +//***************************************************************************** + +#define BAUDCLK (16) +#define UART_CLKFREQ 24000000 + +static void +config_baudrate(uint32_t ui32Module, uint32_t ui32Baudrate, uint32_t ui32UartClkFreq) +{ + uint64_t ui64FractionDivisorLong; + uint64_t ui64IntermediateLong; + uint32_t ui32IntegerDivisor; + uint32_t ui32FractionDivisor; + uint32_t ui32BaudClk; + + // + // Calculate register values. + // + ui32BaudClk = BAUDCLK * ui32Baudrate; + ui32IntegerDivisor = (uint32_t)(ui32UartClkFreq / ui32BaudClk); + ui64IntermediateLong = (ui32UartClkFreq * 64) / ui32BaudClk; + ui64FractionDivisorLong = ui64IntermediateLong - (ui32IntegerDivisor * 64); + ui32FractionDivisor = (uint32_t)ui64FractionDivisorLong; + + // + // Check the result. + // + am_hal_debug_assert_msg(ui32IntegerDivisor > 0, "Integer divisor MUST be greater than or equal to 1."); + + // + // Write the UART regs. + // + AM_REGn(UART, ui32Module, IBRD) = ui32IntegerDivisor; + AM_REGn(UART, ui32Module, IBRD) = ui32IntegerDivisor; + AM_REGn(UART, ui32Module, FBRD) = ui32FractionDivisor; +} + +//***************************************************************************** +// +//! @brief Set up the UART. +//! +//! @param psConfig pointer to a structure that holds the settings for the UART. +//! @param ui32UartclkFreq is clock frequency that the UART is running at. +//! +//! This function should be used to perform the initial set-up of the UART. +//! +//! @return none. +// +//***************************************************************************** +void +am_hal_uart_config(uint32_t ui32Module, am_hal_uart_config_t *psConfig) + +{ + uint32_t ui32ConfigVal = 0; + + // + // Disable the UART. + // + am_hal_uart_disable(ui32Module); + + // + // Configure the Baudrate, and uart clock is 24MHz + // + config_baudrate(ui32Module, psConfig->ui32BaudRate, UART_CLKFREQ); + + // + // Enable the UART, RX, and TX. + // + am_hal_uart_enable(ui32Module); + + // + // OR in the Data bits. + // + ui32ConfigVal |= psConfig->ui32DataBits; + + // + // OR in the Two Stop bit if used. + // + ui32ConfigVal |= psConfig->bTwoStopBits ? AM_REG_UART_LCRH_STP2_M : 0; + + // + // OR in the Parity. + // + ui32ConfigVal |= psConfig->ui32Parity; + + // + // Write config to Line control register. + // + AM_REGn(UART, ui32Module, LCRH) |= ui32ConfigVal; + + // + // Write the flow control settings to the control register. + // + AM_REGn(UART, ui32Module, CR) |= psConfig->ui32FlowCtrl; + + // + // Set the clock select field for 24MHz from the HFRC + // + AM_REGn(UART, ui32Module, CR) |= AM_REG_UART_CR_CLKSEL_24MHZ; +} + +//***************************************************************************** +// +//! @brief Gets the status. +//! +//! This function returns the current status. +//! +//! @return current status. +// +//***************************************************************************** +uint32_t +am_hal_uart_status_get(uint32_t ui32Module) +{ + // + // Read and return the Status. + // + return AM_REGn(UART, ui32Module, RSR); +} + +//***************************************************************************** +// +//! @brief Gets the interrupt status. +//! +//! @param bEnabledOnly - If true returns the enabled interrupt status. +//! +//! This function returns the masked or raw interrupt status. +//! +//! @return Bitwise representation of the current interrupt status. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_REG_UART_IER_TXIM_M +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_RIM +// +//***************************************************************************** +uint32_t +am_hal_uart_int_status_get(uint32_t ui32Module, bool bEnabledOnly) +{ + if (bEnabledOnly) + { + // + // Read and return the Masked Interrupt Status. + // + return AM_REGn(UART, ui32Module, MIS); + } + else + { + // + // Read and return the Raw Interrupt Status. + // + return AM_REGn(UART, ui32Module, IES); + } +} + +//***************************************************************************** +// +//! @brief Clears the desired interrupts. +//! +//! @param ui32Interrupt - Interrupt bits to clear. +//! +//! This function clears the desired interrupts. +//! +//! ui32Interrupt should be a logical or of the following: +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_REG_UART_IER_TXIM_M +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_RIM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Clear the bits. + // + AM_REGn(UART, ui32Module, IEC) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Disables the desired interrupts. +//! +//! @param ui32Interrupt - Interrupt bits to disable. +//! +//! This function disables the desired interrupts. +//! +//! ui32Interrupt should be a logical or of the following: +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_REG_UART_IER_TXIM_M +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_RIM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Disable the bits. + // + AM_REGn(UART, ui32Module, IER) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Enables the desired interrupts. +//! +//! @param ui32Interrupt - Interrupt bits to enable. +//! +//! This function enables the desired interrupts. +//! +//! ui32Interrupt should be a logical or of the following: +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_REG_UART_IER_TXIM_M +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_RIM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt) +{ + // + // Enable the interrupts. + // + AM_REGn(UART, ui32Module, IER) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Returns the enabled interrupts. +//! +//! This function return the enabled interrupts. +//! +//! @return the enabled interrupts. This will be a logical or of the following: +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_REG_UART_IER_TXIM_M +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_RIM +//! +//! @return Returns the enabled interrupts. +// +//***************************************************************************** +uint32_t +am_hal_uart_int_enable_get(uint32_t ui32Module) +{ + // + // Return the enabled interrupts. + // + return AM_REGn(UART, ui32Module, IER); +} + +//***************************************************************************** +// +//! @brief Enable the UART, RX, and TX. +//! +//! This function enables the UART, RX, and TX. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_enable(uint32_t ui32Module) +{ + // + // Enable the UART, RX, and TX. + // + AM_REGan_SET(UART, ui32Module, CR, (AM_REG_UART_CR_UARTEN_M | + AM_REG_UART_CR_RXE_M | + AM_REG_UART_CR_TXE_M) ); +} + +//***************************************************************************** +// +//! @brief Disable the UART, RX, and TX. +//! +//! This function disables the UART, RX, and TX. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_disable(uint32_t ui32Module) +{ + // + // Disable the UART. + // + AM_REGan_CLR(UART, ui32Module, CR, (AM_REG_UART_CR_UARTEN_M | + AM_REG_UART_CR_RXE_M | + AM_REG_UART_CR_TXE_M) ); +} + +//***************************************************************************** +// +//! @brief Enable the UART in the power control block. +//! +//! This function enables the UART device in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_pwrctrl_enable(uint32_t ui32Module) +{ + // + // Check to make sure we're acting on a real UART module. + // + am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES, + "Trying to disable a UART module that doesn't exist"); + + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_UART0 << ui32Module); +} + +//***************************************************************************** +// +//! @brief Disable the UART in the power control block. +//! +//! This function disables the UART device in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_pwrctrl_disable(uint32_t ui32Module) +{ + // + // Check to make sure we're acting on a real UART module. + // + am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES, + "Trying to disable a UART module that doesn't exist"); + + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_UART0 << ui32Module); +} + +//***************************************************************************** +// +//! @brief Enable the UART in the power control block. +//! +//! This function enables the UART device in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_power_on_restore(uint32_t ui32Module) +{ + // + // Check to make sure we're acting on a real UART module. + // + am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES, + "Trying to enable a UART module that doesn't exist"); + + // + // Make sure this restore is a companion to a previous save call. + // + if ( am_hal_uart_pwrsave[ui32Module].bValid == 0 ) + { + return; + } + + // + // Enable power to the selected UART + // + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_UART0 << ui32Module); + + // + // Restore the clock settings + // + am_hal_clkgen_uarten_set(ui32Module, am_hal_uart_pwrsave[ui32Module].UARTEN); + + // + // Restore the configuration registers from the global variable in SRAM. + // + AM_REGn(UART, ui32Module, ILPR) = am_hal_uart_pwrsave[ui32Module].ILPR; + AM_REGn(UART, ui32Module, IBRD) = am_hal_uart_pwrsave[ui32Module].IBRD; + AM_REGn(UART, ui32Module, FBRD) = am_hal_uart_pwrsave[ui32Module].FBRD; + AM_REGn(UART, ui32Module, LCRH) = am_hal_uart_pwrsave[ui32Module].LCRH; + AM_REGn(UART, ui32Module, CR) = am_hal_uart_pwrsave[ui32Module].CR; + AM_REGn(UART, ui32Module, IFLS) = am_hal_uart_pwrsave[ui32Module].IFLS; + AM_REGn(UART, ui32Module, IER) = am_hal_uart_pwrsave[ui32Module].IER; + + // + // Indicates we have restored the configuration. + // + am_hal_uart_pwrsave[ui32Module].bValid = 0; + + return; +} + +//***************************************************************************** +// +//! @brief Disable the UART in the power control block. +//! +//! This function disables the UART device in the power control block. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_power_off_save(uint32_t ui32Module) +{ + // + // Check to make sure we're acting on a real UART module. + // + am_hal_debug_assert_msg(ui32Module < AM_REG_UART_NUM_MODULES, + "Trying to disable a UART module that doesn't exist"); + + // + // Save all of the configuration register information for the selected + // UART. + // + am_hal_uart_pwrsave[ui32Module].ILPR = AM_REGn(UART, ui32Module, ILPR); + am_hal_uart_pwrsave[ui32Module].IBRD = AM_REGn(UART, ui32Module, IBRD); + am_hal_uart_pwrsave[ui32Module].FBRD = AM_REGn(UART, ui32Module, FBRD); + am_hal_uart_pwrsave[ui32Module].LCRH = AM_REGn(UART, ui32Module, LCRH); + am_hal_uart_pwrsave[ui32Module].CR = AM_REGn(UART, ui32Module, CR); + am_hal_uart_pwrsave[ui32Module].IFLS = AM_REGn(UART, ui32Module, IFLS); + am_hal_uart_pwrsave[ui32Module].IER = AM_REGn(UART, ui32Module, IER); + + // + // Save the clock setting and disable power to the selected UART. + // Save the current enable value. + // + am_hal_uart_pwrsave[ui32Module].UARTEN = + (AM_REG(CLKGEN, UARTEN) & AM_HAL_CLKGEN_UARTEN_UARTENn_M(ui32Module)) >> + AM_HAL_CLKGEN_UARTEN_UARTENn_S(ui32Module); + + // + // Disable the UART. + // + am_hal_clkgen_uarten_set(ui32Module, AM_HAL_CLKGEN_UARTEN_DIS); + + // + // Indicates we have a valid saved configuration. + // + am_hal_uart_pwrsave[ui32Module].bValid = 1; + + // + // Disable power to the selected UART. + // + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_UART0 << ui32Module); + + return; +} + +//***************************************************************************** +// +//! @brief Enable the UART clock. +//! +//! This function enables the clock to the UART. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_clock_enable(uint32_t ui32Module) +{ + // + // Set CLKGEN.UARTEN, clear the field then write the desired enable value + // Valid enable values are DIS, EN, REDUCE_FREQ, EN_POWER_SAV. + // + am_hal_clkgen_uarten_set(ui32Module, AM_HAL_CLKGEN_UARTEN_EN); + + // + // Enable the UART clock. + // + AM_REGn(UART, ui32Module, CR) |= AM_REG_UART_CR_CLKEN_M; + + // + // Select default UART clock source + // + AM_REGn(UART, ui32Module, CR) |= AM_REG_UART_CR_CLKSEL_24MHZ; +} + +//***************************************************************************** +// +//! @brief Disable the UART clock. +//! +//! This function disables the clock to the UART. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_clock_disable(uint32_t ui32Module) +{ + // + // Disable the UART clock. + // + AM_REGn(UART, ui32Module, CR) &= ~AM_REG_UART_CR_CLKEN_M; + + // + // Disable the UART clock in the CLKGEN module. + // + am_hal_clkgen_uarten_set(ui32Module, AM_HAL_CLKGEN_UARTEN_DIS); +} + +//***************************************************************************** +// +//! @brief Set and enable the desired interrupt levels for the RX/TX fifo. +//! +//! @param ui32LvlCfg - Desired FIFO RX/TX levels. +//! +//! This function sets the desired interrupt levels for the RX/TX fifo and +//! enables the use of transmit and receive FIFO buffers. +//! +//! Valid values for ui32LvlCfg are: +//! +//! AM_HAL_UART_TX_FIFO_1_8 +//! AM_HAL_UART_TX_FIFO_1_4 +//! AM_HAL_UART_TX_FIFO_1_2 +//! AM_HAL_UART_TX_FIFO_3_4 +//! AM_HAL_UART_TX_FIFO_7_8 +//! +//! AM_HAL_UART_RX_FIFO_1_8 +//! AM_HAL_UART_RX_FIFO_1_4 +//! AM_HAL_UART_RX_FIFO_1_2 +//! AM_HAL_UART_RX_FIFO_3_4 +//! AM_HAL_UART_RX_FIFO_7_8 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_fifo_config(uint32_t ui32Module, uint32_t ui32LvlCfg) +{ + // + // Enable the use of FIFOs. + // + AM_REGn(UART, ui32Module, LCRH) |= AM_REG_UART_LCRH_FEN_M; + + // + // Write the FIFO level register. + // + AM_REGn(UART, ui32Module, IFLS) = ui32LvlCfg; +} + +//***************************************************************************** +// +//! @brief Return the UART Flags. +//! +//! This function reads and returns the UART flags. +//! +//! @return Returns the Flags. +// +//***************************************************************************** +uint32_t +am_hal_uart_flags_get(uint32_t ui32Module) +{ + // + // Read and return the Flags. + // + return AM_REGn(UART, ui32Module, FR); +} + +//***************************************************************************** +// +//! @brief Outputs a single character using polling. +//! +//! @param cChar - Character to send. +//! +//! This function outputs a single character using polling. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_char_transmit_polled(uint32_t ui32Module, char cChar) +{ + // + // Wait for space, i.e. TX FIFO EMPTY + // + while (AM_BFRn(UART, ui32Module, FR, TXFF)); + + // + // Write the char. + // + AM_REGn(UART, ui32Module, DR) = cChar; +} + +//***************************************************************************** +// +//! @brief Outputs a zero terminated string using polling. +//! +//! @param pcString - Pointer to character string to send. +//! +//! This function outputs a zero terminated string using polling. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_string_transmit_polled(uint32_t ui32Module, char *pcString) +{ + while (*pcString) + { + // + // Wait for space, i.e. TX FIFO EMPTY. + // + while (AM_BFRn(UART, ui32Module, FR, TXFF)); + + // + // Write the char. + // + AM_REGn(UART, ui32Module, DR) = *pcString++; + } +} + +//***************************************************************************** +// +//! @brief Receives a character using polling. +//! +//! @param pcChar - Pointer to character to store received char. +//! +//! This function receives a character using polling. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_char_receive_polled(uint32_t ui32Module, char *pcChar) +{ + // + // Wait for data, i.e. RX FIFO NOT EMPTY. + // + while (AM_BFRn(UART, ui32Module, FR, RXFE)); + + // + // Save the char. + // + *pcChar = AM_REGn(UART, ui32Module, DR); +} + +//***************************************************************************** +// +//! @brief Receives one line using polling. +//! +//! @param ui32MaxChars - Maximum number of characters to receive. +//! @param pcChar - Pointer to character string to store received line. +//! +//! This function receives a line (delimited by '/n' or '/r') using polling. +//! Line buffer is 0 (NULL) terminated. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_line_receive_polled(uint32_t ui32Module, + uint32_t ui32MaxChars, + char *pcChar) +{ + char cRecChar; + uint32_t i; + + // + // Loop until we receive ui32MaxChars or receive a line ending. + // + for (i = 0; i < (ui32MaxChars - 1); i++) + { + // + // Get char. + // + am_hal_uart_char_receive_polled(ui32Module, &cRecChar); + + if ((cRecChar == '\n') || (cRecChar == '\r')) + { + // + // Zero terminate the buffer. + // + *pcChar = 0; + + return; + } + + *pcChar++ = cRecChar; + } +} + +//***************************************************************************** +// +//! @brief Initialize the buffered UART. +//! +//! @param pui8RxArray - Pointer to the RX buffer to fill. +//! @param ui32RxSize - size of RX buffer. +//! @param pui8TxArray - Pointer to the TX buffer to fill. +//! @param ui32TxSize - size of TX buffer. +//! +//! This function initializes the buffered UART. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_init_buffered(uint32_t ui32Module, + uint8_t *pui8RxArray, uint32_t ui32RxSize, + uint8_t *pui8TxArray, uint32_t ui32TxSize) +{ + if ( (pui8RxArray != NULL) && (ui32RxSize > 0) ) + { + // + // Enable the UART RX timeout interrupt. + // + AM_REGn(UART, ui32Module, IER) |= (AM_REG_UART_IES_RTRIS_M); + + // + // Initialize the RX ring buffer. + // + am_hal_queue_init(&g_psRxQueue[ui32Module], pui8RxArray, 1, ui32RxSize); + } + + if ( (pui8TxArray != NULL) && (ui32TxSize > 0) ) + { + // + // Enable the UART TX timeout interrupt. + // + AM_REGn(UART, ui32Module, IER) |= (AM_REG_UART_IES_TXRIS_M); + + // + // Initialize the TX ring buffer. + // + am_hal_queue_init(&g_psTxQueue[ui32Module], pui8TxArray, 1, ui32TxSize); + } +} + +//***************************************************************************** +// +//! @brief Get the status of the buffered UART. +//! +//! @param pui32RxSize - Pointer to variable to return the Rx ring data size. +//! @param pui32TxSize - Pointer to variable to return the Tx ring data size. +//! +//! This function gets the status of the buffered UART. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_get_status_buffered(uint32_t ui32Module, + uint32_t *pui32RxSize, + uint32_t *pui32TxSize) +{ + // + // Return the current size of ring buffers. + // + if ( pui32RxSize ) + { + *pui32RxSize = am_hal_queue_data_left(&g_psRxQueue[ui32Module]); + } + + if ( pui32TxSize ) + { + *pui32TxSize = am_hal_queue_data_left(&g_psTxQueue[ui32Module]); + } +} + +//***************************************************************************** +// +//! @brief Services the buffered UART. +//! +//! @param ui32Status is the contents of the UART interrupt status register. +//! +//! This function is responsible for servicing the buffered UART. Designed to +//! be called from the UART interrupt handler. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_uart_service_buffered(uint32_t ui32Module, uint32_t ui32Status) +{ + uint8_t ui8Character = '\x00'; + uint32_t ui32FifoEntry = 0; + + // + // Check to see if we have filled the Rx FIFO past the configured limit, or + // if we have an 'old' character or two sitting in the FIFO. + // + if (ui32Status & (AM_REG_UART_IES_RXRIS_M | AM_REG_UART_IES_RTRIS_M)) + { + // + // While there's stuff in the RX fifo.... + // + while (!AM_BFRn(UART, ui32Module, FR, RXFE)) + { + // + // Read each character out one by one, and add it to the ring + // buffer. This will start losing bytes if the fifo ever overflows. + // + ui32FifoEntry = AM_REGn(UART, ui32Module , DR); + + // + // As long as no error bits were set, we should push this byte to + // the FIFO. + // + if ( (ui32FifoEntry & 0xF00) == 0 ) + { + ui8Character = ui32FifoEntry & 0xFF; + am_hal_queue_item_add(&g_psRxQueue[ui32Module], &ui8Character, 1); + } + } + } + + // + // Check to see if our TX buffer has been recently emptied. If so, we + // should refill it from the TX ring buffer. + // + if (ui32Status & AM_REG_UART_IES_TXRIS_M) + { + // + // Keep refilling until the fifo is full, or the ring buffer is empty, + // whichever happens first. + // + while (am_hal_queue_data_left(&g_psTxQueue[ui32Module]) && + !AM_BFRn(UART, ui32Module, FR, TXFF)) + { + am_hal_queue_item_get(&g_psTxQueue[ui32Module], &ui8Character, 1); + AM_REGn(UART, ui32Module , DR) = ui8Character; + } + } +} + +//***************************************************************************** +// +//! @brief Services the buffered UART. +//! +//! @param ui32Status is the contents of the UART interrupt status register. +//! +//! This function is responsible for servicing the buffered UART. Designed to +//! be called from the UART interrupt handler. +//! +//! This function behaves exactly like am_hal_uart_service_buffered() \e except +//! it does not completely empty the RX FIFO on every interrupt event. Instead, +//! it will leave at least one byte behind until it receives a UART RX TIMEOUT +//! interrupt. If you use this service routine, you can treat the RX TIMEOUT +//! interrupt as a UART IDLE interrupt. Every time the UART RX line goes IDLE +//! for 32 consecutive bit-times you WILL receive a UART RX TIMEOUT interrupt. +//! This behavior is not guaranteed for am_hal_uart_service_buffered(). +//! +//! @return None +// +//***************************************************************************** +void +am_hal_uart_service_buffered_timeout_save(uint32_t ui32Module, uint32_t ui32Status) +{ + uint8_t ui8Character = '\x00'; + uint32_t ui32Count = 0; + uint32_t ui32FifoEntry = 0; + + // + // Check to see if we have filled the Rx FIFO past the configured limit, or + // if we have an 'old' character or two sitting in the FIFO. + // + if (ui32Status & (AM_REG_UART_IES_RXRIS_M | AM_REG_UART_IES_RTRIS_M)) + { + // + // Check to see what our FIFO configuration setting is. + // + uint32_t ui32FifoThreshold; + uint32_t ui32FifoCfg = AM_BFMn(UART, ui32Module, IFLS, RXIFLSEL); + + // + // Compute the number of bytes for receive interrupt from the FIFO level + // register. + // + switch(ui32FifoCfg) + { + case AM_HAL_UART_RX_FIFO_1_8: ui32FifoThreshold = 4; break; + case AM_HAL_UART_RX_FIFO_1_4: ui32FifoThreshold = 8; break; + case AM_HAL_UART_RX_FIFO_1_2: ui32FifoThreshold = 16; break; + case AM_HAL_UART_RX_FIFO_3_4: ui32FifoThreshold = 24; break; + case AM_HAL_UART_RX_FIFO_7_8: ui32FifoThreshold = 28; break; + default: + ui32FifoThreshold = 32; + } + + // + // While there's stuff in the RX fifo.... + // + while (!AM_BFRn(UART, ui32Module, FR, RXFE)) + { + // + // Read each character out one by one, and add it to the ring + // buffer. This will start losing bytes if the fifo ever overflows. + // + ui32FifoEntry = AM_REGn(UART, ui32Module, DR); + + // + // As long as no error bits were set, we should push this byte to + // the FIFO. + // + if ( (ui32FifoEntry & 0xF00) == 0) + { + ui8Character = ui32FifoEntry & 0xFF; + am_hal_queue_item_add(&g_psRxQueue[ui32Module], &ui8Character, 1); + } + + // + // Leave one byte to trigger the RX timeout interrupt. + // + if ( ++ui32Count >= (ui32FifoThreshold - 1) ) + { + break; + } + } + } + + // + // Check to see if our TX buffer has been recently emptied. If so, we + // should refill it from the TX ring buffer. + // + if (ui32Status & AM_REG_UART_IES_TXRIS_M) + { + // + // Keep refilling until the fifo is full, or the ring buffer is empty, + // whichever happens first. + // + while (am_hal_queue_data_left(&g_psTxQueue[ui32Module]) && + !AM_BFRn(UART, ui32Module, FR, TXFF)) + { + am_hal_queue_item_get(&g_psTxQueue[ui32Module], &ui8Character, 1); + AM_REGn(UART, ui32Module , DR) = ui8Character; + } + } +} + +//***************************************************************************** +// +//! @brief Puts a char in the buffer or directly to the fifo if available. +//! +//! @param cChar - Character to send. +//! +//! This function puts a character in the buffer or directly to the fifo. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_char_transmit_buffered(uint32_t ui32Module, char cChar) +{ + // + // Check the status of the Tx fifo and the Tx ring buffer. + // + if (am_hal_queue_empty(&g_psTxQueue[ui32Module]) && + !AM_BFRn(UART, ui32Module, FR, TXFF)) + { + // + // If the fifo isn't full yet, and the ring buffer isn't being used, + // just write the new character directly to the fifo. + // + AM_REGn(UART, ui32Module, DR) = cChar; + } + else + { + // + // If we get here, either the fifo is full, or the ring buffer is + // already in use. In either case, we need to use the ring buffer + // to make sure that the transmitted data gets sent in the right + // order. If the buffer is already full, we will simply lose this + // byte. + // + am_hal_queue_item_add(&g_psTxQueue[ui32Module], &cChar, 1); + } +} + +//***************************************************************************** +// +//! @brief Puts a null terminaled string in the buffer or directly to the fifo. +//! +//! @param pcString - Pointer to buffer used for sending. +//! +//! This function puts a string in the buffer or directly to the fifo if there +//! is space available. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_uart_string_transmit_buffered(uint32_t ui32Module, char *pcString) +{ + // + // Check the status of the Tx fifo and the Tx ring buffer. + // + while (*pcString) + { + if (am_hal_queue_empty(&g_psTxQueue[ui32Module]) && + !AM_BFRn(UART, ui32Module, FR, TXFF)) + { + // + // If the fifo isn't full yet, and the ring buffer isn't being used, + // just write the new character directly to the fifo. + // + AM_REGn(UART, ui32Module, DR) = *pcString; + } + else + { + // + // If we get here, either the fifo is full, or the ring buffer is + // already in use. In either case, we need to use the ring buffer + // to make sure that the transmitted data gets sent in the right + // order. If the buffer is already full, we will simply lose this + // byte. + // + am_hal_queue_item_add(&g_psTxQueue[ui32Module], pcString, 1); + } + + // + // Move the pointer to the next character. + // + pcString++; + } +} + +//***************************************************************************** +// +//! @brief Returns n number of characters from the ring buffer or until empty. +//! +//! @param pcString - Pointer to buffer for putting received characters. +//! @param ui32MaxChars - Maximum number of characters to receive. +//! +//! This function puts a char string in the buffer. +//! +//! @return Returns the number of chars received. +// +//***************************************************************************** +uint32_t +am_hal_uart_char_receive_buffered(uint32_t ui32Module, + char *pcString, + uint32_t ui32MaxChars) +{ + uint32_t ui32NumChars = 0; + + // + // Loop until ui32MaxChars or until empty. + // + while (am_hal_queue_data_left(&g_psRxQueue[ui32Module]) && ui32MaxChars) + { + // + // Pull a char out of the ring buffer. + // + am_hal_queue_item_get(&g_psRxQueue[ui32Module], pcString, 1); + + // + // Subtract from ui32MaxChars. + // Add to ui32NumChars. + // Move pointer in buffer. + // + ui32MaxChars--; + ui32NumChars++; + pcString++; + } + + // + // return the number of chars received. + // + return ui32NumChars; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_uart.h b/mcu/apollo2/hal/am_hal_uart.h new file mode 100644 index 0000000..9d38411 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_uart.h @@ -0,0 +1,345 @@ +//***************************************************************************** +// +// am_hal_uart.h +//! @file +//! +//! @brief Functions for accessing and configuring the UART. +//! +//! @addtogroup uart2 UART +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_UART_H +#define AM_HAL_UART_H + +//***************************************************************************** +// +//! @name UART Interrupts +//! @brief Macro definitions for UART FIFO levels. +//! +//! They may be used with the \e am_hal_uart_fifo_config() function. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_UART_INT_OVER_RUN AM_REG_UART_IER_OEIM_M +#define AM_HAL_UART_INT_BREAK_ERR AM_REG_UART_IER_BEIM_M +#define AM_HAL_UART_INT_PARITY_ERR AM_REG_UART_IER_PEIM_M +#define AM_HAL_UART_INT_FRAME_ERR AM_REG_UART_IER_FEIM_M +#define AM_HAL_UART_INT_RX_TMOUT AM_REG_UART_IER_RTIM_M +#define AM_HAL_UART_INT_TX AM_REG_UART_IER_TXIM_M +#define AM_HAL_UART_INT_RX AM_REG_UART_IER_RXIM_M +#define AM_HAL_UART_INT_DSRM AM_REG_UART_IER_DSRMIM_M +#define AM_HAL_UART_INT_DCDM AM_REG_UART_IER_DCDMIM_M +#define AM_HAL_UART_INT_CTSM AM_REG_UART_IER_CTSMIM_M +#define AM_HAL_UART_INT_TXCMP AM_REG_UART_IER_TXCMPMIM_M +//! @} + +//***************************************************************************** +// +//! @name UART FIFO Levels +//! @brief Macro definitions for RTV interrupt status bits. +//! +//! These macros correspond to the bits in the UART interrupt status register. +//! They may be used with any of the \e am_hal_uart_int_x() functions. +//! +//! @{ +// +//***************************************************************************** +//TX +#define AM_HAL_UART_TX_FIFO_1_8 AM_REG_UART_IFLS_TXIFLSEL(0) +#define AM_HAL_UART_TX_FIFO_1_4 AM_REG_UART_IFLS_TXIFLSEL(1) +#define AM_HAL_UART_TX_FIFO_1_2 AM_REG_UART_IFLS_TXIFLSEL(2) +#define AM_HAL_UART_TX_FIFO_3_4 AM_REG_UART_IFLS_TXIFLSEL(3) +#define AM_HAL_UART_TX_FIFO_7_8 AM_REG_UART_IFLS_TXIFLSEL(4) +// RX +#define AM_HAL_UART_RX_FIFO_1_8 AM_REG_UART_IFLS_RXIFLSEL(0) +#define AM_HAL_UART_RX_FIFO_1_4 AM_REG_UART_IFLS_RXIFLSEL(1) +#define AM_HAL_UART_RX_FIFO_1_2 AM_REG_UART_IFLS_RXIFLSEL(2) +#define AM_HAL_UART_RX_FIFO_3_4 AM_REG_UART_IFLS_RXIFLSEL(3) +#define AM_HAL_UART_RX_FIFO_7_8 AM_REG_UART_IFLS_RXIFLSEL(4) +//! @} + +//***************************************************************************** +// +//! @name UART Status Register +//! @brief Macro definitions for UART Status Register Bits. +//! +//! They may be used with the \e am_hal_uart_status_get() function. +//! +//! @{ +// +//***************************************************************************** +// This is the overrun error indicator. +#define AM_HAL_UART_RSR_OVERRUN_NOERR AM_REG_UART_RSR_OESTAT_NOERR +#define AM_HAL_UART_RSR_OVERRUN_ERROR AM_REG_UART_RSR_OESTAT_ERR + +// This is the break error indicator. +#define AM_HAL_UART_RSR_BREAK_NOERR AM_REG_UART_RSR_BESTAT_NOERR +#define AM_HAL_UART_RSR_BREAK_ERROR AM_REG_UART_RSR_BESTAT_ERR + +// This is the parity error indicator. +#define AM_HAL_UART_RSR_PARITY_NOERR AM_REG_UART_RSR_PESTAT_NOERR +#define AM_HAL_UART_RSR_PARITY_ERROR AM_REG_UART_RSR_PESTAT_ERR + +// This is the framing error indicator. +#define AM_HAL_UART_RSR_FRAME_ERROR_NOERR AM_REG_UART_RSR_FESTAT_NOERR +#define AM_HAL_UART_RSR_FRAME_ERROR_ERROR AM_REG_UART_RSR_FESTAT_ERR +//! @} + +//***************************************************************************** +// +//! @name UART Flag Register +//! @brief Macro definitions for UART Flag Register Bits. +//! +//! They may be used with the \e am_hal_uart_flags_get() function. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_UART_FR_RING AM_REG_UART_FR_RI_M +#define AM_HAL_UART_FR_TX_EMPTY AM_REG_UART_FR_TXFE_XMTFIFO_EMPTY +#define AM_HAL_UART_FR_RX_FULL AM_REG_UART_FR_RXFF_RCVFIFO_FULL +#define AM_HAL_UART_FR_TX_FULL AM_REG_UART_FR_TXFF_XMTFIFO_FULL +#define AM_HAL_UART_FR_RX_EMPTY AM_REG_UART_FR_RXFE_RCVFIFO_EMPTY +#define AM_HAL_UART_FR_BUSY AM_REG_UART_FR_BUSY_BUSY +#define AM_HAL_UART_FR_DCD_DETECTED AM_REG_UART_FR_DCD_DETECTED +#define AM_HAL_UART_FR_DSR_READY AM_REG_UART_FR_DSR_READY +#define AM_HAL_UART_FR_CTS AM_REG_UART_FR_CTS_M +//! @} + + +//***************************************************************************** +// +//! @name UART Config Macros +//! @brief Macro definitions for available Data bits. +//! +//! They may be used with the \e am_hal_uart_config_t structure used by \e +//! am_hal_uart_config(). +//! +//! @{ +// +//***************************************************************************** +//***************************************************************************** +// +// Data bits defines. +// +//***************************************************************************** +#define AM_HAL_UART_DATA_BITS_8 AM_REG_UART_LCRH_WLEN(3) +#define AM_HAL_UART_DATA_BITS_7 AM_REG_UART_LCRH_WLEN(2) +#define AM_HAL_UART_DATA_BITS_6 AM_REG_UART_LCRH_WLEN(1) +#define AM_HAL_UART_DATA_BITS_5 0 + +//***************************************************************************** +// +// Parity defines. +// +//***************************************************************************** +#define AM_HAL_UART_PARITY_NONE 0 +#define AM_HAL_UART_PARITY_ODD AM_REG_UART_LCRH_PEN_M +#define AM_HAL_UART_PARITY_EVEN AM_REG_UART_LCRH_PEN_M | \ + AM_REG_UART_LCRH_EPS_M + +//***************************************************************************** +// +// Flow control defines. +// +//***************************************************************************** +#define AM_HAL_UART_FLOW_CTRL_NONE 0 +#define AM_HAL_UART_FLOW_CTRL_RTS_CTS AM_REG_UART_CR_CTSEN_M | \ + AM_REG_UART_CR_RTSEN_M +//! @} + +//***************************************************************************** +// +//! UART configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Desired Baudrate for the UART. + // + uint32_t ui32BaudRate; + + // + //! Number of data bits. + //! + //! Valid values for ui32DataBits are: + //! + //! AM_HAL_UART_DATA_BITS_8 + //! AM_HAL_UART_DATA_BITS_7 + //! AM_HAL_UART_DATA_BITS_6 + //! AM_HAL_UART_DATA_BITS_5 + // + uint32_t ui32DataBits; + + // + //! Use two stop bits. + // + bool bTwoStopBits; + + // + //! Parity. + //! + //! Valid values for ui32Parity are: + //! + //! AM_HAL_UART_PARITY_NONE + //! AM_HAL_UART_PARITY_ODD + //! AM_HAL_UART_PARITY_EVEN + // + uint32_t ui32Parity; + + // + //! Flow control. + //! + //! Valid values for ui32FlowCtrl are: + //! + //! AM_HAL_UART_FLOW_CTRL_NONE + //! AM_HAL_UART_FLOW_CTRL_RTS_CTS + // + uint32_t ui32FlowCtrl; +} +am_hal_uart_config_t; + +//***************************************************************************** +// +// Structure for containing information about the UART's configuration while +// it is powered down. +// +//***************************************************************************** +typedef struct +{ + uint32_t ILPR; + uint32_t IBRD; + uint32_t FBRD; + uint32_t LCRH; + uint32_t CR; + uint32_t IFLS; + uint32_t IER; + uint32_t UARTEN; + uint32_t bValid; +} +am_hal_uart_pwrsave_t; + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +extern am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_uart_pwrctrl_enable(uint32_t ui32Module); +extern void am_hal_uart_pwrctrl_disable(uint32_t ui32Module); +extern void am_hal_uart_power_on_restore(uint32_t ui32Module); +extern void am_hal_uart_power_off_save(uint32_t ui32Module); +extern void am_hal_uart_config(uint32_t ui32Module, + am_hal_uart_config_t *psConfig); +extern uint32_t am_hal_uart_status_get(uint32_t ui32Module); +extern uint32_t am_hal_uart_int_status_get(uint32_t ui32Module, + bool bEnabledOnly); +extern void am_hal_uart_int_clear(uint32_t ui32Module, + uint32_t ui32Interrupt); +extern void am_hal_uart_int_disable(uint32_t ui32Module, + uint32_t ui32Interrupt); +extern void am_hal_uart_int_enable(uint32_t ui32Module, + uint32_t ui32Interrupt); +extern uint32_t am_hal_uart_int_enable_get(uint32_t ui32Module); +extern void am_hal_uart_enable(uint32_t ui32Module); +extern void am_hal_uart_disable(uint32_t ui32Module); +extern void am_hal_uart_clock_enable(uint32_t ui32Module); +extern void am_hal_uart_clock_disable(uint32_t ui32Module); +extern void am_hal_uart_fifo_config(uint32_t ui32Module, uint32_t ui32LvlCfg); +extern uint32_t am_hal_uart_flags_get(uint32_t ui32Module); + +// rx/tx polled +extern void am_hal_uart_char_transmit_polled(uint32_t ui32Module, + char cChar); +extern void am_hal_uart_string_transmit_polled(uint32_t ui32Module, + char *pcString); +extern void am_hal_uart_char_receive_polled(uint32_t ui32Module, + char *pcChar); +extern void am_hal_uart_line_receive_polled(uint32_t ui32Module, + uint32_t ui32MaxChars, + char *pcChar); + +// rx/tx buffered +extern void am_hal_uart_init_buffered(uint32_t ui32Module, + uint8_t *pui8RxArray, + uint32_t ui32RxSize, + uint8_t *pui8TxArray, + uint32_t ui32TxSize); +extern void am_hal_uart_get_status_buffered(uint32_t ui32Module, + uint32_t *pui32RxSize, + uint32_t *pui32TxSize); +extern void am_hal_uart_service_buffered(uint32_t ui32Module, + uint32_t ui32Status); + +extern void am_hal_uart_service_buffered_timeout_save(uint32_t ui32Module, + uint32_t ui32Status); +extern void am_hal_uart_char_transmit_buffered(uint32_t ui32Module, + char cChar); +extern void am_hal_uart_string_transmit_buffered(uint32_t ui32Module, + char *pcString); +extern uint32_t am_hal_uart_char_receive_buffered(uint32_t ui32Module, + char *pcString, + uint32_t ui32MaxChars); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_UART_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_vcomp.c b/mcu/apollo2/hal/am_hal_vcomp.c new file mode 100644 index 0000000..dfa8c52 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_vcomp.c @@ -0,0 +1,287 @@ +//***************************************************************************** +// +// am_hal_vcomp.c +//! @file +//! +//! @brief Functions for operating the on-chip Voltage Comparator +//! +//! @addtogroup vcomp2 Voltage Comparator (VCOMP) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Configure the Voltage Comparator module. +//! +//! @param psConfig is a structure containing configuration information for the +//! voltage comparator. +//! +//! This function configures the positive and negative input signals for the +//! voltage comparator. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_config(const am_hal_vcomp_config_t *psConfig) +{ + // + // The configuration word should be a simple OR of the components of the + // configuration structure. + // + AM_REG(VCOMP, CFG) = (psConfig->ui32LevelSelect | + psConfig->ui32PosInput | + psConfig->ui32NegInput); +} + +//***************************************************************************** +// +//! @brief Set the Voltage Comparator DAC Level Select in Configuration Reg. +//! +//! @param ui32Level - DAC voltage selector (use macros enumerations) +//! +//! This function sets the DAC level select in the configuration register. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_dac_level_set(uint32_t ui32Level) +{ + // + // Insert the supplied level into the vcomp configuration register + // + AM_BFW(VCOMP, CFG, LVLSEL, ui32Level >> AM_REG_VCOMP_CFG_LVLSEL_S); +} + +//***************************************************************************** +// +//! @brief Read the state of the voltage comparator. +//! +//! This function extracts the comparator state from the status register. +//! +//! @return the voltage comparator state +// +//***************************************************************************** +bool +am_hal_vcomp_read(void) +{ + return (AM_BFR(VCOMP, STAT, CMPOUT) == 1); +} + +//***************************************************************************** +// +//! @brief Enable the voltage comparator. +//! +//! This function powers up the voltage comparator. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_enable(void) +{ + AM_REG(VCOMP, PWDKEY) = 0; +} + +//***************************************************************************** +// +//! @brief Disable the voltage comparator. +//! +//! This function powers down the voltage comparator. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_disable(void) +{ + AM_REG(VCOMP, PWDKEY) = AM_REG_VCOMP_PWDKEY_KEYVAL; +} + +//***************************************************************************** +// +//! @brief Read the state of the voltage comparator interrupt status bits. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! This function extracts the interrupt status bits and returns the raw or +//! only the enabled based on bEnabledOnly. +//! +//! @return Bitwise representation of the current interrupt status. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_VCOMP_INT_OUTHI +//! AM_HAL_VCOMP_INT_OUTLO +// +//***************************************************************************** +uint32_t +am_hal_vcomp_int_status_get(bool bEnabledOnly) +{ + if (bEnabledOnly) + { + uint32_t u32RetVal = AM_REG(VCOMP, INTSTAT); + return u32RetVal & AM_REG(VCOMP, INTEN); + } + else + { + return AM_REG(VCOMP, INTSTAT); + } +} + +//***************************************************************************** +// +//! @brief Set the state of the voltage comparator interrupt status bits. +//! +//! @param ui32Interrupt - interrupts to be set. +//! +//! This function sets the specified interrupt status bits. +//! +//! ui32Interrupt should be a logical or of: +//! +//! AM_HAL_VCOMP_INT_OUTHI +//! AM_HAL_VCOMP_INT_OUTLO +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_int_set(uint32_t ui32Interrupt) +{ + AM_REG(VCOMP, INTSET) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clear the state of the voltage comparator interrupt status bits. +//! +//! @param ui32Interrupt - interrupts to be cleared. +//! +//! This function clears the specified interrupt status bits. +//! +//! ui32Interrupt should be a logical or of: +//! +//! AM_HAL_VCOMP_INT_OUTHI +//! AM_HAL_VCOMP_INT_OUTLO +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_int_clear(uint32_t ui32Interrupt) +{ + AM_REG(VCOMP, INTCLR) = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Enable the voltage comparator interrupt status bits. +//! +//! @param ui32Interrupt - interrupts to be enabled. +//! +//! This function enables desired interrupt status bits. +//! +//! ui32Interrupt should be a logical or of: +//! +//! AM_HAL_VCOMP_INT_OUTHI +//! AM_HAL_VCOMP_INT_OUTLO +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_int_enable(uint32_t ui32Interrupt) +{ + AM_REG(VCOMP, INTEN) |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled, voltage comparator interrupt status bits. +//! +//! This function returns the enabled interrupt status bits +//! +//! @return returns the enabled interrupt status bits. The return is a logical +//! or of: +//! +//! AM_HAL_VCOMP_INT_OUTHI +//! AM_HAL_VCOMP_INT_OUTLO +// +//***************************************************************************** +uint32_t +am_hal_vcomp_int_enable_get(void) +{ + return AM_REG(VCOMP, INTEN); +} + +//***************************************************************************** +// +//! @brief Disable the voltage comparator interrupt status bits. +//! +//! @param ui32Interrupt - interrupts to be disabled. +//! +//! This function disables desired interrupt status bits. +//! +//! ui32Interrupt should be a logical or of: +//! +//! AM_HAL_VCOMP_INT_OUTHI +//! AM_HAL_VCOMP_INT_OUTLO +//! +//! @return None +// +//***************************************************************************** +void +am_hal_vcomp_int_disable(uint32_t ui32Interrupt) +{ + AM_REG(VCOMP, INTEN) &= ~ui32Interrupt; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_vcomp.h b/mcu/apollo2/hal/am_hal_vcomp.h new file mode 100644 index 0000000..8bd7bee --- /dev/null +++ b/mcu/apollo2/hal/am_hal_vcomp.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// am_hal_vcomp.h +//! @file +//! +//! @brief Functions for operating the on-chip Voltage Comparator +//! +//! @addtogroup vcomp2 Voltage Comparator (VCOMP) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_VCOMP_H +#define AM_HAL_VCOMP_H + +//***************************************************************************** +// +//! @name Positive Input Selection +//! @brief Use these macros to determine the positive input to the comparator. +//! @{ +// +//***************************************************************************** +#define AM_HAL_VCOMP_PSEL_VDDADJ AM_REG_VCOMP_CFG_PSEL_VDDADJ +#define AM_HAL_VCOMP_PSEL_VTEMP AM_REG_VCOMP_CFG_PSEL_VTEMP +#define AM_HAL_VCOMP_PSEL_VEXT1 AM_REG_VCOMP_CFG_PSEL_VEXT1 +#define AM_HAL_VCOMP_PSEL_VEXT2 AM_REG_VCOMP_CFG_PSEL_VEXT2 +//! @} + +//***************************************************************************** +// +//! @name Negative Input Selection +//! @brief Use these macros to determine the negative input to the comparator. +//! @{ +// +//***************************************************************************** +#define AM_HAL_VCOMP_NSEL_VREFEXT1 AM_REG_VCOMP_CFG_NSEL_VREFEXT1 +#define AM_HAL_VCOMP_NSEL_VREFEXT2 AM_REG_VCOMP_CFG_NSEL_VREFEXT2 +#define AM_HAL_VCOMP_NSEL_VREFEXT3 AM_REG_VCOMP_CFG_NSEL_VREFEXT3 +#define AM_HAL_VCOMP_NSEL_DAC_LEVEL AM_REG_VCOMP_CFG_NSEL_DAC +//! @} + +//***************************************************************************** +// +//! @name Negative Input DAC Selectioin +//! @brief Use these macros to determine the NSEL DAC voltage setting +//! @{ +// +//***************************************************************************** +#define AM_HAL_VCOMP_DAC_LVLSEL_0_58V AM_REG_VCOMP_CFG_LVLSEL_0P58V +#define AM_HAL_VCOMP_DAC_LVLSEL_0_77V AM_REG_VCOMP_CFG_LVLSEL_0P77V +#define AM_HAL_VCOMP_DAC_LVLSEL_0_97V AM_REG_VCOMP_CFG_LVLSEL_0P97V +#define AM_HAL_VCOMP_DAC_LVLSEL_1_16V AM_REG_VCOMP_CFG_LVLSEL_1P16V +#define AM_HAL_VCOMP_DAC_LVLSEL_1_35V AM_REG_VCOMP_CFG_LVLSEL_1P35V +#define AM_HAL_VCOMP_DAC_LVLSEL_1_55V AM_REG_VCOMP_CFG_LVLSEL_1P55V +#define AM_HAL_VCOMP_DAC_LVLSEL_1_74V AM_REG_VCOMP_CFG_LVLSEL_1P74V +#define AM_HAL_VCOMP_DAC_LVLSEL_1_93V AM_REG_VCOMP_CFG_LVLSEL_1P93V +#define AM_HAL_VCOMP_DAC_LVLSEL_2_13V AM_REG_VCOMP_CFG_LVLSEL_2P13V +#define AM_HAL_VCOMP_DAC_LVLSEL_2_32V AM_REG_VCOMP_CFG_LVLSEL_2P32V +#define AM_HAL_VCOMP_DAC_LVLSEL_2_51V AM_REG_VCOMP_CFG_LVLSEL_2P51V +#define AM_HAL_VCOMP_DAC_LVLSEL_2_71V AM_REG_VCOMP_CFG_LVLSEL_2P71V +#define AM_HAL_VCOMP_DAC_LVLSEL_2_90V AM_REG_VCOMP_CFG_LVLSEL_2P90V +#define AM_HAL_VCOMP_DAC_LVLSEL_3_09V AM_REG_VCOMP_CFG_LVLSEL_3P09V +#define AM_HAL_VCOMP_DAC_LVLSEL_3_29V AM_REG_VCOMP_CFG_LVLSEL_3P29V +#define AM_HAL_VCOMP_DAC_LVLSEL_3_48V AM_REG_VCOMP_CFG_LVLSEL_3P48V +//! @} + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_VCOMP_INT_OUTHI AM_REG_VCOMP_INTEN_OUTHI_M +#define AM_HAL_VCOMP_INT_OUTLO AM_REG_VCOMP_INTEN_OUTLOW_M +//! @} + +//***************************************************************************** +// +//! @brief Configuration struct +// +//***************************************************************************** +typedef struct +{ + // + //! The DAC level setting + // + uint32_t ui32LevelSelect; + + // + //! The "positive" comparator input channel + //! + //! This channel is usually used as the signal to be monitored. + // + uint32_t ui32PosInput; + + // + //! The "negative" comparator input channel + //! + //! This channel is usually used as the reference signal. + // + uint32_t ui32NegInput; +} +am_hal_vcomp_config_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_vcomp_config(const am_hal_vcomp_config_t *psConfig); +extern void am_hal_vcomp_dac_level_set(uint32_t ui3Level); +extern bool am_hal_vcomp_read(void); +extern void am_hal_vcomp_enable(void); +extern void am_hal_vcomp_disable(void); +extern void am_hal_vcomp_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_vcomp_int_enable_get(void); +extern void am_hal_vcomp_int_disable(uint32_t ui32Interrupt); +extern void am_hal_vcomp_int_clear(uint32_t ui32Interrupt); +extern void am_hal_vcomp_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_vcomp_int_status_get(bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_VCOMP_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_wdt.c b/mcu/apollo2/hal/am_hal_wdt.c new file mode 100644 index 0000000..a47e9d6 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_wdt.c @@ -0,0 +1,484 @@ +//***************************************************************************** +// +// am_hal_wdt.c +//! @file +//! +//! @brief Hardware abstraction layer for the Watchdog Timer module. +//! +//! @addtogroup wdt2 Watchdog Timer (WDT) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Adjacency check +// +// This is related to the timer read workaround. This macro checks to see if +// the two supplied count values are within one "tick" of eachother. It should +// still pass in the event of a timer rollover. The "B" read is assumed to +// follow the "A" read. The macro returns "TRUE" when the adjacent timer reads +// can be used. +// +//***************************************************************************** +#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) + +//***************************************************************************** +// +//! @brief Configure the watchdog timer. +//! +//! @param psConfig - pointer to a configuration structure containing the +//! desired watchdog settings. +//! +//! This function will set the watchdog configuration register based on the +//! user's desired settings listed in the structure referenced by psConfig. If +//! the structure indicates that watchdog interrupts are desired, this function +//! will also set the interrupt enable bit in the configuration register. +//! +//! @note In order to actually receive watchdog interrupt and/or watchdog reset +//! events, the caller will also need to make sure that the watchdog interrupt +//! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in +//! the reset generator module. Otherwise, the watchdog-generated interrupt and +//! reset events will have no effect. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) +{ + uint32_t ui32ConfigVal; + uint16_t ui16IntCount, ui16ResetCount; + bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; + bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; + + // + // Read the desired settings from the psConfig structure. + // + ui16IntCount = psConfig->ui16InterruptCount; + ui16ResetCount = psConfig->ui16ResetCount; + + // + // Write the interrupt and reset count values to a temporary variable. + // + // Accept the passed Config value, but clear the Counts that we are about to set. + ui32ConfigVal = psConfig->ui32Config & ~(AM_REG_WDT_CFG_INTVAL_M | AM_REG_WDT_CFG_RESVAL_M); + ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_INTVAL, ui16IntCount); + ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_RESVAL, ui16ResetCount); + + // + // If interrupts should be enabled, set the appropriate bit in the + // temporary variable. Also, enable the interrupt in INTEN register in the + // watchdog module. + // + if ( bInterruptEnabled ) + { + // + // Enable the watchdog interrupt if the configuration calls for them. + // + AM_REGn(WDT, 0, INTEN) |= AM_REG_WDT_INTEN_WDTINT_M; + } + else + { + // + // Disable the watchdog interrupt if the configuration doesn't call for + // watchdog interrupts. + // + AM_REGn(WDT, 0, INTEN) &= ~AM_REG_WDT_INTEN_WDTINT_M; + } + + // + // If resets should be enabled, set the appropriate bit in the temporary + // variable. + // + if ( bResetEnabled ) + { + // + // Also enable watchdog resets in the reset module. + // + AM_REG(RSTGEN, CFG) |= AM_REG_RSTGEN_CFG_WDREN_M; + } + else + { + // + // Disable watchdog resets in the reset module. + // + AM_REG(RSTGEN, CFG) &= ~AM_REG_RSTGEN_CFG_WDREN_M; + } + + // + // Check for a user specified clock select. If none specified then + // set 128Hz. + // + if ( !(psConfig->ui32Config & AM_REG_WDT_CFG_CLKSEL_M) ) + { + ui32ConfigVal |= AM_REG_WDT_CFG_CLKSEL_128HZ; + } + + // + // Write the saved value to the watchdog configuration register. + // + AM_REGn(WDT, 0, CFG) = ui32ConfigVal; +} // am_hal_wdt_init() + +//***************************************************************************** +// +//! @brief Starts the watchdog timer. +//! +//! Enables the watchdog timer tick using the 'enable' bit in the watchdog +//! configuration register. This function does not perform any locking of the +//! watchdog timer, so it can be disabled or reconfigured later. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_start(void) +{ + // + // Make sure the watchdog timer is in the "reset" state, and then set the + // enable bit to start counting. + // + AM_REGn(WDT, 0, CFG) |= AM_REG_WDT_CFG_WDTEN_M; + AM_REGn(WDT, 0, RSTRT) = AM_REG_WDT_RSTRT_RSTRT_KEYVALUE; + +} // am_hal_wdt_start() + +//***************************************************************************** +// +//! @brief Stops the watchdog timer. +//! +//! Disables the watchdog timer tick by clearing the 'enable' bit in the +//! watchdog configuration register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_halt(void) +{ + // + // Clear the watchdog enable bit. + // + AM_REGn(WDT, 0, CFG) &= ~AM_REG_WDT_CFG_WDTEN_M; +} // am_hal_wdt_halt() + +//***************************************************************************** +// +//! @brief Locks the watchdog configuration and starts the watchdog timer. +//! +//! This function sets the watchdog "lock" register, which prevents software +//! from re-configuring the watchdog. This action will also set the enable bit +//! for the watchdog timer, so it will start counting immediately. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_lock_and_start(void) +{ + // + // Write the 'key' value to the watchdog lock register. + // + AM_REGn(WDT, 0, LOCK) = AM_REG_WDT_LOCK_LOCK_KEYVALUE; +} // am_hal_wdt_lock_and_start() + +//***************************************************************************** +// +//! @brief Read the state of the wdt interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! This function extracts the interrupt status bits and returns the enabled or +//! raw based on bEnabledOnly. +//! +//! @return WDT interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_wdt_int_status_get(bool bEnabledOnly) +{ + if (bEnabledOnly) + { + uint32_t u32RetVal = AM_REG(WDT, INTSTAT); + return u32RetVal & AM_REG(WDT, INTEN); + } + else + { + return AM_REG(WDT, INTSTAT); + } +} // am_hal_wdt_int_status_get() + +//***************************************************************************** +// +//! @brief Set the state of the wdt interrupt status bit. +//! +//! This function sets the interrupt bit. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_set(void) +{ + AM_REG(WDT, INTSET) = AM_REG_WDT_INTSET_WDTINT_M; +} // am_hal_wdt_int_set() + +//***************************************************************************** +// +//! @brief Clear the state of the wdt interrupt status bit. +//! +//! This function clear the interrupt bit. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_clear(void) +{ + AM_REGn(WDT, 0, INTCLR) = AM_REG_WDT_INTCLR_WDTINT_M; +} // am_hal_wdt_int_clear() + +//***************************************************************************** +// +//! @brief Enable the wdt interrupt. +//! +//! This function enable the interrupt. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_enable(void) +{ + AM_REG(WDT, INTEN) |= AM_REG_WDT_INTEN_WDTINT_M; +} // am_hal_wdt_int_enable() + +//***************************************************************************** +// +//! @brief Return the enabled WDT interrupts. +//! +//! This function returns the enabled WDT interrupts. +//! +//! @return enabled WDT interrupts. +// +//***************************************************************************** +uint32_t +am_hal_wdt_int_enable_get(void) +{ + return AM_REG(WDT, INTEN); +} // am_hal_wdt_int_enable_get() + +//***************************************************************************** +// +//! @brief Disable the wdt interrupt. +//! +//! This function disablee the interrupt. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_disable(void) +{ + AM_REG(WDT, INTEN) &= ~AM_REG_WDT_INTEN_WDTINT_M; +} // am_hal_wdt_int_disable() + +//***************************************************************************** +// +// Static function for reading the WDT counter value. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm static uint32_t +back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register) +{ + ldr r2, [r1, #0] // Get TMRn register value + ldr r3, [r1, #0] // Get TMRn register value again + ldr r1, [r1, #0] // Get TMRn register value for a third time + str r2, [r0, #0] // Store register value to variable + str r3, [r0, #4] // Store register value to variable + str r1, [r0, #8] // Store register value to variable + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +static +void +back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register) +{ + // pui32Array[] is a pointer to a 3 word data array provided by the caller. + // pui32Register = address of the timer to be read. + __asm + ( + // Do 3 back-to-back reads of the register + " ldr r1, [%[pui32Register], #0]\n" // Get counter register value + " ldr r3, [%[pui32Register], #0]\n" // Get counter register value again + " ldr r4, [%[pui32Register], #0]\n" // Get counter register value for a third time + " str r1, [%[pui32Array], #0]\n" // Store register value to variable + " str r3, [%[pui32Array], #4]\n" // Store register value to variable + " str r4, [%[pui32Array], #8]\n" // Store register value to variable + " bx lr\n" + : + : [pui32Array] "r" (&pui32Array[0]), + [pui32Register] "r" (&pui32Register[0]) + : "r0", "r1", "r3", "r4" + ); +} +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +static +void +back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register) +{ + // pui32Array[] is a pointer to a 3 word data array provided by the caller. + // pui32Register = address of the timer to be read. + __asm + ( + // Do 3 back-to-back reads of the register + " ldr r2, [r1, #0]\n" // Get counter register value + " ldr r3, [r1, #0]\n" // Get counter register value again + " ldr r1, [r1, #0]\n" // Get counter register value for a third time + " str r2, [r0, #0]\n" // Store register value to variable + " str r3, [r0, #4]\n" // Store register value to variable + " str r1, [r0, #8]\n" // Store register value to variable + " bx lr\n" + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless static uint32_t +back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register) +{ + __asm(" ldr r2, [r1, #0]"); // Get TMRn register value + __asm(" ldr r3, [r1, #0]"); // Get TMRn register value again + __asm(" ldr r1, [r1, #0]"); // Get TMRn register value for a third time + __asm(" str r2, [r0, #0]"); // Store register value to variable + __asm(" str r3, [r0, #4]"); // Store register value to variable + __asm(" str r1, [r0, #8]"); // Store register value to variable + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + + +//***************************************************************************** +// +//! @brief Get the wdt counter value. +//! +//! This function reads the current value of watch dog timer counter register. +//! +//! WARNING caller is responsible for masking interrutps before calling this +//! function. +//! +//! @return None +// +//***************************************************************************** +uint32_t +am_hal_wdt_counter_get(void) +{ + uint32_t ui32Values[3] = {0}; + uint32_t ui32Value; + + // + // First, go read the value from the counter register 3 times + // back to back in assembly language. + // + back2back_read_asm(ui32Values, (uint32_t *)(AM_REG_WDTn(0) + + AM_REG_WDT_COUNT_O)); + + // + // Mask out the COUNT field from the 3 read values. + // + ui32Values[0] = AM_REG_WDT_COUNT_COUNT(ui32Values[0]); + ui32Values[1] = AM_REG_WDT_COUNT_COUNT(ui32Values[1]); + ui32Values[2] = AM_REG_WDT_COUNT_COUNT(ui32Values[2]); + + // + // Now, we'll figure out which of the three values is the correct time. + // + if (ui32Values[0] == ui32Values[1]) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32Value = ui32Values[1]; + } + else + { + // + // If the first two values didn't match, then one of them might be bad. + // If one of the first two values is bad, then the third one should + // always be correct. We'll take the third value as the correct count. + // + ui32Value = ui32Values[2]; + + // + // If all of the statements about the architecture are true, the third + // value should be correct, and it should always be within one count of + // either the first or the second value. + // + // Just in case, we'll check against the previous two values to make + // sure that our final answer was reasonable. If it isn't, we will + // flag it as a "bad read", and fail this assert statement. + // + // This shouldn't ever happen, and it hasn't ever happened in any of + // our tests so far. + // + am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) || + adjacent(ui32Values[0], ui32Values[2])), + "Bad CDT read"); + } + + return ui32Value; +} // am_hal_wdt_counter_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/hal/am_hal_wdt.h b/mcu/apollo2/hal/am_hal_wdt.h new file mode 100644 index 0000000..547bb38 --- /dev/null +++ b/mcu/apollo2/hal/am_hal_wdt.h @@ -0,0 +1,186 @@ +//***************************************************************************** +// +// am_hal_wdt.h +//! @file +//! +//! @brief Hardware abstraction layer for the Watchdog Timer module. +//! +//! @addtogroup wdt2 Watchdog Timer (WDT) +//! @ingroup apollo2hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_HAL_WDT_H +#define AM_HAL_WDT_H + +#include +#include + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @name WDT Clock Divider Selections. +//! @brief Macro definitions for WDT clock frequencies. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to set the +//! clock frequency of the watch dog timer. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_LFRC_CLK_DEFAULT AM_REG_WDT_CFG_CLKSEL_128HZ +#define AM_HAL_WDT_LFRC_CLK_128HZ AM_REG_WDT_CFG_CLKSEL_128HZ +#define AM_HAL_WDT_LFRC_CLK_16HZ AM_REG_WDT_CFG_CLKSEL_16HZ +#define AM_HAL_WDT_LFRC_CLK_1HZ AM_REG_WDT_CFG_CLKSEL_1HZ +#define AM_HAL_WDT_LFRC_CLK_1_16HZ AM_REG_WDT_CFG_CLKSEL_1_16HZ +#define AM_HAL_WDT_LFRC_CLK_OFF AM_REG_WDT_CFG_CLKSEL_OFF +//! @} + +//***************************************************************************** +// +//! @name WDT Enable Reset in the WDT Configuration. +//! @brief Macro definitions for WDT Reset Enable. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to enable +//! the watch dog timer to generate resets to the chip. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_ENABLE_RESET AM_REG_WDT_CFG_RESEN(1) +#define AM_HAL_WDT_DISABLE_RESET AM_REG_WDT_CFG_RESEN(0) +//! @} + +//***************************************************************************** +// +//! @name WDT Enable Interrupt Generation from the WDT Configuration. +//! @brief Macro definitions for WDT Interrupt Enable. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to enable +//! the watch dog timer to generate generate WDT interrupts. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_ENABLE_INTERRUPT AM_REG_WDT_CFG_INTEN(1) +#define AM_HAL_WDT_DISABLE_INTERRUPT AM_REG_WDT_CFG_INTEN(0) +//! @} + +//***************************************************************************** +// +//! @brief Watchdog timer configuration structure. +//! +//! This structure is made to be used with the am_hal_wdt_init() function. It +//! describes the configuration of the watchdog timer. +// +//***************************************************************************** +typedef struct +{ + //! Configuration Values for watchdog timer + //! event is generated. + uint32_t ui32Config; + + //! Number of watchdog timer ticks allowed before a watchdog interrupt + //! event is generated. + uint16_t ui16InterruptCount; + + //! Number of watchdog timer ticks allowed before the watchdog will issue a + //! system reset. + uint16_t ui16ResetCount; + +} +am_hal_wdt_config_t; + + +//***************************************************************************** +// +//! @brief Restarts the watchdog timer ("Pets" the dog) +//! +//! This function restarts the watchdog timer from the beginning, preventing +//! any interrupt or reset even from occuring until the next time the watchdog +//! timer expires. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_wdt_restart() \ + do \ + { \ + AM_REGn(WDT, 0, RSTRT) = AM_REG_WDT_RSTRT_RSTRT_KEYVALUE; \ + (void)AM_REGn(WDT, 0, RSTRT); \ + } \ + while(0) + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig); +extern void am_hal_wdt_start(void); +extern void am_hal_wdt_halt(void); +extern void am_hal_wdt_lock_and_start(void); +extern void am_hal_wdt_int_enable(void); +extern uint32_t am_hal_wdt_int_enable_get(void); +extern void am_hal_wdt_int_disable(void); +extern void am_hal_wdt_int_clear(void); +extern void am_hal_wdt_int_set(void); +extern uint32_t am_hal_wdt_int_status_get(bool bEnabledOnly); +extern uint32_t am_hal_wdt_counter_get(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_WDT_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/mcu/apollo2/regs/am_reg_adc.h b/mcu/apollo2/regs/am_reg_adc.h new file mode 100644 index 0000000..7af6bf0 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_adc.h @@ -0,0 +1,865 @@ +//***************************************************************************** +// +// am_reg_adc.h +//! @file +//! +//! @brief Register macros for the ADC module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_ADC_H +#define AM_REG_ADC_H + +//***************************************************************************** +// +// ADC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_ADC_NUM_MODULES 1 +#define AM_REG_ADCn(n) \ + (REG_ADC_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_ADC_CFG_O 0x00000000 +#define AM_REG_ADC_STAT_O 0x00000004 +#define AM_REG_ADC_SWT_O 0x00000008 +#define AM_REG_ADC_SL0CFG_O 0x0000000C +#define AM_REG_ADC_SL1CFG_O 0x00000010 +#define AM_REG_ADC_SL2CFG_O 0x00000014 +#define AM_REG_ADC_SL3CFG_O 0x00000018 +#define AM_REG_ADC_SL4CFG_O 0x0000001C +#define AM_REG_ADC_SL5CFG_O 0x00000020 +#define AM_REG_ADC_SL6CFG_O 0x00000024 +#define AM_REG_ADC_SL7CFG_O 0x00000028 +#define AM_REG_ADC_WULIM_O 0x0000002C +#define AM_REG_ADC_WLLIM_O 0x00000030 +#define AM_REG_ADC_FIFO_O 0x00000038 +#define AM_REG_ADC_INTEN_O 0x00000200 +#define AM_REG_ADC_INTSTAT_O 0x00000204 +#define AM_REG_ADC_INTCLR_O 0x00000208 +#define AM_REG_ADC_INTSET_O 0x0000020C + +//***************************************************************************** +// +// ADC_INTEN - ADC Interrupt registers: Enable +// +//***************************************************************************** +// Window comparator voltage incursion interrupt. +#define AM_REG_ADC_INTEN_WCINC_S 5 +#define AM_REG_ADC_INTEN_WCINC_M 0x00000020 +#define AM_REG_ADC_INTEN_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_ADC_INTEN_WCINC_WCINCINT 0x00000020 + +// Window comparator voltage excursion interrupt. +#define AM_REG_ADC_INTEN_WCEXC_S 4 +#define AM_REG_ADC_INTEN_WCEXC_M 0x00000010 +#define AM_REG_ADC_INTEN_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_ADC_INTEN_WCEXC_WCEXCINT 0x00000010 + +// FIFO 100 percent full interrupt. +#define AM_REG_ADC_INTEN_FIFOOVR2_S 3 +#define AM_REG_ADC_INTEN_FIFOOVR2_M 0x00000008 +#define AM_REG_ADC_INTEN_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_ADC_INTEN_FIFOOVR2_FIFOFULLINT 0x00000008 + +// FIFO 75 percent full interrupt. +#define AM_REG_ADC_INTEN_FIFOOVR1_S 2 +#define AM_REG_ADC_INTEN_FIFOOVR1_M 0x00000004 +#define AM_REG_ADC_INTEN_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_ADC_INTEN_FIFOOVR1_FIFO75INT 0x00000004 + +// ADC scan complete interrupt. +#define AM_REG_ADC_INTEN_SCNCMP_S 1 +#define AM_REG_ADC_INTEN_SCNCMP_M 0x00000002 +#define AM_REG_ADC_INTEN_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_INTEN_SCNCMP_SCNCMPINT 0x00000002 + +// ADC conversion complete interrupt. +#define AM_REG_ADC_INTEN_CNVCMP_S 0 +#define AM_REG_ADC_INTEN_CNVCMP_M 0x00000001 +#define AM_REG_ADC_INTEN_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_INTEN_CNVCMP_CNVCMPINT 0x00000001 + +//***************************************************************************** +// +// ADC_INTSTAT - ADC Interrupt registers: Status +// +//***************************************************************************** +// Window comparator voltage incursion interrupt. +#define AM_REG_ADC_INTSTAT_WCINC_S 5 +#define AM_REG_ADC_INTSTAT_WCINC_M 0x00000020 +#define AM_REG_ADC_INTSTAT_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_ADC_INTSTAT_WCINC_WCINCINT 0x00000020 + +// Window comparator voltage excursion interrupt. +#define AM_REG_ADC_INTSTAT_WCEXC_S 4 +#define AM_REG_ADC_INTSTAT_WCEXC_M 0x00000010 +#define AM_REG_ADC_INTSTAT_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_ADC_INTSTAT_WCEXC_WCEXCINT 0x00000010 + +// FIFO 100 percent full interrupt. +#define AM_REG_ADC_INTSTAT_FIFOOVR2_S 3 +#define AM_REG_ADC_INTSTAT_FIFOOVR2_M 0x00000008 +#define AM_REG_ADC_INTSTAT_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_ADC_INTSTAT_FIFOOVR2_FIFOFULLINT 0x00000008 + +// FIFO 75 percent full interrupt. +#define AM_REG_ADC_INTSTAT_FIFOOVR1_S 2 +#define AM_REG_ADC_INTSTAT_FIFOOVR1_M 0x00000004 +#define AM_REG_ADC_INTSTAT_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_ADC_INTSTAT_FIFOOVR1_FIFO75INT 0x00000004 + +// ADC scan complete interrupt. +#define AM_REG_ADC_INTSTAT_SCNCMP_S 1 +#define AM_REG_ADC_INTSTAT_SCNCMP_M 0x00000002 +#define AM_REG_ADC_INTSTAT_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_INTSTAT_SCNCMP_SCNCMPINT 0x00000002 + +// ADC conversion complete interrupt. +#define AM_REG_ADC_INTSTAT_CNVCMP_S 0 +#define AM_REG_ADC_INTSTAT_CNVCMP_M 0x00000001 +#define AM_REG_ADC_INTSTAT_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_INTSTAT_CNVCMP_CNVCMPINT 0x00000001 + +//***************************************************************************** +// +// ADC_INTCLR - ADC Interrupt registers: Clear +// +//***************************************************************************** +// Window comparator voltage incursion interrupt. +#define AM_REG_ADC_INTCLR_WCINC_S 5 +#define AM_REG_ADC_INTCLR_WCINC_M 0x00000020 +#define AM_REG_ADC_INTCLR_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_ADC_INTCLR_WCINC_WCINCINT 0x00000020 + +// Window comparator voltage excursion interrupt. +#define AM_REG_ADC_INTCLR_WCEXC_S 4 +#define AM_REG_ADC_INTCLR_WCEXC_M 0x00000010 +#define AM_REG_ADC_INTCLR_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_ADC_INTCLR_WCEXC_WCEXCINT 0x00000010 + +// FIFO 100 percent full interrupt. +#define AM_REG_ADC_INTCLR_FIFOOVR2_S 3 +#define AM_REG_ADC_INTCLR_FIFOOVR2_M 0x00000008 +#define AM_REG_ADC_INTCLR_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_ADC_INTCLR_FIFOOVR2_FIFOFULLINT 0x00000008 + +// FIFO 75 percent full interrupt. +#define AM_REG_ADC_INTCLR_FIFOOVR1_S 2 +#define AM_REG_ADC_INTCLR_FIFOOVR1_M 0x00000004 +#define AM_REG_ADC_INTCLR_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_ADC_INTCLR_FIFOOVR1_FIFO75INT 0x00000004 + +// ADC scan complete interrupt. +#define AM_REG_ADC_INTCLR_SCNCMP_S 1 +#define AM_REG_ADC_INTCLR_SCNCMP_M 0x00000002 +#define AM_REG_ADC_INTCLR_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_INTCLR_SCNCMP_SCNCMPINT 0x00000002 + +// ADC conversion complete interrupt. +#define AM_REG_ADC_INTCLR_CNVCMP_S 0 +#define AM_REG_ADC_INTCLR_CNVCMP_M 0x00000001 +#define AM_REG_ADC_INTCLR_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_INTCLR_CNVCMP_CNVCMPINT 0x00000001 + +//***************************************************************************** +// +// ADC_INTSET - ADC Interrupt registers: Set +// +//***************************************************************************** +// Window comparator voltage incursion interrupt. +#define AM_REG_ADC_INTSET_WCINC_S 5 +#define AM_REG_ADC_INTSET_WCINC_M 0x00000020 +#define AM_REG_ADC_INTSET_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_ADC_INTSET_WCINC_WCINCINT 0x00000020 + +// Window comparator voltage excursion interrupt. +#define AM_REG_ADC_INTSET_WCEXC_S 4 +#define AM_REG_ADC_INTSET_WCEXC_M 0x00000010 +#define AM_REG_ADC_INTSET_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_ADC_INTSET_WCEXC_WCEXCINT 0x00000010 + +// FIFO 100 percent full interrupt. +#define AM_REG_ADC_INTSET_FIFOOVR2_S 3 +#define AM_REG_ADC_INTSET_FIFOOVR2_M 0x00000008 +#define AM_REG_ADC_INTSET_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_ADC_INTSET_FIFOOVR2_FIFOFULLINT 0x00000008 + +// FIFO 75 percent full interrupt. +#define AM_REG_ADC_INTSET_FIFOOVR1_S 2 +#define AM_REG_ADC_INTSET_FIFOOVR1_M 0x00000004 +#define AM_REG_ADC_INTSET_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_ADC_INTSET_FIFOOVR1_FIFO75INT 0x00000004 + +// ADC scan complete interrupt. +#define AM_REG_ADC_INTSET_SCNCMP_S 1 +#define AM_REG_ADC_INTSET_SCNCMP_M 0x00000002 +#define AM_REG_ADC_INTSET_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_INTSET_SCNCMP_SCNCMPINT 0x00000002 + +// ADC conversion complete interrupt. +#define AM_REG_ADC_INTSET_CNVCMP_S 0 +#define AM_REG_ADC_INTSET_CNVCMP_M 0x00000001 +#define AM_REG_ADC_INTSET_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_INTSET_CNVCMP_CNVCMPINT 0x00000001 + +//***************************************************************************** +// +// ADC_CFG - Configuration Register +// +//***************************************************************************** +// Select the source and frequency for the ADC clock. All values not enumerated +// below are undefined. +#define AM_REG_ADC_CFG_CLKSEL_S 24 +#define AM_REG_ADC_CFG_CLKSEL_M 0x03000000 +#define AM_REG_ADC_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x03000000) +#define AM_REG_ADC_CFG_CLKSEL_OFF 0x00000000 +#define AM_REG_ADC_CFG_CLKSEL_HFRC 0x01000000 +#define AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2 0x02000000 + +// This bit selects the ADC trigger polarity for external off chip triggers. +#define AM_REG_ADC_CFG_TRIGPOL_S 19 +#define AM_REG_ADC_CFG_TRIGPOL_M 0x00080000 +#define AM_REG_ADC_CFG_TRIGPOL(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE 0x00000000 +#define AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE 0x00080000 + +// Select the ADC trigger source. +#define AM_REG_ADC_CFG_TRIGSEL_S 16 +#define AM_REG_ADC_CFG_TRIGSEL_M 0x00070000 +#define AM_REG_ADC_CFG_TRIGSEL(n) (((uint32_t)(n) << 16) & 0x00070000) +#define AM_REG_ADC_CFG_TRIGSEL_EXT0 0x00000000 +#define AM_REG_ADC_CFG_TRIGSEL_EXT1 0x00010000 +#define AM_REG_ADC_CFG_TRIGSEL_EXT2 0x00020000 +#define AM_REG_ADC_CFG_TRIGSEL_EXT3 0x00030000 +#define AM_REG_ADC_CFG_TRIGSEL_VCOMP 0x00040000 +#define AM_REG_ADC_CFG_TRIGSEL_SWT 0x00070000 + +// Select the ADC reference voltage. +#define AM_REG_ADC_CFG_REFSEL_S 8 +#define AM_REG_ADC_CFG_REFSEL_M 0x00000300 +#define AM_REG_ADC_CFG_REFSEL(n) (((uint32_t)(n) << 8) & 0x00000300) +#define AM_REG_ADC_CFG_REFSEL_INT2P0 0x00000000 +#define AM_REG_ADC_CFG_REFSEL_INT1P5 0x00000100 +#define AM_REG_ADC_CFG_REFSEL_EXT2P0 0x00000200 +#define AM_REG_ADC_CFG_REFSEL_EXT1P5 0x00000300 + +// Clock mode register +#define AM_REG_ADC_CFG_CKMODE_S 4 +#define AM_REG_ADC_CFG_CKMODE_M 0x00000010 +#define AM_REG_ADC_CFG_CKMODE(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_ADC_CFG_CKMODE_LPCKMODE 0x00000000 +#define AM_REG_ADC_CFG_CKMODE_LLCKMODE 0x00000010 + +// Select power mode to enter between active scans. +#define AM_REG_ADC_CFG_LPMODE_S 3 +#define AM_REG_ADC_CFG_LPMODE_M 0x00000008 +#define AM_REG_ADC_CFG_LPMODE(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_ADC_CFG_LPMODE_MODE0 0x00000000 +#define AM_REG_ADC_CFG_LPMODE_MODE1 0x00000008 + +// This bit enables Repeating Scan Mode. +#define AM_REG_ADC_CFG_RPTEN_S 2 +#define AM_REG_ADC_CFG_RPTEN_M 0x00000004 +#define AM_REG_ADC_CFG_RPTEN(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_ADC_CFG_RPTEN_SINGLE_SCAN 0x00000000 +#define AM_REG_ADC_CFG_RPTEN_REPEATING_SCAN 0x00000004 + +// This bit enables the ADC module. While the ADC is enabled, the ADCCFG and +// SLOT Configuration regsiter settings must remain stable and unchanged. All +// configuration register settings, slot configuration settings and window +// comparison settings should be written prior to setting the ADCEN bit to '1'. +#define AM_REG_ADC_CFG_ADCEN_S 0 +#define AM_REG_ADC_CFG_ADCEN_M 0x00000001 +#define AM_REG_ADC_CFG_ADCEN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_CFG_ADCEN_DIS 0x00000000 +#define AM_REG_ADC_CFG_ADCEN_EN 0x00000001 + +//***************************************************************************** +// +// ADC_STAT - ADC Power Status +// +//***************************************************************************** +// Indicates the power-status of the ADC. +#define AM_REG_ADC_STAT_PWDSTAT_S 0 +#define AM_REG_ADC_STAT_PWDSTAT_M 0x00000001 +#define AM_REG_ADC_STAT_PWDSTAT(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_STAT_PWDSTAT_ON 0x00000000 +#define AM_REG_ADC_STAT_PWDSTAT_POWERED_DOWN 0x00000001 + +//***************************************************************************** +// +// ADC_SWT - Software trigger +// +//***************************************************************************** +// Writing 0x37 to this register generates a software trigger. +#define AM_REG_ADC_SWT_SWT_S 0 +#define AM_REG_ADC_SWT_SWT_M 0x000000FF +#define AM_REG_ADC_SWT_SWT(n) (((uint32_t)(n) << 0) & 0x000000FF) +#define AM_REG_ADC_SWT_SWT_GEN_SW_TRIGGER 0x00000037 + +//***************************************************************************** +// +// ADC_SL0CFG - Slot 0 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL0CFG_ADSEL0_S 24 +#define AM_REG_ADC_SL0CFG_ADSEL0_M 0x07000000 +#define AM_REG_ADC_SL0CFG_ADSEL0(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL0CFG_PRMODE0_S 16 +#define AM_REG_ADC_SL0CFG_PRMODE0_M 0x00030000 +#define AM_REG_ADC_SL0CFG_PRMODE0(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL0CFG_PRMODE0_P14B 0x00000000 +#define AM_REG_ADC_SL0CFG_PRMODE0_P12B 0x00010000 +#define AM_REG_ADC_SL0CFG_PRMODE0_P10B 0x00020000 +#define AM_REG_ADC_SL0CFG_PRMODE0_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL0CFG_CHSEL0_S 8 +#define AM_REG_ADC_SL0CFG_CHSEL0_M 0x00000F00 +#define AM_REG_ADC_SL0CFG_CHSEL0(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL0CFG_CHSEL0_SE0 0x00000000 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE1 0x00000100 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE2 0x00000200 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE3 0x00000300 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE4 0x00000400 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE5 0x00000500 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE6 0x00000600 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE7 0x00000700 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE8 0x00000800 +#define AM_REG_ADC_SL0CFG_CHSEL0_SE9 0x00000900 +#define AM_REG_ADC_SL0CFG_CHSEL0_DF0 0x00000A00 +#define AM_REG_ADC_SL0CFG_CHSEL0_DF1 0x00000B00 +#define AM_REG_ADC_SL0CFG_CHSEL0_TEMP 0x00000C00 +#define AM_REG_ADC_SL0CFG_CHSEL0_BATT 0x00000D00 +#define AM_REG_ADC_SL0CFG_CHSEL0_VSS 0x00000E00 + +// This bit enables the window compare function for slot 0. +#define AM_REG_ADC_SL0CFG_WCEN0_S 1 +#define AM_REG_ADC_SL0CFG_WCEN0_M 0x00000002 +#define AM_REG_ADC_SL0CFG_WCEN0(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL0CFG_WCEN0_WCEN 0x00000002 + +// This bit enables slot 0 for ADC conversions. +#define AM_REG_ADC_SL0CFG_SLEN0_S 0 +#define AM_REG_ADC_SL0CFG_SLEN0_M 0x00000001 +#define AM_REG_ADC_SL0CFG_SLEN0(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL0CFG_SLEN0_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL1CFG - Slot 1 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL1CFG_ADSEL1_S 24 +#define AM_REG_ADC_SL1CFG_ADSEL1_M 0x07000000 +#define AM_REG_ADC_SL1CFG_ADSEL1(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL1CFG_PRMODE1_S 16 +#define AM_REG_ADC_SL1CFG_PRMODE1_M 0x00030000 +#define AM_REG_ADC_SL1CFG_PRMODE1(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL1CFG_PRMODE1_P14B 0x00000000 +#define AM_REG_ADC_SL1CFG_PRMODE1_P12B 0x00010000 +#define AM_REG_ADC_SL1CFG_PRMODE1_P10B 0x00020000 +#define AM_REG_ADC_SL1CFG_PRMODE1_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL1CFG_CHSEL1_S 8 +#define AM_REG_ADC_SL1CFG_CHSEL1_M 0x00000F00 +#define AM_REG_ADC_SL1CFG_CHSEL1(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL1CFG_CHSEL1_SE0 0x00000000 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE1 0x00000100 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE2 0x00000200 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE3 0x00000300 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE4 0x00000400 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE5 0x00000500 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE6 0x00000600 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE7 0x00000700 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE8 0x00000800 +#define AM_REG_ADC_SL1CFG_CHSEL1_SE9 0x00000900 +#define AM_REG_ADC_SL1CFG_CHSEL1_DF0 0x00000A00 +#define AM_REG_ADC_SL1CFG_CHSEL1_DF1 0x00000B00 +#define AM_REG_ADC_SL1CFG_CHSEL1_TEMP 0x00000C00 +#define AM_REG_ADC_SL1CFG_CHSEL1_BATT 0x00000D00 +#define AM_REG_ADC_SL1CFG_CHSEL1_VSS 0x00000E00 + +// This bit enables the window compare function for slot 1. +#define AM_REG_ADC_SL1CFG_WCEN1_S 1 +#define AM_REG_ADC_SL1CFG_WCEN1_M 0x00000002 +#define AM_REG_ADC_SL1CFG_WCEN1(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL1CFG_WCEN1_WCEN 0x00000002 + +// This bit enables slot 1 for ADC conversions. +#define AM_REG_ADC_SL1CFG_SLEN1_S 0 +#define AM_REG_ADC_SL1CFG_SLEN1_M 0x00000001 +#define AM_REG_ADC_SL1CFG_SLEN1(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL1CFG_SLEN1_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL2CFG - Slot 2 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL2CFG_ADSEL2_S 24 +#define AM_REG_ADC_SL2CFG_ADSEL2_M 0x07000000 +#define AM_REG_ADC_SL2CFG_ADSEL2(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL2CFG_PRMODE2_S 16 +#define AM_REG_ADC_SL2CFG_PRMODE2_M 0x00030000 +#define AM_REG_ADC_SL2CFG_PRMODE2(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL2CFG_PRMODE2_P14B 0x00000000 +#define AM_REG_ADC_SL2CFG_PRMODE2_P12B 0x00010000 +#define AM_REG_ADC_SL2CFG_PRMODE2_P10B 0x00020000 +#define AM_REG_ADC_SL2CFG_PRMODE2_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL2CFG_CHSEL2_S 8 +#define AM_REG_ADC_SL2CFG_CHSEL2_M 0x00000F00 +#define AM_REG_ADC_SL2CFG_CHSEL2(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL2CFG_CHSEL2_SE0 0x00000000 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE1 0x00000100 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE2 0x00000200 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE3 0x00000300 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE4 0x00000400 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE5 0x00000500 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE6 0x00000600 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE7 0x00000700 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE8 0x00000800 +#define AM_REG_ADC_SL2CFG_CHSEL2_SE9 0x00000900 +#define AM_REG_ADC_SL2CFG_CHSEL2_DF0 0x00000A00 +#define AM_REG_ADC_SL2CFG_CHSEL2_DF1 0x00000B00 +#define AM_REG_ADC_SL2CFG_CHSEL2_TEMP 0x00000C00 +#define AM_REG_ADC_SL2CFG_CHSEL2_BATT 0x00000D00 +#define AM_REG_ADC_SL2CFG_CHSEL2_VSS 0x00000E00 + +// This bit enables the window compare function for slot 2. +#define AM_REG_ADC_SL2CFG_WCEN2_S 1 +#define AM_REG_ADC_SL2CFG_WCEN2_M 0x00000002 +#define AM_REG_ADC_SL2CFG_WCEN2(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL2CFG_WCEN2_WCEN 0x00000002 + +// This bit enables slot 2 for ADC conversions. +#define AM_REG_ADC_SL2CFG_SLEN2_S 0 +#define AM_REG_ADC_SL2CFG_SLEN2_M 0x00000001 +#define AM_REG_ADC_SL2CFG_SLEN2(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL2CFG_SLEN2_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL3CFG - Slot 3 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL3CFG_ADSEL3_S 24 +#define AM_REG_ADC_SL3CFG_ADSEL3_M 0x07000000 +#define AM_REG_ADC_SL3CFG_ADSEL3(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL3CFG_PRMODE3_S 16 +#define AM_REG_ADC_SL3CFG_PRMODE3_M 0x00030000 +#define AM_REG_ADC_SL3CFG_PRMODE3(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL3CFG_PRMODE3_P14B 0x00000000 +#define AM_REG_ADC_SL3CFG_PRMODE3_P12B 0x00010000 +#define AM_REG_ADC_SL3CFG_PRMODE3_P10B 0x00020000 +#define AM_REG_ADC_SL3CFG_PRMODE3_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL3CFG_CHSEL3_S 8 +#define AM_REG_ADC_SL3CFG_CHSEL3_M 0x00000F00 +#define AM_REG_ADC_SL3CFG_CHSEL3(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL3CFG_CHSEL3_SE0 0x00000000 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE1 0x00000100 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE2 0x00000200 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE3 0x00000300 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE4 0x00000400 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE5 0x00000500 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE6 0x00000600 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE7 0x00000700 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE8 0x00000800 +#define AM_REG_ADC_SL3CFG_CHSEL3_SE9 0x00000900 +#define AM_REG_ADC_SL3CFG_CHSEL3_DF0 0x00000A00 +#define AM_REG_ADC_SL3CFG_CHSEL3_DF1 0x00000B00 +#define AM_REG_ADC_SL3CFG_CHSEL3_TEMP 0x00000C00 +#define AM_REG_ADC_SL3CFG_CHSEL3_BATT 0x00000D00 +#define AM_REG_ADC_SL3CFG_CHSEL3_VSS 0x00000E00 + +// This bit enables the window compare function for slot 3. +#define AM_REG_ADC_SL3CFG_WCEN3_S 1 +#define AM_REG_ADC_SL3CFG_WCEN3_M 0x00000002 +#define AM_REG_ADC_SL3CFG_WCEN3(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL3CFG_WCEN3_WCEN 0x00000002 + +// This bit enables slot 3 for ADC conversions. +#define AM_REG_ADC_SL3CFG_SLEN3_S 0 +#define AM_REG_ADC_SL3CFG_SLEN3_M 0x00000001 +#define AM_REG_ADC_SL3CFG_SLEN3(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL3CFG_SLEN3_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL4CFG - Slot 4 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL4CFG_ADSEL4_S 24 +#define AM_REG_ADC_SL4CFG_ADSEL4_M 0x07000000 +#define AM_REG_ADC_SL4CFG_ADSEL4(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL4CFG_PRMODE4_S 16 +#define AM_REG_ADC_SL4CFG_PRMODE4_M 0x00030000 +#define AM_REG_ADC_SL4CFG_PRMODE4(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL4CFG_PRMODE4_P14B 0x00000000 +#define AM_REG_ADC_SL4CFG_PRMODE4_P12B 0x00010000 +#define AM_REG_ADC_SL4CFG_PRMODE4_P10B 0x00020000 +#define AM_REG_ADC_SL4CFG_PRMODE4_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL4CFG_CHSEL4_S 8 +#define AM_REG_ADC_SL4CFG_CHSEL4_M 0x00000F00 +#define AM_REG_ADC_SL4CFG_CHSEL4(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL4CFG_CHSEL4_SE0 0x00000000 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE1 0x00000100 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE2 0x00000200 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE3 0x00000300 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE4 0x00000400 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE5 0x00000500 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE6 0x00000600 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE7 0x00000700 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE8 0x00000800 +#define AM_REG_ADC_SL4CFG_CHSEL4_SE9 0x00000900 +#define AM_REG_ADC_SL4CFG_CHSEL4_DF0 0x00000A00 +#define AM_REG_ADC_SL4CFG_CHSEL4_DF1 0x00000B00 +#define AM_REG_ADC_SL4CFG_CHSEL4_TEMP 0x00000C00 +#define AM_REG_ADC_SL4CFG_CHSEL4_BATT 0x00000D00 +#define AM_REG_ADC_SL4CFG_CHSEL4_VSS 0x00000E00 + +// This bit enables the window compare function for slot 4. +#define AM_REG_ADC_SL4CFG_WCEN4_S 1 +#define AM_REG_ADC_SL4CFG_WCEN4_M 0x00000002 +#define AM_REG_ADC_SL4CFG_WCEN4(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL4CFG_WCEN4_WCEN 0x00000002 + +// This bit enables slot 4 for ADC conversions. +#define AM_REG_ADC_SL4CFG_SLEN4_S 0 +#define AM_REG_ADC_SL4CFG_SLEN4_M 0x00000001 +#define AM_REG_ADC_SL4CFG_SLEN4(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL4CFG_SLEN4_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL5CFG - Slot 5 Configuration Register +// +//***************************************************************************** +// Select number of measurements to average in the accumulate divide module for +// this slot. +#define AM_REG_ADC_SL5CFG_ADSEL5_S 24 +#define AM_REG_ADC_SL5CFG_ADSEL5_M 0x07000000 +#define AM_REG_ADC_SL5CFG_ADSEL5(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL5CFG_PRMODE5_S 16 +#define AM_REG_ADC_SL5CFG_PRMODE5_M 0x00030000 +#define AM_REG_ADC_SL5CFG_PRMODE5(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL5CFG_PRMODE5_P14B 0x00000000 +#define AM_REG_ADC_SL5CFG_PRMODE5_P12B 0x00010000 +#define AM_REG_ADC_SL5CFG_PRMODE5_P10B 0x00020000 +#define AM_REG_ADC_SL5CFG_PRMODE5_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL5CFG_CHSEL5_S 8 +#define AM_REG_ADC_SL5CFG_CHSEL5_M 0x00000F00 +#define AM_REG_ADC_SL5CFG_CHSEL5(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL5CFG_CHSEL5_SE0 0x00000000 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE1 0x00000100 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE2 0x00000200 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE3 0x00000300 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE4 0x00000400 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE5 0x00000500 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE6 0x00000600 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE7 0x00000700 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE8 0x00000800 +#define AM_REG_ADC_SL5CFG_CHSEL5_SE9 0x00000900 +#define AM_REG_ADC_SL5CFG_CHSEL5_DF0 0x00000A00 +#define AM_REG_ADC_SL5CFG_CHSEL5_DF1 0x00000B00 +#define AM_REG_ADC_SL5CFG_CHSEL5_TEMP 0x00000C00 +#define AM_REG_ADC_SL5CFG_CHSEL5_BATT 0x00000D00 +#define AM_REG_ADC_SL5CFG_CHSEL5_VSS 0x00000E00 + +// This bit enables the window compare function for slot 5. +#define AM_REG_ADC_SL5CFG_WCEN5_S 1 +#define AM_REG_ADC_SL5CFG_WCEN5_M 0x00000002 +#define AM_REG_ADC_SL5CFG_WCEN5(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL5CFG_WCEN5_WCEN 0x00000002 + +// This bit enables slot 5 for ADC conversions. +#define AM_REG_ADC_SL5CFG_SLEN5_S 0 +#define AM_REG_ADC_SL5CFG_SLEN5_M 0x00000001 +#define AM_REG_ADC_SL5CFG_SLEN5(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL5CFG_SLEN5_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL6CFG - Slot 6 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL6CFG_ADSEL6_S 24 +#define AM_REG_ADC_SL6CFG_ADSEL6_M 0x07000000 +#define AM_REG_ADC_SL6CFG_ADSEL6(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL6CFG_PRMODE6_S 16 +#define AM_REG_ADC_SL6CFG_PRMODE6_M 0x00030000 +#define AM_REG_ADC_SL6CFG_PRMODE6(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL6CFG_PRMODE6_P14B 0x00000000 +#define AM_REG_ADC_SL6CFG_PRMODE6_P12B 0x00010000 +#define AM_REG_ADC_SL6CFG_PRMODE6_P10B 0x00020000 +#define AM_REG_ADC_SL6CFG_PRMODE6_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL6CFG_CHSEL6_S 8 +#define AM_REG_ADC_SL6CFG_CHSEL6_M 0x00000F00 +#define AM_REG_ADC_SL6CFG_CHSEL6(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL6CFG_CHSEL6_SE0 0x00000000 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE1 0x00000100 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE2 0x00000200 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE3 0x00000300 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE4 0x00000400 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE5 0x00000500 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE6 0x00000600 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE7 0x00000700 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE8 0x00000800 +#define AM_REG_ADC_SL6CFG_CHSEL6_SE9 0x00000900 +#define AM_REG_ADC_SL6CFG_CHSEL6_DF0 0x00000A00 +#define AM_REG_ADC_SL6CFG_CHSEL6_DF1 0x00000B00 +#define AM_REG_ADC_SL6CFG_CHSEL6_TEMP 0x00000C00 +#define AM_REG_ADC_SL6CFG_CHSEL6_BATT 0x00000D00 +#define AM_REG_ADC_SL6CFG_CHSEL6_VSS 0x00000E00 + +// This bit enables the window compare function for slot 6. +#define AM_REG_ADC_SL6CFG_WCEN6_S 1 +#define AM_REG_ADC_SL6CFG_WCEN6_M 0x00000002 +#define AM_REG_ADC_SL6CFG_WCEN6(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL6CFG_WCEN6_WCEN 0x00000002 + +// This bit enables slot 6 for ADC conversions. +#define AM_REG_ADC_SL6CFG_SLEN6_S 0 +#define AM_REG_ADC_SL6CFG_SLEN6_M 0x00000001 +#define AM_REG_ADC_SL6CFG_SLEN6(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL6CFG_SLEN6_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_SL7CFG - Slot 7 Configuration Register +// +//***************************************************************************** +// Select the number of measurements to average in the accumulate divide module +// for this slot. +#define AM_REG_ADC_SL7CFG_ADSEL7_S 24 +#define AM_REG_ADC_SL7CFG_ADSEL7_M 0x07000000 +#define AM_REG_ADC_SL7CFG_ADSEL7(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_1_MSRMT 0x00000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS 0x01000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS 0x02000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_8_MSRMT 0x03000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS 0x04000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS 0x05000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS 0x06000000 +#define AM_REG_ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS 0x07000000 + +// Set the Precision Mode For Slot. +#define AM_REG_ADC_SL7CFG_PRMODE7_S 16 +#define AM_REG_ADC_SL7CFG_PRMODE7_M 0x00030000 +#define AM_REG_ADC_SL7CFG_PRMODE7(n) (((uint32_t)(n) << 16) & 0x00030000) +#define AM_REG_ADC_SL7CFG_PRMODE7_P14B 0x00000000 +#define AM_REG_ADC_SL7CFG_PRMODE7_P12B 0x00010000 +#define AM_REG_ADC_SL7CFG_PRMODE7_P10B 0x00020000 +#define AM_REG_ADC_SL7CFG_PRMODE7_P8B 0x00030000 + +// Select one of the 14 channel inputs for this slot. +#define AM_REG_ADC_SL7CFG_CHSEL7_S 8 +#define AM_REG_ADC_SL7CFG_CHSEL7_M 0x00000F00 +#define AM_REG_ADC_SL7CFG_CHSEL7(n) (((uint32_t)(n) << 8) & 0x00000F00) +#define AM_REG_ADC_SL7CFG_CHSEL7_SE0 0x00000000 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE1 0x00000100 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE2 0x00000200 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE3 0x00000300 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE4 0x00000400 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE5 0x00000500 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE6 0x00000600 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE7 0x00000700 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE8 0x00000800 +#define AM_REG_ADC_SL7CFG_CHSEL7_SE9 0x00000900 +#define AM_REG_ADC_SL7CFG_CHSEL7_DF0 0x00000A00 +#define AM_REG_ADC_SL7CFG_CHSEL7_DF1 0x00000B00 +#define AM_REG_ADC_SL7CFG_CHSEL7_TEMP 0x00000C00 +#define AM_REG_ADC_SL7CFG_CHSEL7_BATT 0x00000D00 +#define AM_REG_ADC_SL7CFG_CHSEL7_VSS 0x00000E00 + +// This bit enables the window compare function for slot 7. +#define AM_REG_ADC_SL7CFG_WCEN7_S 1 +#define AM_REG_ADC_SL7CFG_WCEN7_M 0x00000002 +#define AM_REG_ADC_SL7CFG_WCEN7(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_ADC_SL7CFG_WCEN7_WCEN 0x00000002 + +// This bit enables slot 7 for ADC conversions. +#define AM_REG_ADC_SL7CFG_SLEN7_S 0 +#define AM_REG_ADC_SL7CFG_SLEN7_M 0x00000001 +#define AM_REG_ADC_SL7CFG_SLEN7(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_ADC_SL7CFG_SLEN7_SLEN 0x00000001 + +//***************************************************************************** +// +// ADC_WULIM - Window Comparator Upper Limits Register +// +//***************************************************************************** +// Sets the upper limit for the wondow comparator. +#define AM_REG_ADC_WULIM_ULIM_S 0 +#define AM_REG_ADC_WULIM_ULIM_M 0x000FFFFF +#define AM_REG_ADC_WULIM_ULIM(n) (((uint32_t)(n) << 0) & 0x000FFFFF) + +//***************************************************************************** +// +// ADC_WLLIM - Window Comparator Lower Limits Register +// +//***************************************************************************** +// Sets the lower limit for the wondow comparator. +#define AM_REG_ADC_WLLIM_LLIM_S 0 +#define AM_REG_ADC_WLLIM_LLIM_M 0x000FFFFF +#define AM_REG_ADC_WLLIM_LLIM(n) (((uint32_t)(n) << 0) & 0x000FFFFF) + +//***************************************************************************** +// +// ADC_FIFO - FIFO Data and Valid Count Register +// +//***************************************************************************** +// RESERVED. +#define AM_REG_ADC_FIFO_RSVD_S 31 +#define AM_REG_ADC_FIFO_RSVD_M 0x80000000 +#define AM_REG_ADC_FIFO_RSVD(n) (((uint32_t)(n) << 31) & 0x80000000) + +// Slot number associated with this FIFO data. +#define AM_REG_ADC_FIFO_SLOTNUM_S 28 +#define AM_REG_ADC_FIFO_SLOTNUM_M 0x70000000 +#define AM_REG_ADC_FIFO_SLOTNUM(n) (((uint32_t)(n) << 28) & 0x70000000) + +// Number of valid entries in the ADC FIFO. +#define AM_REG_ADC_FIFO_COUNT_S 20 +#define AM_REG_ADC_FIFO_COUNT_M 0x0FF00000 +#define AM_REG_ADC_FIFO_COUNT(n) (((uint32_t)(n) << 20) & 0x0FF00000) + +// Oldest data in the FIFO. +#define AM_REG_ADC_FIFO_DATA_S 0 +#define AM_REG_ADC_FIFO_DATA_M 0x000FFFFF +#define AM_REG_ADC_FIFO_DATA(n) (((uint32_t)(n) << 0) & 0x000FFFFF) + +#endif // AM_REG_ADC_H diff --git a/mcu/apollo2/regs/am_reg_base_addresses.h b/mcu/apollo2/regs/am_reg_base_addresses.h new file mode 100644 index 0000000..749c653 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_base_addresses.h @@ -0,0 +1,76 @@ +//***************************************************************************** +// +//! @file am_reg_base_addresses.h +//! +//! @brief Register defines for all module base addresses +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_BASE_ADDRESSES_H +#define AM_REG_BASE_ADDRESSES_H + +#include "stdint.h" + +// ARM standard register space (needed for macros) +#define REG_ITM_BASEADDR (0x00000000UL) +#define REG_JEDEC_BASEADDR (0x00000000UL) +#define REG_NVIC_BASEADDR (0x00000000UL) +#define REG_SYSCTRL_BASEADDR (0x00000000UL) +#define REG_SYSTICK_BASEADDR (0x00000000UL) +#define REG_TPIU_BASEADDR (0x00000000UL) + +// Peripheral register space +#define REG_ADC_BASEADDR (0x50010000UL) +#define REG_CACHECTRL_BASEADDR (0x40018000UL) +#define REG_CLKGEN_BASEADDR (0x40004000UL) +#define REG_CTIMER_BASEADDR (0x40008000UL) +#define REG_GPIO_BASEADDR (0x40010000UL) +#define REG_IOMSTR_BASEADDR (0x50004000UL) +#define REG_IOSLAVE_BASEADDR (0x50000000UL) +#define REG_MCUCTRL_BASEADDR (0x40020000UL) +#define REG_PDM_BASEADDR (0x50011000UL) +#define REG_PWRCTRL_BASEADDR (0x40021000UL) +#define REG_RSTGEN_BASEADDR (0x40000000UL) +#define REG_RTC_BASEADDR (0x40004040UL) +#define REG_UART_BASEADDR (0x4001C000UL) +#define REG_VCOMP_BASEADDR (0x4000C000UL) +#define REG_WDT_BASEADDR (0x40024000UL) + +// SRAM address space +#define SRAM_BASEADDR (0x10000000UL) + +#endif // AM_REG_BASE_ADDRESSES_H diff --git a/mcu/apollo2/regs/am_reg_cachectrl.h b/mcu/apollo2/regs/am_reg_cachectrl.h new file mode 100644 index 0000000..d745f59 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_cachectrl.h @@ -0,0 +1,416 @@ +//***************************************************************************** +// +// am_reg_cachectrl.h +//! @file +//! +//! @brief Register macros for the CACHECTRL module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_CACHECTRL_H +#define AM_REG_CACHECTRL_H + +//***************************************************************************** +// +// CACHECTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CACHECTRL_NUM_MODULES 1 +#define AM_REG_CACHECTRLn(n) \ + (REG_CACHECTRL_BASEADDR + 0x00001000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_CACHECTRL_CACHECFG_O 0x00000000 +#define AM_REG_CACHECTRL_FLASHCFG_O 0x00000004 +#define AM_REG_CACHECTRL_CTRL_O 0x00000008 +#define AM_REG_CACHECTRL_NCR0START_O 0x00000010 +#define AM_REG_CACHECTRL_NCR0END_O 0x00000014 +#define AM_REG_CACHECTRL_NCR1START_O 0x00000018 +#define AM_REG_CACHECTRL_NCR1END_O 0x0000001C +#define AM_REG_CACHECTRL_CACHEMODE_O 0x00000030 +#define AM_REG_CACHECTRL_DMON0_O 0x00000040 +#define AM_REG_CACHECTRL_DMON1_O 0x00000044 +#define AM_REG_CACHECTRL_DMON2_O 0x00000048 +#define AM_REG_CACHECTRL_DMON3_O 0x0000004C +#define AM_REG_CACHECTRL_IMON0_O 0x00000050 +#define AM_REG_CACHECTRL_IMON1_O 0x00000054 +#define AM_REG_CACHECTRL_IMON2_O 0x00000058 +#define AM_REG_CACHECTRL_IMON3_O 0x0000005C + +//***************************************************************************** +// +// CACHECTRL_CACHECFG - Flash Cache Control Register +// +//***************************************************************************** +// Enable Cache Monitoring Stats. Only enable this for debug/performance +// analysis since it will consume additional power. See IMON/DMON registers for +// data. +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_S 24 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M 0x01000000 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Enable clock gating of entire cache data array subsystem. This should be +// enabled for normal operation. +#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_S 20 +#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M 0x00100000 +#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(n) (((uint32_t)(n) << 20) & 0x00100000) + +// Unused. Should be left at default value. +#define AM_REG_CACHECTRL_CACHECFG_SMDLY_S 16 +#define AM_REG_CACHECTRL_CACHECFG_SMDLY_M 0x000F0000 +#define AM_REG_CACHECTRL_CACHECFG_SMDLY(n) (((uint32_t)(n) << 16) & 0x000F0000) + +// Unused. Should be left at default value. +#define AM_REG_CACHECTRL_CACHECFG_DLY_S 12 +#define AM_REG_CACHECTRL_CACHECFG_DLY_M 0x0000F000 +#define AM_REG_CACHECTRL_CACHECFG_DLY(n) (((uint32_t)(n) << 12) & 0x0000F000) + +// Enable LS (light sleep) of cache RAMs. This should not be enabled for normal +// operation. When this bit is set, the cache's RAMS will be put into light +// sleep mode while inactive. NOTE: if the cache is actively used, this may +// have an adverse affect on power since entering/exiting LS mode may consume +// more power than would be saved. +#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_S 11 +#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M 0x00000800 +#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Enable clock gating of individual cache RAMs. This bit should be enabled for +// normal operation for lowest power consumption. +#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_S 10 +#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M 0x00000400 +#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Enable Flash Data Caching. When set to 1, all instruction accesses to flash +// will be cached. +#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_S 9 +#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M 0x00000200 +#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Enable Flash Instruction Caching. When set to 1, all instruction accesses to +// flash will be cached. +#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_S 8 +#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M 0x00000100 +#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Bitfield should always be programmed to 0. +#define AM_REG_CACHECTRL_CACHECFG_SERIAL_S 7 +#define AM_REG_CACHECTRL_CACHECFG_SERIAL_M 0x00000080 +#define AM_REG_CACHECTRL_CACHECFG_SERIAL(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Sets the cache configuration. Only a single configuration of 0x5 is valid. +#define AM_REG_CACHECTRL_CACHECFG_CONFIG_S 4 +#define AM_REG_CACHECTRL_CACHECFG_CONFIG_M 0x00000070 +#define AM_REG_CACHECTRL_CACHECFG_CONFIG(n) (((uint32_t)(n) << 4) & 0x00000070) +#define AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E 0x00000050 + +// Enable Non-cacheable region 1. See the NCR1 registers to set the region +// boundaries and size. +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_S 3 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M 0x00000008 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Enable Non-cacheable region 0. See the NCR0 registers to set the region +// boundaries and size. +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_S 2 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M 0x00000004 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU +// (least recently used). LRR minimizes writes to the TAG SRAM and is +// recommended. +#define AM_REG_CACHECTRL_CACHECFG_LRU_S 1 +#define AM_REG_CACHECTRL_CACHECFG_LRU_M 0x00000002 +#define AM_REG_CACHECTRL_CACHECFG_LRU(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Enables the main flash cache controller logic and enables power to the cache +// RAMs. Instruction and Data caching need to be enabled independently using +// the ICACHE_ENABLE and DCACHE_ENABLE bits. +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_S 0 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE_M 0x00000001 +#define AM_REG_CACHECTRL_CACHECFG_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CACHECTRL_FLASHCFG - Flash Control Register +// +//***************************************************************************** +// Sets read waitstates for flash accesses (in clock cycles). This should be +// left at the default value for normal flash operation. +#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_S 0 +#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_M 0x00000007 +#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(n) (((uint32_t)(n) << 0) & 0x00000007) + +//***************************************************************************** +// +// CACHECTRL_CTRL - Cache Control +// +//***************************************************************************** +// Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will +// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash +// access occurs. Wake from SLM requires ~5us, so this should only be set if +// the flash will not be accessed for reasonably long time. +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE_S 10 +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE_M 0x00000400 +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_ENABLE(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. +// Performing a flash read will also wake the array. +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE_S 9 +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE_M 0x00000200 +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_DISABLE(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Flash Sleep Mode Status. When 1, flash instance 1 is asleep. +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS_S 8 +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS_M 0x00000100 +#define AM_REG_CACHECTRL_CTRL_FLASH1_SLM_STATUS(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will +// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash +// access occurs. Wake from SLM requires ~5us, so this should only be set if +// the flash will not be accessed for reasonably long time. +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE_S 6 +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE_M 0x00000040 +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_ENABLE(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. +// Performing a flash read will also wake the array. +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE_S 5 +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE_M 0x00000020 +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_DISABLE(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Flash Sleep Mode Status. When 1, flash instance 0 is asleep. +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS_S 4 +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS_M 0x00000010 +#define AM_REG_CACHECTRL_CTRL_FLASH0_SLM_STATUS(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Cache Ready Status. A value of 1 indicates the cache is enabled and not +// processing an invalidate operation. +#define AM_REG_CACHECTRL_CTRL_CACHE_READY_S 2 +#define AM_REG_CACHECTRL_CTRL_CACHE_READY_M 0x00000004 +#define AM_REG_CACHECTRL_CTRL_CACHE_READY(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Writing a 1 to this bitfield will reset the cache monitor statistics +// (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling +// the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values +// until the stats are reset by writing this bitfield. +#define AM_REG_CACHECTRL_CTRL_RESET_STAT_S 1 +#define AM_REG_CACHECTRL_CTRL_RESET_STAT_M 0x00000002 +#define AM_REG_CACHECTRL_CTRL_RESET_STAT(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CACHECTRL_CTRL_RESET_STAT_CLEAR 0x00000002 + +// Writing a 1 to this bitfield invalidates the flash cache contents. +#define AM_REG_CACHECTRL_CTRL_INVALIDATE_S 0 +#define AM_REG_CACHECTRL_CTRL_INVALIDATE_M 0x00000001 +#define AM_REG_CACHECTRL_CTRL_INVALIDATE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CACHECTRL_CTRL_INVALIDATE_GO 0x00000001 + +//***************************************************************************** +// +// CACHECTRL_NCR0START - Flash Cache Noncachable Region 0 Start Address. +// +//***************************************************************************** +// Start address for non-cacheable region 0. The physical address of the start +// of this region should be programmed to this register and must be aligned to a +// 16-byte boundary (thus the lower 4 address bits are unused). +#define AM_REG_CACHECTRL_NCR0START_ADDR_S 4 +#define AM_REG_CACHECTRL_NCR0START_ADDR_M 0x000FFFF0 +#define AM_REG_CACHECTRL_NCR0START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) + +//***************************************************************************** +// +// CACHECTRL_NCR0END - Flash Cache Noncachable Region 0 End +// +//***************************************************************************** +// End address for non-cacheable region 0. The physical address of the end of +// this region should be programmed to this register and must be aligned to a +// 16-byte boundary (thus the lower 4 address bits are unused). +#define AM_REG_CACHECTRL_NCR0END_ADDR_S 4 +#define AM_REG_CACHECTRL_NCR0END_ADDR_M 0x000FFFF0 +#define AM_REG_CACHECTRL_NCR0END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) + +//***************************************************************************** +// +// CACHECTRL_NCR1START - Flash Cache Noncachable Region 1 Start +// +//***************************************************************************** +// Start address for non-cacheable region 1. The physical address of the start +// of this region should be programmed to this register and must be aligned to a +// 16-byte boundary (thus the lower 4 address bits are unused). +#define AM_REG_CACHECTRL_NCR1START_ADDR_S 4 +#define AM_REG_CACHECTRL_NCR1START_ADDR_M 0x000FFFF0 +#define AM_REG_CACHECTRL_NCR1START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) + +//***************************************************************************** +// +// CACHECTRL_NCR1END - Flash Cache Noncachable Region 1 End +// +//***************************************************************************** +// End address for non-cacheable region 1. The physical address of the end of +// this region should be programmed to this register and must be aligned to a +// 16-byte boundary (thus the lower 4 address bits are unused). +#define AM_REG_CACHECTRL_NCR1END_ADDR_S 4 +#define AM_REG_CACHECTRL_NCR1END_ADDR_M 0x000FFFF0 +#define AM_REG_CACHECTRL_NCR1END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) + +//***************************************************************************** +// +// CACHECTRL_CACHEMODE - Flash Cache Mode Register. Used to trim +// performance/power. +// +//***************************************************************************** +// Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value +// should be left at zero for optimal performance. +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_S 5 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_M 0x00000020 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Disallow Data RAM reads (from line hits) during lookup read ops. Value +// should be left at zero for optimal performance. +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_S 4 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_M 0x00000010 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should +// be left at zero for optimal performance. +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_S 3 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_M 0x00000008 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Disallow cache data RAM writes on data RAM read cycles. Value should be left +// at zero for optimal performance. +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_S 2 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_M 0x00000004 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Disallow cache data RAM writes on tag RAM read cycles. Value should be left +// at zero for optimal performance. +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_S 1 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_M 0x00000002 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Disallow cache data RAM writes on tag RAM fill cycles. Value should be left +// at zero for optimal performance. +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_S 0 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_M 0x00000001 +#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CACHECTRL_DMON0 - Data Cache Total Accesses +// +//***************************************************************************** +// Total accesses to data cache +#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_S 0 +#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_DMON1 - Data Cache Tag Lookups +// +//***************************************************************************** +// Total tag lookups from data cache +#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_S 0 +#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_DMON2 - Data Cache Hits +// +//***************************************************************************** +// Cache hits from lookup operations +#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_S 0 +#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_DMON3 - Data Cache Line Hits +// +//***************************************************************************** +// Cache hits from line cache +#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_S 0 +#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_IMON0 - Instruction Cache Total Accesses +// +//***************************************************************************** +// Total accesses to Instruction cache +#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_S 0 +#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_IMON1 - Instruction Cache Tag Lookups +// +//***************************************************************************** +// Total tag lookups from Instruction cache +#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_S 0 +#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_IMON2 - Instruction Cache Hits +// +//***************************************************************************** +// Cache hits from lookup operations +#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_S 0 +#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CACHECTRL_IMON3 - Instruction Cache Line Hits +// +//***************************************************************************** +// Cache hits from line cache +#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_S 0 +#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_M 0xFFFFFFFF +#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +#endif // AM_REG_CACHECTRL_H diff --git a/mcu/apollo2/regs/am_reg_clkgen.h b/mcu/apollo2/regs/am_reg_clkgen.h new file mode 100644 index 0000000..48ef552 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_clkgen.h @@ -0,0 +1,491 @@ +//***************************************************************************** +// +// am_reg_clkgen.h +//! @file +//! +//! @brief Register macros for the CLKGEN module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_CLKGEN_H +#define AM_REG_CLKGEN_H + +//***************************************************************************** +// +// CLKGEN +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CLKGEN_NUM_MODULES 1 +#define AM_REG_CLKGENn(n) \ + (REG_CLKGEN_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_CLKGEN_CALXT_O 0x00000000 +#define AM_REG_CLKGEN_CALRC_O 0x00000004 +#define AM_REG_CLKGEN_ACALCTR_O 0x00000008 +#define AM_REG_CLKGEN_OCTRL_O 0x0000000C +#define AM_REG_CLKGEN_CLKOUT_O 0x00000010 +#define AM_REG_CLKGEN_CCTRL_O 0x00000018 +#define AM_REG_CLKGEN_STATUS_O 0x0000001C +#define AM_REG_CLKGEN_HFADJ_O 0x00000020 +#define AM_REG_CLKGEN_CLOCKEN_O 0x00000028 +#define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C +#define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030 +#define AM_REG_CLKGEN_UARTEN_O 0x00000034 +#define AM_REG_CLKGEN_CLKKEY_O 0x00000014 +#define AM_REG_CLKGEN_INTEN_O 0x00000100 +#define AM_REG_CLKGEN_INTSTAT_O 0x00000104 +#define AM_REG_CLKGEN_INTCLR_O 0x00000108 +#define AM_REG_CLKGEN_INTSET_O 0x0000010C + +//***************************************************************************** +// +// Key values. +// +//***************************************************************************** +#define AM_REG_CLKGEN_CLKKEY_KEYVAL 0x00000047 + +//***************************************************************************** +// +// CLKGEN_INTEN - CLKGEN Interrupt Register: Enable +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_CLKGEN_INTEN_ALM_S 3 +#define AM_REG_CLKGEN_INTEN_ALM_M 0x00000008 +#define AM_REG_CLKGEN_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_CLKGEN_INTEN_OF_S 2 +#define AM_REG_CLKGEN_INTEN_OF_M 0x00000004 +#define AM_REG_CLKGEN_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_CLKGEN_INTEN_ACC_S 1 +#define AM_REG_CLKGEN_INTEN_ACC_M 0x00000002 +#define AM_REG_CLKGEN_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_CLKGEN_INTEN_ACF_S 0 +#define AM_REG_CLKGEN_INTEN_ACF_M 0x00000001 +#define AM_REG_CLKGEN_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CLKGEN_INTSTAT - CLKGEN Interrupt Register: Status +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_CLKGEN_INTSTAT_ALM_S 3 +#define AM_REG_CLKGEN_INTSTAT_ALM_M 0x00000008 +#define AM_REG_CLKGEN_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_CLKGEN_INTSTAT_OF_S 2 +#define AM_REG_CLKGEN_INTSTAT_OF_M 0x00000004 +#define AM_REG_CLKGEN_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_CLKGEN_INTSTAT_ACC_S 1 +#define AM_REG_CLKGEN_INTSTAT_ACC_M 0x00000002 +#define AM_REG_CLKGEN_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_CLKGEN_INTSTAT_ACF_S 0 +#define AM_REG_CLKGEN_INTSTAT_ACF_M 0x00000001 +#define AM_REG_CLKGEN_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CLKGEN_INTCLR - CLKGEN Interrupt Register: Clear +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_CLKGEN_INTCLR_ALM_S 3 +#define AM_REG_CLKGEN_INTCLR_ALM_M 0x00000008 +#define AM_REG_CLKGEN_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_CLKGEN_INTCLR_OF_S 2 +#define AM_REG_CLKGEN_INTCLR_OF_M 0x00000004 +#define AM_REG_CLKGEN_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_CLKGEN_INTCLR_ACC_S 1 +#define AM_REG_CLKGEN_INTCLR_ACC_M 0x00000002 +#define AM_REG_CLKGEN_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_CLKGEN_INTCLR_ACF_S 0 +#define AM_REG_CLKGEN_INTCLR_ACF_M 0x00000001 +#define AM_REG_CLKGEN_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CLKGEN_INTSET - CLKGEN Interrupt Register: Set +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_CLKGEN_INTSET_ALM_S 3 +#define AM_REG_CLKGEN_INTSET_ALM_M 0x00000008 +#define AM_REG_CLKGEN_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_CLKGEN_INTSET_OF_S 2 +#define AM_REG_CLKGEN_INTSET_OF_M 0x00000004 +#define AM_REG_CLKGEN_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_CLKGEN_INTSET_ACC_S 1 +#define AM_REG_CLKGEN_INTSET_ACC_M 0x00000002 +#define AM_REG_CLKGEN_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_CLKGEN_INTSET_ACF_S 0 +#define AM_REG_CLKGEN_INTSET_ACF_M 0x00000001 +#define AM_REG_CLKGEN_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CLKGEN_CALXT - XT Oscillator Control +// +//***************************************************************************** +// XT Oscillator calibration value +#define AM_REG_CLKGEN_CALXT_CALXT_S 0 +#define AM_REG_CLKGEN_CALXT_CALXT_M 0x000007FF +#define AM_REG_CLKGEN_CALXT_CALXT(n) (((uint32_t)(n) << 0) & 0x000007FF) + +//***************************************************************************** +// +// CLKGEN_CALRC - RC Oscillator Control +// +//***************************************************************************** +// LFRC Oscillator calibration value +#define AM_REG_CLKGEN_CALRC_CALRC_S 0 +#define AM_REG_CLKGEN_CALRC_CALRC_M 0x0003FFFF +#define AM_REG_CLKGEN_CALRC_CALRC(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// CLKGEN_ACALCTR - Autocalibration Counter +// +//***************************************************************************** +// Autocalibration Counter result. +#define AM_REG_CLKGEN_ACALCTR_ACALCTR_S 0 +#define AM_REG_CLKGEN_ACALCTR_ACALCTR_M 0x00FFFFFF +#define AM_REG_CLKGEN_ACALCTR_ACALCTR(n) (((uint32_t)(n) << 0) & 0x00FFFFFF) + +//***************************************************************************** +// +// CLKGEN_OCTRL - Oscillator Control +// +//***************************************************************************** +// Autocalibration control +#define AM_REG_CLKGEN_OCTRL_ACAL_S 8 +#define AM_REG_CLKGEN_OCTRL_ACAL_M 0x00000700 +#define AM_REG_CLKGEN_OCTRL_ACAL(n) (((uint32_t)(n) << 8) & 0x00000700) +#define AM_REG_CLKGEN_OCTRL_ACAL_DIS 0x00000000 +#define AM_REG_CLKGEN_OCTRL_ACAL_1024SEC 0x00000200 +#define AM_REG_CLKGEN_OCTRL_ACAL_512SEC 0x00000300 +#define AM_REG_CLKGEN_OCTRL_ACAL_XTFREQ 0x00000600 +#define AM_REG_CLKGEN_OCTRL_ACAL_EXTFREQ 0x00000700 + +// Selects the RTC oscillator (1 => LFRC, 0 => XT) +#define AM_REG_CLKGEN_OCTRL_OSEL_S 7 +#define AM_REG_CLKGEN_OCTRL_OSEL_M 0x00000080 +#define AM_REG_CLKGEN_OCTRL_OSEL(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_XT 0x00000000 +#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_LFRC 0x00000080 + +// Oscillator switch on failure function +#define AM_REG_CLKGEN_OCTRL_FOS_S 6 +#define AM_REG_CLKGEN_OCTRL_FOS_M 0x00000040 +#define AM_REG_CLKGEN_OCTRL_FOS(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_CLKGEN_OCTRL_FOS_DIS 0x00000000 +#define AM_REG_CLKGEN_OCTRL_FOS_EN 0x00000040 + +// Stop the LFRC Oscillator to the RTC +#define AM_REG_CLKGEN_OCTRL_STOPRC_S 1 +#define AM_REG_CLKGEN_OCTRL_STOPRC_M 0x00000002 +#define AM_REG_CLKGEN_OCTRL_STOPRC(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CLKGEN_OCTRL_STOPRC_EN 0x00000000 +#define AM_REG_CLKGEN_OCTRL_STOPRC_STOP 0x00000002 + +// Stop the XT Oscillator to the RTC +#define AM_REG_CLKGEN_OCTRL_STOPXT_S 0 +#define AM_REG_CLKGEN_OCTRL_STOPXT_M 0x00000001 +#define AM_REG_CLKGEN_OCTRL_STOPXT(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CLKGEN_OCTRL_STOPXT_EN 0x00000000 +#define AM_REG_CLKGEN_OCTRL_STOPXT_STOP 0x00000001 + +//***************************************************************************** +// +// CLKGEN_CLKOUT - CLKOUT Frequency Select +// +//***************************************************************************** +// Enable the CLKOUT signal +#define AM_REG_CLKGEN_CLKOUT_CKEN_S 7 +#define AM_REG_CLKGEN_CLKOUT_CKEN_M 0x00000080 +#define AM_REG_CLKGEN_CLKOUT_CKEN(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_CLKGEN_CLKOUT_CKEN_DIS 0x00000000 +#define AM_REG_CLKGEN_CLKOUT_CKEN_EN 0x00000080 + +// CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high +// frequencies (such as from HFRC) are selected for CLKOUT. +#define AM_REG_CLKGEN_CLKOUT_CKSEL_S 0 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_M 0x0000003F +#define AM_REG_CLKGEN_CLKOUT_CKSEL(n) (((uint32_t)(n) << 0) & 0x0000003F) +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC 0x00000000 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2 0x00000001 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4 0x00000002 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8 0x00000003 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16 0x00000004 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32 0x00000005 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_1Hz 0x00000010 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M 0x00000016 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT 0x00000017 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz 0x00000018 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC 0x00000019 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 0x0000001A +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 0x0000001B +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 0x0000001C +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 0x0000001D +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 0x0000001E +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 0x0000001F +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 0x00000020 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK 0x00000022 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 0x00000023 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 0x00000024 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 0x00000025 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K 0x00000026 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256 0x00000027 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K 0x00000028 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K 0x00000029 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 0x0000002A +#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 0x0000002B +#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz 0x0000002C +#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K 0x0000002D +#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M 0x0000002E +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K 0x0000002F +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M 0x00000030 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M 0x00000031 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE 0x00000032 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 0x00000033 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE 0x00000035 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 0x00000036 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 0x00000037 +#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE 0x00000039 + +//***************************************************************************** +// +// CLKGEN_CCTRL - HFRC Clock Control +// +//***************************************************************************** +// Core Clock divisor +#define AM_REG_CLKGEN_CCTRL_CORESEL_S 0 +#define AM_REG_CLKGEN_CCTRL_CORESEL_M 0x00000001 +#define AM_REG_CLKGEN_CCTRL_CORESEL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC 0x00000000 +#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2 0x00000001 + +//***************************************************************************** +// +// CLKGEN_STATUS - Clock Generator Status +// +//***************************************************************************** +// XT Oscillator is enabled but not oscillating +#define AM_REG_CLKGEN_STATUS_OSCF_S 1 +#define AM_REG_CLKGEN_STATUS_OSCF_M 0x00000002 +#define AM_REG_CLKGEN_STATUS_OSCF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Current RTC oscillator (1 => LFRC, 0 => XT) +#define AM_REG_CLKGEN_STATUS_OMODE_S 0 +#define AM_REG_CLKGEN_STATUS_OMODE_M 0x00000001 +#define AM_REG_CLKGEN_STATUS_OMODE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CLKGEN_HFADJ - HFRC Adjustment +// +//***************************************************************************** +// Gain control for HFRC adjustment +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_S 21 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_M 0x00E00000 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN(n) (((uint32_t)(n) << 21) & 0x00E00000) +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1 0x00000000 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 0x00200000 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_4 0x00400000 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_8 0x00600000 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_16 0x00800000 +#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_32 0x00A00000 + +// XT warmup period for HFRC adjustment +#define AM_REG_CLKGEN_HFADJ_HFWARMUP_S 20 +#define AM_REG_CLKGEN_HFADJ_HFWARMUP_M 0x00100000 +#define AM_REG_CLKGEN_HFADJ_HFWARMUP(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC 0x00000000 +#define AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC 0x00100000 + +// Target HFRC adjustment value. +#define AM_REG_CLKGEN_HFADJ_HFXTADJ_S 8 +#define AM_REG_CLKGEN_HFADJ_HFXTADJ_M 0x000FFF00 +#define AM_REG_CLKGEN_HFADJ_HFXTADJ(n) (((uint32_t)(n) << 8) & 0x000FFF00) + +// Repeat period for HFRC adjustment +#define AM_REG_CLKGEN_HFADJ_HFADJCK_S 1 +#define AM_REG_CLKGEN_HFADJ_HFADJCK_M 0x0000000E +#define AM_REG_CLKGEN_HFADJ_HFADJCK(n) (((uint32_t)(n) << 1) & 0x0000000E) +#define AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC 0x00000000 +#define AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC 0x00000002 +#define AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC 0x00000004 +#define AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC 0x00000006 +#define AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC 0x00000008 +#define AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC 0x0000000A +#define AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC 0x0000000C +#define AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC 0x0000000E + +// HFRC adjustment control +#define AM_REG_CLKGEN_HFADJ_HFADJEN_S 0 +#define AM_REG_CLKGEN_HFADJ_HFADJEN_M 0x00000001 +#define AM_REG_CLKGEN_HFADJ_HFADJEN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000 +#define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001 + +//***************************************************************************** +// +// CLKGEN_CLOCKEN - Clock Enable Status +// +//***************************************************************************** +// Clock enable status +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_S 0 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_M 0xFFFFFFFF +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_ADC_CLKEN 0x00000001 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER_CLKEN 0x00000002 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0A_CLKEN 0x00000004 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0B_CLKEN 0x00000008 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1A_CLKEN 0x00000010 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1B_CLKEN 0x00000020 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2A_CLKEN 0x00000040 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2B_CLKEN 0x00000080 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3A_CLKEN 0x00000100 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3B_CLKEN 0x00000200 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR0_CLKEN 0x00000400 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR1_CLKEN 0x00000800 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR2_CLKEN 0x00001000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR3_CLKEN 0x00002000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR4_CLKEN 0x00004000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR5_CLKEN 0x00008000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC0_CLKEN 0x00010000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC1_CLKEN 0x00020000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC2_CLKEN 0x00040000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC3_CLKEN 0x00080000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC4_CLKEN 0x00100000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC5_CLKEN 0x00200000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOSLAVE_CLKEN 0x00400000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDM_CLKEN 0x00800000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDMIFC_CLKEN 0x01000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_RSTGEN_CLKEN 0x02000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_SRAM_WIPE_CLKEN 0x04000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CLKEN 0x08000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CNT_CLKEN 0x10000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_TPIU_CLKEN 0x20000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0_HCLK_CLKEN 0x40000000 +#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0HF_CLKEN 0x80000000 + +//***************************************************************************** +// +// CLKGEN_CLOCKEN2 - Clock Enable Status +// +//***************************************************************************** +// Clock enable status 2 +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_S 0 +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_M 0xFFFFFFFF +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1_HCLK_CLKEN 0x00000001 +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1HF_CLKEN 0x00000002 +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_WDT_CLKEN 0x00000004 +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_XT_32KHz_EN 0x40000000 +#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_FRCHFRC 0x80000000 + +//***************************************************************************** +// +// CLKGEN_CLOCKEN3 - Clock Enable Status +// +//***************************************************************************** +// Clock enable status 3 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_S 0 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_M 0xFFFFFFFF +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_xtal_en 0x01000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_hfrc_en 0x02000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFADJEN 0x04000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_en_out 0x08000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_RTC_SOURCE 0x10000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_XTAL_EN 0x20000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_EN 0x40000000 +#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_FLASHCLK_EN 0x80000000 + +//***************************************************************************** +// +// CLKGEN_UARTEN - UART Enable +// +//***************************************************************************** +// UART1 system clock control +#define AM_REG_CLKGEN_UARTEN_UART1EN_S 8 +#define AM_REG_CLKGEN_UARTEN_UART1EN_M 0x00000300 +#define AM_REG_CLKGEN_UARTEN_UART1EN(n) (((uint32_t)(n) << 8) & 0x00000300) +#define AM_REG_CLKGEN_UARTEN_UART1EN_DIS 0x00000000 +#define AM_REG_CLKGEN_UARTEN_UART1EN_EN 0x00000100 +#define AM_REG_CLKGEN_UARTEN_UART1EN_REDUCE_FREQ 0x00000200 +#define AM_REG_CLKGEN_UARTEN_UART1EN_EN_POWER_SAV 0x00000300 + +// UART0 system clock control +#define AM_REG_CLKGEN_UARTEN_UART0EN_S 0 +#define AM_REG_CLKGEN_UARTEN_UART0EN_M 0x00000003 +#define AM_REG_CLKGEN_UARTEN_UART0EN(n) (((uint32_t)(n) << 0) & 0x00000003) +#define AM_REG_CLKGEN_UARTEN_UART0EN_DIS 0x00000000 +#define AM_REG_CLKGEN_UARTEN_UART0EN_EN 0x00000001 +#define AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ 0x00000002 +#define AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV 0x00000003 + +#endif // AM_REG_CLKGEN_H diff --git a/mcu/apollo2/regs/am_reg_ctimer.h b/mcu/apollo2/regs/am_reg_ctimer.h new file mode 100644 index 0000000..7899126 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_ctimer.h @@ -0,0 +1,1916 @@ +//***************************************************************************** +// +// am_reg_ctimer.h +//! @file +//! +//! @brief Register macros for the CTIMER module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_CTIMER_H +#define AM_REG_CTIMER_H + +//***************************************************************************** +// +// CTIMER +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CTIMER_NUM_MODULES 1 +#define AM_REG_CTIMERn(n) \ + (REG_CTIMER_BASEADDR + 0x00000010 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_CTIMER_TMR0_O 0x00000000 +#define AM_REG_CTIMER_CMPRA0_O 0x00000004 +#define AM_REG_CTIMER_CMPRB0_O 0x00000008 +#define AM_REG_CTIMER_CTRL0_O 0x0000000C +#define AM_REG_CTIMER_TMR1_O 0x00000010 +#define AM_REG_CTIMER_CMPRA1_O 0x00000014 +#define AM_REG_CTIMER_CMPRB1_O 0x00000018 +#define AM_REG_CTIMER_CTRL1_O 0x0000001C +#define AM_REG_CTIMER_TMR2_O 0x00000020 +#define AM_REG_CTIMER_CMPRA2_O 0x00000024 +#define AM_REG_CTIMER_CMPRB2_O 0x00000028 +#define AM_REG_CTIMER_CTRL2_O 0x0000002C +#define AM_REG_CTIMER_TMR3_O 0x00000030 +#define AM_REG_CTIMER_CMPRA3_O 0x00000034 +#define AM_REG_CTIMER_CMPRB3_O 0x00000038 +#define AM_REG_CTIMER_CTRL3_O 0x0000003C +#define AM_REG_CTIMER_STCFG_O 0x00000100 +#define AM_REG_CTIMER_STTMR_O 0x00000104 +#define AM_REG_CTIMER_CAPTURE_CONTROL_O 0x00000108 +#define AM_REG_CTIMER_SCMPR0_O 0x00000110 +#define AM_REG_CTIMER_SCMPR1_O 0x00000114 +#define AM_REG_CTIMER_SCMPR2_O 0x00000118 +#define AM_REG_CTIMER_SCMPR3_O 0x0000011C +#define AM_REG_CTIMER_SCMPR4_O 0x00000120 +#define AM_REG_CTIMER_SCMPR5_O 0x00000124 +#define AM_REG_CTIMER_SCMPR6_O 0x00000128 +#define AM_REG_CTIMER_SCMPR7_O 0x0000012C +#define AM_REG_CTIMER_SCAPT0_O 0x000001E0 +#define AM_REG_CTIMER_SCAPT1_O 0x000001E4 +#define AM_REG_CTIMER_SCAPT2_O 0x000001E8 +#define AM_REG_CTIMER_SCAPT3_O 0x000001EC +#define AM_REG_CTIMER_SNVR0_O 0x000001F0 +#define AM_REG_CTIMER_SNVR1_O 0x000001F4 +#define AM_REG_CTIMER_SNVR2_O 0x000001F8 +#define AM_REG_CTIMER_INTEN_O 0x00000200 +#define AM_REG_CTIMER_INTSTAT_O 0x00000204 +#define AM_REG_CTIMER_INTCLR_O 0x00000208 +#define AM_REG_CTIMER_INTSET_O 0x0000020C +#define AM_REG_CTIMER_STMINTEN_O 0x00000300 +#define AM_REG_CTIMER_STMINTSTAT_O 0x00000304 +#define AM_REG_CTIMER_STMINTCLR_O 0x00000308 +#define AM_REG_CTIMER_STMINTSET_O 0x0000030C + +//***************************************************************************** +// +// CTIMER_INTEN - Counter/Timer Interrupts: Enable +// +//***************************************************************************** +// Counter/Timer B3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRB3C1INT_S 15 +#define AM_REG_CTIMER_INTEN_CTMRB3C1INT_M 0x00008000 +#define AM_REG_CTIMER_INTEN_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Counter/Timer A3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRA3C1INT_S 14 +#define AM_REG_CTIMER_INTEN_CTMRA3C1INT_M 0x00004000 +#define AM_REG_CTIMER_INTEN_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) + +// Counter/Timer B2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRB2C1INT_S 13 +#define AM_REG_CTIMER_INTEN_CTMRB2C1INT_M 0x00002000 +#define AM_REG_CTIMER_INTEN_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) + +// Counter/Timer A2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRA2C1INT_S 12 +#define AM_REG_CTIMER_INTEN_CTMRA2C1INT_M 0x00001000 +#define AM_REG_CTIMER_INTEN_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) + +// Counter/Timer B1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRB1C1INT_S 11 +#define AM_REG_CTIMER_INTEN_CTMRB1C1INT_M 0x00000800 +#define AM_REG_CTIMER_INTEN_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Counter/Timer A1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRA1C1INT_S 10 +#define AM_REG_CTIMER_INTEN_CTMRA1C1INT_M 0x00000400 +#define AM_REG_CTIMER_INTEN_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Counter/Timer B0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRB0C1INT_S 9 +#define AM_REG_CTIMER_INTEN_CTMRB0C1INT_M 0x00000200 +#define AM_REG_CTIMER_INTEN_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Counter/Timer A0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTEN_CTMRA0C1INT_S 8 +#define AM_REG_CTIMER_INTEN_CTMRA0C1INT_M 0x00000100 +#define AM_REG_CTIMER_INTEN_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Counter/Timer B3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRB3C0INT_S 7 +#define AM_REG_CTIMER_INTEN_CTMRB3C0INT_M 0x00000080 +#define AM_REG_CTIMER_INTEN_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Counter/Timer A3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRA3C0INT_S 6 +#define AM_REG_CTIMER_INTEN_CTMRA3C0INT_M 0x00000040 +#define AM_REG_CTIMER_INTEN_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Counter/Timer B2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRB2C0INT_S 5 +#define AM_REG_CTIMER_INTEN_CTMRB2C0INT_M 0x00000020 +#define AM_REG_CTIMER_INTEN_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Counter/Timer A2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRA2C0INT_S 4 +#define AM_REG_CTIMER_INTEN_CTMRA2C0INT_M 0x00000010 +#define AM_REG_CTIMER_INTEN_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Counter/Timer B1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRB1C0INT_S 3 +#define AM_REG_CTIMER_INTEN_CTMRB1C0INT_M 0x00000008 +#define AM_REG_CTIMER_INTEN_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Counter/Timer A1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRA1C0INT_S 2 +#define AM_REG_CTIMER_INTEN_CTMRA1C0INT_M 0x00000004 +#define AM_REG_CTIMER_INTEN_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Counter/Timer B0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRB0C0INT_S 1 +#define AM_REG_CTIMER_INTEN_CTMRB0C0INT_M 0x00000002 +#define AM_REG_CTIMER_INTEN_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Counter/Timer A0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTEN_CTMRA0C0INT_S 0 +#define AM_REG_CTIMER_INTEN_CTMRA0C0INT_M 0x00000001 +#define AM_REG_CTIMER_INTEN_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CTIMER_INTSTAT - Counter/Timer Interrupts: Status +// +//***************************************************************************** +// Counter/Timer B3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT_S 15 +#define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT_M 0x00008000 +#define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Counter/Timer A3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT_S 14 +#define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT_M 0x00004000 +#define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) + +// Counter/Timer B2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT_S 13 +#define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT_M 0x00002000 +#define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) + +// Counter/Timer A2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT_S 12 +#define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT_M 0x00001000 +#define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) + +// Counter/Timer B1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT_S 11 +#define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT_M 0x00000800 +#define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Counter/Timer A1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT_S 10 +#define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT_M 0x00000400 +#define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Counter/Timer B0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT_S 9 +#define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT_M 0x00000200 +#define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Counter/Timer A0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT_S 8 +#define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT_M 0x00000100 +#define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Counter/Timer B3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT_S 7 +#define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT_M 0x00000080 +#define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Counter/Timer A3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT_S 6 +#define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT_M 0x00000040 +#define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Counter/Timer B2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT_S 5 +#define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT_M 0x00000020 +#define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Counter/Timer A2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT_S 4 +#define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT_M 0x00000010 +#define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Counter/Timer B1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT_S 3 +#define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT_M 0x00000008 +#define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Counter/Timer A1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT_S 2 +#define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT_M 0x00000004 +#define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Counter/Timer B0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT_S 1 +#define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT_M 0x00000002 +#define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Counter/Timer A0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT_S 0 +#define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT_M 0x00000001 +#define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CTIMER_INTCLR - Counter/Timer Interrupts: Clear +// +//***************************************************************************** +// Counter/Timer B3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRB3C1INT_S 15 +#define AM_REG_CTIMER_INTCLR_CTMRB3C1INT_M 0x00008000 +#define AM_REG_CTIMER_INTCLR_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Counter/Timer A3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRA3C1INT_S 14 +#define AM_REG_CTIMER_INTCLR_CTMRA3C1INT_M 0x00004000 +#define AM_REG_CTIMER_INTCLR_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) + +// Counter/Timer B2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRB2C1INT_S 13 +#define AM_REG_CTIMER_INTCLR_CTMRB2C1INT_M 0x00002000 +#define AM_REG_CTIMER_INTCLR_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) + +// Counter/Timer A2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRA2C1INT_S 12 +#define AM_REG_CTIMER_INTCLR_CTMRA2C1INT_M 0x00001000 +#define AM_REG_CTIMER_INTCLR_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) + +// Counter/Timer B1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRB1C1INT_S 11 +#define AM_REG_CTIMER_INTCLR_CTMRB1C1INT_M 0x00000800 +#define AM_REG_CTIMER_INTCLR_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Counter/Timer A1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRA1C1INT_S 10 +#define AM_REG_CTIMER_INTCLR_CTMRA1C1INT_M 0x00000400 +#define AM_REG_CTIMER_INTCLR_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Counter/Timer B0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRB0C1INT_S 9 +#define AM_REG_CTIMER_INTCLR_CTMRB0C1INT_M 0x00000200 +#define AM_REG_CTIMER_INTCLR_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Counter/Timer A0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTCLR_CTMRA0C1INT_S 8 +#define AM_REG_CTIMER_INTCLR_CTMRA0C1INT_M 0x00000100 +#define AM_REG_CTIMER_INTCLR_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Counter/Timer B3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRB3C0INT_S 7 +#define AM_REG_CTIMER_INTCLR_CTMRB3C0INT_M 0x00000080 +#define AM_REG_CTIMER_INTCLR_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Counter/Timer A3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRA3C0INT_S 6 +#define AM_REG_CTIMER_INTCLR_CTMRA3C0INT_M 0x00000040 +#define AM_REG_CTIMER_INTCLR_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Counter/Timer B2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRB2C0INT_S 5 +#define AM_REG_CTIMER_INTCLR_CTMRB2C0INT_M 0x00000020 +#define AM_REG_CTIMER_INTCLR_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Counter/Timer A2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRA2C0INT_S 4 +#define AM_REG_CTIMER_INTCLR_CTMRA2C0INT_M 0x00000010 +#define AM_REG_CTIMER_INTCLR_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Counter/Timer B1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRB1C0INT_S 3 +#define AM_REG_CTIMER_INTCLR_CTMRB1C0INT_M 0x00000008 +#define AM_REG_CTIMER_INTCLR_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Counter/Timer A1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRA1C0INT_S 2 +#define AM_REG_CTIMER_INTCLR_CTMRA1C0INT_M 0x00000004 +#define AM_REG_CTIMER_INTCLR_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Counter/Timer B0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRB0C0INT_S 1 +#define AM_REG_CTIMER_INTCLR_CTMRB0C0INT_M 0x00000002 +#define AM_REG_CTIMER_INTCLR_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Counter/Timer A0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTCLR_CTMRA0C0INT_S 0 +#define AM_REG_CTIMER_INTCLR_CTMRA0C0INT_M 0x00000001 +#define AM_REG_CTIMER_INTCLR_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CTIMER_INTSET - Counter/Timer Interrupts: Set +// +//***************************************************************************** +// Counter/Timer B3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRB3C1INT_S 15 +#define AM_REG_CTIMER_INTSET_CTMRB3C1INT_M 0x00008000 +#define AM_REG_CTIMER_INTSET_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Counter/Timer A3 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRA3C1INT_S 14 +#define AM_REG_CTIMER_INTSET_CTMRA3C1INT_M 0x00004000 +#define AM_REG_CTIMER_INTSET_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) + +// Counter/Timer B2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRB2C1INT_S 13 +#define AM_REG_CTIMER_INTSET_CTMRB2C1INT_M 0x00002000 +#define AM_REG_CTIMER_INTSET_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) + +// Counter/Timer A2 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRA2C1INT_S 12 +#define AM_REG_CTIMER_INTSET_CTMRA2C1INT_M 0x00001000 +#define AM_REG_CTIMER_INTSET_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) + +// Counter/Timer B1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRB1C1INT_S 11 +#define AM_REG_CTIMER_INTSET_CTMRB1C1INT_M 0x00000800 +#define AM_REG_CTIMER_INTSET_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Counter/Timer A1 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRA1C1INT_S 10 +#define AM_REG_CTIMER_INTSET_CTMRA1C1INT_M 0x00000400 +#define AM_REG_CTIMER_INTSET_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Counter/Timer B0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRB0C1INT_S 9 +#define AM_REG_CTIMER_INTSET_CTMRB0C1INT_M 0x00000200 +#define AM_REG_CTIMER_INTSET_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Counter/Timer A0 interrupt based on COMPR1. +#define AM_REG_CTIMER_INTSET_CTMRA0C1INT_S 8 +#define AM_REG_CTIMER_INTSET_CTMRA0C1INT_M 0x00000100 +#define AM_REG_CTIMER_INTSET_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Counter/Timer B3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRB3C0INT_S 7 +#define AM_REG_CTIMER_INTSET_CTMRB3C0INT_M 0x00000080 +#define AM_REG_CTIMER_INTSET_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Counter/Timer A3 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRA3C0INT_S 6 +#define AM_REG_CTIMER_INTSET_CTMRA3C0INT_M 0x00000040 +#define AM_REG_CTIMER_INTSET_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Counter/Timer B2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRB2C0INT_S 5 +#define AM_REG_CTIMER_INTSET_CTMRB2C0INT_M 0x00000020 +#define AM_REG_CTIMER_INTSET_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Counter/Timer A2 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRA2C0INT_S 4 +#define AM_REG_CTIMER_INTSET_CTMRA2C0INT_M 0x00000010 +#define AM_REG_CTIMER_INTSET_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Counter/Timer B1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRB1C0INT_S 3 +#define AM_REG_CTIMER_INTSET_CTMRB1C0INT_M 0x00000008 +#define AM_REG_CTIMER_INTSET_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Counter/Timer A1 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRA1C0INT_S 2 +#define AM_REG_CTIMER_INTSET_CTMRA1C0INT_M 0x00000004 +#define AM_REG_CTIMER_INTSET_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Counter/Timer B0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRB0C0INT_S 1 +#define AM_REG_CTIMER_INTSET_CTMRB0C0INT_M 0x00000002 +#define AM_REG_CTIMER_INTSET_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Counter/Timer A0 interrupt based on COMPR0. +#define AM_REG_CTIMER_INTSET_CTMRA0C0INT_S 0 +#define AM_REG_CTIMER_INTSET_CTMRA0C0INT_M 0x00000001 +#define AM_REG_CTIMER_INTSET_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// CTIMER_STMINTEN - STIMER Interrupt registers: Enable +// +//***************************************************************************** +// CAPTURE register D has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTEN_CAPTURED_S 12 +#define AM_REG_CTIMER_STMINTEN_CAPTURED_M 0x00001000 +#define AM_REG_CTIMER_STMINTEN_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_STMINTEN_CAPTURED_CAPD_INT 0x00001000 + +// CAPTURE register C has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTEN_CAPTUREC_S 11 +#define AM_REG_CTIMER_STMINTEN_CAPTUREC_M 0x00000800 +#define AM_REG_CTIMER_STMINTEN_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_STMINTEN_CAPTUREC_CAPC_INT 0x00000800 + +// CAPTURE register B has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTEN_CAPTUREB_S 10 +#define AM_REG_CTIMER_STMINTEN_CAPTUREB_M 0x00000400 +#define AM_REG_CTIMER_STMINTEN_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_STMINTEN_CAPTUREB_CAPB_INT 0x00000400 + +// CAPTURE register A has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTEN_CAPTUREA_S 9 +#define AM_REG_CTIMER_STMINTEN_CAPTUREA_M 0x00000200 +#define AM_REG_CTIMER_STMINTEN_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_STMINTEN_CAPTUREA_CAPA_INT 0x00000200 + +// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. +#define AM_REG_CTIMER_STMINTEN_OVERFLOW_S 8 +#define AM_REG_CTIMER_STMINTEN_OVERFLOW_M 0x00000100 +#define AM_REG_CTIMER_STMINTEN_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_CTIMER_STMINTEN_OVERFLOW_OFLOW_INT 0x00000100 + +// COUNTER is greater than or equal to COMPARE register H. +#define AM_REG_CTIMER_STMINTEN_COMPAREH_S 7 +#define AM_REG_CTIMER_STMINTEN_COMPAREH_M 0x00000080 +#define AM_REG_CTIMER_STMINTEN_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_CTIMER_STMINTEN_COMPAREH_COMPARED 0x00000080 + +// COUNTER is greater than or equal to COMPARE register G. +#define AM_REG_CTIMER_STMINTEN_COMPAREG_S 6 +#define AM_REG_CTIMER_STMINTEN_COMPAREG_M 0x00000040 +#define AM_REG_CTIMER_STMINTEN_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_CTIMER_STMINTEN_COMPAREG_COMPARED 0x00000040 + +// COUNTER is greater than or equal to COMPARE register F. +#define AM_REG_CTIMER_STMINTEN_COMPAREF_S 5 +#define AM_REG_CTIMER_STMINTEN_COMPAREF_M 0x00000020 +#define AM_REG_CTIMER_STMINTEN_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_CTIMER_STMINTEN_COMPAREF_COMPARED 0x00000020 + +// COUNTER is greater than or equal to COMPARE register E. +#define AM_REG_CTIMER_STMINTEN_COMPAREE_S 4 +#define AM_REG_CTIMER_STMINTEN_COMPAREE_M 0x00000010 +#define AM_REG_CTIMER_STMINTEN_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_CTIMER_STMINTEN_COMPAREE_COMPARED 0x00000010 + +// COUNTER is greater than or equal to COMPARE register D. +#define AM_REG_CTIMER_STMINTEN_COMPARED_S 3 +#define AM_REG_CTIMER_STMINTEN_COMPARED_M 0x00000008 +#define AM_REG_CTIMER_STMINTEN_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_CTIMER_STMINTEN_COMPARED_COMPARED 0x00000008 + +// COUNTER is greater than or equal to COMPARE register C. +#define AM_REG_CTIMER_STMINTEN_COMPAREC_S 2 +#define AM_REG_CTIMER_STMINTEN_COMPAREC_M 0x00000004 +#define AM_REG_CTIMER_STMINTEN_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_CTIMER_STMINTEN_COMPAREC_COMPARED 0x00000004 + +// COUNTER is greater than or equal to COMPARE register B. +#define AM_REG_CTIMER_STMINTEN_COMPAREB_S 1 +#define AM_REG_CTIMER_STMINTEN_COMPAREB_M 0x00000002 +#define AM_REG_CTIMER_STMINTEN_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CTIMER_STMINTEN_COMPAREB_COMPARED 0x00000002 + +// COUNTER is greater than or equal to COMPARE register A. +#define AM_REG_CTIMER_STMINTEN_COMPAREA_S 0 +#define AM_REG_CTIMER_STMINTEN_COMPAREA_M 0x00000001 +#define AM_REG_CTIMER_STMINTEN_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_STMINTEN_COMPAREA_COMPARED 0x00000001 + +//***************************************************************************** +// +// CTIMER_STMINTSTAT - STIMER Interrupt registers: Status +// +//***************************************************************************** +// CAPTURE register D has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSTAT_CAPTURED_S 12 +#define AM_REG_CTIMER_STMINTSTAT_CAPTURED_M 0x00001000 +#define AM_REG_CTIMER_STMINTSTAT_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_STMINTSTAT_CAPTURED_CAPD_INT 0x00001000 + +// CAPTURE register C has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_S 11 +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_M 0x00000800 +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT 0x00000800 + +// CAPTURE register B has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_S 10 +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_M 0x00000400 +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT 0x00000400 + +// CAPTURE register A has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_S 9 +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_M 0x00000200 +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT 0x00000200 + +// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. +#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_S 8 +#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_M 0x00000100 +#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT 0x00000100 + +// COUNTER is greater than or equal to COMPARE register H. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREH_S 7 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREH_M 0x00000080 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREH_COMPARED 0x00000080 + +// COUNTER is greater than or equal to COMPARE register G. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREG_S 6 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREG_M 0x00000040 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREG_COMPARED 0x00000040 + +// COUNTER is greater than or equal to COMPARE register F. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREF_S 5 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREF_M 0x00000020 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREF_COMPARED 0x00000020 + +// COUNTER is greater than or equal to COMPARE register E. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREE_S 4 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREE_M 0x00000010 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREE_COMPARED 0x00000010 + +// COUNTER is greater than or equal to COMPARE register D. +#define AM_REG_CTIMER_STMINTSTAT_COMPARED_S 3 +#define AM_REG_CTIMER_STMINTSTAT_COMPARED_M 0x00000008 +#define AM_REG_CTIMER_STMINTSTAT_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_CTIMER_STMINTSTAT_COMPARED_COMPARED 0x00000008 + +// COUNTER is greater than or equal to COMPARE register C. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREC_S 2 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREC_M 0x00000004 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREC_COMPARED 0x00000004 + +// COUNTER is greater than or equal to COMPARE register B. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREB_S 1 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREB_M 0x00000002 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREB_COMPARED 0x00000002 + +// COUNTER is greater than or equal to COMPARE register A. +#define AM_REG_CTIMER_STMINTSTAT_COMPAREA_S 0 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREA_M 0x00000001 +#define AM_REG_CTIMER_STMINTSTAT_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_STMINTSTAT_COMPAREA_COMPARED 0x00000001 + +//***************************************************************************** +// +// CTIMER_STMINTCLR - STIMER Interrupt registers: Clear +// +//***************************************************************************** +// CAPTURE register D has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTCLR_CAPTURED_S 12 +#define AM_REG_CTIMER_STMINTCLR_CAPTURED_M 0x00001000 +#define AM_REG_CTIMER_STMINTCLR_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_STMINTCLR_CAPTURED_CAPD_INT 0x00001000 + +// CAPTURE register C has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTCLR_CAPTUREC_S 11 +#define AM_REG_CTIMER_STMINTCLR_CAPTUREC_M 0x00000800 +#define AM_REG_CTIMER_STMINTCLR_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_STMINTCLR_CAPTUREC_CAPC_INT 0x00000800 + +// CAPTURE register B has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTCLR_CAPTUREB_S 10 +#define AM_REG_CTIMER_STMINTCLR_CAPTUREB_M 0x00000400 +#define AM_REG_CTIMER_STMINTCLR_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_STMINTCLR_CAPTUREB_CAPB_INT 0x00000400 + +// CAPTURE register A has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTCLR_CAPTUREA_S 9 +#define AM_REG_CTIMER_STMINTCLR_CAPTUREA_M 0x00000200 +#define AM_REG_CTIMER_STMINTCLR_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_STMINTCLR_CAPTUREA_CAPA_INT 0x00000200 + +// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. +#define AM_REG_CTIMER_STMINTCLR_OVERFLOW_S 8 +#define AM_REG_CTIMER_STMINTCLR_OVERFLOW_M 0x00000100 +#define AM_REG_CTIMER_STMINTCLR_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT 0x00000100 + +// COUNTER is greater than or equal to COMPARE register H. +#define AM_REG_CTIMER_STMINTCLR_COMPAREH_S 7 +#define AM_REG_CTIMER_STMINTCLR_COMPAREH_M 0x00000080 +#define AM_REG_CTIMER_STMINTCLR_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_CTIMER_STMINTCLR_COMPAREH_COMPARED 0x00000080 + +// COUNTER is greater than or equal to COMPARE register G. +#define AM_REG_CTIMER_STMINTCLR_COMPAREG_S 6 +#define AM_REG_CTIMER_STMINTCLR_COMPAREG_M 0x00000040 +#define AM_REG_CTIMER_STMINTCLR_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_CTIMER_STMINTCLR_COMPAREG_COMPARED 0x00000040 + +// COUNTER is greater than or equal to COMPARE register F. +#define AM_REG_CTIMER_STMINTCLR_COMPAREF_S 5 +#define AM_REG_CTIMER_STMINTCLR_COMPAREF_M 0x00000020 +#define AM_REG_CTIMER_STMINTCLR_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_CTIMER_STMINTCLR_COMPAREF_COMPARED 0x00000020 + +// COUNTER is greater than or equal to COMPARE register E. +#define AM_REG_CTIMER_STMINTCLR_COMPAREE_S 4 +#define AM_REG_CTIMER_STMINTCLR_COMPAREE_M 0x00000010 +#define AM_REG_CTIMER_STMINTCLR_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_CTIMER_STMINTCLR_COMPAREE_COMPARED 0x00000010 + +// COUNTER is greater than or equal to COMPARE register D. +#define AM_REG_CTIMER_STMINTCLR_COMPARED_S 3 +#define AM_REG_CTIMER_STMINTCLR_COMPARED_M 0x00000008 +#define AM_REG_CTIMER_STMINTCLR_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_CTIMER_STMINTCLR_COMPARED_COMPARED 0x00000008 + +// COUNTER is greater than or equal to COMPARE register C. +#define AM_REG_CTIMER_STMINTCLR_COMPAREC_S 2 +#define AM_REG_CTIMER_STMINTCLR_COMPAREC_M 0x00000004 +#define AM_REG_CTIMER_STMINTCLR_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_CTIMER_STMINTCLR_COMPAREC_COMPARED 0x00000004 + +// COUNTER is greater than or equal to COMPARE register B. +#define AM_REG_CTIMER_STMINTCLR_COMPAREB_S 1 +#define AM_REG_CTIMER_STMINTCLR_COMPAREB_M 0x00000002 +#define AM_REG_CTIMER_STMINTCLR_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CTIMER_STMINTCLR_COMPAREB_COMPARED 0x00000002 + +// COUNTER is greater than or equal to COMPARE register A. +#define AM_REG_CTIMER_STMINTCLR_COMPAREA_S 0 +#define AM_REG_CTIMER_STMINTCLR_COMPAREA_M 0x00000001 +#define AM_REG_CTIMER_STMINTCLR_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_STMINTCLR_COMPAREA_COMPARED 0x00000001 + +//***************************************************************************** +// +// CTIMER_STMINTSET - STIMER Interrupt registers: Set +// +//***************************************************************************** +// CAPTURE register D has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSET_CAPTURED_S 12 +#define AM_REG_CTIMER_STMINTSET_CAPTURED_M 0x00001000 +#define AM_REG_CTIMER_STMINTSET_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_STMINTSET_CAPTURED_CAPD_INT 0x00001000 + +// CAPTURE register C has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSET_CAPTUREC_S 11 +#define AM_REG_CTIMER_STMINTSET_CAPTUREC_M 0x00000800 +#define AM_REG_CTIMER_STMINTSET_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_STMINTSET_CAPTUREC_CAPC_INT 0x00000800 + +// CAPTURE register B has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSET_CAPTUREB_S 10 +#define AM_REG_CTIMER_STMINTSET_CAPTUREB_M 0x00000400 +#define AM_REG_CTIMER_STMINTSET_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_STMINTSET_CAPTUREB_CAPB_INT 0x00000400 + +// CAPTURE register A has grabbed the value in the counter +#define AM_REG_CTIMER_STMINTSET_CAPTUREA_S 9 +#define AM_REG_CTIMER_STMINTSET_CAPTUREA_M 0x00000200 +#define AM_REG_CTIMER_STMINTSET_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_STMINTSET_CAPTUREA_CAPA_INT 0x00000200 + +// COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. +#define AM_REG_CTIMER_STMINTSET_OVERFLOW_S 8 +#define AM_REG_CTIMER_STMINTSET_OVERFLOW_M 0x00000100 +#define AM_REG_CTIMER_STMINTSET_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_CTIMER_STMINTSET_OVERFLOW_OFLOW_INT 0x00000100 + +// COUNTER is greater than or equal to COMPARE register H. +#define AM_REG_CTIMER_STMINTSET_COMPAREH_S 7 +#define AM_REG_CTIMER_STMINTSET_COMPAREH_M 0x00000080 +#define AM_REG_CTIMER_STMINTSET_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_CTIMER_STMINTSET_COMPAREH_COMPARED 0x00000080 + +// COUNTER is greater than or equal to COMPARE register G. +#define AM_REG_CTIMER_STMINTSET_COMPAREG_S 6 +#define AM_REG_CTIMER_STMINTSET_COMPAREG_M 0x00000040 +#define AM_REG_CTIMER_STMINTSET_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_CTIMER_STMINTSET_COMPAREG_COMPARED 0x00000040 + +// COUNTER is greater than or equal to COMPARE register F. +#define AM_REG_CTIMER_STMINTSET_COMPAREF_S 5 +#define AM_REG_CTIMER_STMINTSET_COMPAREF_M 0x00000020 +#define AM_REG_CTIMER_STMINTSET_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_CTIMER_STMINTSET_COMPAREF_COMPARED 0x00000020 + +// COUNTER is greater than or equal to COMPARE register E. +#define AM_REG_CTIMER_STMINTSET_COMPAREE_S 4 +#define AM_REG_CTIMER_STMINTSET_COMPAREE_M 0x00000010 +#define AM_REG_CTIMER_STMINTSET_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_CTIMER_STMINTSET_COMPAREE_COMPARED 0x00000010 + +// COUNTER is greater than or equal to COMPARE register D. +#define AM_REG_CTIMER_STMINTSET_COMPARED_S 3 +#define AM_REG_CTIMER_STMINTSET_COMPARED_M 0x00000008 +#define AM_REG_CTIMER_STMINTSET_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_CTIMER_STMINTSET_COMPARED_COMPARED 0x00000008 + +// COUNTER is greater than or equal to COMPARE register C. +#define AM_REG_CTIMER_STMINTSET_COMPAREC_S 2 +#define AM_REG_CTIMER_STMINTSET_COMPAREC_M 0x00000004 +#define AM_REG_CTIMER_STMINTSET_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_CTIMER_STMINTSET_COMPAREC_COMPARED 0x00000004 + +// COUNTER is greater than or equal to COMPARE register B. +#define AM_REG_CTIMER_STMINTSET_COMPAREB_S 1 +#define AM_REG_CTIMER_STMINTSET_COMPAREB_M 0x00000002 +#define AM_REG_CTIMER_STMINTSET_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CTIMER_STMINTSET_COMPAREB_COMPARED 0x00000002 + +// COUNTER is greater than or equal to COMPARE register A. +#define AM_REG_CTIMER_STMINTSET_COMPAREA_S 0 +#define AM_REG_CTIMER_STMINTSET_COMPAREA_M 0x00000001 +#define AM_REG_CTIMER_STMINTSET_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_STMINTSET_COMPAREA_COMPARED 0x00000001 + +//***************************************************************************** +// +// CTIMER_TMR0 - Counter/Timer Register +// +//***************************************************************************** +// Counter/Timer B0. +#define AM_REG_CTIMER_TMR0_CTTMRB0_S 16 +#define AM_REG_CTIMER_TMR0_CTTMRB0_M 0xFFFF0000 +#define AM_REG_CTIMER_TMR0_CTTMRB0(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A0. +#define AM_REG_CTIMER_TMR0_CTTMRA0_S 0 +#define AM_REG_CTIMER_TMR0_CTTMRA0_M 0x0000FFFF +#define AM_REG_CTIMER_TMR0_CTTMRA0(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRA0 - Counter/Timer A0 Compare Registers +// +//***************************************************************************** +// Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A. +#define AM_REG_CTIMER_CMPRA0_CMPR1A0_S 16 +#define AM_REG_CTIMER_CMPRA0_CMPR1A0_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRA0_CMPR1A0(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A. +#define AM_REG_CTIMER_CMPRA0_CMPR0A0_S 0 +#define AM_REG_CTIMER_CMPRA0_CMPR0A0_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRA0_CMPR0A0(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRB0 - Counter/Timer B0 Compare Registers +// +//***************************************************************************** +// Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B. +#define AM_REG_CTIMER_CMPRB0_CMPR1B0_S 16 +#define AM_REG_CTIMER_CMPRB0_CMPR1B0_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRB0_CMPR1B0(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B. +#define AM_REG_CTIMER_CMPRB0_CMPR0B0_S 0 +#define AM_REG_CTIMER_CMPRB0_CMPR0B0_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRB0_CMPR0B0(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CTRL0 - Counter/Timer Control +// +//***************************************************************************** +// Counter/Timer A0/B0 Link bit. +#define AM_REG_CTIMER_CTRL0_CTLINK0_S 31 +#define AM_REG_CTIMER_CTRL0_CTLINK0_M 0x80000000 +#define AM_REG_CTIMER_CTRL0_CTLINK0(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS 0x00000000 +#define AM_REG_CTIMER_CTRL0_CTLINK0_32BIT_TIMER 0x80000000 + +// Counter/Timer B0 Output Enable bit. +#define AM_REG_CTIMER_CTRL0_TMRB0PE_S 29 +#define AM_REG_CTIMER_CTRL0_TMRB0PE_M 0x20000000 +#define AM_REG_CTIMER_CTRL0_TMRB0PE(n) (((uint32_t)(n) << 29) & 0x20000000) +#define AM_REG_CTIMER_CTRL0_TMRB0PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0PE_EN 0x20000000 + +// Counter/Timer B0 output polarity. +#define AM_REG_CTIMER_CTRL0_TMRB0POL_S 28 +#define AM_REG_CTIMER_CTRL0_TMRB0POL_M 0x10000000 +#define AM_REG_CTIMER_CTRL0_TMRB0POL(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_CTIMER_CTRL0_TMRB0POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0POL_INVERTED 0x10000000 + +// Counter/Timer B0 Clear bit. +#define AM_REG_CTIMER_CTRL0_TMRB0CLR_S 27 +#define AM_REG_CTIMER_CTRL0_TMRB0CLR_M 0x08000000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLR(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_CTIMER_CTRL0_TMRB0CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLR_CLEAR 0x08000000 + +// Counter/Timer B0 Interrupt Enable bit for COMPR1. +#define AM_REG_CTIMER_CTRL0_TMRB0IE1_S 26 +#define AM_REG_CTIMER_CTRL0_TMRB0IE1_M 0x04000000 +#define AM_REG_CTIMER_CTRL0_TMRB0IE1(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_CTIMER_CTRL0_TMRB0IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0IE1_EN 0x04000000 + +// Counter/Timer B0 Interrupt Enable bit for COMPR0. +#define AM_REG_CTIMER_CTRL0_TMRB0IE0_S 25 +#define AM_REG_CTIMER_CTRL0_TMRB0IE0_M 0x02000000 +#define AM_REG_CTIMER_CTRL0_TMRB0IE0(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_CTIMER_CTRL0_TMRB0IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0IE0_EN 0x02000000 + +// Counter/Timer B0 Function Select. +#define AM_REG_CTIMER_CTRL0_TMRB0FN_S 22 +#define AM_REG_CTIMER_CTRL0_TMRB0FN_M 0x01C00000 +#define AM_REG_CTIMER_CTRL0_TMRB0FN(n) (((uint32_t)(n) << 22) & 0x01C00000) +#define AM_REG_CTIMER_CTRL0_TMRB0FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT 0x00400000 +#define AM_REG_CTIMER_CTRL0_TMRB0FN_PULSE_ONCE 0x00800000 +#define AM_REG_CTIMER_CTRL0_TMRB0FN_PULSE_CONT 0x00C00000 +#define AM_REG_CTIMER_CTRL0_TMRB0FN_CONTINUOUS 0x01000000 + +// Counter/Timer B0 Clock Select. +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_S 17 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_M 0x003E0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 0x00020000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 0x00040000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 0x00060000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 0x00080000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K 0x000A0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT 0x000C0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV2 0x000E0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV16 0x00100000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV256 0x00120000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 0x00140000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 0x00160000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K 0x00180000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC 0x001A0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_RTC_100HZ 0x001C0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_HCLK 0x001E0000 +#define AM_REG_CTIMER_CTRL0_TMRB0CLK_BUCKB 0x00200000 + +// Counter/Timer B0 Enable bit. +#define AM_REG_CTIMER_CTRL0_TMRB0EN_S 16 +#define AM_REG_CTIMER_CTRL0_TMRB0EN_M 0x00010000 +#define AM_REG_CTIMER_CTRL0_TMRB0EN(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_CTIMER_CTRL0_TMRB0EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRB0EN_EN 0x00010000 + +// Counter/Timer A0 Output Enable bit. +#define AM_REG_CTIMER_CTRL0_TMRA0PE_S 13 +#define AM_REG_CTIMER_CTRL0_TMRA0PE_M 0x00002000 +#define AM_REG_CTIMER_CTRL0_TMRA0PE(n) (((uint32_t)(n) << 13) & 0x00002000) +#define AM_REG_CTIMER_CTRL0_TMRA0PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0PE_EN 0x00002000 + +// Counter/Timer A0 output polarity. +#define AM_REG_CTIMER_CTRL0_TMRA0POL_S 12 +#define AM_REG_CTIMER_CTRL0_TMRA0POL_M 0x00001000 +#define AM_REG_CTIMER_CTRL0_TMRA0POL(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_CTRL0_TMRA0POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0POL_INVERTED 0x00001000 + +// Counter/Timer A0 Clear bit. +#define AM_REG_CTIMER_CTRL0_TMRA0CLR_S 11 +#define AM_REG_CTIMER_CTRL0_TMRA0CLR_M 0x00000800 +#define AM_REG_CTIMER_CTRL0_TMRA0CLR(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_CTRL0_TMRA0CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0CLR_CLEAR 0x00000800 + +// Counter/Timer A0 Interrupt Enable bit based on COMPR1. +#define AM_REG_CTIMER_CTRL0_TMRA0IE1_S 10 +#define AM_REG_CTIMER_CTRL0_TMRA0IE1_M 0x00000400 +#define AM_REG_CTIMER_CTRL0_TMRA0IE1(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_CTRL0_TMRA0IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0IE1_EN 0x00000400 + +// Counter/Timer A0 Interrupt Enable bit based on COMPR0. +#define AM_REG_CTIMER_CTRL0_TMRA0IE0_S 9 +#define AM_REG_CTIMER_CTRL0_TMRA0IE0_M 0x00000200 +#define AM_REG_CTIMER_CTRL0_TMRA0IE0(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_CTRL0_TMRA0IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0IE0_EN 0x00000200 + +// Counter/Timer A0 Function Select. +#define AM_REG_CTIMER_CTRL0_TMRA0FN_S 6 +#define AM_REG_CTIMER_CTRL0_TMRA0FN_M 0x000001C0 +#define AM_REG_CTIMER_CTRL0_TMRA0FN(n) (((uint32_t)(n) << 6) & 0x000001C0) +#define AM_REG_CTIMER_CTRL0_TMRA0FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT 0x00000040 +#define AM_REG_CTIMER_CTRL0_TMRA0FN_PULSE_ONCE 0x00000080 +#define AM_REG_CTIMER_CTRL0_TMRA0FN_PULSE_CONT 0x000000C0 +#define AM_REG_CTIMER_CTRL0_TMRA0FN_CONTINUOUS 0x00000100 + +// Counter/Timer A0 Clock Select. +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_S 1 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_M 0x0000003E +#define AM_REG_CTIMER_CTRL0_TMRA0CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 0x00000002 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 0x00000004 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 0x00000006 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 0x00000008 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K 0x0000000A +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT 0x0000000C +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV2 0x0000000E +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV16 0x00000010 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV256 0x00000012 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 0x00000014 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 0x00000016 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K 0x00000018 +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC 0x0000001A +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_RTC_100HZ 0x0000001C +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 0x0000001E +#define AM_REG_CTIMER_CTRL0_TMRA0CLK_BUCKA 0x00000020 + +// Counter/Timer A0 Enable bit. +#define AM_REG_CTIMER_CTRL0_TMRA0EN_S 0 +#define AM_REG_CTIMER_CTRL0_TMRA0EN_M 0x00000001 +#define AM_REG_CTIMER_CTRL0_TMRA0EN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_CTRL0_TMRA0EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL0_TMRA0EN_EN 0x00000001 + +//***************************************************************************** +// +// CTIMER_TMR1 - Counter/Timer Register +// +//***************************************************************************** +// Counter/Timer B1. +#define AM_REG_CTIMER_TMR1_CTTMRB1_S 16 +#define AM_REG_CTIMER_TMR1_CTTMRB1_M 0xFFFF0000 +#define AM_REG_CTIMER_TMR1_CTTMRB1(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A1. +#define AM_REG_CTIMER_TMR1_CTTMRA1_S 0 +#define AM_REG_CTIMER_TMR1_CTTMRA1_M 0x0000FFFF +#define AM_REG_CTIMER_TMR1_CTTMRA1(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRA1 - Counter/Timer A1 Compare Registers +// +//***************************************************************************** +// Counter/Timer A1 Compare Register 1. +#define AM_REG_CTIMER_CMPRA1_CMPR1A1_S 16 +#define AM_REG_CTIMER_CMPRA1_CMPR1A1_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRA1_CMPR1A1(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A1 Compare Register 0. +#define AM_REG_CTIMER_CMPRA1_CMPR0A1_S 0 +#define AM_REG_CTIMER_CMPRA1_CMPR0A1_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRA1_CMPR0A1(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRB1 - Counter/Timer B1 Compare Registers +// +//***************************************************************************** +// Counter/Timer B1 Compare Register 1. +#define AM_REG_CTIMER_CMPRB1_CMPR1B1_S 16 +#define AM_REG_CTIMER_CMPRB1_CMPR1B1_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRB1_CMPR1B1(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer B1 Compare Register 0. +#define AM_REG_CTIMER_CMPRB1_CMPR0B1_S 0 +#define AM_REG_CTIMER_CMPRB1_CMPR0B1_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRB1_CMPR0B1(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CTRL1 - Counter/Timer Control +// +//***************************************************************************** +// Counter/Timer A1/B1 Link bit. +#define AM_REG_CTIMER_CTRL1_CTLINK1_S 31 +#define AM_REG_CTIMER_CTRL1_CTLINK1_M 0x80000000 +#define AM_REG_CTIMER_CTRL1_CTLINK1(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS 0x00000000 +#define AM_REG_CTIMER_CTRL1_CTLINK1_32BIT_TIMER 0x80000000 + +// Counter/Timer B1 Output Enable bit. +#define AM_REG_CTIMER_CTRL1_TMRB1PE_S 29 +#define AM_REG_CTIMER_CTRL1_TMRB1PE_M 0x20000000 +#define AM_REG_CTIMER_CTRL1_TMRB1PE(n) (((uint32_t)(n) << 29) & 0x20000000) +#define AM_REG_CTIMER_CTRL1_TMRB1PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1PE_EN 0x20000000 + +// Counter/Timer B1 output polarity. +#define AM_REG_CTIMER_CTRL1_TMRB1POL_S 28 +#define AM_REG_CTIMER_CTRL1_TMRB1POL_M 0x10000000 +#define AM_REG_CTIMER_CTRL1_TMRB1POL(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_CTIMER_CTRL1_TMRB1POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1POL_INVERTED 0x10000000 + +// Counter/Timer B1 Clear bit. +#define AM_REG_CTIMER_CTRL1_TMRB1CLR_S 27 +#define AM_REG_CTIMER_CTRL1_TMRB1CLR_M 0x08000000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLR(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_CTIMER_CTRL1_TMRB1CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLR_CLEAR 0x08000000 + +// Counter/Timer B1 Interrupt Enable bit for COMPR1. +#define AM_REG_CTIMER_CTRL1_TMRB1IE1_S 26 +#define AM_REG_CTIMER_CTRL1_TMRB1IE1_M 0x04000000 +#define AM_REG_CTIMER_CTRL1_TMRB1IE1(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_CTIMER_CTRL1_TMRB1IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1IE1_EN 0x04000000 + +// Counter/Timer B1 Interrupt Enable bit for COMPR0. +#define AM_REG_CTIMER_CTRL1_TMRB1IE0_S 25 +#define AM_REG_CTIMER_CTRL1_TMRB1IE0_M 0x02000000 +#define AM_REG_CTIMER_CTRL1_TMRB1IE0(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_CTIMER_CTRL1_TMRB1IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1IE0_EN 0x02000000 + +// Counter/Timer B1 Function Select. +#define AM_REG_CTIMER_CTRL1_TMRB1FN_S 22 +#define AM_REG_CTIMER_CTRL1_TMRB1FN_M 0x01C00000 +#define AM_REG_CTIMER_CTRL1_TMRB1FN(n) (((uint32_t)(n) << 22) & 0x01C00000) +#define AM_REG_CTIMER_CTRL1_TMRB1FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT 0x00400000 +#define AM_REG_CTIMER_CTRL1_TMRB1FN_PULSE_ONCE 0x00800000 +#define AM_REG_CTIMER_CTRL1_TMRB1FN_PULSE_CONT 0x00C00000 +#define AM_REG_CTIMER_CTRL1_TMRB1FN_CONTINUOUS 0x01000000 + +// Counter/Timer B1 Clock Select. +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_S 17 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_M 0x003E0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 0x00020000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 0x00040000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 0x00060000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 0x00080000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K 0x000A0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT 0x000C0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV2 0x000E0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV16 0x00100000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV256 0x00120000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 0x00140000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 0x00160000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K 0x00180000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC 0x001A0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_RTC_100HZ 0x001C0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_HCLK 0x001E0000 +#define AM_REG_CTIMER_CTRL1_TMRB1CLK_BUCKB 0x00200000 + +// Counter/Timer B1 Enable bit. +#define AM_REG_CTIMER_CTRL1_TMRB1EN_S 16 +#define AM_REG_CTIMER_CTRL1_TMRB1EN_M 0x00010000 +#define AM_REG_CTIMER_CTRL1_TMRB1EN(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_CTIMER_CTRL1_TMRB1EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRB1EN_EN 0x00010000 + +// Counter/Timer A1 Output Enable bit. +#define AM_REG_CTIMER_CTRL1_TMRA1PE_S 13 +#define AM_REG_CTIMER_CTRL1_TMRA1PE_M 0x00002000 +#define AM_REG_CTIMER_CTRL1_TMRA1PE(n) (((uint32_t)(n) << 13) & 0x00002000) +#define AM_REG_CTIMER_CTRL1_TMRA1PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1PE_EN 0x00002000 + +// Counter/Timer A1 output polarity. +#define AM_REG_CTIMER_CTRL1_TMRA1POL_S 12 +#define AM_REG_CTIMER_CTRL1_TMRA1POL_M 0x00001000 +#define AM_REG_CTIMER_CTRL1_TMRA1POL(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_CTRL1_TMRA1POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1POL_INVERTED 0x00001000 + +// Counter/Timer A1 Clear bit. +#define AM_REG_CTIMER_CTRL1_TMRA1CLR_S 11 +#define AM_REG_CTIMER_CTRL1_TMRA1CLR_M 0x00000800 +#define AM_REG_CTIMER_CTRL1_TMRA1CLR(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_CTRL1_TMRA1CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1CLR_CLEAR 0x00000800 + +// Counter/Timer A1 Interrupt Enable bit based on COMPR1. +#define AM_REG_CTIMER_CTRL1_TMRA1IE1_S 10 +#define AM_REG_CTIMER_CTRL1_TMRA1IE1_M 0x00000400 +#define AM_REG_CTIMER_CTRL1_TMRA1IE1(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_CTRL1_TMRA1IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1IE1_EN 0x00000400 + +// Counter/Timer A1 Interrupt Enable bit based on COMPR0. +#define AM_REG_CTIMER_CTRL1_TMRA1IE0_S 9 +#define AM_REG_CTIMER_CTRL1_TMRA1IE0_M 0x00000200 +#define AM_REG_CTIMER_CTRL1_TMRA1IE0(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_CTRL1_TMRA1IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1IE0_EN 0x00000200 + +// Counter/Timer A1 Function Select. +#define AM_REG_CTIMER_CTRL1_TMRA1FN_S 6 +#define AM_REG_CTIMER_CTRL1_TMRA1FN_M 0x000001C0 +#define AM_REG_CTIMER_CTRL1_TMRA1FN(n) (((uint32_t)(n) << 6) & 0x000001C0) +#define AM_REG_CTIMER_CTRL1_TMRA1FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT 0x00000040 +#define AM_REG_CTIMER_CTRL1_TMRA1FN_PULSE_ONCE 0x00000080 +#define AM_REG_CTIMER_CTRL1_TMRA1FN_PULSE_CONT 0x000000C0 +#define AM_REG_CTIMER_CTRL1_TMRA1FN_CONTINUOUS 0x00000100 + +// Counter/Timer A1 Clock Select. +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_S 1 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_M 0x0000003E +#define AM_REG_CTIMER_CTRL1_TMRA1CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 0x00000002 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 0x00000004 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 0x00000006 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 0x00000008 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K 0x0000000A +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT 0x0000000C +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV2 0x0000000E +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV16 0x00000010 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV256 0x00000012 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 0x00000014 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 0x00000016 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K 0x00000018 +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC 0x0000001A +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_RTC_100HZ 0x0000001C +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_HCLK 0x0000001E +#define AM_REG_CTIMER_CTRL1_TMRA1CLK_BUCKA 0x00000020 + +// Counter/Timer A1 Enable bit. +#define AM_REG_CTIMER_CTRL1_TMRA1EN_S 0 +#define AM_REG_CTIMER_CTRL1_TMRA1EN_M 0x00000001 +#define AM_REG_CTIMER_CTRL1_TMRA1EN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_CTRL1_TMRA1EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL1_TMRA1EN_EN 0x00000001 + +//***************************************************************************** +// +// CTIMER_TMR2 - Counter/Timer Register +// +//***************************************************************************** +// Counter/Timer B2. +#define AM_REG_CTIMER_TMR2_CTTMRB2_S 16 +#define AM_REG_CTIMER_TMR2_CTTMRB2_M 0xFFFF0000 +#define AM_REG_CTIMER_TMR2_CTTMRB2(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A2. +#define AM_REG_CTIMER_TMR2_CTTMRA2_S 0 +#define AM_REG_CTIMER_TMR2_CTTMRA2_M 0x0000FFFF +#define AM_REG_CTIMER_TMR2_CTTMRA2(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRA2 - Counter/Timer A2 Compare Registers +// +//***************************************************************************** +// Counter/Timer A2 Compare Register 1. +#define AM_REG_CTIMER_CMPRA2_CMPR1A2_S 16 +#define AM_REG_CTIMER_CMPRA2_CMPR1A2_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRA2_CMPR1A2(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A2 Compare Register 0. +#define AM_REG_CTIMER_CMPRA2_CMPR0A2_S 0 +#define AM_REG_CTIMER_CMPRA2_CMPR0A2_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRA2_CMPR0A2(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRB2 - Counter/Timer B2 Compare Registers +// +//***************************************************************************** +// Counter/Timer B2 Compare Register 1. +#define AM_REG_CTIMER_CMPRB2_CMPR1B2_S 16 +#define AM_REG_CTIMER_CMPRB2_CMPR1B2_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRB2_CMPR1B2(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer B2 Compare Register 0. +#define AM_REG_CTIMER_CMPRB2_CMPR0B2_S 0 +#define AM_REG_CTIMER_CMPRB2_CMPR0B2_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRB2_CMPR0B2(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CTRL2 - Counter/Timer Control +// +//***************************************************************************** +// Counter/Timer A2/B2 Link bit. +#define AM_REG_CTIMER_CTRL2_CTLINK2_S 31 +#define AM_REG_CTIMER_CTRL2_CTLINK2_M 0x80000000 +#define AM_REG_CTIMER_CTRL2_CTLINK2(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS 0x00000000 +#define AM_REG_CTIMER_CTRL2_CTLINK2_32BIT_TIMER 0x80000000 + +// Counter/Timer B2 Output Enable bit. +#define AM_REG_CTIMER_CTRL2_TMRB2PE_S 29 +#define AM_REG_CTIMER_CTRL2_TMRB2PE_M 0x20000000 +#define AM_REG_CTIMER_CTRL2_TMRB2PE(n) (((uint32_t)(n) << 29) & 0x20000000) +#define AM_REG_CTIMER_CTRL2_TMRB2PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2PE_EN 0x20000000 + +// Counter/Timer B2 output polarity. +#define AM_REG_CTIMER_CTRL2_TMRB2POL_S 28 +#define AM_REG_CTIMER_CTRL2_TMRB2POL_M 0x10000000 +#define AM_REG_CTIMER_CTRL2_TMRB2POL(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_CTIMER_CTRL2_TMRB2POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2POL_INVERTED 0x10000000 + +// Counter/Timer B2 Clear bit. +#define AM_REG_CTIMER_CTRL2_TMRB2CLR_S 27 +#define AM_REG_CTIMER_CTRL2_TMRB2CLR_M 0x08000000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLR(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_CTIMER_CTRL2_TMRB2CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLR_CLEAR 0x08000000 + +// Counter/Timer B2 Interrupt Enable bit for COMPR1. +#define AM_REG_CTIMER_CTRL2_TMRB2IE1_S 26 +#define AM_REG_CTIMER_CTRL2_TMRB2IE1_M 0x04000000 +#define AM_REG_CTIMER_CTRL2_TMRB2IE1(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_CTIMER_CTRL2_TMRB2IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2IE1_EN 0x04000000 + +// Counter/Timer B2 Interrupt Enable bit for COMPR0. +#define AM_REG_CTIMER_CTRL2_TMRB2IE0_S 25 +#define AM_REG_CTIMER_CTRL2_TMRB2IE0_M 0x02000000 +#define AM_REG_CTIMER_CTRL2_TMRB2IE0(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_CTIMER_CTRL2_TMRB2IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2IE0_EN 0x02000000 + +// Counter/Timer B2 Function Select. +#define AM_REG_CTIMER_CTRL2_TMRB2FN_S 22 +#define AM_REG_CTIMER_CTRL2_TMRB2FN_M 0x01C00000 +#define AM_REG_CTIMER_CTRL2_TMRB2FN(n) (((uint32_t)(n) << 22) & 0x01C00000) +#define AM_REG_CTIMER_CTRL2_TMRB2FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT 0x00400000 +#define AM_REG_CTIMER_CTRL2_TMRB2FN_PULSE_ONCE 0x00800000 +#define AM_REG_CTIMER_CTRL2_TMRB2FN_PULSE_CONT 0x00C00000 +#define AM_REG_CTIMER_CTRL2_TMRB2FN_CONTINUOUS 0x01000000 + +// Counter/Timer B2 Clock Select. +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_S 17 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_M 0x003E0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 0x00020000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 0x00040000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 0x00060000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 0x00080000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K 0x000A0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT 0x000C0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV2 0x000E0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV16 0x00100000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV256 0x00120000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 0x00140000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 0x00160000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K 0x00180000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC 0x001A0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_RTC_100HZ 0x001C0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_HCLK 0x001E0000 +#define AM_REG_CTIMER_CTRL2_TMRB2CLK_BUCKA 0x00200000 + +// Counter/Timer B2 Enable bit. +#define AM_REG_CTIMER_CTRL2_TMRB2EN_S 16 +#define AM_REG_CTIMER_CTRL2_TMRB2EN_M 0x00010000 +#define AM_REG_CTIMER_CTRL2_TMRB2EN(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_CTIMER_CTRL2_TMRB2EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRB2EN_EN 0x00010000 + +// Counter/Timer A2 Output Enable bit. +#define AM_REG_CTIMER_CTRL2_TMRA2PE_S 13 +#define AM_REG_CTIMER_CTRL2_TMRA2PE_M 0x00002000 +#define AM_REG_CTIMER_CTRL2_TMRA2PE(n) (((uint32_t)(n) << 13) & 0x00002000) +#define AM_REG_CTIMER_CTRL2_TMRA2PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2PE_EN 0x00002000 + +// Counter/Timer A2 output polarity. +#define AM_REG_CTIMER_CTRL2_TMRA2POL_S 12 +#define AM_REG_CTIMER_CTRL2_TMRA2POL_M 0x00001000 +#define AM_REG_CTIMER_CTRL2_TMRA2POL(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_CTRL2_TMRA2POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2POL_INVERTED 0x00001000 + +// Counter/Timer A2 Clear bit. +#define AM_REG_CTIMER_CTRL2_TMRA2CLR_S 11 +#define AM_REG_CTIMER_CTRL2_TMRA2CLR_M 0x00000800 +#define AM_REG_CTIMER_CTRL2_TMRA2CLR(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_CTRL2_TMRA2CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2CLR_CLEAR 0x00000800 + +// Counter/Timer A2 Interrupt Enable bit based on COMPR1. +#define AM_REG_CTIMER_CTRL2_TMRA2IE1_S 10 +#define AM_REG_CTIMER_CTRL2_TMRA2IE1_M 0x00000400 +#define AM_REG_CTIMER_CTRL2_TMRA2IE1(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_CTRL2_TMRA2IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2IE1_EN 0x00000400 + +// Counter/Timer A2 Interrupt Enable bit based on COMPR0. +#define AM_REG_CTIMER_CTRL2_TMRA2IE0_S 9 +#define AM_REG_CTIMER_CTRL2_TMRA2IE0_M 0x00000200 +#define AM_REG_CTIMER_CTRL2_TMRA2IE0(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_CTRL2_TMRA2IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2IE0_EN 0x00000200 + +// Counter/Timer A2 Function Select. +#define AM_REG_CTIMER_CTRL2_TMRA2FN_S 6 +#define AM_REG_CTIMER_CTRL2_TMRA2FN_M 0x000001C0 +#define AM_REG_CTIMER_CTRL2_TMRA2FN(n) (((uint32_t)(n) << 6) & 0x000001C0) +#define AM_REG_CTIMER_CTRL2_TMRA2FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT 0x00000040 +#define AM_REG_CTIMER_CTRL2_TMRA2FN_PULSE_ONCE 0x00000080 +#define AM_REG_CTIMER_CTRL2_TMRA2FN_PULSE_CONT 0x000000C0 +#define AM_REG_CTIMER_CTRL2_TMRA2FN_CONTINUOUS 0x00000100 + +// Counter/Timer A2 Clock Select. +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_S 1 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_M 0x0000003E +#define AM_REG_CTIMER_CTRL2_TMRA2CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 0x00000002 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 0x00000004 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 0x00000006 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 0x00000008 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K 0x0000000A +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT 0x0000000C +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV2 0x0000000E +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV16 0x00000010 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV256 0x00000012 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 0x00000014 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 0x00000016 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K 0x00000018 +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC 0x0000001A +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_RTC_100HZ 0x0000001C +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_HCLK 0x0000001E +#define AM_REG_CTIMER_CTRL2_TMRA2CLK_BUCKB 0x00000020 + +// Counter/Timer A2 Enable bit. +#define AM_REG_CTIMER_CTRL2_TMRA2EN_S 0 +#define AM_REG_CTIMER_CTRL2_TMRA2EN_M 0x00000001 +#define AM_REG_CTIMER_CTRL2_TMRA2EN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_CTRL2_TMRA2EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL2_TMRA2EN_EN 0x00000001 + +//***************************************************************************** +// +// CTIMER_TMR3 - Counter/Timer Register +// +//***************************************************************************** +// Counter/Timer B3. +#define AM_REG_CTIMER_TMR3_CTTMRB3_S 16 +#define AM_REG_CTIMER_TMR3_CTTMRB3_M 0xFFFF0000 +#define AM_REG_CTIMER_TMR3_CTTMRB3(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A3. +#define AM_REG_CTIMER_TMR3_CTTMRA3_S 0 +#define AM_REG_CTIMER_TMR3_CTTMRA3_M 0x0000FFFF +#define AM_REG_CTIMER_TMR3_CTTMRA3(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRA3 - Counter/Timer A3 Compare Registers +// +//***************************************************************************** +// Counter/Timer A3 Compare Register 1. +#define AM_REG_CTIMER_CMPRA3_CMPR1A3_S 16 +#define AM_REG_CTIMER_CMPRA3_CMPR1A3_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRA3_CMPR1A3(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer A3 Compare Register 0. +#define AM_REG_CTIMER_CMPRA3_CMPR0A3_S 0 +#define AM_REG_CTIMER_CMPRA3_CMPR0A3_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRA3_CMPR0A3(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CMPRB3 - Counter/Timer B3 Compare Registers +// +//***************************************************************************** +// Counter/Timer B3 Compare Register 1. +#define AM_REG_CTIMER_CMPRB3_CMPR1B3_S 16 +#define AM_REG_CTIMER_CMPRB3_CMPR1B3_M 0xFFFF0000 +#define AM_REG_CTIMER_CMPRB3_CMPR1B3(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Counter/Timer B3 Compare Register 0. +#define AM_REG_CTIMER_CMPRB3_CMPR0B3_S 0 +#define AM_REG_CTIMER_CMPRB3_CMPR0B3_M 0x0000FFFF +#define AM_REG_CTIMER_CMPRB3_CMPR0B3(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// CTIMER_CTRL3 - Counter/Timer Control +// +//***************************************************************************** +// Counter/Timer A3/B3 Link bit. +#define AM_REG_CTIMER_CTRL3_CTLINK3_S 31 +#define AM_REG_CTIMER_CTRL3_CTLINK3_M 0x80000000 +#define AM_REG_CTIMER_CTRL3_CTLINK3(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS 0x00000000 +#define AM_REG_CTIMER_CTRL3_CTLINK3_32BIT_TIMER 0x80000000 + +// Counter/Timer B3 Output Enable bit. +#define AM_REG_CTIMER_CTRL3_TMRB3PE_S 29 +#define AM_REG_CTIMER_CTRL3_TMRB3PE_M 0x20000000 +#define AM_REG_CTIMER_CTRL3_TMRB3PE(n) (((uint32_t)(n) << 29) & 0x20000000) +#define AM_REG_CTIMER_CTRL3_TMRB3PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3PE_EN 0x20000000 + +// Counter/Timer B3 output polarity. +#define AM_REG_CTIMER_CTRL3_TMRB3POL_S 28 +#define AM_REG_CTIMER_CTRL3_TMRB3POL_M 0x10000000 +#define AM_REG_CTIMER_CTRL3_TMRB3POL(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_CTIMER_CTRL3_TMRB3POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3POL_INVERTED 0x10000000 + +// Counter/Timer B3 Clear bit. +#define AM_REG_CTIMER_CTRL3_TMRB3CLR_S 27 +#define AM_REG_CTIMER_CTRL3_TMRB3CLR_M 0x08000000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLR(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_CTIMER_CTRL3_TMRB3CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLR_CLEAR 0x08000000 + +// Counter/Timer B3 Interrupt Enable bit for COMPR1. +#define AM_REG_CTIMER_CTRL3_TMRB3IE1_S 26 +#define AM_REG_CTIMER_CTRL3_TMRB3IE1_M 0x04000000 +#define AM_REG_CTIMER_CTRL3_TMRB3IE1(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_CTIMER_CTRL3_TMRB3IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3IE1_EN 0x04000000 + +// Counter/Timer B3 Interrupt Enable bit for COMPR0. +#define AM_REG_CTIMER_CTRL3_TMRB3IE0_S 25 +#define AM_REG_CTIMER_CTRL3_TMRB3IE0_M 0x02000000 +#define AM_REG_CTIMER_CTRL3_TMRB3IE0(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_CTIMER_CTRL3_TMRB3IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3IE0_EN 0x02000000 + +// Counter/Timer B3 Function Select. +#define AM_REG_CTIMER_CTRL3_TMRB3FN_S 22 +#define AM_REG_CTIMER_CTRL3_TMRB3FN_M 0x01C00000 +#define AM_REG_CTIMER_CTRL3_TMRB3FN(n) (((uint32_t)(n) << 22) & 0x01C00000) +#define AM_REG_CTIMER_CTRL3_TMRB3FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT 0x00400000 +#define AM_REG_CTIMER_CTRL3_TMRB3FN_PULSE_ONCE 0x00800000 +#define AM_REG_CTIMER_CTRL3_TMRB3FN_PULSE_CONT 0x00C00000 +#define AM_REG_CTIMER_CTRL3_TMRB3FN_CONTINUOUS 0x01000000 + +// Counter/Timer B3 Clock Select. +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_S 17 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_M 0x003E0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 0x00020000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 0x00040000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 0x00060000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 0x00080000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K 0x000A0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT 0x000C0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV2 0x000E0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV16 0x00100000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV256 0x00120000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 0x00140000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 0x00160000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K 0x00180000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC 0x001A0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_RTC_100HZ 0x001C0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_HCLK 0x001E0000 +#define AM_REG_CTIMER_CTRL3_TMRB3CLK_BUCKA 0x00200000 + +// Counter/Timer B3 Enable bit. +#define AM_REG_CTIMER_CTRL3_TMRB3EN_S 16 +#define AM_REG_CTIMER_CTRL3_TMRB3EN_M 0x00010000 +#define AM_REG_CTIMER_CTRL3_TMRB3EN(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_CTIMER_CTRL3_TMRB3EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRB3EN_EN 0x00010000 + +// Special Timer A3 enable for ADC function. +#define AM_REG_CTIMER_CTRL3_ADCEN_S 15 +#define AM_REG_CTIMER_CTRL3_ADCEN_M 0x00008000 +#define AM_REG_CTIMER_CTRL3_ADCEN(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Counter/Timer A3 Output Enable bit. +#define AM_REG_CTIMER_CTRL3_TMRA3PE_S 13 +#define AM_REG_CTIMER_CTRL3_TMRA3PE_M 0x00002000 +#define AM_REG_CTIMER_CTRL3_TMRA3PE(n) (((uint32_t)(n) << 13) & 0x00002000) +#define AM_REG_CTIMER_CTRL3_TMRA3PE_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3PE_EN 0x00002000 + +// Counter/Timer A3 output polarity. +#define AM_REG_CTIMER_CTRL3_TMRA3POL_S 12 +#define AM_REG_CTIMER_CTRL3_TMRA3POL_M 0x00001000 +#define AM_REG_CTIMER_CTRL3_TMRA3POL(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_CTRL3_TMRA3POL_NORMAL 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3POL_INVERTED 0x00001000 + +// Counter/Timer A3 Clear bit. +#define AM_REG_CTIMER_CTRL3_TMRA3CLR_S 11 +#define AM_REG_CTIMER_CTRL3_TMRA3CLR_M 0x00000800 +#define AM_REG_CTIMER_CTRL3_TMRA3CLR(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_CTRL3_TMRA3CLR_RUN 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3CLR_CLEAR 0x00000800 + +// Counter/Timer A3 Interrupt Enable bit based on COMPR1. +#define AM_REG_CTIMER_CTRL3_TMRA3IE1_S 10 +#define AM_REG_CTIMER_CTRL3_TMRA3IE1_M 0x00000400 +#define AM_REG_CTIMER_CTRL3_TMRA3IE1(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_CTRL3_TMRA3IE1_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3IE1_EN 0x00000400 + +// Counter/Timer A3 Interrupt Enable bit based on COMPR0. +#define AM_REG_CTIMER_CTRL3_TMRA3IE0_S 9 +#define AM_REG_CTIMER_CTRL3_TMRA3IE0_M 0x00000200 +#define AM_REG_CTIMER_CTRL3_TMRA3IE0(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_CTRL3_TMRA3IE0_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3IE0_EN 0x00000200 + +// Counter/Timer A3 Function Select. +#define AM_REG_CTIMER_CTRL3_TMRA3FN_S 6 +#define AM_REG_CTIMER_CTRL3_TMRA3FN_M 0x000001C0 +#define AM_REG_CTIMER_CTRL3_TMRA3FN(n) (((uint32_t)(n) << 6) & 0x000001C0) +#define AM_REG_CTIMER_CTRL3_TMRA3FN_SINGLECOUNT 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT 0x00000040 +#define AM_REG_CTIMER_CTRL3_TMRA3FN_PULSE_ONCE 0x00000080 +#define AM_REG_CTIMER_CTRL3_TMRA3FN_PULSE_CONT 0x000000C0 +#define AM_REG_CTIMER_CTRL3_TMRA3FN_CONTINUOUS 0x00000100 + +// Counter/Timer A3 Clock Select. +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_S 1 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_M 0x0000003E +#define AM_REG_CTIMER_CTRL3_TMRA3CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_TMRPIN 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 0x00000002 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 0x00000004 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 0x00000006 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 0x00000008 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K 0x0000000A +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT 0x0000000C +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV2 0x0000000E +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV16 0x00000010 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV256 0x00000012 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 0x00000014 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 0x00000016 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K 0x00000018 +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC 0x0000001A +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_RTC_100HZ 0x0000001C +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_HCLK 0x0000001E +#define AM_REG_CTIMER_CTRL3_TMRA3CLK_BUCKB 0x00000020 + +// Counter/Timer A3 Enable bit. +#define AM_REG_CTIMER_CTRL3_TMRA3EN_S 0 +#define AM_REG_CTIMER_CTRL3_TMRA3EN_M 0x00000001 +#define AM_REG_CTIMER_CTRL3_TMRA3EN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_CTRL3_TMRA3EN_DIS 0x00000000 +#define AM_REG_CTIMER_CTRL3_TMRA3EN_EN 0x00000001 + +//***************************************************************************** +// +// CTIMER_STCFG - Configuration Register +// +//***************************************************************************** +// Set this bit to one to freeze the clock input to the COUNTER register. Once +// frozen, the value can be safely written from the MCU. Unfreeze to resume. +#define AM_REG_CTIMER_STCFG_FREEZE_S 31 +#define AM_REG_CTIMER_STCFG_FREEZE_M 0x80000000 +#define AM_REG_CTIMER_STCFG_FREEZE(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_CTIMER_STCFG_FREEZE_THAW 0x00000000 +#define AM_REG_CTIMER_STCFG_FREEZE_FREEZE 0x80000000 + +// Set this bit to one to clear the System Timer register. If this bit is set +// to '1', the system timer register will stay cleared. It needs to be set to +// '0' for the system timer to start running. +#define AM_REG_CTIMER_STCFG_CLEAR_S 30 +#define AM_REG_CTIMER_STCFG_CLEAR_M 0x40000000 +#define AM_REG_CTIMER_STCFG_CLEAR(n) (((uint32_t)(n) << 30) & 0x40000000) +#define AM_REG_CTIMER_STCFG_CLEAR_RUN 0x00000000 +#define AM_REG_CTIMER_STCFG_CLEAR_CLEAR 0x40000000 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_S 15 +#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_M 0x00008000 +#define AM_REG_CTIMER_STCFG_COMPARE_H_EN(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_H_EN_ENABLE 0x00008000 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_S 14 +#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_M 0x00004000 +#define AM_REG_CTIMER_STCFG_COMPARE_G_EN(n) (((uint32_t)(n) << 14) & 0x00004000) +#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_G_EN_ENABLE 0x00004000 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_S 13 +#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_M 0x00002000 +#define AM_REG_CTIMER_STCFG_COMPARE_F_EN(n) (((uint32_t)(n) << 13) & 0x00002000) +#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_F_EN_ENABLE 0x00002000 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_S 12 +#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_M 0x00001000 +#define AM_REG_CTIMER_STCFG_COMPARE_E_EN(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_E_EN_ENABLE 0x00001000 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_S 11 +#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_M 0x00000800 +#define AM_REG_CTIMER_STCFG_COMPARE_D_EN(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_D_EN_ENABLE 0x00000800 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_S 10 +#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_M 0x00000400 +#define AM_REG_CTIMER_STCFG_COMPARE_C_EN(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_C_EN_ENABLE 0x00000400 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_S 9 +#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_M 0x00000200 +#define AM_REG_CTIMER_STCFG_COMPARE_B_EN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_B_EN_ENABLE 0x00000200 + +// Selects whether compare is enabled for the corresponding SCMPR register. If +// compare is enabled, the interrupt status is set once the comparision is met. +#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_S 8 +#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_M 0x00000100 +#define AM_REG_CTIMER_STCFG_COMPARE_A_EN(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_DISABLE 0x00000000 +#define AM_REG_CTIMER_STCFG_COMPARE_A_EN_ENABLE 0x00000100 + +// Selects an appropriate clock source and divider to use for the System Timer +// clock. +#define AM_REG_CTIMER_STCFG_CLKSEL_S 0 +#define AM_REG_CTIMER_STCFG_CLKSEL_M 0x0000000F +#define AM_REG_CTIMER_STCFG_CLKSEL(n) (((uint32_t)(n) << 0) & 0x0000000F) +#define AM_REG_CTIMER_STCFG_CLKSEL_NOCLK 0x00000000 +#define AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16 0x00000001 +#define AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256 0x00000002 +#define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV1 0x00000003 +#define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV2 0x00000004 +#define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV32 0x00000005 +#define AM_REG_CTIMER_STCFG_CLKSEL_LFRC_DIV1 0x00000006 +#define AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0A 0x00000007 +#define AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0B 0x00000008 + +//***************************************************************************** +// +// CTIMER_STTMR - System Timer Count Register (Real Time Counter) +// +//***************************************************************************** +// Value of the 32-bit counter as it ticks over. +#define AM_REG_CTIMER_STTMR_VALUE_S 0 +#define AM_REG_CTIMER_STTMR_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_STTMR_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_CAPTURE_CONTROL - Capture Control Register +// +//***************************************************************************** +// Selects whether capture is enabled for the specified capture register. +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_S 3 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_M 0x00000008 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_DISABLE 0x00000000 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_ENABLE 0x00000008 + +// Selects whether capture is enabled for the specified capture register. +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_S 2 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_M 0x00000004 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_DISABLE 0x00000000 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_ENABLE 0x00000004 + +// Selects whether capture is enabled for the specified capture register. +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_S 1 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_M 0x00000002 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_DISABLE 0x00000000 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_ENABLE 0x00000002 + +// Selects whether capture is enabled for the specified capture register. +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_S 0 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M 0x00000001 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_DISABLE 0x00000000 +#define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_ENABLE 0x00000001 + +//***************************************************************************** +// +// CTIMER_SCMPR0 - Compare Register A +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR0_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR0_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR1 - Compare Register B +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR1_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR1_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR2 - Compare Register C +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR2_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR2_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR2_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR3 - Compare Register D +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR3_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR3_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR3_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR4 - Compare Register E +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR4_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR4_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR4_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR5 - Compare Register F +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR5_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR5_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR5_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR6 - Compare Register G +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR6_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR6_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR6_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCMPR7 - Compare Register H +// +//***************************************************************************** +// Compare this value to the value in the COUNTER register according to the +// match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF +// register. +#define AM_REG_CTIMER_SCMPR7_VALUE_S 0 +#define AM_REG_CTIMER_SCMPR7_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCMPR7_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCAPT0 - Capture Register A +// +//***************************************************************************** +// Whenever the event is detected, the value in the COUNTER is copied into this +// register and the corresponding interrupt status bit is set. +#define AM_REG_CTIMER_SCAPT0_VALUE_S 0 +#define AM_REG_CTIMER_SCAPT0_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCAPT0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCAPT1 - Capture Register B +// +//***************************************************************************** +// Whenever the event is detected, the value in the COUNTER is copied into this +// register and the corresponding interrupt status bit is set. +#define AM_REG_CTIMER_SCAPT1_VALUE_S 0 +#define AM_REG_CTIMER_SCAPT1_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCAPT1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCAPT2 - Capture Register C +// +//***************************************************************************** +// Whenever the event is detected, the value in the COUNTER is copied into this +// register and the corresponding interrupt status bit is set. +#define AM_REG_CTIMER_SCAPT2_VALUE_S 0 +#define AM_REG_CTIMER_SCAPT2_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCAPT2_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SCAPT3 - Capture Register D +// +//***************************************************************************** +// Whenever the event is detected, the value in the COUNTER is copied into this +// register and the corresponding interrupt status bit is set. +#define AM_REG_CTIMER_SCAPT3_VALUE_S 0 +#define AM_REG_CTIMER_SCAPT3_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SCAPT3_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SNVR0 - System Timer NVRAM_A Register +// +//***************************************************************************** +// Value of the 32-bit counter as it ticks over. +#define AM_REG_CTIMER_SNVR0_VALUE_S 0 +#define AM_REG_CTIMER_SNVR0_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SNVR0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SNVR1 - System Timer NVRAM_B Register +// +//***************************************************************************** +// Value of the 32-bit counter as it ticks over. +#define AM_REG_CTIMER_SNVR1_VALUE_S 0 +#define AM_REG_CTIMER_SNVR1_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SNVR1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// CTIMER_SNVR2 - System Timer NVRAM_C Register +// +//***************************************************************************** +// Value of the 32-bit counter as it ticks over. +#define AM_REG_CTIMER_SNVR2_VALUE_S 0 +#define AM_REG_CTIMER_SNVR2_VALUE_M 0xFFFFFFFF +#define AM_REG_CTIMER_SNVR2_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +#endif // AM_REG_CTIMER_H diff --git a/mcu/apollo2/regs/am_reg_flashctrl.h b/mcu/apollo2/regs/am_reg_flashctrl.h new file mode 100644 index 0000000..d9b3622 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_flashctrl.h @@ -0,0 +1,69 @@ +//***************************************************************************** +// +// am_reg_flashctrl.h +//! @file +//! +//! @brief Register macros for the FLASHCTRL module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_FLASHCTRL_H +#define AM_REG_FLASHCTRL_H + +//***************************************************************************** +// +// FLASHCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_FLASHCTRL_NUM_MODULES 1 +#define AM_REG_FLASHCTRLn(n) \ + (REG_FLASHCTRL_BASEADDR + 0x00001000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** + +//***************************************************************************** +// +// Key values. +// +//***************************************************************************** + +#endif // AM_REG_FLASHCTRL_H diff --git a/mcu/apollo2/regs/am_reg_gpio.h b/mcu/apollo2/regs/am_reg_gpio.h new file mode 100644 index 0000000..7078c2a --- /dev/null +++ b/mcu/apollo2/regs/am_reg_gpio.h @@ -0,0 +1,5219 @@ +//***************************************************************************** +// +// am_reg_gpio.h +//! @file +//! +//! @brief Register macros for the GPIO module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_GPIO_H +#define AM_REG_GPIO_H + +//***************************************************************************** +// +// GPIO +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_GPIO_NUM_MODULES 1 +#define AM_REG_GPIOn(n) \ + (REG_GPIO_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_GPIO_PADREGA_O 0x00000000 +#define AM_REG_GPIO_PADREGB_O 0x00000004 +#define AM_REG_GPIO_PADREGC_O 0x00000008 +#define AM_REG_GPIO_PADREGD_O 0x0000000C +#define AM_REG_GPIO_PADREGE_O 0x00000010 +#define AM_REG_GPIO_PADREGF_O 0x00000014 +#define AM_REG_GPIO_PADREGG_O 0x00000018 +#define AM_REG_GPIO_PADREGH_O 0x0000001C +#define AM_REG_GPIO_PADREGI_O 0x00000020 +#define AM_REG_GPIO_PADREGJ_O 0x00000024 +#define AM_REG_GPIO_PADREGK_O 0x00000028 +#define AM_REG_GPIO_PADREGL_O 0x0000002C +#define AM_REG_GPIO_PADREGM_O 0x00000030 +#define AM_REG_GPIO_CFGA_O 0x00000040 +#define AM_REG_GPIO_CFGB_O 0x00000044 +#define AM_REG_GPIO_CFGC_O 0x00000048 +#define AM_REG_GPIO_CFGD_O 0x0000004C +#define AM_REG_GPIO_CFGE_O 0x00000050 +#define AM_REG_GPIO_CFGF_O 0x00000054 +#define AM_REG_GPIO_CFGG_O 0x00000058 +#define AM_REG_GPIO_RDA_O 0x00000080 +#define AM_REG_GPIO_RDB_O 0x00000084 +#define AM_REG_GPIO_WTA_O 0x00000088 +#define AM_REG_GPIO_WTB_O 0x0000008C +#define AM_REG_GPIO_WTSA_O 0x00000090 +#define AM_REG_GPIO_WTSB_O 0x00000094 +#define AM_REG_GPIO_WTCA_O 0x00000098 +#define AM_REG_GPIO_WTCB_O 0x0000009C +#define AM_REG_GPIO_ENA_O 0x000000A0 +#define AM_REG_GPIO_ENB_O 0x000000A4 +#define AM_REG_GPIO_ENSA_O 0x000000A8 +#define AM_REG_GPIO_ENSB_O 0x000000AC +#define AM_REG_GPIO_ENCA_O 0x000000B4 +#define AM_REG_GPIO_ENCB_O 0x000000B8 +#define AM_REG_GPIO_STMRCAP_O 0x000000BC +#define AM_REG_GPIO_IOM0IRQ_O 0x000000C0 +#define AM_REG_GPIO_IOM1IRQ_O 0x000000C4 +#define AM_REG_GPIO_IOM2IRQ_O 0x000000C8 +#define AM_REG_GPIO_IOM3IRQ_O 0x000000CC +#define AM_REG_GPIO_IOM4IRQ_O 0x000000D0 +#define AM_REG_GPIO_IOM5IRQ_O 0x000000D4 +#define AM_REG_GPIO_LOOPBACK_O 0x000000D8 +#define AM_REG_GPIO_GPIOOBS_O 0x000000DC +#define AM_REG_GPIO_ALTPADCFGA_O 0x000000E0 +#define AM_REG_GPIO_ALTPADCFGB_O 0x000000E4 +#define AM_REG_GPIO_ALTPADCFGC_O 0x000000E8 +#define AM_REG_GPIO_ALTPADCFGD_O 0x000000EC +#define AM_REG_GPIO_ALTPADCFGE_O 0x000000F0 +#define AM_REG_GPIO_ALTPADCFGF_O 0x000000F4 +#define AM_REG_GPIO_ALTPADCFGG_O 0x000000F8 +#define AM_REG_GPIO_ALTPADCFGH_O 0x000000FC +#define AM_REG_GPIO_ALTPADCFGI_O 0x00000100 +#define AM_REG_GPIO_ALTPADCFGJ_O 0x00000104 +#define AM_REG_GPIO_ALTPADCFGK_O 0x00000108 +#define AM_REG_GPIO_ALTPADCFGL_O 0x0000010C +#define AM_REG_GPIO_ALTPADCFGM_O 0x00000110 +#define AM_REG_GPIO_PADKEY_O 0x00000060 +#define AM_REG_GPIO_INT0EN_O 0x00000200 +#define AM_REG_GPIO_INT0STAT_O 0x00000204 +#define AM_REG_GPIO_INT0CLR_O 0x00000208 +#define AM_REG_GPIO_INT0SET_O 0x0000020C +#define AM_REG_GPIO_INT1EN_O 0x00000210 +#define AM_REG_GPIO_INT1STAT_O 0x00000214 +#define AM_REG_GPIO_INT1CLR_O 0x00000218 +#define AM_REG_GPIO_INT1SET_O 0x0000021C + +//***************************************************************************** +// +// Key values. +// +//***************************************************************************** +#define AM_REG_GPIO_PADKEY_KEYVAL 0x00000073 + +//***************************************************************************** +// +// GPIO_INT0EN - GPIO Interrupt Registers 31-0: Enable +// +//***************************************************************************** +// GPIO31 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO31_S 31 +#define AM_REG_GPIO_INT0EN_GPIO31_M 0x80000000 +#define AM_REG_GPIO_INT0EN_GPIO31(n) (((uint32_t)(n) << 31) & 0x80000000) + +// GPIO30 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO30_S 30 +#define AM_REG_GPIO_INT0EN_GPIO30_M 0x40000000 +#define AM_REG_GPIO_INT0EN_GPIO30(n) (((uint32_t)(n) << 30) & 0x40000000) + +// GPIO29 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO29_S 29 +#define AM_REG_GPIO_INT0EN_GPIO29_M 0x20000000 +#define AM_REG_GPIO_INT0EN_GPIO29(n) (((uint32_t)(n) << 29) & 0x20000000) + +// GPIO28 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO28_S 28 +#define AM_REG_GPIO_INT0EN_GPIO28_M 0x10000000 +#define AM_REG_GPIO_INT0EN_GPIO28(n) (((uint32_t)(n) << 28) & 0x10000000) + +// GPIO27 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO27_S 27 +#define AM_REG_GPIO_INT0EN_GPIO27_M 0x08000000 +#define AM_REG_GPIO_INT0EN_GPIO27(n) (((uint32_t)(n) << 27) & 0x08000000) + +// GPIO26 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO26_S 26 +#define AM_REG_GPIO_INT0EN_GPIO26_M 0x04000000 +#define AM_REG_GPIO_INT0EN_GPIO26(n) (((uint32_t)(n) << 26) & 0x04000000) + +// GPIO25 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO25_S 25 +#define AM_REG_GPIO_INT0EN_GPIO25_M 0x02000000 +#define AM_REG_GPIO_INT0EN_GPIO25(n) (((uint32_t)(n) << 25) & 0x02000000) + +// GPIO24 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO24_S 24 +#define AM_REG_GPIO_INT0EN_GPIO24_M 0x01000000 +#define AM_REG_GPIO_INT0EN_GPIO24(n) (((uint32_t)(n) << 24) & 0x01000000) + +// GPIO23 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO23_S 23 +#define AM_REG_GPIO_INT0EN_GPIO23_M 0x00800000 +#define AM_REG_GPIO_INT0EN_GPIO23(n) (((uint32_t)(n) << 23) & 0x00800000) + +// GPIO22 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO22_S 22 +#define AM_REG_GPIO_INT0EN_GPIO22_M 0x00400000 +#define AM_REG_GPIO_INT0EN_GPIO22(n) (((uint32_t)(n) << 22) & 0x00400000) + +// GPIO21 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO21_S 21 +#define AM_REG_GPIO_INT0EN_GPIO21_M 0x00200000 +#define AM_REG_GPIO_INT0EN_GPIO21(n) (((uint32_t)(n) << 21) & 0x00200000) + +// GPIO20 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO20_S 20 +#define AM_REG_GPIO_INT0EN_GPIO20_M 0x00100000 +#define AM_REG_GPIO_INT0EN_GPIO20(n) (((uint32_t)(n) << 20) & 0x00100000) + +// GPIO19 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO19_S 19 +#define AM_REG_GPIO_INT0EN_GPIO19_M 0x00080000 +#define AM_REG_GPIO_INT0EN_GPIO19(n) (((uint32_t)(n) << 19) & 0x00080000) + +// GPIO18interrupt. +#define AM_REG_GPIO_INT0EN_GPIO18_S 18 +#define AM_REG_GPIO_INT0EN_GPIO18_M 0x00040000 +#define AM_REG_GPIO_INT0EN_GPIO18(n) (((uint32_t)(n) << 18) & 0x00040000) + +// GPIO17 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO17_S 17 +#define AM_REG_GPIO_INT0EN_GPIO17_M 0x00020000 +#define AM_REG_GPIO_INT0EN_GPIO17(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO16 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO16_S 16 +#define AM_REG_GPIO_INT0EN_GPIO16_M 0x00010000 +#define AM_REG_GPIO_INT0EN_GPIO16(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO15 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO15_S 15 +#define AM_REG_GPIO_INT0EN_GPIO15_M 0x00008000 +#define AM_REG_GPIO_INT0EN_GPIO15(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO14 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO14_S 14 +#define AM_REG_GPIO_INT0EN_GPIO14_M 0x00004000 +#define AM_REG_GPIO_INT0EN_GPIO14(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO13 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO13_S 13 +#define AM_REG_GPIO_INT0EN_GPIO13_M 0x00002000 +#define AM_REG_GPIO_INT0EN_GPIO13(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO12 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO12_S 12 +#define AM_REG_GPIO_INT0EN_GPIO12_M 0x00001000 +#define AM_REG_GPIO_INT0EN_GPIO12(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO11 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO11_S 11 +#define AM_REG_GPIO_INT0EN_GPIO11_M 0x00000800 +#define AM_REG_GPIO_INT0EN_GPIO11(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO10 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO10_S 10 +#define AM_REG_GPIO_INT0EN_GPIO10_M 0x00000400 +#define AM_REG_GPIO_INT0EN_GPIO10(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO9 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO9_S 9 +#define AM_REG_GPIO_INT0EN_GPIO9_M 0x00000200 +#define AM_REG_GPIO_INT0EN_GPIO9(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO8 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO8_S 8 +#define AM_REG_GPIO_INT0EN_GPIO8_M 0x00000100 +#define AM_REG_GPIO_INT0EN_GPIO8(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO7 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO7_S 7 +#define AM_REG_GPIO_INT0EN_GPIO7_M 0x00000080 +#define AM_REG_GPIO_INT0EN_GPIO7(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO6 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO6_S 6 +#define AM_REG_GPIO_INT0EN_GPIO6_M 0x00000040 +#define AM_REG_GPIO_INT0EN_GPIO6(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO5 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO5_S 5 +#define AM_REG_GPIO_INT0EN_GPIO5_M 0x00000020 +#define AM_REG_GPIO_INT0EN_GPIO5(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO4 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO4_S 4 +#define AM_REG_GPIO_INT0EN_GPIO4_M 0x00000010 +#define AM_REG_GPIO_INT0EN_GPIO4(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO3 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO3_S 3 +#define AM_REG_GPIO_INT0EN_GPIO3_M 0x00000008 +#define AM_REG_GPIO_INT0EN_GPIO3(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO2 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO2_S 2 +#define AM_REG_GPIO_INT0EN_GPIO2_M 0x00000004 +#define AM_REG_GPIO_INT0EN_GPIO2(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO1 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO1_S 1 +#define AM_REG_GPIO_INT0EN_GPIO1_M 0x00000002 +#define AM_REG_GPIO_INT0EN_GPIO1(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO0 interrupt. +#define AM_REG_GPIO_INT0EN_GPIO0_S 0 +#define AM_REG_GPIO_INT0EN_GPIO0_M 0x00000001 +#define AM_REG_GPIO_INT0EN_GPIO0(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT0STAT - GPIO Interrupt Registers 31-0: Status +// +//***************************************************************************** +// GPIO31 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO31_S 31 +#define AM_REG_GPIO_INT0STAT_GPIO31_M 0x80000000 +#define AM_REG_GPIO_INT0STAT_GPIO31(n) (((uint32_t)(n) << 31) & 0x80000000) + +// GPIO30 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO30_S 30 +#define AM_REG_GPIO_INT0STAT_GPIO30_M 0x40000000 +#define AM_REG_GPIO_INT0STAT_GPIO30(n) (((uint32_t)(n) << 30) & 0x40000000) + +// GPIO29 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO29_S 29 +#define AM_REG_GPIO_INT0STAT_GPIO29_M 0x20000000 +#define AM_REG_GPIO_INT0STAT_GPIO29(n) (((uint32_t)(n) << 29) & 0x20000000) + +// GPIO28 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO28_S 28 +#define AM_REG_GPIO_INT0STAT_GPIO28_M 0x10000000 +#define AM_REG_GPIO_INT0STAT_GPIO28(n) (((uint32_t)(n) << 28) & 0x10000000) + +// GPIO27 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO27_S 27 +#define AM_REG_GPIO_INT0STAT_GPIO27_M 0x08000000 +#define AM_REG_GPIO_INT0STAT_GPIO27(n) (((uint32_t)(n) << 27) & 0x08000000) + +// GPIO26 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO26_S 26 +#define AM_REG_GPIO_INT0STAT_GPIO26_M 0x04000000 +#define AM_REG_GPIO_INT0STAT_GPIO26(n) (((uint32_t)(n) << 26) & 0x04000000) + +// GPIO25 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO25_S 25 +#define AM_REG_GPIO_INT0STAT_GPIO25_M 0x02000000 +#define AM_REG_GPIO_INT0STAT_GPIO25(n) (((uint32_t)(n) << 25) & 0x02000000) + +// GPIO24 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO24_S 24 +#define AM_REG_GPIO_INT0STAT_GPIO24_M 0x01000000 +#define AM_REG_GPIO_INT0STAT_GPIO24(n) (((uint32_t)(n) << 24) & 0x01000000) + +// GPIO23 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO23_S 23 +#define AM_REG_GPIO_INT0STAT_GPIO23_M 0x00800000 +#define AM_REG_GPIO_INT0STAT_GPIO23(n) (((uint32_t)(n) << 23) & 0x00800000) + +// GPIO22 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO22_S 22 +#define AM_REG_GPIO_INT0STAT_GPIO22_M 0x00400000 +#define AM_REG_GPIO_INT0STAT_GPIO22(n) (((uint32_t)(n) << 22) & 0x00400000) + +// GPIO21 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO21_S 21 +#define AM_REG_GPIO_INT0STAT_GPIO21_M 0x00200000 +#define AM_REG_GPIO_INT0STAT_GPIO21(n) (((uint32_t)(n) << 21) & 0x00200000) + +// GPIO20 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO20_S 20 +#define AM_REG_GPIO_INT0STAT_GPIO20_M 0x00100000 +#define AM_REG_GPIO_INT0STAT_GPIO20(n) (((uint32_t)(n) << 20) & 0x00100000) + +// GPIO19 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO19_S 19 +#define AM_REG_GPIO_INT0STAT_GPIO19_M 0x00080000 +#define AM_REG_GPIO_INT0STAT_GPIO19(n) (((uint32_t)(n) << 19) & 0x00080000) + +// GPIO18interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO18_S 18 +#define AM_REG_GPIO_INT0STAT_GPIO18_M 0x00040000 +#define AM_REG_GPIO_INT0STAT_GPIO18(n) (((uint32_t)(n) << 18) & 0x00040000) + +// GPIO17 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO17_S 17 +#define AM_REG_GPIO_INT0STAT_GPIO17_M 0x00020000 +#define AM_REG_GPIO_INT0STAT_GPIO17(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO16 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO16_S 16 +#define AM_REG_GPIO_INT0STAT_GPIO16_M 0x00010000 +#define AM_REG_GPIO_INT0STAT_GPIO16(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO15 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO15_S 15 +#define AM_REG_GPIO_INT0STAT_GPIO15_M 0x00008000 +#define AM_REG_GPIO_INT0STAT_GPIO15(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO14 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO14_S 14 +#define AM_REG_GPIO_INT0STAT_GPIO14_M 0x00004000 +#define AM_REG_GPIO_INT0STAT_GPIO14(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO13 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO13_S 13 +#define AM_REG_GPIO_INT0STAT_GPIO13_M 0x00002000 +#define AM_REG_GPIO_INT0STAT_GPIO13(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO12 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO12_S 12 +#define AM_REG_GPIO_INT0STAT_GPIO12_M 0x00001000 +#define AM_REG_GPIO_INT0STAT_GPIO12(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO11 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO11_S 11 +#define AM_REG_GPIO_INT0STAT_GPIO11_M 0x00000800 +#define AM_REG_GPIO_INT0STAT_GPIO11(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO10 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO10_S 10 +#define AM_REG_GPIO_INT0STAT_GPIO10_M 0x00000400 +#define AM_REG_GPIO_INT0STAT_GPIO10(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO9 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO9_S 9 +#define AM_REG_GPIO_INT0STAT_GPIO9_M 0x00000200 +#define AM_REG_GPIO_INT0STAT_GPIO9(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO8 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO8_S 8 +#define AM_REG_GPIO_INT0STAT_GPIO8_M 0x00000100 +#define AM_REG_GPIO_INT0STAT_GPIO8(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO7 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO7_S 7 +#define AM_REG_GPIO_INT0STAT_GPIO7_M 0x00000080 +#define AM_REG_GPIO_INT0STAT_GPIO7(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO6 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO6_S 6 +#define AM_REG_GPIO_INT0STAT_GPIO6_M 0x00000040 +#define AM_REG_GPIO_INT0STAT_GPIO6(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO5 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO5_S 5 +#define AM_REG_GPIO_INT0STAT_GPIO5_M 0x00000020 +#define AM_REG_GPIO_INT0STAT_GPIO5(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO4 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO4_S 4 +#define AM_REG_GPIO_INT0STAT_GPIO4_M 0x00000010 +#define AM_REG_GPIO_INT0STAT_GPIO4(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO3 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO3_S 3 +#define AM_REG_GPIO_INT0STAT_GPIO3_M 0x00000008 +#define AM_REG_GPIO_INT0STAT_GPIO3(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO2 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO2_S 2 +#define AM_REG_GPIO_INT0STAT_GPIO2_M 0x00000004 +#define AM_REG_GPIO_INT0STAT_GPIO2(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO1 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO1_S 1 +#define AM_REG_GPIO_INT0STAT_GPIO1_M 0x00000002 +#define AM_REG_GPIO_INT0STAT_GPIO1(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO0 interrupt. +#define AM_REG_GPIO_INT0STAT_GPIO0_S 0 +#define AM_REG_GPIO_INT0STAT_GPIO0_M 0x00000001 +#define AM_REG_GPIO_INT0STAT_GPIO0(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT0CLR - GPIO Interrupt Registers 31-0: Clear +// +//***************************************************************************** +// GPIO31 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO31_S 31 +#define AM_REG_GPIO_INT0CLR_GPIO31_M 0x80000000 +#define AM_REG_GPIO_INT0CLR_GPIO31(n) (((uint32_t)(n) << 31) & 0x80000000) + +// GPIO30 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO30_S 30 +#define AM_REG_GPIO_INT0CLR_GPIO30_M 0x40000000 +#define AM_REG_GPIO_INT0CLR_GPIO30(n) (((uint32_t)(n) << 30) & 0x40000000) + +// GPIO29 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO29_S 29 +#define AM_REG_GPIO_INT0CLR_GPIO29_M 0x20000000 +#define AM_REG_GPIO_INT0CLR_GPIO29(n) (((uint32_t)(n) << 29) & 0x20000000) + +// GPIO28 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO28_S 28 +#define AM_REG_GPIO_INT0CLR_GPIO28_M 0x10000000 +#define AM_REG_GPIO_INT0CLR_GPIO28(n) (((uint32_t)(n) << 28) & 0x10000000) + +// GPIO27 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO27_S 27 +#define AM_REG_GPIO_INT0CLR_GPIO27_M 0x08000000 +#define AM_REG_GPIO_INT0CLR_GPIO27(n) (((uint32_t)(n) << 27) & 0x08000000) + +// GPIO26 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO26_S 26 +#define AM_REG_GPIO_INT0CLR_GPIO26_M 0x04000000 +#define AM_REG_GPIO_INT0CLR_GPIO26(n) (((uint32_t)(n) << 26) & 0x04000000) + +// GPIO25 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO25_S 25 +#define AM_REG_GPIO_INT0CLR_GPIO25_M 0x02000000 +#define AM_REG_GPIO_INT0CLR_GPIO25(n) (((uint32_t)(n) << 25) & 0x02000000) + +// GPIO24 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO24_S 24 +#define AM_REG_GPIO_INT0CLR_GPIO24_M 0x01000000 +#define AM_REG_GPIO_INT0CLR_GPIO24(n) (((uint32_t)(n) << 24) & 0x01000000) + +// GPIO23 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO23_S 23 +#define AM_REG_GPIO_INT0CLR_GPIO23_M 0x00800000 +#define AM_REG_GPIO_INT0CLR_GPIO23(n) (((uint32_t)(n) << 23) & 0x00800000) + +// GPIO22 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO22_S 22 +#define AM_REG_GPIO_INT0CLR_GPIO22_M 0x00400000 +#define AM_REG_GPIO_INT0CLR_GPIO22(n) (((uint32_t)(n) << 22) & 0x00400000) + +// GPIO21 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO21_S 21 +#define AM_REG_GPIO_INT0CLR_GPIO21_M 0x00200000 +#define AM_REG_GPIO_INT0CLR_GPIO21(n) (((uint32_t)(n) << 21) & 0x00200000) + +// GPIO20 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO20_S 20 +#define AM_REG_GPIO_INT0CLR_GPIO20_M 0x00100000 +#define AM_REG_GPIO_INT0CLR_GPIO20(n) (((uint32_t)(n) << 20) & 0x00100000) + +// GPIO19 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO19_S 19 +#define AM_REG_GPIO_INT0CLR_GPIO19_M 0x00080000 +#define AM_REG_GPIO_INT0CLR_GPIO19(n) (((uint32_t)(n) << 19) & 0x00080000) + +// GPIO18interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO18_S 18 +#define AM_REG_GPIO_INT0CLR_GPIO18_M 0x00040000 +#define AM_REG_GPIO_INT0CLR_GPIO18(n) (((uint32_t)(n) << 18) & 0x00040000) + +// GPIO17 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO17_S 17 +#define AM_REG_GPIO_INT0CLR_GPIO17_M 0x00020000 +#define AM_REG_GPIO_INT0CLR_GPIO17(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO16 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO16_S 16 +#define AM_REG_GPIO_INT0CLR_GPIO16_M 0x00010000 +#define AM_REG_GPIO_INT0CLR_GPIO16(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO15 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO15_S 15 +#define AM_REG_GPIO_INT0CLR_GPIO15_M 0x00008000 +#define AM_REG_GPIO_INT0CLR_GPIO15(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO14 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO14_S 14 +#define AM_REG_GPIO_INT0CLR_GPIO14_M 0x00004000 +#define AM_REG_GPIO_INT0CLR_GPIO14(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO13 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO13_S 13 +#define AM_REG_GPIO_INT0CLR_GPIO13_M 0x00002000 +#define AM_REG_GPIO_INT0CLR_GPIO13(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO12 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO12_S 12 +#define AM_REG_GPIO_INT0CLR_GPIO12_M 0x00001000 +#define AM_REG_GPIO_INT0CLR_GPIO12(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO11 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO11_S 11 +#define AM_REG_GPIO_INT0CLR_GPIO11_M 0x00000800 +#define AM_REG_GPIO_INT0CLR_GPIO11(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO10 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO10_S 10 +#define AM_REG_GPIO_INT0CLR_GPIO10_M 0x00000400 +#define AM_REG_GPIO_INT0CLR_GPIO10(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO9 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO9_S 9 +#define AM_REG_GPIO_INT0CLR_GPIO9_M 0x00000200 +#define AM_REG_GPIO_INT0CLR_GPIO9(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO8 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO8_S 8 +#define AM_REG_GPIO_INT0CLR_GPIO8_M 0x00000100 +#define AM_REG_GPIO_INT0CLR_GPIO8(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO7 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO7_S 7 +#define AM_REG_GPIO_INT0CLR_GPIO7_M 0x00000080 +#define AM_REG_GPIO_INT0CLR_GPIO7(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO6 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO6_S 6 +#define AM_REG_GPIO_INT0CLR_GPIO6_M 0x00000040 +#define AM_REG_GPIO_INT0CLR_GPIO6(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO5 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO5_S 5 +#define AM_REG_GPIO_INT0CLR_GPIO5_M 0x00000020 +#define AM_REG_GPIO_INT0CLR_GPIO5(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO4 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO4_S 4 +#define AM_REG_GPIO_INT0CLR_GPIO4_M 0x00000010 +#define AM_REG_GPIO_INT0CLR_GPIO4(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO3 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO3_S 3 +#define AM_REG_GPIO_INT0CLR_GPIO3_M 0x00000008 +#define AM_REG_GPIO_INT0CLR_GPIO3(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO2 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO2_S 2 +#define AM_REG_GPIO_INT0CLR_GPIO2_M 0x00000004 +#define AM_REG_GPIO_INT0CLR_GPIO2(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO1 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO1_S 1 +#define AM_REG_GPIO_INT0CLR_GPIO1_M 0x00000002 +#define AM_REG_GPIO_INT0CLR_GPIO1(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO0 interrupt. +#define AM_REG_GPIO_INT0CLR_GPIO0_S 0 +#define AM_REG_GPIO_INT0CLR_GPIO0_M 0x00000001 +#define AM_REG_GPIO_INT0CLR_GPIO0(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT0SET - GPIO Interrupt Registers 31-0: Set +// +//***************************************************************************** +// GPIO31 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO31_S 31 +#define AM_REG_GPIO_INT0SET_GPIO31_M 0x80000000 +#define AM_REG_GPIO_INT0SET_GPIO31(n) (((uint32_t)(n) << 31) & 0x80000000) + +// GPIO30 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO30_S 30 +#define AM_REG_GPIO_INT0SET_GPIO30_M 0x40000000 +#define AM_REG_GPIO_INT0SET_GPIO30(n) (((uint32_t)(n) << 30) & 0x40000000) + +// GPIO29 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO29_S 29 +#define AM_REG_GPIO_INT0SET_GPIO29_M 0x20000000 +#define AM_REG_GPIO_INT0SET_GPIO29(n) (((uint32_t)(n) << 29) & 0x20000000) + +// GPIO28 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO28_S 28 +#define AM_REG_GPIO_INT0SET_GPIO28_M 0x10000000 +#define AM_REG_GPIO_INT0SET_GPIO28(n) (((uint32_t)(n) << 28) & 0x10000000) + +// GPIO27 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO27_S 27 +#define AM_REG_GPIO_INT0SET_GPIO27_M 0x08000000 +#define AM_REG_GPIO_INT0SET_GPIO27(n) (((uint32_t)(n) << 27) & 0x08000000) + +// GPIO26 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO26_S 26 +#define AM_REG_GPIO_INT0SET_GPIO26_M 0x04000000 +#define AM_REG_GPIO_INT0SET_GPIO26(n) (((uint32_t)(n) << 26) & 0x04000000) + +// GPIO25 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO25_S 25 +#define AM_REG_GPIO_INT0SET_GPIO25_M 0x02000000 +#define AM_REG_GPIO_INT0SET_GPIO25(n) (((uint32_t)(n) << 25) & 0x02000000) + +// GPIO24 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO24_S 24 +#define AM_REG_GPIO_INT0SET_GPIO24_M 0x01000000 +#define AM_REG_GPIO_INT0SET_GPIO24(n) (((uint32_t)(n) << 24) & 0x01000000) + +// GPIO23 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO23_S 23 +#define AM_REG_GPIO_INT0SET_GPIO23_M 0x00800000 +#define AM_REG_GPIO_INT0SET_GPIO23(n) (((uint32_t)(n) << 23) & 0x00800000) + +// GPIO22 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO22_S 22 +#define AM_REG_GPIO_INT0SET_GPIO22_M 0x00400000 +#define AM_REG_GPIO_INT0SET_GPIO22(n) (((uint32_t)(n) << 22) & 0x00400000) + +// GPIO21 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO21_S 21 +#define AM_REG_GPIO_INT0SET_GPIO21_M 0x00200000 +#define AM_REG_GPIO_INT0SET_GPIO21(n) (((uint32_t)(n) << 21) & 0x00200000) + +// GPIO20 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO20_S 20 +#define AM_REG_GPIO_INT0SET_GPIO20_M 0x00100000 +#define AM_REG_GPIO_INT0SET_GPIO20(n) (((uint32_t)(n) << 20) & 0x00100000) + +// GPIO19 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO19_S 19 +#define AM_REG_GPIO_INT0SET_GPIO19_M 0x00080000 +#define AM_REG_GPIO_INT0SET_GPIO19(n) (((uint32_t)(n) << 19) & 0x00080000) + +// GPIO18interrupt. +#define AM_REG_GPIO_INT0SET_GPIO18_S 18 +#define AM_REG_GPIO_INT0SET_GPIO18_M 0x00040000 +#define AM_REG_GPIO_INT0SET_GPIO18(n) (((uint32_t)(n) << 18) & 0x00040000) + +// GPIO17 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO17_S 17 +#define AM_REG_GPIO_INT0SET_GPIO17_M 0x00020000 +#define AM_REG_GPIO_INT0SET_GPIO17(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO16 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO16_S 16 +#define AM_REG_GPIO_INT0SET_GPIO16_M 0x00010000 +#define AM_REG_GPIO_INT0SET_GPIO16(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO15 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO15_S 15 +#define AM_REG_GPIO_INT0SET_GPIO15_M 0x00008000 +#define AM_REG_GPIO_INT0SET_GPIO15(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO14 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO14_S 14 +#define AM_REG_GPIO_INT0SET_GPIO14_M 0x00004000 +#define AM_REG_GPIO_INT0SET_GPIO14(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO13 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO13_S 13 +#define AM_REG_GPIO_INT0SET_GPIO13_M 0x00002000 +#define AM_REG_GPIO_INT0SET_GPIO13(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO12 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO12_S 12 +#define AM_REG_GPIO_INT0SET_GPIO12_M 0x00001000 +#define AM_REG_GPIO_INT0SET_GPIO12(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO11 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO11_S 11 +#define AM_REG_GPIO_INT0SET_GPIO11_M 0x00000800 +#define AM_REG_GPIO_INT0SET_GPIO11(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO10 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO10_S 10 +#define AM_REG_GPIO_INT0SET_GPIO10_M 0x00000400 +#define AM_REG_GPIO_INT0SET_GPIO10(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO9 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO9_S 9 +#define AM_REG_GPIO_INT0SET_GPIO9_M 0x00000200 +#define AM_REG_GPIO_INT0SET_GPIO9(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO8 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO8_S 8 +#define AM_REG_GPIO_INT0SET_GPIO8_M 0x00000100 +#define AM_REG_GPIO_INT0SET_GPIO8(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO7 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO7_S 7 +#define AM_REG_GPIO_INT0SET_GPIO7_M 0x00000080 +#define AM_REG_GPIO_INT0SET_GPIO7(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO6 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO6_S 6 +#define AM_REG_GPIO_INT0SET_GPIO6_M 0x00000040 +#define AM_REG_GPIO_INT0SET_GPIO6(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO5 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO5_S 5 +#define AM_REG_GPIO_INT0SET_GPIO5_M 0x00000020 +#define AM_REG_GPIO_INT0SET_GPIO5(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO4 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO4_S 4 +#define AM_REG_GPIO_INT0SET_GPIO4_M 0x00000010 +#define AM_REG_GPIO_INT0SET_GPIO4(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO3 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO3_S 3 +#define AM_REG_GPIO_INT0SET_GPIO3_M 0x00000008 +#define AM_REG_GPIO_INT0SET_GPIO3(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO2 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO2_S 2 +#define AM_REG_GPIO_INT0SET_GPIO2_M 0x00000004 +#define AM_REG_GPIO_INT0SET_GPIO2(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO1 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO1_S 1 +#define AM_REG_GPIO_INT0SET_GPIO1_M 0x00000002 +#define AM_REG_GPIO_INT0SET_GPIO1(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO0 interrupt. +#define AM_REG_GPIO_INT0SET_GPIO0_S 0 +#define AM_REG_GPIO_INT0SET_GPIO0_M 0x00000001 +#define AM_REG_GPIO_INT0SET_GPIO0(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT1EN - GPIO Interrupt Registers 49-32: Enable +// +//***************************************************************************** +// GPIO49 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO49_S 17 +#define AM_REG_GPIO_INT1EN_GPIO49_M 0x00020000 +#define AM_REG_GPIO_INT1EN_GPIO49(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO48 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO48_S 16 +#define AM_REG_GPIO_INT1EN_GPIO48_M 0x00010000 +#define AM_REG_GPIO_INT1EN_GPIO48(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO47 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO47_S 15 +#define AM_REG_GPIO_INT1EN_GPIO47_M 0x00008000 +#define AM_REG_GPIO_INT1EN_GPIO47(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO46 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO46_S 14 +#define AM_REG_GPIO_INT1EN_GPIO46_M 0x00004000 +#define AM_REG_GPIO_INT1EN_GPIO46(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO45 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO45_S 13 +#define AM_REG_GPIO_INT1EN_GPIO45_M 0x00002000 +#define AM_REG_GPIO_INT1EN_GPIO45(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO44 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO44_S 12 +#define AM_REG_GPIO_INT1EN_GPIO44_M 0x00001000 +#define AM_REG_GPIO_INT1EN_GPIO44(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO43 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO43_S 11 +#define AM_REG_GPIO_INT1EN_GPIO43_M 0x00000800 +#define AM_REG_GPIO_INT1EN_GPIO43(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO42 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO42_S 10 +#define AM_REG_GPIO_INT1EN_GPIO42_M 0x00000400 +#define AM_REG_GPIO_INT1EN_GPIO42(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO41 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO41_S 9 +#define AM_REG_GPIO_INT1EN_GPIO41_M 0x00000200 +#define AM_REG_GPIO_INT1EN_GPIO41(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO40 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO40_S 8 +#define AM_REG_GPIO_INT1EN_GPIO40_M 0x00000100 +#define AM_REG_GPIO_INT1EN_GPIO40(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO39 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO39_S 7 +#define AM_REG_GPIO_INT1EN_GPIO39_M 0x00000080 +#define AM_REG_GPIO_INT1EN_GPIO39(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO38 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO38_S 6 +#define AM_REG_GPIO_INT1EN_GPIO38_M 0x00000040 +#define AM_REG_GPIO_INT1EN_GPIO38(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO37 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO37_S 5 +#define AM_REG_GPIO_INT1EN_GPIO37_M 0x00000020 +#define AM_REG_GPIO_INT1EN_GPIO37(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO36 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO36_S 4 +#define AM_REG_GPIO_INT1EN_GPIO36_M 0x00000010 +#define AM_REG_GPIO_INT1EN_GPIO36(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO35 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO35_S 3 +#define AM_REG_GPIO_INT1EN_GPIO35_M 0x00000008 +#define AM_REG_GPIO_INT1EN_GPIO35(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO34 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO34_S 2 +#define AM_REG_GPIO_INT1EN_GPIO34_M 0x00000004 +#define AM_REG_GPIO_INT1EN_GPIO34(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO33 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO33_S 1 +#define AM_REG_GPIO_INT1EN_GPIO33_M 0x00000002 +#define AM_REG_GPIO_INT1EN_GPIO33(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO32 interrupt. +#define AM_REG_GPIO_INT1EN_GPIO32_S 0 +#define AM_REG_GPIO_INT1EN_GPIO32_M 0x00000001 +#define AM_REG_GPIO_INT1EN_GPIO32(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT1STAT - GPIO Interrupt Registers 49-32: Status +// +//***************************************************************************** +// GPIO49 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO49_S 17 +#define AM_REG_GPIO_INT1STAT_GPIO49_M 0x00020000 +#define AM_REG_GPIO_INT1STAT_GPIO49(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO48 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO48_S 16 +#define AM_REG_GPIO_INT1STAT_GPIO48_M 0x00010000 +#define AM_REG_GPIO_INT1STAT_GPIO48(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO47 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO47_S 15 +#define AM_REG_GPIO_INT1STAT_GPIO47_M 0x00008000 +#define AM_REG_GPIO_INT1STAT_GPIO47(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO46 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO46_S 14 +#define AM_REG_GPIO_INT1STAT_GPIO46_M 0x00004000 +#define AM_REG_GPIO_INT1STAT_GPIO46(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO45 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO45_S 13 +#define AM_REG_GPIO_INT1STAT_GPIO45_M 0x00002000 +#define AM_REG_GPIO_INT1STAT_GPIO45(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO44 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO44_S 12 +#define AM_REG_GPIO_INT1STAT_GPIO44_M 0x00001000 +#define AM_REG_GPIO_INT1STAT_GPIO44(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO43 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO43_S 11 +#define AM_REG_GPIO_INT1STAT_GPIO43_M 0x00000800 +#define AM_REG_GPIO_INT1STAT_GPIO43(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO42 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO42_S 10 +#define AM_REG_GPIO_INT1STAT_GPIO42_M 0x00000400 +#define AM_REG_GPIO_INT1STAT_GPIO42(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO41 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO41_S 9 +#define AM_REG_GPIO_INT1STAT_GPIO41_M 0x00000200 +#define AM_REG_GPIO_INT1STAT_GPIO41(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO40 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO40_S 8 +#define AM_REG_GPIO_INT1STAT_GPIO40_M 0x00000100 +#define AM_REG_GPIO_INT1STAT_GPIO40(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO39 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO39_S 7 +#define AM_REG_GPIO_INT1STAT_GPIO39_M 0x00000080 +#define AM_REG_GPIO_INT1STAT_GPIO39(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO38 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO38_S 6 +#define AM_REG_GPIO_INT1STAT_GPIO38_M 0x00000040 +#define AM_REG_GPIO_INT1STAT_GPIO38(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO37 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO37_S 5 +#define AM_REG_GPIO_INT1STAT_GPIO37_M 0x00000020 +#define AM_REG_GPIO_INT1STAT_GPIO37(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO36 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO36_S 4 +#define AM_REG_GPIO_INT1STAT_GPIO36_M 0x00000010 +#define AM_REG_GPIO_INT1STAT_GPIO36(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO35 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO35_S 3 +#define AM_REG_GPIO_INT1STAT_GPIO35_M 0x00000008 +#define AM_REG_GPIO_INT1STAT_GPIO35(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO34 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO34_S 2 +#define AM_REG_GPIO_INT1STAT_GPIO34_M 0x00000004 +#define AM_REG_GPIO_INT1STAT_GPIO34(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO33 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO33_S 1 +#define AM_REG_GPIO_INT1STAT_GPIO33_M 0x00000002 +#define AM_REG_GPIO_INT1STAT_GPIO33(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO32 interrupt. +#define AM_REG_GPIO_INT1STAT_GPIO32_S 0 +#define AM_REG_GPIO_INT1STAT_GPIO32_M 0x00000001 +#define AM_REG_GPIO_INT1STAT_GPIO32(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT1CLR - GPIO Interrupt Registers 49-32: Clear +// +//***************************************************************************** +// GPIO49 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO49_S 17 +#define AM_REG_GPIO_INT1CLR_GPIO49_M 0x00020000 +#define AM_REG_GPIO_INT1CLR_GPIO49(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO48 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO48_S 16 +#define AM_REG_GPIO_INT1CLR_GPIO48_M 0x00010000 +#define AM_REG_GPIO_INT1CLR_GPIO48(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO47 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO47_S 15 +#define AM_REG_GPIO_INT1CLR_GPIO47_M 0x00008000 +#define AM_REG_GPIO_INT1CLR_GPIO47(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO46 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO46_S 14 +#define AM_REG_GPIO_INT1CLR_GPIO46_M 0x00004000 +#define AM_REG_GPIO_INT1CLR_GPIO46(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO45 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO45_S 13 +#define AM_REG_GPIO_INT1CLR_GPIO45_M 0x00002000 +#define AM_REG_GPIO_INT1CLR_GPIO45(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO44 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO44_S 12 +#define AM_REG_GPIO_INT1CLR_GPIO44_M 0x00001000 +#define AM_REG_GPIO_INT1CLR_GPIO44(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO43 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO43_S 11 +#define AM_REG_GPIO_INT1CLR_GPIO43_M 0x00000800 +#define AM_REG_GPIO_INT1CLR_GPIO43(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO42 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO42_S 10 +#define AM_REG_GPIO_INT1CLR_GPIO42_M 0x00000400 +#define AM_REG_GPIO_INT1CLR_GPIO42(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO41 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO41_S 9 +#define AM_REG_GPIO_INT1CLR_GPIO41_M 0x00000200 +#define AM_REG_GPIO_INT1CLR_GPIO41(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO40 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO40_S 8 +#define AM_REG_GPIO_INT1CLR_GPIO40_M 0x00000100 +#define AM_REG_GPIO_INT1CLR_GPIO40(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO39 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO39_S 7 +#define AM_REG_GPIO_INT1CLR_GPIO39_M 0x00000080 +#define AM_REG_GPIO_INT1CLR_GPIO39(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO38 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO38_S 6 +#define AM_REG_GPIO_INT1CLR_GPIO38_M 0x00000040 +#define AM_REG_GPIO_INT1CLR_GPIO38(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO37 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO37_S 5 +#define AM_REG_GPIO_INT1CLR_GPIO37_M 0x00000020 +#define AM_REG_GPIO_INT1CLR_GPIO37(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO36 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO36_S 4 +#define AM_REG_GPIO_INT1CLR_GPIO36_M 0x00000010 +#define AM_REG_GPIO_INT1CLR_GPIO36(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO35 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO35_S 3 +#define AM_REG_GPIO_INT1CLR_GPIO35_M 0x00000008 +#define AM_REG_GPIO_INT1CLR_GPIO35(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO34 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO34_S 2 +#define AM_REG_GPIO_INT1CLR_GPIO34_M 0x00000004 +#define AM_REG_GPIO_INT1CLR_GPIO34(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO33 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO33_S 1 +#define AM_REG_GPIO_INT1CLR_GPIO33_M 0x00000002 +#define AM_REG_GPIO_INT1CLR_GPIO33(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO32 interrupt. +#define AM_REG_GPIO_INT1CLR_GPIO32_S 0 +#define AM_REG_GPIO_INT1CLR_GPIO32_M 0x00000001 +#define AM_REG_GPIO_INT1CLR_GPIO32(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_INT1SET - GPIO Interrupt Registers 49-32: Set +// +//***************************************************************************** +// GPIO49 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO49_S 17 +#define AM_REG_GPIO_INT1SET_GPIO49_M 0x00020000 +#define AM_REG_GPIO_INT1SET_GPIO49(n) (((uint32_t)(n) << 17) & 0x00020000) + +// GPIO48 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO48_S 16 +#define AM_REG_GPIO_INT1SET_GPIO48_M 0x00010000 +#define AM_REG_GPIO_INT1SET_GPIO48(n) (((uint32_t)(n) << 16) & 0x00010000) + +// GPIO47 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO47_S 15 +#define AM_REG_GPIO_INT1SET_GPIO47_M 0x00008000 +#define AM_REG_GPIO_INT1SET_GPIO47(n) (((uint32_t)(n) << 15) & 0x00008000) + +// GPIO46 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO46_S 14 +#define AM_REG_GPIO_INT1SET_GPIO46_M 0x00004000 +#define AM_REG_GPIO_INT1SET_GPIO46(n) (((uint32_t)(n) << 14) & 0x00004000) + +// GPIO45 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO45_S 13 +#define AM_REG_GPIO_INT1SET_GPIO45_M 0x00002000 +#define AM_REG_GPIO_INT1SET_GPIO45(n) (((uint32_t)(n) << 13) & 0x00002000) + +// GPIO44 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO44_S 12 +#define AM_REG_GPIO_INT1SET_GPIO44_M 0x00001000 +#define AM_REG_GPIO_INT1SET_GPIO44(n) (((uint32_t)(n) << 12) & 0x00001000) + +// GPIO43 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO43_S 11 +#define AM_REG_GPIO_INT1SET_GPIO43_M 0x00000800 +#define AM_REG_GPIO_INT1SET_GPIO43(n) (((uint32_t)(n) << 11) & 0x00000800) + +// GPIO42 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO42_S 10 +#define AM_REG_GPIO_INT1SET_GPIO42_M 0x00000400 +#define AM_REG_GPIO_INT1SET_GPIO42(n) (((uint32_t)(n) << 10) & 0x00000400) + +// GPIO41 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO41_S 9 +#define AM_REG_GPIO_INT1SET_GPIO41_M 0x00000200 +#define AM_REG_GPIO_INT1SET_GPIO41(n) (((uint32_t)(n) << 9) & 0x00000200) + +// GPIO40 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO40_S 8 +#define AM_REG_GPIO_INT1SET_GPIO40_M 0x00000100 +#define AM_REG_GPIO_INT1SET_GPIO40(n) (((uint32_t)(n) << 8) & 0x00000100) + +// GPIO39 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO39_S 7 +#define AM_REG_GPIO_INT1SET_GPIO39_M 0x00000080 +#define AM_REG_GPIO_INT1SET_GPIO39(n) (((uint32_t)(n) << 7) & 0x00000080) + +// GPIO38 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO38_S 6 +#define AM_REG_GPIO_INT1SET_GPIO38_M 0x00000040 +#define AM_REG_GPIO_INT1SET_GPIO38(n) (((uint32_t)(n) << 6) & 0x00000040) + +// GPIO37 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO37_S 5 +#define AM_REG_GPIO_INT1SET_GPIO37_M 0x00000020 +#define AM_REG_GPIO_INT1SET_GPIO37(n) (((uint32_t)(n) << 5) & 0x00000020) + +// GPIO36 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO36_S 4 +#define AM_REG_GPIO_INT1SET_GPIO36_M 0x00000010 +#define AM_REG_GPIO_INT1SET_GPIO36(n) (((uint32_t)(n) << 4) & 0x00000010) + +// GPIO35 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO35_S 3 +#define AM_REG_GPIO_INT1SET_GPIO35_M 0x00000008 +#define AM_REG_GPIO_INT1SET_GPIO35(n) (((uint32_t)(n) << 3) & 0x00000008) + +// GPIO34 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO34_S 2 +#define AM_REG_GPIO_INT1SET_GPIO34_M 0x00000004 +#define AM_REG_GPIO_INT1SET_GPIO34(n) (((uint32_t)(n) << 2) & 0x00000004) + +// GPIO33 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO33_S 1 +#define AM_REG_GPIO_INT1SET_GPIO33_M 0x00000002 +#define AM_REG_GPIO_INT1SET_GPIO33(n) (((uint32_t)(n) << 1) & 0x00000002) + +// GPIO32 interrupt. +#define AM_REG_GPIO_INT1SET_GPIO32_S 0 +#define AM_REG_GPIO_INT1SET_GPIO32_M 0x00000001 +#define AM_REG_GPIO_INT1SET_GPIO32(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_PADREGA - Pad Configuration Register A +// +//***************************************************************************** +// Pad 3 function select +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_S 27 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_UA0RTS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_SLnCE 0x08000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_M1nCE4 0x10000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_GPIO3 0x18000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_MxnCELB 0x20000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_M2nCE0 0x28000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_TRIG1 0x30000000 +#define AM_REG_GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK 0x38000000 + +// Pad 3 drive strength. +#define AM_REG_GPIO_PADREGA_PAD3STRNG_S 26 +#define AM_REG_GPIO_PADREGA_PAD3STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGA_PAD3STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGA_PAD3STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD3STRNG_HIGH 0x04000000 + +// Pad 3 input enable. +#define AM_REG_GPIO_PADREGA_PAD3INPEN_S 25 +#define AM_REG_GPIO_PADREGA_PAD3INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGA_PAD3INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGA_PAD3INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD3INPEN_EN 0x02000000 + +// Pad 3 pullup enable +#define AM_REG_GPIO_PADREGA_PAD3PULL_S 24 +#define AM_REG_GPIO_PADREGA_PAD3PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGA_PAD3PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGA_PAD3PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD3PULL_EN 0x01000000 + +// Pad 2 function select +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_S 19 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_SLWIR3 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_SLMOSI 0x00080000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_UART0RX 0x00100000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_GPIO2 0x00180000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_MxMOSILB 0x00200000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_M2MOSI 0x00280000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_MxWIR3LB 0x00300000 +#define AM_REG_GPIO_PADREGA_PAD2FNCSEL_M2WIR3 0x00380000 + +// Pad 2 drive strength +#define AM_REG_GPIO_PADREGA_PAD2STRNG_S 18 +#define AM_REG_GPIO_PADREGA_PAD2STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGA_PAD2STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGA_PAD2STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD2STRNG_HIGH 0x00040000 + +// Pad 2 input enable +#define AM_REG_GPIO_PADREGA_PAD2INPEN_S 17 +#define AM_REG_GPIO_PADREGA_PAD2INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGA_PAD2INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGA_PAD2INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD2INPEN_EN 0x00020000 + +// Pad 2 pullup enable +#define AM_REG_GPIO_PADREGA_PAD2PULL_S 16 +#define AM_REG_GPIO_PADREGA_PAD2PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGA_PAD2PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGA_PAD2PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD2PULL_EN 0x00010000 + +// Pad 1 pullup resistor selection. +#define AM_REG_GPIO_PADREGA_PAD1RSEL_S 14 +#define AM_REG_GPIO_PADREGA_PAD1RSEL_M 0x0000C000 +#define AM_REG_GPIO_PADREGA_PAD1RSEL(n) (((uint32_t)(n) << 14) & 0x0000C000) +#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL6K 0x00004000 +#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL12K 0x00008000 +#define AM_REG_GPIO_PADREGA_PAD1RSEL_PULL24K 0x0000C000 + +// Pad 1 function select +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_S 11 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_SLSDA 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_SLMISO 0x00000800 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_UART0TX 0x00001000 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_GPIO1 0x00001800 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_MxMISOLB 0x00002000 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_M2MISO 0x00002800 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_MxSDALB 0x00003000 +#define AM_REG_GPIO_PADREGA_PAD1FNCSEL_M2SDA 0x00003800 + +// Pad 1 drive strength +#define AM_REG_GPIO_PADREGA_PAD1STRNG_S 10 +#define AM_REG_GPIO_PADREGA_PAD1STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGA_PAD1STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGA_PAD1STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD1STRNG_HIGH 0x00000400 + +// Pad 1 input enable +#define AM_REG_GPIO_PADREGA_PAD1INPEN_S 9 +#define AM_REG_GPIO_PADREGA_PAD1INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGA_PAD1INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGA_PAD1INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD1INPEN_EN 0x00000200 + +// Pad 1 pullup enable +#define AM_REG_GPIO_PADREGA_PAD1PULL_S 8 +#define AM_REG_GPIO_PADREGA_PAD1PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGA_PAD1PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGA_PAD1PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD1PULL_EN 0x00000100 + +// Pad 0 pullup resistor selection. +#define AM_REG_GPIO_PADREGA_PAD0RSEL_S 6 +#define AM_REG_GPIO_PADREGA_PAD0RSEL_M 0x000000C0 +#define AM_REG_GPIO_PADREGA_PAD0RSEL(n) (((uint32_t)(n) << 6) & 0x000000C0) +#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL6K 0x00000040 +#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL12K 0x00000080 +#define AM_REG_GPIO_PADREGA_PAD0RSEL_PULL24K 0x000000C0 + +// Pad 0 function select +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_S 3 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_SLSCL 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_SLSCK 0x00000008 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_CLKOUT 0x00000010 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_GPIO0 0x00000018 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_MxSCKLB 0x00000020 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_M2SCK 0x00000028 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_MxSCLLB 0x00000030 +#define AM_REG_GPIO_PADREGA_PAD0FNCSEL_M2SCL 0x00000038 + +// Pad 0 drive strength +#define AM_REG_GPIO_PADREGA_PAD0STRNG_S 2 +#define AM_REG_GPIO_PADREGA_PAD0STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGA_PAD0STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGA_PAD0STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD0STRNG_HIGH 0x00000004 + +// Pad 0 input enable +#define AM_REG_GPIO_PADREGA_PAD0INPEN_S 1 +#define AM_REG_GPIO_PADREGA_PAD0INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGA_PAD0INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGA_PAD0INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD0INPEN_EN 0x00000002 + +// Pad 0 pullup enable +#define AM_REG_GPIO_PADREGA_PAD0PULL_S 0 +#define AM_REG_GPIO_PADREGA_PAD0PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGA_PAD0PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGA_PAD0PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGA_PAD0PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGB - Pad Configuration Register B +// +//***************************************************************************** +// Pad 7 function select +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_S 27 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M0WIR3 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M0MOSI 0x08000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_CLKOUT 0x10000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_GPIO7 0x18000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_TRIG0 0x20000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_UART0TX 0x28000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_SLWIR3LB 0x30000000 +#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M1nCE1 0x38000000 + +// Pad 7 drive strength +#define AM_REG_GPIO_PADREGB_PAD7STRNG_S 26 +#define AM_REG_GPIO_PADREGB_PAD7STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGB_PAD7STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGB_PAD7STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD7STRNG_HIGH 0x04000000 + +// Pad 7 input enable +#define AM_REG_GPIO_PADREGB_PAD7INPEN_S 25 +#define AM_REG_GPIO_PADREGB_PAD7INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGB_PAD7INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGB_PAD7INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD7INPEN_EN 0x02000000 + +// Pad 7 pullup enable +#define AM_REG_GPIO_PADREGB_PAD7PULL_S 24 +#define AM_REG_GPIO_PADREGB_PAD7PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGB_PAD7PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGB_PAD7PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD7PULL_EN 0x01000000 + +// Pad 6 pullup resistor selection. +#define AM_REG_GPIO_PADREGB_PAD6RSEL_S 22 +#define AM_REG_GPIO_PADREGB_PAD6RSEL_M 0x00C00000 +#define AM_REG_GPIO_PADREGB_PAD6RSEL(n) (((uint32_t)(n) << 22) & 0x00C00000) +#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL6K 0x00400000 +#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL12K 0x00800000 +#define AM_REG_GPIO_PADREGB_PAD6RSEL_PULL24K 0x00C00000 + +// Pad 6 function select +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_S 19 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M0SDA 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M0MISO 0x00080000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_UA0CTS 0x00100000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_GPIO6 0x00180000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_SLMISOLB 0x00200000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_M1nCE0 0x00280000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_SLSDALB 0x00300000 +#define AM_REG_GPIO_PADREGB_PAD6FNCSEL_I2S_DAT 0x00380000 + +// Pad 6 drive strength +#define AM_REG_GPIO_PADREGB_PAD6STRNG_S 18 +#define AM_REG_GPIO_PADREGB_PAD6STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGB_PAD6STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGB_PAD6STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD6STRNG_HIGH 0x00040000 + +// Pad 6 input enable +#define AM_REG_GPIO_PADREGB_PAD6INPEN_S 17 +#define AM_REG_GPIO_PADREGB_PAD6INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGB_PAD6INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGB_PAD6INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD6INPEN_EN 0x00020000 + +// Pad 6 pullup enable +#define AM_REG_GPIO_PADREGB_PAD6PULL_S 16 +#define AM_REG_GPIO_PADREGB_PAD6PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGB_PAD6PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGB_PAD6PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD6PULL_EN 0x00010000 + +// Pad 5 pullup resistor selection. +#define AM_REG_GPIO_PADREGB_PAD5RSEL_S 14 +#define AM_REG_GPIO_PADREGB_PAD5RSEL_M 0x0000C000 +#define AM_REG_GPIO_PADREGB_PAD5RSEL(n) (((uint32_t)(n) << 14) & 0x0000C000) +#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL6K 0x00004000 +#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL12K 0x00008000 +#define AM_REG_GPIO_PADREGB_PAD5RSEL_PULL24K 0x0000C000 + +// Pad 5 function select +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_S 11 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCL 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCK 0x00000800 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_UA0RTS 0x00001000 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_GPIO5 0x00001800 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCKLB 0x00002000 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_EXTHFA 0x00002800 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M0SCLLB 0x00003000 +#define AM_REG_GPIO_PADREGB_PAD5FNCSEL_M1nCE2 0x00003800 + +// Pad 5 drive strength +#define AM_REG_GPIO_PADREGB_PAD5STRNG_S 10 +#define AM_REG_GPIO_PADREGB_PAD5STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGB_PAD5STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGB_PAD5STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD5STRNG_HIGH 0x00000400 + +// Pad 5 input enable +#define AM_REG_GPIO_PADREGB_PAD5INPEN_S 9 +#define AM_REG_GPIO_PADREGB_PAD5INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGB_PAD5INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGB_PAD5INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD5INPEN_EN 0x00000200 + +// Pad 5 pullup enable +#define AM_REG_GPIO_PADREGB_PAD5PULL_S 8 +#define AM_REG_GPIO_PADREGB_PAD5PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGB_PAD5PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGB_PAD5PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD5PULL_EN 0x00000100 + +// Pad 4 VSS power switch enable +#define AM_REG_GPIO_PADREGB_PAD4PWRDN_S 7 +#define AM_REG_GPIO_PADREGB_PAD4PWRDN_M 0x00000080 +#define AM_REG_GPIO_PADREGB_PAD4PWRDN(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_PADREGB_PAD4PWRDN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD4PWRDN_EN 0x00000080 + +// Pad 4 function select +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_S 3 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_UA0CTS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_SLINT 0x00000008 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_M0nCE5 0x00000010 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_GPIO4 0x00000018 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_SLINTGP 0x00000020 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_M2nCE5 0x00000028 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_CLKOUT 0x00000030 +#define AM_REG_GPIO_PADREGB_PAD4FNCSEL_32khz_XT 0x00000038 + +// Pad 4 drive strength +#define AM_REG_GPIO_PADREGB_PAD4STRNG_S 2 +#define AM_REG_GPIO_PADREGB_PAD4STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGB_PAD4STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGB_PAD4STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD4STRNG_HIGH 0x00000004 + +// Pad 4 input enable +#define AM_REG_GPIO_PADREGB_PAD4INPEN_S 1 +#define AM_REG_GPIO_PADREGB_PAD4INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGB_PAD4INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGB_PAD4INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD4INPEN_EN 0x00000002 + +// Pad 4 pullup enable +#define AM_REG_GPIO_PADREGB_PAD4PULL_S 0 +#define AM_REG_GPIO_PADREGB_PAD4PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGB_PAD4PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGB_PAD4PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGB_PAD4PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGC - Pad Configuration Register C +// +//***************************************************************************** +// Pad 11 function select +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_S 27 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_ADCSE2 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_M0nCE0 0x08000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_CLKOUT 0x10000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_GPIO11 0x18000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_M2nCE7 0x20000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UA1CTS 0x28000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UART0RX 0x30000000 +#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_PDM_DATA 0x38000000 + +// Pad 11 drive strength +#define AM_REG_GPIO_PADREGC_PAD11STRNG_S 26 +#define AM_REG_GPIO_PADREGC_PAD11STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGC_PAD11STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGC_PAD11STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD11STRNG_HIGH 0x04000000 + +// Pad 11 input enable +#define AM_REG_GPIO_PADREGC_PAD11INPEN_S 25 +#define AM_REG_GPIO_PADREGC_PAD11INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGC_PAD11INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGC_PAD11INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD11INPEN_EN 0x02000000 + +// Pad 11 pullup enable +#define AM_REG_GPIO_PADREGC_PAD11PULL_S 24 +#define AM_REG_GPIO_PADREGC_PAD11PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGC_PAD11PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGC_PAD11PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD11PULL_EN 0x01000000 + +// Pad 10 function select +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_S 19 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M1WIR3 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M1MOSI 0x00080000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M0nCE6 0x00100000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_GPIO10 0x00180000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M2nCE6 0x00200000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_UA1RTS 0x00280000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_M4nCE4 0x00300000 +#define AM_REG_GPIO_PADREGC_PAD10FNCSEL_SLWIR3LB 0x00380000 + +// Pad 10 drive strength +#define AM_REG_GPIO_PADREGC_PAD10STRNG_S 18 +#define AM_REG_GPIO_PADREGC_PAD10STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGC_PAD10STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGC_PAD10STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD10STRNG_HIGH 0x00040000 + +// Pad 10 input enable +#define AM_REG_GPIO_PADREGC_PAD10INPEN_S 17 +#define AM_REG_GPIO_PADREGC_PAD10INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGC_PAD10INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGC_PAD10INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD10INPEN_EN 0x00020000 + +// Pad 10 pullup enable +#define AM_REG_GPIO_PADREGC_PAD10PULL_S 16 +#define AM_REG_GPIO_PADREGC_PAD10PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGC_PAD10PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGC_PAD10PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD10PULL_EN 0x00010000 + +// Pad 9 pullup resistor selection +#define AM_REG_GPIO_PADREGC_PAD9RSEL_S 14 +#define AM_REG_GPIO_PADREGC_PAD9RSEL_M 0x0000C000 +#define AM_REG_GPIO_PADREGC_PAD9RSEL(n) (((uint32_t)(n) << 14) & 0x0000C000) +#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL6K 0x00004000 +#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL12K 0x00008000 +#define AM_REG_GPIO_PADREGC_PAD9RSEL_PULL24K 0x0000C000 + +// Pad 9 function select +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_S 11 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M1SDA 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M1MISO 0x00000800 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M0nCE5 0x00001000 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_GPIO9 0x00001800 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_M4nCE5 0x00002000 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_SLMISOLB 0x00002800 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_UART1RX 0x00003000 +#define AM_REG_GPIO_PADREGC_PAD9FNCSEL_SLSDALB 0x00003800 + +// Pad 9 drive strength +#define AM_REG_GPIO_PADREGC_PAD9STRNG_S 10 +#define AM_REG_GPIO_PADREGC_PAD9STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGC_PAD9STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGC_PAD9STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD9STRNG_HIGH 0x00000400 + +// Pad 9 input enable +#define AM_REG_GPIO_PADREGC_PAD9INPEN_S 9 +#define AM_REG_GPIO_PADREGC_PAD9INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGC_PAD9INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGC_PAD9INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD9INPEN_EN 0x00000200 + +// Pad 9 pullup enable +#define AM_REG_GPIO_PADREGC_PAD9PULL_S 8 +#define AM_REG_GPIO_PADREGC_PAD9PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGC_PAD9PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGC_PAD9PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD9PULL_EN 0x00000100 + +// Pad 8 pullup resistor selection. +#define AM_REG_GPIO_PADREGC_PAD8RSEL_S 6 +#define AM_REG_GPIO_PADREGC_PAD8RSEL_M 0x000000C0 +#define AM_REG_GPIO_PADREGC_PAD8RSEL(n) (((uint32_t)(n) << 6) & 0x000000C0) +#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL6K 0x00000040 +#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL12K 0x00000080 +#define AM_REG_GPIO_PADREGC_PAD8RSEL_PULL24K 0x000000C0 + +// Pad 8 function select +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_S 3 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCL 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCK 0x00000008 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M0nCE4 0x00000010 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_GPIO8 0x00000018 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M2nCE4 0x00000020 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCKLB 0x00000028 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_UART1TX 0x00000030 +#define AM_REG_GPIO_PADREGC_PAD8FNCSEL_M1SCLLB 0x00000038 + +// Pad 8 drive strength +#define AM_REG_GPIO_PADREGC_PAD8STRNG_S 2 +#define AM_REG_GPIO_PADREGC_PAD8STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGC_PAD8STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGC_PAD8STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD8STRNG_HIGH 0x00000004 + +// Pad 8 input enable +#define AM_REG_GPIO_PADREGC_PAD8INPEN_S 1 +#define AM_REG_GPIO_PADREGC_PAD8INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGC_PAD8INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGC_PAD8INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD8INPEN_EN 0x00000002 + +// Pad 8 pullup enable +#define AM_REG_GPIO_PADREGC_PAD8PULL_S 0 +#define AM_REG_GPIO_PADREGC_PAD8PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGC_PAD8PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGC_PAD8PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGC_PAD8PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGD - Pad Configuration Register D +// +//***************************************************************************** +// Pad 15 function select +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_S 27 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_ADCD1N 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_M1nCE3 0x08000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_UART1RX 0x10000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_GPIO15 0x18000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_M2nCE2 0x20000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_EXTXT 0x28000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWDIO 0x30000000 +#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWO 0x38000000 + +// Pad 15 drive strength +#define AM_REG_GPIO_PADREGD_PAD15STRNG_S 26 +#define AM_REG_GPIO_PADREGD_PAD15STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGD_PAD15STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGD_PAD15STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD15STRNG_HIGH 0x04000000 + +// Pad 15 input enable +#define AM_REG_GPIO_PADREGD_PAD15INPEN_S 25 +#define AM_REG_GPIO_PADREGD_PAD15INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGD_PAD15INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGD_PAD15INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD15INPEN_EN 0x02000000 + +// Pad 15 pullup enable +#define AM_REG_GPIO_PADREGD_PAD15PULL_S 24 +#define AM_REG_GPIO_PADREGD_PAD15PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGD_PAD15PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGD_PAD15PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD15PULL_EN 0x01000000 + +// Pad 14 function select +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_S 19 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_ADCD1P 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_M1nCE2 0x00080000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_UART1TX 0x00100000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_GPIO14 0x00180000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_M2nCE1 0x00200000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_EXTHFS 0x00280000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_SWDCK 0x00300000 +#define AM_REG_GPIO_PADREGD_PAD14FNCSEL_32khz_XT 0x00380000 + +// Pad 14 drive strength +#define AM_REG_GPIO_PADREGD_PAD14STRNG_S 18 +#define AM_REG_GPIO_PADREGD_PAD14STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGD_PAD14STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGD_PAD14STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD14STRNG_HIGH 0x00040000 + +// Pad 14 input enable +#define AM_REG_GPIO_PADREGD_PAD14INPEN_S 17 +#define AM_REG_GPIO_PADREGD_PAD14INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGD_PAD14INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGD_PAD14INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD14INPEN_EN 0x00020000 + +// Pad 14 pullup enable +#define AM_REG_GPIO_PADREGD_PAD14PULL_S 16 +#define AM_REG_GPIO_PADREGD_PAD14PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGD_PAD14PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGD_PAD14PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD14PULL_EN 0x00010000 + +// Pad 13 function select +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_S 11 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_M1nCE1 0x00000800 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_TCTB0 0x00001000 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_GPIO13 0x00001800 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_M2nCE3 0x00002000 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_EXTHFB 0x00002800 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_UA0RTS 0x00003000 +#define AM_REG_GPIO_PADREGD_PAD13FNCSEL_UART1RX 0x00003800 + +// Pad 13 drive strength +#define AM_REG_GPIO_PADREGD_PAD13STRNG_S 10 +#define AM_REG_GPIO_PADREGD_PAD13STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGD_PAD13STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGD_PAD13STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD13STRNG_HIGH 0x00000400 + +// Pad 13 input enable +#define AM_REG_GPIO_PADREGD_PAD13INPEN_S 9 +#define AM_REG_GPIO_PADREGD_PAD13INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGD_PAD13INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGD_PAD13INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD13INPEN_EN 0x00000200 + +// Pad 13 pullup enable +#define AM_REG_GPIO_PADREGD_PAD13PULL_S 8 +#define AM_REG_GPIO_PADREGD_PAD13PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGD_PAD13PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGD_PAD13PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD13PULL_EN 0x00000100 + +// Pad 12 function select +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_S 3 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_M1nCE0 0x00000008 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_TCTA0 0x00000010 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_GPIO12 0x00000018 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_CLKOUT 0x00000020 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_PDM_CLK 0x00000028 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_UA0CTS 0x00000030 +#define AM_REG_GPIO_PADREGD_PAD12FNCSEL_UART1TX 0x00000038 + +// Pad 12 drive strength +#define AM_REG_GPIO_PADREGD_PAD12STRNG_S 2 +#define AM_REG_GPIO_PADREGD_PAD12STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGD_PAD12STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGD_PAD12STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD12STRNG_HIGH 0x00000004 + +// Pad 12 input enable +#define AM_REG_GPIO_PADREGD_PAD12INPEN_S 1 +#define AM_REG_GPIO_PADREGD_PAD12INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGD_PAD12INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGD_PAD12INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD12INPEN_EN 0x00000002 + +// Pad 12 pullup enable +#define AM_REG_GPIO_PADREGD_PAD12PULL_S 0 +#define AM_REG_GPIO_PADREGD_PAD12PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGD_PAD12PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGD_PAD12PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGD_PAD12PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGE - Pad Configuration Register E +// +//***************************************************************************** +// Pad 19 function select +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_S 27 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_CMPRF0 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_M0nCE3 0x08000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_TCTB1 0x10000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_GPIO19 0x18000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_TCTA1 0x20000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_ANATEST1 0x28000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_UART1RX 0x30000000 +#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_I2S_BCLK 0x38000000 + +// Pad 19 drive strength +#define AM_REG_GPIO_PADREGE_PAD19STRNG_S 26 +#define AM_REG_GPIO_PADREGE_PAD19STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGE_PAD19STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGE_PAD19STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD19STRNG_HIGH 0x04000000 + +// Pad 19 input enable +#define AM_REG_GPIO_PADREGE_PAD19INPEN_S 25 +#define AM_REG_GPIO_PADREGE_PAD19INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGE_PAD19INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGE_PAD19INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD19INPEN_EN 0x02000000 + +// Pad 19 pullup enable +#define AM_REG_GPIO_PADREGE_PAD19PULL_S 24 +#define AM_REG_GPIO_PADREGE_PAD19PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGE_PAD19PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGE_PAD19PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD19PULL_EN 0x01000000 + +// Pad 18 function select +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_S 19 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_CMPIN1 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_M0nCE2 0x00080000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_TCTA1 0x00100000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_GPIO18 0x00180000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_M4nCE1 0x00200000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_ANATEST2 0x00280000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_UART1TX 0x00300000 +#define AM_REG_GPIO_PADREGE_PAD18FNCSEL_32khz_XT 0x00380000 + +// Pad 18 drive strength +#define AM_REG_GPIO_PADREGE_PAD18STRNG_S 18 +#define AM_REG_GPIO_PADREGE_PAD18STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGE_PAD18STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGE_PAD18STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD18STRNG_HIGH 0x00040000 + +// Pad 18 input enable +#define AM_REG_GPIO_PADREGE_PAD18INPEN_S 17 +#define AM_REG_GPIO_PADREGE_PAD18INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGE_PAD18INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGE_PAD18INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD18INPEN_EN 0x00020000 + +// Pad 18 pullup enable +#define AM_REG_GPIO_PADREGE_PAD18PULL_S 16 +#define AM_REG_GPIO_PADREGE_PAD18PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGE_PAD18PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGE_PAD18PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD18PULL_EN 0x00010000 + +// Pad 17 function select +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_S 11 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_CMPRF1 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_M0nCE1 0x00000800 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_TRIG1 0x00001000 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_GPIO17 0x00001800 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_M4nCE3 0x00002000 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_EXTLF 0x00002800 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_UART0RX 0x00003000 +#define AM_REG_GPIO_PADREGE_PAD17FNCSEL_UA1CTS 0x00003800 + +// Pad 17 drive strength +#define AM_REG_GPIO_PADREGE_PAD17STRNG_S 10 +#define AM_REG_GPIO_PADREGE_PAD17STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGE_PAD17STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGE_PAD17STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD17STRNG_HIGH 0x00000400 + +// Pad 17 input enable +#define AM_REG_GPIO_PADREGE_PAD17INPEN_S 9 +#define AM_REG_GPIO_PADREGE_PAD17INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGE_PAD17INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGE_PAD17INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD17INPEN_EN 0x00000200 + +// Pad 17 pullup enable +#define AM_REG_GPIO_PADREGE_PAD17PULL_S 8 +#define AM_REG_GPIO_PADREGE_PAD17PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGE_PAD17PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGE_PAD17PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD17PULL_EN 0x00000100 + +// Pad 16 function select +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_S 3 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_ADCSE0 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_M0nCE4 0x00000008 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_TRIG0 0x00000010 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_GPIO16 0x00000018 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_M2nCE3 0x00000020 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_CMPIN0 0x00000028 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_UART0TX 0x00000030 +#define AM_REG_GPIO_PADREGE_PAD16FNCSEL_UA1RTS 0x00000038 + +// Pad 16 drive strength +#define AM_REG_GPIO_PADREGE_PAD16STRNG_S 2 +#define AM_REG_GPIO_PADREGE_PAD16STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGE_PAD16STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGE_PAD16STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD16STRNG_HIGH 0x00000004 + +// Pad 16 input enable +#define AM_REG_GPIO_PADREGE_PAD16INPEN_S 1 +#define AM_REG_GPIO_PADREGE_PAD16INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGE_PAD16INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGE_PAD16INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD16INPEN_EN 0x00000002 + +// Pad 16 pullup enable +#define AM_REG_GPIO_PADREGE_PAD16PULL_S 0 +#define AM_REG_GPIO_PADREGE_PAD16PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGE_PAD16PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGE_PAD16PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGE_PAD16PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGF - Pad Configuration Register F +// +//***************************************************************************** +// Pad 23 function select +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_S 27 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UART0RX 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_M0nCE0 0x08000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB3 0x10000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_GPIO23 0x18000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_PDM_DATA 0x20000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_CMPOUT 0x28000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB1 0x30000000 +#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UNDEF7 0x38000000 + +// Pad 23 drive strength +#define AM_REG_GPIO_PADREGF_PAD23STRNG_S 26 +#define AM_REG_GPIO_PADREGF_PAD23STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGF_PAD23STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGF_PAD23STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD23STRNG_HIGH 0x04000000 + +// Pad 23 input enable +#define AM_REG_GPIO_PADREGF_PAD23INPEN_S 25 +#define AM_REG_GPIO_PADREGF_PAD23INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGF_PAD23INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGF_PAD23INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD23INPEN_EN 0x02000000 + +// Pad 23 pullup enable +#define AM_REG_GPIO_PADREGF_PAD23PULL_S 24 +#define AM_REG_GPIO_PADREGF_PAD23PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGF_PAD23PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGF_PAD23PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD23PULL_EN 0x01000000 + +// Pad 22 upper power switch enable +#define AM_REG_GPIO_PADREGF_PAD22PWRUP_S 23 +#define AM_REG_GPIO_PADREGF_PAD22PWRUP_M 0x00800000 +#define AM_REG_GPIO_PADREGF_PAD22PWRUP(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_PADREGF_PAD22PWRUP_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD22PWRUP_EN 0x00800000 + +// Pad 22 function select +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_S 19 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_UART0TX 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_M1nCE7 0x00080000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_TCTA3 0x00100000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_GPIO22 0x00180000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_PDM_CLK 0x00200000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_UNDEF5 0x00280000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_TCTB1 0x00300000 +#define AM_REG_GPIO_PADREGF_PAD22FNCSEL_SWO 0x00380000 + +// Pad 22 drive strength +#define AM_REG_GPIO_PADREGF_PAD22STRNG_S 18 +#define AM_REG_GPIO_PADREGF_PAD22STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGF_PAD22STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGF_PAD22STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD22STRNG_HIGH 0x00040000 + +// Pad 22 input enable +#define AM_REG_GPIO_PADREGF_PAD22INPEN_S 17 +#define AM_REG_GPIO_PADREGF_PAD22INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGF_PAD22INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGF_PAD22INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD22INPEN_EN 0x00020000 + +// Pad 22 pullup enable +#define AM_REG_GPIO_PADREGF_PAD22PULL_S 16 +#define AM_REG_GPIO_PADREGF_PAD22PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGF_PAD22PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGF_PAD22PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD22PULL_EN 0x00010000 + +// Pad 21 function select +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_S 11 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_SWDIO 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_M1nCE6 0x00000800 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_TCTB2 0x00001000 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_GPIO21 0x00001800 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UART0RX 0x00002000 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UART1RX 0x00002800 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UNDEF6 0x00003000 +#define AM_REG_GPIO_PADREGF_PAD21FNCSEL_UNDEF7 0x00003800 + +// Pad 21 drive strength +#define AM_REG_GPIO_PADREGF_PAD21STRNG_S 10 +#define AM_REG_GPIO_PADREGF_PAD21STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGF_PAD21STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGF_PAD21STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD21STRNG_HIGH 0x00000400 + +// Pad 21 input enable +#define AM_REG_GPIO_PADREGF_PAD21INPEN_S 9 +#define AM_REG_GPIO_PADREGF_PAD21INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGF_PAD21INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGF_PAD21INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD21INPEN_EN 0x00000200 + +// Pad 21 pullup enable +#define AM_REG_GPIO_PADREGF_PAD21PULL_S 8 +#define AM_REG_GPIO_PADREGF_PAD21PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGF_PAD21PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGF_PAD21PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD21PULL_EN 0x00000100 + +// Pad 20 function select +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_S 3 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_SWDCK 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_M1nCE5 0x00000008 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_TCTA2 0x00000010 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_GPIO20 0x00000018 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UART0TX 0x00000020 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UART1TX 0x00000028 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UNDEF6 0x00000030 +#define AM_REG_GPIO_PADREGF_PAD20FNCSEL_UNDEF7 0x00000038 + +// Pad 20 drive strength +#define AM_REG_GPIO_PADREGF_PAD20STRNG_S 2 +#define AM_REG_GPIO_PADREGF_PAD20STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGF_PAD20STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGF_PAD20STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD20STRNG_HIGH 0x00000004 + +// Pad 20 input enable +#define AM_REG_GPIO_PADREGF_PAD20INPEN_S 1 +#define AM_REG_GPIO_PADREGF_PAD20INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGF_PAD20INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGF_PAD20INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD20INPEN_EN 0x00000002 + +// Pad 20 pulldown enable +#define AM_REG_GPIO_PADREGF_PAD20PULL_S 0 +#define AM_REG_GPIO_PADREGF_PAD20PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGF_PAD20PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGF_PAD20PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGF_PAD20PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGG - Pad Configuration Register G +// +//***************************************************************************** +// Pad 27 pullup resistor selection. +#define AM_REG_GPIO_PADREGG_PAD27RSEL_S 30 +#define AM_REG_GPIO_PADREGG_PAD27RSEL_M 0xC0000000 +#define AM_REG_GPIO_PADREGG_PAD27RSEL(n) (((uint32_t)(n) << 30) & 0xC0000000) +#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL6K 0x40000000 +#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL12K 0x80000000 +#define AM_REG_GPIO_PADREGG_PAD27RSEL_PULL24K 0xC0000000 + +// Pad 27 function select +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_S 27 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_EXTHF 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M1nCE4 0x08000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_TCTA1 0x10000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_GPIO27 0x18000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCL 0x20000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCK 0x28000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCKLB 0x30000000 +#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCLLB 0x38000000 + +// Pad 27 drive strength +#define AM_REG_GPIO_PADREGG_PAD27STRNG_S 26 +#define AM_REG_GPIO_PADREGG_PAD27STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGG_PAD27STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGG_PAD27STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD27STRNG_HIGH 0x04000000 + +// Pad 27 input enable +#define AM_REG_GPIO_PADREGG_PAD27INPEN_S 25 +#define AM_REG_GPIO_PADREGG_PAD27INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGG_PAD27INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGG_PAD27INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD27INPEN_EN 0x02000000 + +// Pad 27 pullup enable +#define AM_REG_GPIO_PADREGG_PAD27PULL_S 24 +#define AM_REG_GPIO_PADREGG_PAD27PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGG_PAD27PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGG_PAD27PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD27PULL_EN 0x01000000 + +// Pad 26 function select +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_S 19 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_EXTLF 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M0nCE3 0x00080000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_TCTB0 0x00100000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_GPIO26 0x00180000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M2nCE0 0x00200000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_TCTA1 0x00280000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M5nCE1 0x00300000 +#define AM_REG_GPIO_PADREGG_PAD26FNCSEL_M3nCE0 0x00380000 + +// Pad 26 drive strength +#define AM_REG_GPIO_PADREGG_PAD26STRNG_S 18 +#define AM_REG_GPIO_PADREGG_PAD26STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGG_PAD26STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGG_PAD26STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD26STRNG_HIGH 0x00040000 + +// Pad 26 input enable +#define AM_REG_GPIO_PADREGG_PAD26INPEN_S 17 +#define AM_REG_GPIO_PADREGG_PAD26INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGG_PAD26INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGG_PAD26INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD26INPEN_EN 0x00020000 + +// Pad 26 pullup enable +#define AM_REG_GPIO_PADREGG_PAD26PULL_S 16 +#define AM_REG_GPIO_PADREGG_PAD26PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGG_PAD26PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGG_PAD26PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD26PULL_EN 0x00010000 + +// Pad 25 pullup resistor selection. +#define AM_REG_GPIO_PADREGG_PAD25RSEL_S 14 +#define AM_REG_GPIO_PADREGG_PAD25RSEL_M 0x0000C000 +#define AM_REG_GPIO_PADREGG_PAD25RSEL(n) (((uint32_t)(n) << 14) & 0x0000C000) +#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL6K 0x00004000 +#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL12K 0x00008000 +#define AM_REG_GPIO_PADREGG_PAD25RSEL_PULL24K 0x0000C000 + +// Pad 25 function select +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_S 11 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_EXTXT 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M0nCE2 0x00000800 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_TCTA0 0x00001000 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_GPIO25 0x00001800 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M2SDA 0x00002000 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_M2MISO 0x00002800 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_SLMISOLB 0x00003000 +#define AM_REG_GPIO_PADREGG_PAD25FNCSEL_SLSDALB 0x00003800 + +// Pad 25 drive strength +#define AM_REG_GPIO_PADREGG_PAD25STRNG_S 10 +#define AM_REG_GPIO_PADREGG_PAD25STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGG_PAD25STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGG_PAD25STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD25STRNG_HIGH 0x00000400 + +// Pad 25 input enable +#define AM_REG_GPIO_PADREGG_PAD25INPEN_S 9 +#define AM_REG_GPIO_PADREGG_PAD25INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGG_PAD25INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGG_PAD25INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD25INPEN_EN 0x00000200 + +// Pad 25 pullup enable +#define AM_REG_GPIO_PADREGG_PAD25PULL_S 8 +#define AM_REG_GPIO_PADREGG_PAD25PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGG_PAD25PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGG_PAD25PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD25PULL_EN 0x00000100 + +// Pad 24 function select +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_S 3 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M2nCE1 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M0nCE1 0x00000008 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_CLKOUT 0x00000010 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_GPIO24 0x00000018 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_M5nCE0 0x00000020 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_TCTA1 0x00000028 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_I2S_BCLK 0x00000030 +#define AM_REG_GPIO_PADREGG_PAD24FNCSEL_SWO 0x00000038 + +// Pad 24 drive strength +#define AM_REG_GPIO_PADREGG_PAD24STRNG_S 2 +#define AM_REG_GPIO_PADREGG_PAD24STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGG_PAD24STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGG_PAD24STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD24STRNG_HIGH 0x00000004 + +// Pad 24 input enable +#define AM_REG_GPIO_PADREGG_PAD24INPEN_S 1 +#define AM_REG_GPIO_PADREGG_PAD24INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGG_PAD24INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGG_PAD24INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD24INPEN_EN 0x00000002 + +// Pad 24 pullup enable +#define AM_REG_GPIO_PADREGG_PAD24PULL_S 0 +#define AM_REG_GPIO_PADREGG_PAD24PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGG_PAD24PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGG_PAD24PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGG_PAD24PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGH - Pad Configuration Register H +// +//***************************************************************************** +// Pad 31 function select +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_S 27 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_ADCSE3 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_M0nCE4 0x08000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_TCTA3 0x10000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_GPIO31 0x18000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UART0RX 0x20000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_TCTB1 0x28000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF6 0x30000000 +#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF7 0x38000000 + +// Pad 31 drive strength +#define AM_REG_GPIO_PADREGH_PAD31STRNG_S 26 +#define AM_REG_GPIO_PADREGH_PAD31STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGH_PAD31STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGH_PAD31STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD31STRNG_HIGH 0x04000000 + +// Pad 31 input enable +#define AM_REG_GPIO_PADREGH_PAD31INPEN_S 25 +#define AM_REG_GPIO_PADREGH_PAD31INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGH_PAD31INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGH_PAD31INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD31INPEN_EN 0x02000000 + +// Pad 31 pullup enable +#define AM_REG_GPIO_PADREGH_PAD31PULL_S 24 +#define AM_REG_GPIO_PADREGH_PAD31PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGH_PAD31PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGH_PAD31PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD31PULL_EN 0x01000000 + +// Pad 30 function select +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_S 19 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UNDEF0 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_M1nCE7 0x00080000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_TCTB2 0x00100000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_GPIO30 0x00180000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UART0TX 0x00200000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UA1RTS 0x00280000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_UNDEF6 0x00300000 +#define AM_REG_GPIO_PADREGH_PAD30FNCSEL_I2S_DAT 0x00380000 + +// Pad 30 drive strength +#define AM_REG_GPIO_PADREGH_PAD30STRNG_S 18 +#define AM_REG_GPIO_PADREGH_PAD30STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGH_PAD30STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGH_PAD30STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD30STRNG_HIGH 0x00040000 + +// Pad 30 input enable +#define AM_REG_GPIO_PADREGH_PAD30INPEN_S 17 +#define AM_REG_GPIO_PADREGH_PAD30INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGH_PAD30INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGH_PAD30INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD30INPEN_EN 0x00020000 + +// Pad 30 pullup enable +#define AM_REG_GPIO_PADREGH_PAD30PULL_S 16 +#define AM_REG_GPIO_PADREGH_PAD30PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGH_PAD30PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGH_PAD30PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD30PULL_EN 0x00010000 + +// Pad 29 function select +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_S 11 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_ADCSE1 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_M1nCE6 0x00000800 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_TCTA2 0x00001000 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_GPIO29 0x00001800 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_UA0CTS 0x00002000 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_UA1CTS 0x00002800 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_M4nCE0 0x00003000 +#define AM_REG_GPIO_PADREGH_PAD29FNCSEL_PDM_DATA 0x00003800 + +// Pad 29 drive strength +#define AM_REG_GPIO_PADREGH_PAD29STRNG_S 10 +#define AM_REG_GPIO_PADREGH_PAD29STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGH_PAD29STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGH_PAD29STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD29STRNG_HIGH 0x00000400 + +// Pad 29 input enable +#define AM_REG_GPIO_PADREGH_PAD29INPEN_S 9 +#define AM_REG_GPIO_PADREGH_PAD29INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGH_PAD29INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGH_PAD29INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD29INPEN_EN 0x00000200 + +// Pad 29 pullup enable +#define AM_REG_GPIO_PADREGH_PAD29PULL_S 8 +#define AM_REG_GPIO_PADREGH_PAD29PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGH_PAD29PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGH_PAD29PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD29PULL_EN 0x00000100 + +// Pad 28 function select +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_S 3 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M1nCE5 0x00000008 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_TCTB1 0x00000010 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_GPIO28 0x00000018 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M2WIR3 0x00000020 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M2MOSI 0x00000028 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_M5nCE3 0x00000030 +#define AM_REG_GPIO_PADREGH_PAD28FNCSEL_SLWIR3LB 0x00000038 + +// Pad 28 drive strength +#define AM_REG_GPIO_PADREGH_PAD28STRNG_S 2 +#define AM_REG_GPIO_PADREGH_PAD28STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGH_PAD28STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGH_PAD28STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD28STRNG_HIGH 0x00000004 + +// Pad 28 input enable +#define AM_REG_GPIO_PADREGH_PAD28INPEN_S 1 +#define AM_REG_GPIO_PADREGH_PAD28INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGH_PAD28INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGH_PAD28INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD28INPEN_EN 0x00000002 + +// Pad 28 pullup enable +#define AM_REG_GPIO_PADREGH_PAD28PULL_S 0 +#define AM_REG_GPIO_PADREGH_PAD28PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGH_PAD28PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGH_PAD28PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGH_PAD28PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGI - Pad Configuration Register I +// +//***************************************************************************** +// Pad 35 function select +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_S 27 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_ADCSE7 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M1nCE0 0x08000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UART1TX 0x10000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_GPIO35 0x18000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M4nCE6 0x20000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_TCTA1 0x28000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UA0RTS 0x30000000 +#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M3nCE2 0x38000000 + +// Pad 35 drive strength +#define AM_REG_GPIO_PADREGI_PAD35STRNG_S 26 +#define AM_REG_GPIO_PADREGI_PAD35STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGI_PAD35STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGI_PAD35STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD35STRNG_HIGH 0x04000000 + +// Pad 35 input enable +#define AM_REG_GPIO_PADREGI_PAD35INPEN_S 25 +#define AM_REG_GPIO_PADREGI_PAD35INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGI_PAD35INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGI_PAD35INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD35INPEN_EN 0x02000000 + +// Pad 35 pullup enable +#define AM_REG_GPIO_PADREGI_PAD35PULL_S 24 +#define AM_REG_GPIO_PADREGI_PAD35PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGI_PAD35PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGI_PAD35PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD35PULL_EN 0x01000000 + +// Pad 34 function select +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_S 19 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_ADCSE6 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M0nCE7 0x00080000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M2nCE3 0x00100000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_GPIO34 0x00180000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_CMPRF2 0x00200000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M3nCE1 0x00280000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M4nCE0 0x00300000 +#define AM_REG_GPIO_PADREGI_PAD34FNCSEL_M5nCE2 0x00380000 + +// Pad 34 drive strength +#define AM_REG_GPIO_PADREGI_PAD34STRNG_S 18 +#define AM_REG_GPIO_PADREGI_PAD34STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGI_PAD34STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGI_PAD34STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD34STRNG_HIGH 0x00040000 + +// Pad 34 input enable +#define AM_REG_GPIO_PADREGI_PAD34INPEN_S 17 +#define AM_REG_GPIO_PADREGI_PAD34INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGI_PAD34INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGI_PAD34INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD34INPEN_EN 0x00020000 + +// Pad 34 pullup enable +#define AM_REG_GPIO_PADREGI_PAD34PULL_S 16 +#define AM_REG_GPIO_PADREGI_PAD34PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGI_PAD34PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGI_PAD34PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD34PULL_EN 0x00010000 + +// Pad 33 function select +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_S 11 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_ADCSE5 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_M0nCE6 0x00000800 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_32khz_XT 0x00001000 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_GPIO33 0x00001800 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_UNDEF4 0x00002000 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_M3nCE7 0x00002800 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_TCTB1 0x00003000 +#define AM_REG_GPIO_PADREGI_PAD33FNCSEL_SWO 0x00003800 + +// Pad 33 drive strength +#define AM_REG_GPIO_PADREGI_PAD33STRNG_S 10 +#define AM_REG_GPIO_PADREGI_PAD33STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGI_PAD33STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGI_PAD33STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD33STRNG_HIGH 0x00000400 + +// Pad 33 input enable +#define AM_REG_GPIO_PADREGI_PAD33INPEN_S 9 +#define AM_REG_GPIO_PADREGI_PAD33INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGI_PAD33INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGI_PAD33INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD33INPEN_EN 0x00000200 + +// Pad 33 pullup enable +#define AM_REG_GPIO_PADREGI_PAD33PULL_S 8 +#define AM_REG_GPIO_PADREGI_PAD33PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGI_PAD33PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGI_PAD33PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD33PULL_EN 0x00000100 + +// Pad 32 function select +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_S 3 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_ADCSE4 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_M0nCE5 0x00000008 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_TCTB3 0x00000010 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_GPIO32 0x00000018 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_UNDEF4 0x00000020 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_TCTB1 0x00000028 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_UNDEF6 0x00000030 +#define AM_REG_GPIO_PADREGI_PAD32FNCSEL_UNDEF7 0x00000038 + +// Pad 32 drive strength +#define AM_REG_GPIO_PADREGI_PAD32STRNG_S 2 +#define AM_REG_GPIO_PADREGI_PAD32STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGI_PAD32STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGI_PAD32STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD32STRNG_HIGH 0x00000004 + +// Pad 32 input enable +#define AM_REG_GPIO_PADREGI_PAD32INPEN_S 1 +#define AM_REG_GPIO_PADREGI_PAD32INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGI_PAD32INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGI_PAD32INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD32INPEN_EN 0x00000002 + +// Pad 32 pullup enable +#define AM_REG_GPIO_PADREGI_PAD32PULL_S 0 +#define AM_REG_GPIO_PADREGI_PAD32PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGI_PAD32PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGI_PAD32PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGI_PAD32PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGJ - Pad Configuration Register J +// +//***************************************************************************** +// Pad 39 pullup resistor selection. +#define AM_REG_GPIO_PADREGJ_PAD39RSEL_S 30 +#define AM_REG_GPIO_PADREGJ_PAD39RSEL_M 0xC0000000 +#define AM_REG_GPIO_PADREGJ_PAD39RSEL(n) (((uint32_t)(n) << 30) & 0xC0000000) +#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL6K 0x40000000 +#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL12K 0x80000000 +#define AM_REG_GPIO_PADREGJ_PAD39RSEL_PULL24K 0xC0000000 + +// Pad 39 function select +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_S 27 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_UART0TX 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_UART1TX 0x08000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_CLKOUT 0x10000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_GPIO39 0x18000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCL 0x20000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCK 0x28000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCKLB 0x30000000 +#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCLLB 0x38000000 + +// Pad 39 drive strength +#define AM_REG_GPIO_PADREGJ_PAD39STRNG_S 26 +#define AM_REG_GPIO_PADREGJ_PAD39STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGJ_PAD39STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGJ_PAD39STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD39STRNG_HIGH 0x04000000 + +// Pad 39 input enable +#define AM_REG_GPIO_PADREGJ_PAD39INPEN_S 25 +#define AM_REG_GPIO_PADREGJ_PAD39INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGJ_PAD39INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGJ_PAD39INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD39INPEN_EN 0x02000000 + +// Pad 39 pullup enable +#define AM_REG_GPIO_PADREGJ_PAD39PULL_S 24 +#define AM_REG_GPIO_PADREGJ_PAD39PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGJ_PAD39PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGJ_PAD39PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD39PULL_EN 0x01000000 + +// Pad 38 function select +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_S 19 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_TRIG3 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M1nCE3 0x00080000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_UA0CTS 0x00100000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_GPIO38 0x00180000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M3WIR3 0x00200000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M3MOSI 0x00280000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_M4nCE7 0x00300000 +#define AM_REG_GPIO_PADREGJ_PAD38FNCSEL_SLWIR3LB 0x00380000 + +// Pad 38 drive strength +#define AM_REG_GPIO_PADREGJ_PAD38STRNG_S 18 +#define AM_REG_GPIO_PADREGJ_PAD38STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGJ_PAD38STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGJ_PAD38STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD38STRNG_HIGH 0x00040000 + +// Pad 38 input enable +#define AM_REG_GPIO_PADREGJ_PAD38INPEN_S 17 +#define AM_REG_GPIO_PADREGJ_PAD38INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGJ_PAD38INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGJ_PAD38INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD38INPEN_EN 0x00020000 + +// Pad 38 pullup enable +#define AM_REG_GPIO_PADREGJ_PAD38PULL_S 16 +#define AM_REG_GPIO_PADREGJ_PAD38PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGJ_PAD38PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGJ_PAD38PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD38PULL_EN 0x00010000 + +// Pad 37 function select +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_S 11 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_TRIG2 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M1nCE2 0x00000800 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_UA0RTS 0x00001000 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_GPIO37 0x00001800 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M3nCE4 0x00002000 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_M4nCE1 0x00002800 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_PDM_CLK 0x00003000 +#define AM_REG_GPIO_PADREGJ_PAD37FNCSEL_TCTA1 0x00003800 + +// Pad 37 drive strength +#define AM_REG_GPIO_PADREGJ_PAD37STRNG_S 10 +#define AM_REG_GPIO_PADREGJ_PAD37STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGJ_PAD37STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGJ_PAD37STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD37STRNG_HIGH 0x00000400 + +// Pad 37 input enable +#define AM_REG_GPIO_PADREGJ_PAD37INPEN_S 9 +#define AM_REG_GPIO_PADREGJ_PAD37INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGJ_PAD37INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGJ_PAD37INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD37INPEN_EN 0x00000200 + +// Pad 37 pullup enable +#define AM_REG_GPIO_PADREGJ_PAD37PULL_S 8 +#define AM_REG_GPIO_PADREGJ_PAD37PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGJ_PAD37PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGJ_PAD37PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD37PULL_EN 0x00000100 + +// Pad 36 function select +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_S 3 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_TRIG1 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M1nCE1 0x00000008 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_UART1RX 0x00000010 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_GPIO36 0x00000018 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_32khz_XT 0x00000020 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M2nCE0 0x00000028 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_UA0CTS 0x00000030 +#define AM_REG_GPIO_PADREGJ_PAD36FNCSEL_M3nCE3 0x00000038 + +// Pad 36 drive strength +#define AM_REG_GPIO_PADREGJ_PAD36STRNG_S 2 +#define AM_REG_GPIO_PADREGJ_PAD36STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGJ_PAD36STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGJ_PAD36STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD36STRNG_HIGH 0x00000004 + +// Pad 36 input enable +#define AM_REG_GPIO_PADREGJ_PAD36INPEN_S 1 +#define AM_REG_GPIO_PADREGJ_PAD36INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGJ_PAD36INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGJ_PAD36INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD36INPEN_EN 0x00000002 + +// Pad 36 pullup enable +#define AM_REG_GPIO_PADREGJ_PAD36PULL_S 0 +#define AM_REG_GPIO_PADREGJ_PAD36PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGJ_PAD36PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGJ_PAD36PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGJ_PAD36PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGK - Pad Configuration Register K +// +//***************************************************************************** +// Pad 43 pullup resistor selection. +#define AM_REG_GPIO_PADREGK_PAD43RSEL_S 30 +#define AM_REG_GPIO_PADREGK_PAD43RSEL_M 0xC0000000 +#define AM_REG_GPIO_PADREGK_PAD43RSEL(n) (((uint32_t)(n) << 30) & 0xC0000000) +#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL6K 0x40000000 +#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL12K 0x80000000 +#define AM_REG_GPIO_PADREGK_PAD43RSEL_PULL24K 0xC0000000 + +// Pad 43 function select +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_S 27 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M2nCE4 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M0nCE1 0x08000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_TCTB0 0x10000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_GPIO43 0x18000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M3SDA 0x20000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_M3MISO 0x28000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLMISOLB 0x30000000 +#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLSDALB 0x38000000 + +// Pad 43 drive strength +#define AM_REG_GPIO_PADREGK_PAD43STRNG_S 26 +#define AM_REG_GPIO_PADREGK_PAD43STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGK_PAD43STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGK_PAD43STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD43STRNG_HIGH 0x04000000 + +// Pad 43 input enable +#define AM_REG_GPIO_PADREGK_PAD43INPEN_S 25 +#define AM_REG_GPIO_PADREGK_PAD43INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGK_PAD43INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGK_PAD43INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD43INPEN_EN 0x02000000 + +// Pad 43 pullup enable +#define AM_REG_GPIO_PADREGK_PAD43PULL_S 24 +#define AM_REG_GPIO_PADREGK_PAD43PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGK_PAD43PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGK_PAD43PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD43PULL_EN 0x01000000 + +// Pad 42 pullup resistor selection. +#define AM_REG_GPIO_PADREGK_PAD42RSEL_S 22 +#define AM_REG_GPIO_PADREGK_PAD42RSEL_M 0x00C00000 +#define AM_REG_GPIO_PADREGK_PAD42RSEL(n) (((uint32_t)(n) << 22) & 0x00C00000) +#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL6K 0x00400000 +#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL12K 0x00800000 +#define AM_REG_GPIO_PADREGK_PAD42RSEL_PULL24K 0x00C00000 + +// Pad 42 function select +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_S 19 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M2nCE2 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M0nCE0 0x00080000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_TCTA0 0x00100000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_GPIO42 0x00180000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCL 0x00200000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCK 0x00280000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCKLB 0x00300000 +#define AM_REG_GPIO_PADREGK_PAD42FNCSEL_M3SCLLB 0x00380000 + +// Pad 42 drive strength +#define AM_REG_GPIO_PADREGK_PAD42STRNG_S 18 +#define AM_REG_GPIO_PADREGK_PAD42STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGK_PAD42STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGK_PAD42STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD42STRNG_HIGH 0x00040000 + +// Pad 42 input enable +#define AM_REG_GPIO_PADREGK_PAD42INPEN_S 17 +#define AM_REG_GPIO_PADREGK_PAD42INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGK_PAD42INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGK_PAD42INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD42INPEN_EN 0x00020000 + +// Pad 42 pullup enable +#define AM_REG_GPIO_PADREGK_PAD42PULL_S 16 +#define AM_REG_GPIO_PADREGK_PAD42PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGK_PAD42PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGK_PAD42PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD42PULL_EN 0x00010000 + +// Pad 41 upper power switch enable +#define AM_REG_GPIO_PADREGK_PAD41PWRUP_S 15 +#define AM_REG_GPIO_PADREGK_PAD41PWRUP_M 0x00008000 +#define AM_REG_GPIO_PADREGK_PAD41PWRUP(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_PADREGK_PAD41PWRUP_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD41PWRUP_EN 0x00008000 + +// Pad 41 function select +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_S 11 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M2nCE1 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_CLKOUT 0x00000800 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_SWO 0x00001000 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_GPIO41 0x00001800 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M3nCE5 0x00002000 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M5nCE7 0x00002800 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_M4nCE2 0x00003000 +#define AM_REG_GPIO_PADREGK_PAD41FNCSEL_UA0RTS 0x00003800 + +// Pad 41 drive strength +#define AM_REG_GPIO_PADREGK_PAD41STRNG_S 10 +#define AM_REG_GPIO_PADREGK_PAD41STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGK_PAD41STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGK_PAD41STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD41STRNG_HIGH 0x00000400 + +// Pad 41 input enable +#define AM_REG_GPIO_PADREGK_PAD41INPEN_S 9 +#define AM_REG_GPIO_PADREGK_PAD41INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGK_PAD41INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGK_PAD41INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD41INPEN_EN 0x00000200 + +// Pad 41 pullup enable +#define AM_REG_GPIO_PADREGK_PAD41PULL_S 8 +#define AM_REG_GPIO_PADREGK_PAD41PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGK_PAD41PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGK_PAD41PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD41PULL_EN 0x00000100 + +// Pad 40 pullup resistor selection. +#define AM_REG_GPIO_PADREGK_PAD40RSEL_S 6 +#define AM_REG_GPIO_PADREGK_PAD40RSEL_M 0x000000C0 +#define AM_REG_GPIO_PADREGK_PAD40RSEL(n) (((uint32_t)(n) << 6) & 0x000000C0) +#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL6K 0x00000040 +#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL12K 0x00000080 +#define AM_REG_GPIO_PADREGK_PAD40RSEL_PULL24K 0x000000C0 + +// Pad 40 function select +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_S 3 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_UART0RX 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_UART1RX 0x00000008 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_TRIG0 0x00000010 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_GPIO40 0x00000018 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_M4SDA 0x00000020 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_M4MISO 0x00000028 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_SLMISOLB 0x00000030 +#define AM_REG_GPIO_PADREGK_PAD40FNCSEL_SLSDALB 0x00000038 + +// Pad 40 drive strength +#define AM_REG_GPIO_PADREGK_PAD40STRNG_S 2 +#define AM_REG_GPIO_PADREGK_PAD40STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGK_PAD40STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGK_PAD40STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD40STRNG_HIGH 0x00000004 + +// Pad 40 input enable +#define AM_REG_GPIO_PADREGK_PAD40INPEN_S 1 +#define AM_REG_GPIO_PADREGK_PAD40INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGK_PAD40INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGK_PAD40INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD40INPEN_EN 0x00000002 + +// Pad 40 pullup enable +#define AM_REG_GPIO_PADREGK_PAD40PULL_S 0 +#define AM_REG_GPIO_PADREGK_PAD40PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGK_PAD40PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGK_PAD40PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGK_PAD40PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGL - Pad Configuration Register L +// +//***************************************************************************** +// Pad 47 function select +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_S 27 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M 0x38000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M2nCE5 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M0nCE5 0x08000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_TCTB2 0x10000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_GPIO47 0x18000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M5WIR3 0x20000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M5MOSI 0x28000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M4nCE5 0x30000000 +#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_SLWIR3LB 0x38000000 + +// Pad 47 drive strength +#define AM_REG_GPIO_PADREGL_PAD47STRNG_S 26 +#define AM_REG_GPIO_PADREGL_PAD47STRNG_M 0x04000000 +#define AM_REG_GPIO_PADREGL_PAD47STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_GPIO_PADREGL_PAD47STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD47STRNG_HIGH 0x04000000 + +// Pad 47 input enable +#define AM_REG_GPIO_PADREGL_PAD47INPEN_S 25 +#define AM_REG_GPIO_PADREGL_PAD47INPEN_M 0x02000000 +#define AM_REG_GPIO_PADREGL_PAD47INPEN(n) (((uint32_t)(n) << 25) & 0x02000000) +#define AM_REG_GPIO_PADREGL_PAD47INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD47INPEN_EN 0x02000000 + +// Pad 47 pullup enable +#define AM_REG_GPIO_PADREGL_PAD47PULL_S 24 +#define AM_REG_GPIO_PADREGL_PAD47PULL_M 0x01000000 +#define AM_REG_GPIO_PADREGL_PAD47PULL(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_PADREGL_PAD47PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD47PULL_EN 0x01000000 + +// Pad 46 function select +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_S 19 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M 0x00380000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL(n) (((uint32_t)(n) << 19) & 0x00380000) +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_32khz_XT 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M0nCE4 0x00080000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_TCTA2 0x00100000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_GPIO46 0x00180000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_TCTA1 0x00200000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M5nCE4 0x00280000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_M4nCE4 0x00300000 +#define AM_REG_GPIO_PADREGL_PAD46FNCSEL_SWO 0x00380000 + +// Pad 46 drive strength +#define AM_REG_GPIO_PADREGL_PAD46STRNG_S 18 +#define AM_REG_GPIO_PADREGL_PAD46STRNG_M 0x00040000 +#define AM_REG_GPIO_PADREGL_PAD46STRNG(n) (((uint32_t)(n) << 18) & 0x00040000) +#define AM_REG_GPIO_PADREGL_PAD46STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD46STRNG_HIGH 0x00040000 + +// Pad 46 input enable +#define AM_REG_GPIO_PADREGL_PAD46INPEN_S 17 +#define AM_REG_GPIO_PADREGL_PAD46INPEN_M 0x00020000 +#define AM_REG_GPIO_PADREGL_PAD46INPEN(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_GPIO_PADREGL_PAD46INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD46INPEN_EN 0x00020000 + +// Pad 46 pullup enable +#define AM_REG_GPIO_PADREGL_PAD46PULL_S 16 +#define AM_REG_GPIO_PADREGL_PAD46PULL_M 0x00010000 +#define AM_REG_GPIO_PADREGL_PAD46PULL(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_PADREGL_PAD46PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD46PULL_EN 0x00010000 + +// Pad 45 function select +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_S 11 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_UA1CTS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M0nCE3 0x00000800 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_TCTB1 0x00001000 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_GPIO45 0x00001800 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M4nCE3 0x00002000 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M3nCE6 0x00002800 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_M5nCE5 0x00003000 +#define AM_REG_GPIO_PADREGL_PAD45FNCSEL_TCTA1 0x00003800 + +// Pad 45 drive strength +#define AM_REG_GPIO_PADREGL_PAD45STRNG_S 10 +#define AM_REG_GPIO_PADREGL_PAD45STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGL_PAD45STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGL_PAD45STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD45STRNG_HIGH 0x00000400 + +// Pad 45 input enable +#define AM_REG_GPIO_PADREGL_PAD45INPEN_S 9 +#define AM_REG_GPIO_PADREGL_PAD45INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGL_PAD45INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGL_PAD45INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD45INPEN_EN 0x00000200 + +// Pad 45 pullup enable +#define AM_REG_GPIO_PADREGL_PAD45PULL_S 8 +#define AM_REG_GPIO_PADREGL_PAD45PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGL_PAD45PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGL_PAD45PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD45PULL_EN 0x00000100 + +// Pad 44 function select +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_S 3 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_UA1RTS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M0nCE2 0x00000008 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_TCTA1 0x00000010 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_GPIO44 0x00000018 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M4WIR3 0x00000020 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M4MOSI 0x00000028 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_M5nCE6 0x00000030 +#define AM_REG_GPIO_PADREGL_PAD44FNCSEL_SLWIR3LB 0x00000038 + +// Pad 44 drive strength +#define AM_REG_GPIO_PADREGL_PAD44STRNG_S 2 +#define AM_REG_GPIO_PADREGL_PAD44STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGL_PAD44STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGL_PAD44STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD44STRNG_HIGH 0x00000004 + +// Pad 44 input enable +#define AM_REG_GPIO_PADREGL_PAD44INPEN_S 1 +#define AM_REG_GPIO_PADREGL_PAD44INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGL_PAD44INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGL_PAD44INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD44INPEN_EN 0x00000002 + +// Pad 44 pullup enable +#define AM_REG_GPIO_PADREGL_PAD44PULL_S 0 +#define AM_REG_GPIO_PADREGL_PAD44PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGL_PAD44PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGL_PAD44PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGL_PAD44PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_PADREGM - Pad Configuration Register M +// +//***************************************************************************** +// Pad 49 pullup resistor selection. +#define AM_REG_GPIO_PADREGM_PAD49RSEL_S 14 +#define AM_REG_GPIO_PADREGM_PAD49RSEL_M 0x0000C000 +#define AM_REG_GPIO_PADREGM_PAD49RSEL(n) (((uint32_t)(n) << 14) & 0x0000C000) +#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL6K 0x00004000 +#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL12K 0x00008000 +#define AM_REG_GPIO_PADREGM_PAD49RSEL_PULL24K 0x0000C000 + +// Pad 49 function select +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_S 11 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M 0x00003800 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL(n) (((uint32_t)(n) << 11) & 0x00003800) +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M2nCE7 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M0nCE7 0x00000800 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_TCTB3 0x00001000 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_GPIO49 0x00001800 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M5SDA 0x00002000 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_M5MISO 0x00002800 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_SLMISOLB 0x00003000 +#define AM_REG_GPIO_PADREGM_PAD49FNCSEL_SLSDALB 0x00003800 + +// Pad 49 drive strength +#define AM_REG_GPIO_PADREGM_PAD49STRNG_S 10 +#define AM_REG_GPIO_PADREGM_PAD49STRNG_M 0x00000400 +#define AM_REG_GPIO_PADREGM_PAD49STRNG(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_GPIO_PADREGM_PAD49STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD49STRNG_HIGH 0x00000400 + +// Pad 49 input enable +#define AM_REG_GPIO_PADREGM_PAD49INPEN_S 9 +#define AM_REG_GPIO_PADREGM_PAD49INPEN_M 0x00000200 +#define AM_REG_GPIO_PADREGM_PAD49INPEN(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_GPIO_PADREGM_PAD49INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD49INPEN_EN 0x00000200 + +// Pad 49 pullup enable +#define AM_REG_GPIO_PADREGM_PAD49PULL_S 8 +#define AM_REG_GPIO_PADREGM_PAD49PULL_M 0x00000100 +#define AM_REG_GPIO_PADREGM_PAD49PULL(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_PADREGM_PAD49PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD49PULL_EN 0x00000100 + +// Pad 48 pullup resistor selection. +#define AM_REG_GPIO_PADREGM_PAD48RSEL_S 6 +#define AM_REG_GPIO_PADREGM_PAD48RSEL_M 0x000000C0 +#define AM_REG_GPIO_PADREGM_PAD48RSEL(n) (((uint32_t)(n) << 6) & 0x000000C0) +#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL1_5K 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL6K 0x00000040 +#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL12K 0x00000080 +#define AM_REG_GPIO_PADREGM_PAD48RSEL_PULL24K 0x000000C0 + +// Pad 48 function select +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_S 3 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M 0x00000038 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL(n) (((uint32_t)(n) << 3) & 0x00000038) +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M2nCE6 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M0nCE6 0x00000008 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_TCTA3 0x00000010 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_GPIO48 0x00000018 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCL 0x00000020 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCK 0x00000028 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCKLB 0x00000030 +#define AM_REG_GPIO_PADREGM_PAD48FNCSEL_M5SCLLB 0x00000038 + +// Pad 48 drive strength +#define AM_REG_GPIO_PADREGM_PAD48STRNG_S 2 +#define AM_REG_GPIO_PADREGM_PAD48STRNG_M 0x00000004 +#define AM_REG_GPIO_PADREGM_PAD48STRNG(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_GPIO_PADREGM_PAD48STRNG_LOW 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD48STRNG_HIGH 0x00000004 + +// Pad 48 input enable +#define AM_REG_GPIO_PADREGM_PAD48INPEN_S 1 +#define AM_REG_GPIO_PADREGM_PAD48INPEN_M 0x00000002 +#define AM_REG_GPIO_PADREGM_PAD48INPEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_GPIO_PADREGM_PAD48INPEN_DIS 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD48INPEN_EN 0x00000002 + +// Pad 48 pullup enable +#define AM_REG_GPIO_PADREGM_PAD48PULL_S 0 +#define AM_REG_GPIO_PADREGM_PAD48PULL_M 0x00000001 +#define AM_REG_GPIO_PADREGM_PAD48PULL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_PADREGM_PAD48PULL_DIS 0x00000000 +#define AM_REG_GPIO_PADREGM_PAD48PULL_EN 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGA - GPIO Configuration Register A +// +//***************************************************************************** +// GPIO7 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO7INTD_S 31 +#define AM_REG_GPIO_CFGA_GPIO7INTD_M 0x80000000 +#define AM_REG_GPIO_CFGA_GPIO7INTD(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_GPIO_CFGA_GPIO7INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO7INTD_INTHL 0x80000000 + +// GPIO7 output configuration. +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_S 29 +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_M 0x60000000 +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG(n) (((uint32_t)(n) << 29) & 0x60000000) +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_PUSHPULL 0x20000000 +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_OD 0x40000000 +#define AM_REG_GPIO_CFGA_GPIO7OUTCFG_TS 0x60000000 + +// GPIO7 input enable. +#define AM_REG_GPIO_CFGA_GPIO7INCFG_S 28 +#define AM_REG_GPIO_CFGA_GPIO7INCFG_M 0x10000000 +#define AM_REG_GPIO_CFGA_GPIO7INCFG(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_CFGA_GPIO7INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO7INCFG_RDZERO 0x10000000 + +// GPIO6 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO6INTD_S 27 +#define AM_REG_GPIO_CFGA_GPIO6INTD_M 0x08000000 +#define AM_REG_GPIO_CFGA_GPIO6INTD(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_GPIO_CFGA_GPIO6INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO6INTD_INTHL 0x08000000 + +// GPIO6 output configuration. +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_S 25 +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_M 0x06000000 +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG(n) (((uint32_t)(n) << 25) & 0x06000000) +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_PUSHPULL 0x02000000 +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_OD 0x04000000 +#define AM_REG_GPIO_CFGA_GPIO6OUTCFG_TS 0x06000000 + +// GPIO6 input enable. +#define AM_REG_GPIO_CFGA_GPIO6INCFG_S 24 +#define AM_REG_GPIO_CFGA_GPIO6INCFG_M 0x01000000 +#define AM_REG_GPIO_CFGA_GPIO6INCFG(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_CFGA_GPIO6INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO6INCFG_RDZERO 0x01000000 + +// GPIO5 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO5INTD_S 23 +#define AM_REG_GPIO_CFGA_GPIO5INTD_M 0x00800000 +#define AM_REG_GPIO_CFGA_GPIO5INTD(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_CFGA_GPIO5INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO5INTD_INTHL 0x00800000 + +// GPIO5 output configuration. +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_S 21 +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_M 0x00600000 +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG(n) (((uint32_t)(n) << 21) & 0x00600000) +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_PUSHPULL 0x00200000 +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_OD 0x00400000 +#define AM_REG_GPIO_CFGA_GPIO5OUTCFG_TS 0x00600000 + +// GPIO5 input enable. +#define AM_REG_GPIO_CFGA_GPIO5INCFG_S 20 +#define AM_REG_GPIO_CFGA_GPIO5INCFG_M 0x00100000 +#define AM_REG_GPIO_CFGA_GPIO5INCFG(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_CFGA_GPIO5INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO5INCFG_RDZERO 0x00100000 + +// GPIO4 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO4INTD_S 19 +#define AM_REG_GPIO_CFGA_GPIO4INTD_M 0x00080000 +#define AM_REG_GPIO_CFGA_GPIO4INTD(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_GPIO_CFGA_GPIO4INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO4INTD_INTHL 0x00080000 + +// GPIO4 output configuration. +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_S 17 +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_M 0x00060000 +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_PUSHPULL 0x00020000 +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_OD 0x00040000 +#define AM_REG_GPIO_CFGA_GPIO4OUTCFG_TS 0x00060000 + +// GPIO4 input enable. +#define AM_REG_GPIO_CFGA_GPIO4INCFG_S 16 +#define AM_REG_GPIO_CFGA_GPIO4INCFG_M 0x00010000 +#define AM_REG_GPIO_CFGA_GPIO4INCFG(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_CFGA_GPIO4INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO4INCFG_RDZERO 0x00010000 + +// GPIO3 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO3INTD_S 15 +#define AM_REG_GPIO_CFGA_GPIO3INTD_M 0x00008000 +#define AM_REG_GPIO_CFGA_GPIO3INTD(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_CFGA_GPIO3INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO3INTD_INTHL 0x00008000 + +// GPIO3 output configuration. +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_S 13 +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_M 0x00006000 +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG(n) (((uint32_t)(n) << 13) & 0x00006000) +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_PUSHPULL 0x00002000 +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_OD 0x00004000 +#define AM_REG_GPIO_CFGA_GPIO3OUTCFG_TS 0x00006000 + +// GPIO3 input enable. +#define AM_REG_GPIO_CFGA_GPIO3INCFG_S 12 +#define AM_REG_GPIO_CFGA_GPIO3INCFG_M 0x00001000 +#define AM_REG_GPIO_CFGA_GPIO3INCFG(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_CFGA_GPIO3INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO3INCFG_RDZERO 0x00001000 + +// GPIO2 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO2INTD_S 11 +#define AM_REG_GPIO_CFGA_GPIO2INTD_M 0x00000800 +#define AM_REG_GPIO_CFGA_GPIO2INTD(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_GPIO_CFGA_GPIO2INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO2INTD_INTHL 0x00000800 + +// GPIO2 output configuration. +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_S 9 +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_M 0x00000600 +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG(n) (((uint32_t)(n) << 9) & 0x00000600) +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_PUSHPULL 0x00000200 +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_OD 0x00000400 +#define AM_REG_GPIO_CFGA_GPIO2OUTCFG_TS 0x00000600 + +// GPIO2 input enable. +#define AM_REG_GPIO_CFGA_GPIO2INCFG_S 8 +#define AM_REG_GPIO_CFGA_GPIO2INCFG_M 0x00000100 +#define AM_REG_GPIO_CFGA_GPIO2INCFG(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_CFGA_GPIO2INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO2INCFG_RDZERO 0x00000100 + +// GPIO1 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO1INTD_S 7 +#define AM_REG_GPIO_CFGA_GPIO1INTD_M 0x00000080 +#define AM_REG_GPIO_CFGA_GPIO1INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGA_GPIO1INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO1INTD_INTHL 0x00000080 + +// GPIO1 output configuration. +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_S 5 +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGA_GPIO1OUTCFG_TS 0x00000060 + +// GPIO1 input enable. +#define AM_REG_GPIO_CFGA_GPIO1INCFG_S 4 +#define AM_REG_GPIO_CFGA_GPIO1INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGA_GPIO1INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGA_GPIO1INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO1INCFG_RDZERO 0x00000010 + +// GPIO0 interrupt direction. +#define AM_REG_GPIO_CFGA_GPIO0INTD_S 3 +#define AM_REG_GPIO_CFGA_GPIO0INTD_M 0x00000008 +#define AM_REG_GPIO_CFGA_GPIO0INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGA_GPIO0INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO0INTD_INTHL 0x00000008 + +// GPIO0 output configuration. +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_S 1 +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGA_GPIO0OUTCFG_TS 0x00000006 + +// GPIO0 input enable. +#define AM_REG_GPIO_CFGA_GPIO0INCFG_S 0 +#define AM_REG_GPIO_CFGA_GPIO0INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGA_GPIO0INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGA_GPIO0INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGA_GPIO0INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGB - GPIO Configuration Register B +// +//***************************************************************************** +// GPIO15 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO15INTD_S 31 +#define AM_REG_GPIO_CFGB_GPIO15INTD_M 0x80000000 +#define AM_REG_GPIO_CFGB_GPIO15INTD(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_GPIO_CFGB_GPIO15INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO15INTD_INTHL 0x80000000 + +// GPIO15 output configuration. +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_S 29 +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_M 0x60000000 +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG(n) (((uint32_t)(n) << 29) & 0x60000000) +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_PUSHPULL 0x20000000 +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_OD 0x40000000 +#define AM_REG_GPIO_CFGB_GPIO15OUTCFG_TS 0x60000000 + +// GPIO15 input enable. +#define AM_REG_GPIO_CFGB_GPIO15INCFG_S 28 +#define AM_REG_GPIO_CFGB_GPIO15INCFG_M 0x10000000 +#define AM_REG_GPIO_CFGB_GPIO15INCFG(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_CFGB_GPIO15INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO15INCFG_RDZERO 0x10000000 + +// GPIO14 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO14INTD_S 27 +#define AM_REG_GPIO_CFGB_GPIO14INTD_M 0x08000000 +#define AM_REG_GPIO_CFGB_GPIO14INTD(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_GPIO_CFGB_GPIO14INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO14INTD_INTHL 0x08000000 + +// GPIO14 output configuration. +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_S 25 +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_M 0x06000000 +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG(n) (((uint32_t)(n) << 25) & 0x06000000) +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_PUSHPULL 0x02000000 +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_OD 0x04000000 +#define AM_REG_GPIO_CFGB_GPIO14OUTCFG_TS 0x06000000 + +// GPIO14 input enable. +#define AM_REG_GPIO_CFGB_GPIO14INCFG_S 24 +#define AM_REG_GPIO_CFGB_GPIO14INCFG_M 0x01000000 +#define AM_REG_GPIO_CFGB_GPIO14INCFG(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_CFGB_GPIO14INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO14INCFG_RDZERO 0x01000000 + +// GPIO13 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO13INTD_S 23 +#define AM_REG_GPIO_CFGB_GPIO13INTD_M 0x00800000 +#define AM_REG_GPIO_CFGB_GPIO13INTD(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_CFGB_GPIO13INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO13INTD_INTHL 0x00800000 + +// GPIO13 output configuration. +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_S 21 +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_M 0x00600000 +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG(n) (((uint32_t)(n) << 21) & 0x00600000) +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_PUSHPULL 0x00200000 +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_OD 0x00400000 +#define AM_REG_GPIO_CFGB_GPIO13OUTCFG_TS 0x00600000 + +// GPIO13 input enable. +#define AM_REG_GPIO_CFGB_GPIO13INCFG_S 20 +#define AM_REG_GPIO_CFGB_GPIO13INCFG_M 0x00100000 +#define AM_REG_GPIO_CFGB_GPIO13INCFG(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_CFGB_GPIO13INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO13INCFG_RDZERO 0x00100000 + +// GPIO12 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO12INTD_S 19 +#define AM_REG_GPIO_CFGB_GPIO12INTD_M 0x00080000 +#define AM_REG_GPIO_CFGB_GPIO12INTD(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_GPIO_CFGB_GPIO12INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO12INTD_INTHL 0x00080000 + +// GPIO12 output configuration. +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_S 17 +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_M 0x00060000 +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_PUSHPULL 0x00020000 +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_OD 0x00040000 +#define AM_REG_GPIO_CFGB_GPIO12OUTCFG_TS 0x00060000 + +// GPIO12 input enable. +#define AM_REG_GPIO_CFGB_GPIO12INCFG_S 16 +#define AM_REG_GPIO_CFGB_GPIO12INCFG_M 0x00010000 +#define AM_REG_GPIO_CFGB_GPIO12INCFG(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_CFGB_GPIO12INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO12INCFG_RDZERO 0x00010000 + +// GPIO11 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO11INTD_S 15 +#define AM_REG_GPIO_CFGB_GPIO11INTD_M 0x00008000 +#define AM_REG_GPIO_CFGB_GPIO11INTD(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_CFGB_GPIO11INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO11INTD_INTHL 0x00008000 + +// GPIO11 output configuration. +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_S 13 +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_M 0x00006000 +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG(n) (((uint32_t)(n) << 13) & 0x00006000) +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_PUSHPULL 0x00002000 +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_OD 0x00004000 +#define AM_REG_GPIO_CFGB_GPIO11OUTCFG_TS 0x00006000 + +// GPIO11 input enable. +#define AM_REG_GPIO_CFGB_GPIO11INCFG_S 12 +#define AM_REG_GPIO_CFGB_GPIO11INCFG_M 0x00001000 +#define AM_REG_GPIO_CFGB_GPIO11INCFG(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_CFGB_GPIO11INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO11INCFG_RDZERO 0x00001000 + +// GPIO10 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO10INTD_S 11 +#define AM_REG_GPIO_CFGB_GPIO10INTD_M 0x00000800 +#define AM_REG_GPIO_CFGB_GPIO10INTD(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_GPIO_CFGB_GPIO10INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO10INTD_INTHL 0x00000800 + +// GPIO10 output configuration. +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_S 9 +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_M 0x00000600 +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG(n) (((uint32_t)(n) << 9) & 0x00000600) +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_PUSHPULL 0x00000200 +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_OD 0x00000400 +#define AM_REG_GPIO_CFGB_GPIO10OUTCFG_TS 0x00000600 + +// GPIO10 input enable. +#define AM_REG_GPIO_CFGB_GPIO10INCFG_S 8 +#define AM_REG_GPIO_CFGB_GPIO10INCFG_M 0x00000100 +#define AM_REG_GPIO_CFGB_GPIO10INCFG(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_CFGB_GPIO10INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO10INCFG_RDZERO 0x00000100 + +// GPIO9 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO9INTD_S 7 +#define AM_REG_GPIO_CFGB_GPIO9INTD_M 0x00000080 +#define AM_REG_GPIO_CFGB_GPIO9INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGB_GPIO9INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO9INTD_INTHL 0x00000080 + +// GPIO9 output configuration. +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_S 5 +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGB_GPIO9OUTCFG_TS 0x00000060 + +// GPIO9 input enable. +#define AM_REG_GPIO_CFGB_GPIO9INCFG_S 4 +#define AM_REG_GPIO_CFGB_GPIO9INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGB_GPIO9INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGB_GPIO9INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO9INCFG_RDZERO 0x00000010 + +// GPIO8 interrupt direction. +#define AM_REG_GPIO_CFGB_GPIO8INTD_S 3 +#define AM_REG_GPIO_CFGB_GPIO8INTD_M 0x00000008 +#define AM_REG_GPIO_CFGB_GPIO8INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGB_GPIO8INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO8INTD_INTHL 0x00000008 + +// GPIO8 output configuration. +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_S 1 +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGB_GPIO8OUTCFG_TS 0x00000006 + +// GPIO8 input enable. +#define AM_REG_GPIO_CFGB_GPIO8INCFG_S 0 +#define AM_REG_GPIO_CFGB_GPIO8INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGB_GPIO8INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGB_GPIO8INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGB_GPIO8INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGC - GPIO Configuration Register C +// +//***************************************************************************** +// GPIO23 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO23INTD_S 31 +#define AM_REG_GPIO_CFGC_GPIO23INTD_M 0x80000000 +#define AM_REG_GPIO_CFGC_GPIO23INTD(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_GPIO_CFGC_GPIO23INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO23INTD_INTHL 0x80000000 + +// GPIO23 output configuration. +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_S 29 +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_M 0x60000000 +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG(n) (((uint32_t)(n) << 29) & 0x60000000) +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_PUSHPULL 0x20000000 +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_OD 0x40000000 +#define AM_REG_GPIO_CFGC_GPIO23OUTCFG_TS 0x60000000 + +// GPIO23 input enable. +#define AM_REG_GPIO_CFGC_GPIO23INCFG_S 28 +#define AM_REG_GPIO_CFGC_GPIO23INCFG_M 0x10000000 +#define AM_REG_GPIO_CFGC_GPIO23INCFG(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_CFGC_GPIO23INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO23INCFG_RDZERO 0x10000000 + +// GPIO22 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO22INTD_S 27 +#define AM_REG_GPIO_CFGC_GPIO22INTD_M 0x08000000 +#define AM_REG_GPIO_CFGC_GPIO22INTD(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_GPIO_CFGC_GPIO22INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO22INTD_INTHL 0x08000000 + +// GPIO22 output configuration. +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_S 25 +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_M 0x06000000 +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG(n) (((uint32_t)(n) << 25) & 0x06000000) +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_PUSHPULL 0x02000000 +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_OD 0x04000000 +#define AM_REG_GPIO_CFGC_GPIO22OUTCFG_TS 0x06000000 + +// GPIO22 input enable. +#define AM_REG_GPIO_CFGC_GPIO22INCFG_S 24 +#define AM_REG_GPIO_CFGC_GPIO22INCFG_M 0x01000000 +#define AM_REG_GPIO_CFGC_GPIO22INCFG(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_CFGC_GPIO22INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO22INCFG_RDZERO 0x01000000 + +// GPIO21 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO21INTD_S 23 +#define AM_REG_GPIO_CFGC_GPIO21INTD_M 0x00800000 +#define AM_REG_GPIO_CFGC_GPIO21INTD(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_CFGC_GPIO21INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO21INTD_INTHL 0x00800000 + +// GPIO21 output configuration. +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_S 21 +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_M 0x00600000 +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG(n) (((uint32_t)(n) << 21) & 0x00600000) +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_PUSHPULL 0x00200000 +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_OD 0x00400000 +#define AM_REG_GPIO_CFGC_GPIO21OUTCFG_TS 0x00600000 + +// GPIO21 input enable. +#define AM_REG_GPIO_CFGC_GPIO21INCFG_S 20 +#define AM_REG_GPIO_CFGC_GPIO21INCFG_M 0x00100000 +#define AM_REG_GPIO_CFGC_GPIO21INCFG(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_CFGC_GPIO21INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO21INCFG_RDZERO 0x00100000 + +// GPIO20 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO20INTD_S 19 +#define AM_REG_GPIO_CFGC_GPIO20INTD_M 0x00080000 +#define AM_REG_GPIO_CFGC_GPIO20INTD(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_GPIO_CFGC_GPIO20INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO20INTD_INTHL 0x00080000 + +// GPIO20 output configuration. +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_S 17 +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_M 0x00060000 +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_PUSHPULL 0x00020000 +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_OD 0x00040000 +#define AM_REG_GPIO_CFGC_GPIO20OUTCFG_TS 0x00060000 + +// GPIO20 input enable. +#define AM_REG_GPIO_CFGC_GPIO20INCFG_S 16 +#define AM_REG_GPIO_CFGC_GPIO20INCFG_M 0x00010000 +#define AM_REG_GPIO_CFGC_GPIO20INCFG(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_CFGC_GPIO20INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO20INCFG_RDZERO 0x00010000 + +// GPIO19 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO19INTD_S 15 +#define AM_REG_GPIO_CFGC_GPIO19INTD_M 0x00008000 +#define AM_REG_GPIO_CFGC_GPIO19INTD(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_CFGC_GPIO19INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO19INTD_INTHL 0x00008000 + +// GPIO19 output configuration. +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_S 13 +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_M 0x00006000 +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG(n) (((uint32_t)(n) << 13) & 0x00006000) +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_PUSHPULL 0x00002000 +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_OD 0x00004000 +#define AM_REG_GPIO_CFGC_GPIO19OUTCFG_TS 0x00006000 + +// GPIO19 input enable. +#define AM_REG_GPIO_CFGC_GPIO19INCFG_S 12 +#define AM_REG_GPIO_CFGC_GPIO19INCFG_M 0x00001000 +#define AM_REG_GPIO_CFGC_GPIO19INCFG(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_CFGC_GPIO19INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO19INCFG_RDZERO 0x00001000 + +// GPIO18 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO18INTD_S 11 +#define AM_REG_GPIO_CFGC_GPIO18INTD_M 0x00000800 +#define AM_REG_GPIO_CFGC_GPIO18INTD(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_GPIO_CFGC_GPIO18INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO18INTD_INTHL 0x00000800 + +// GPIO18 output configuration. +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_S 9 +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_M 0x00000600 +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG(n) (((uint32_t)(n) << 9) & 0x00000600) +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_PUSHPULL 0x00000200 +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_OD 0x00000400 +#define AM_REG_GPIO_CFGC_GPIO18OUTCFG_TS 0x00000600 + +// GPIO18 input enable. +#define AM_REG_GPIO_CFGC_GPIO18INCFG_S 8 +#define AM_REG_GPIO_CFGC_GPIO18INCFG_M 0x00000100 +#define AM_REG_GPIO_CFGC_GPIO18INCFG(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_CFGC_GPIO18INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO18INCFG_RDZERO 0x00000100 + +// GPIO17 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO17INTD_S 7 +#define AM_REG_GPIO_CFGC_GPIO17INTD_M 0x00000080 +#define AM_REG_GPIO_CFGC_GPIO17INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGC_GPIO17INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO17INTD_INTHL 0x00000080 + +// GPIO17 output configuration. +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_S 5 +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGC_GPIO17OUTCFG_TS 0x00000060 + +// GPIO17 input enable. +#define AM_REG_GPIO_CFGC_GPIO17INCFG_S 4 +#define AM_REG_GPIO_CFGC_GPIO17INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGC_GPIO17INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGC_GPIO17INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO17INCFG_RDZERO 0x00000010 + +// GPIO16 interrupt direction. +#define AM_REG_GPIO_CFGC_GPIO16INTD_S 3 +#define AM_REG_GPIO_CFGC_GPIO16INTD_M 0x00000008 +#define AM_REG_GPIO_CFGC_GPIO16INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGC_GPIO16INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO16INTD_INTHL 0x00000008 + +// GPIO16 output configuration. +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_S 1 +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGC_GPIO16OUTCFG_TS 0x00000006 + +// GPIO16 input enable. +#define AM_REG_GPIO_CFGC_GPIO16INCFG_S 0 +#define AM_REG_GPIO_CFGC_GPIO16INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGC_GPIO16INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGC_GPIO16INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGC_GPIO16INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGD - GPIO Configuration Register D +// +//***************************************************************************** +// GPIO31 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO31INTD_S 31 +#define AM_REG_GPIO_CFGD_GPIO31INTD_M 0x80000000 +#define AM_REG_GPIO_CFGD_GPIO31INTD(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_GPIO_CFGD_GPIO31INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO31INTD_INTHL 0x80000000 + +// GPIO31 output configuration. +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_S 29 +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_M 0x60000000 +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG(n) (((uint32_t)(n) << 29) & 0x60000000) +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_PUSHPULL 0x20000000 +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_OD 0x40000000 +#define AM_REG_GPIO_CFGD_GPIO31OUTCFG_TS 0x60000000 + +// GPIO31 input enable. +#define AM_REG_GPIO_CFGD_GPIO31INCFG_S 28 +#define AM_REG_GPIO_CFGD_GPIO31INCFG_M 0x10000000 +#define AM_REG_GPIO_CFGD_GPIO31INCFG(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_CFGD_GPIO31INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO31INCFG_RDZERO 0x10000000 + +// GPIO30 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO30INTD_S 27 +#define AM_REG_GPIO_CFGD_GPIO30INTD_M 0x08000000 +#define AM_REG_GPIO_CFGD_GPIO30INTD(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_GPIO_CFGD_GPIO30INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO30INTD_INTHL 0x08000000 + +// GPIO30 output configuration. +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_S 25 +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_M 0x06000000 +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG(n) (((uint32_t)(n) << 25) & 0x06000000) +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_PUSHPULL 0x02000000 +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_OD 0x04000000 +#define AM_REG_GPIO_CFGD_GPIO30OUTCFG_TS 0x06000000 + +// GPIO30 input enable. +#define AM_REG_GPIO_CFGD_GPIO30INCFG_S 24 +#define AM_REG_GPIO_CFGD_GPIO30INCFG_M 0x01000000 +#define AM_REG_GPIO_CFGD_GPIO30INCFG(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_CFGD_GPIO30INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO30INCFG_RDZERO 0x01000000 + +// GPIO29 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO29INTD_S 23 +#define AM_REG_GPIO_CFGD_GPIO29INTD_M 0x00800000 +#define AM_REG_GPIO_CFGD_GPIO29INTD(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_CFGD_GPIO29INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO29INTD_INTHL 0x00800000 + +// GPIO29 output configuration. +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_S 21 +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_M 0x00600000 +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG(n) (((uint32_t)(n) << 21) & 0x00600000) +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_PUSHPULL 0x00200000 +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_OD 0x00400000 +#define AM_REG_GPIO_CFGD_GPIO29OUTCFG_TS 0x00600000 + +// GPIO29 input enable. +#define AM_REG_GPIO_CFGD_GPIO29INCFG_S 20 +#define AM_REG_GPIO_CFGD_GPIO29INCFG_M 0x00100000 +#define AM_REG_GPIO_CFGD_GPIO29INCFG(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_CFGD_GPIO29INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO29INCFG_RDZERO 0x00100000 + +// GPIO28 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO28INTD_S 19 +#define AM_REG_GPIO_CFGD_GPIO28INTD_M 0x00080000 +#define AM_REG_GPIO_CFGD_GPIO28INTD(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_GPIO_CFGD_GPIO28INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO28INTD_INTHL 0x00080000 + +// GPIO28 output configuration. +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_S 17 +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_M 0x00060000 +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_PUSHPULL 0x00020000 +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_OD 0x00040000 +#define AM_REG_GPIO_CFGD_GPIO28OUTCFG_TS 0x00060000 + +// GPIO28 input enable. +#define AM_REG_GPIO_CFGD_GPIO28INCFG_S 16 +#define AM_REG_GPIO_CFGD_GPIO28INCFG_M 0x00010000 +#define AM_REG_GPIO_CFGD_GPIO28INCFG(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_CFGD_GPIO28INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO28INCFG_RDZERO 0x00010000 + +// GPIO27 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO27INTD_S 15 +#define AM_REG_GPIO_CFGD_GPIO27INTD_M 0x00008000 +#define AM_REG_GPIO_CFGD_GPIO27INTD(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_CFGD_GPIO27INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO27INTD_INTHL 0x00008000 + +// GPIO27 output configuration. +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_S 13 +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_M 0x00006000 +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG(n) (((uint32_t)(n) << 13) & 0x00006000) +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_PUSHPULL 0x00002000 +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_OD 0x00004000 +#define AM_REG_GPIO_CFGD_GPIO27OUTCFG_TS 0x00006000 + +// GPIO27 input enable. +#define AM_REG_GPIO_CFGD_GPIO27INCFG_S 12 +#define AM_REG_GPIO_CFGD_GPIO27INCFG_M 0x00001000 +#define AM_REG_GPIO_CFGD_GPIO27INCFG(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_CFGD_GPIO27INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO27INCFG_RDZERO 0x00001000 + +// GPIO26 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO26INTD_S 11 +#define AM_REG_GPIO_CFGD_GPIO26INTD_M 0x00000800 +#define AM_REG_GPIO_CFGD_GPIO26INTD(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_GPIO_CFGD_GPIO26INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO26INTD_INTHL 0x00000800 + +// GPIO26 output configuration. +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_S 9 +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_M 0x00000600 +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG(n) (((uint32_t)(n) << 9) & 0x00000600) +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_PUSHPULL 0x00000200 +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_OD 0x00000400 +#define AM_REG_GPIO_CFGD_GPIO26OUTCFG_TS 0x00000600 + +// GPIO26 input enable. +#define AM_REG_GPIO_CFGD_GPIO26INCFG_S 8 +#define AM_REG_GPIO_CFGD_GPIO26INCFG_M 0x00000100 +#define AM_REG_GPIO_CFGD_GPIO26INCFG(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_CFGD_GPIO26INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO26INCFG_RDZERO 0x00000100 + +// GPIO25 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO25INTD_S 7 +#define AM_REG_GPIO_CFGD_GPIO25INTD_M 0x00000080 +#define AM_REG_GPIO_CFGD_GPIO25INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGD_GPIO25INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO25INTD_INTHL 0x00000080 + +// GPIO25 output configuration. +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_S 5 +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGD_GPIO25OUTCFG_TS 0x00000060 + +// GPIO25 input enable. +#define AM_REG_GPIO_CFGD_GPIO25INCFG_S 4 +#define AM_REG_GPIO_CFGD_GPIO25INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGD_GPIO25INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGD_GPIO25INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO25INCFG_RDZERO 0x00000010 + +// GPIO24 interrupt direction. +#define AM_REG_GPIO_CFGD_GPIO24INTD_S 3 +#define AM_REG_GPIO_CFGD_GPIO24INTD_M 0x00000008 +#define AM_REG_GPIO_CFGD_GPIO24INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGD_GPIO24INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO24INTD_INTHL 0x00000008 + +// GPIO24 output configuration. +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_S 1 +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGD_GPIO24OUTCFG_TS 0x00000006 + +// GPIO24 input enable. +#define AM_REG_GPIO_CFGD_GPIO24INCFG_S 0 +#define AM_REG_GPIO_CFGD_GPIO24INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGD_GPIO24INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGD_GPIO24INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGD_GPIO24INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGE - GPIO Configuration Register E +// +//***************************************************************************** +// GPIO39 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO39INTD_S 31 +#define AM_REG_GPIO_CFGE_GPIO39INTD_M 0x80000000 +#define AM_REG_GPIO_CFGE_GPIO39INTD(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_GPIO_CFGE_GPIO39INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO39INTD_INTHL 0x80000000 + +// GPIO39 output configuration. +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_S 29 +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_M 0x60000000 +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG(n) (((uint32_t)(n) << 29) & 0x60000000) +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_PUSHPULL 0x20000000 +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_OD 0x40000000 +#define AM_REG_GPIO_CFGE_GPIO39OUTCFG_TS 0x60000000 + +// GPIO39 input enable. +#define AM_REG_GPIO_CFGE_GPIO39INCFG_S 28 +#define AM_REG_GPIO_CFGE_GPIO39INCFG_M 0x10000000 +#define AM_REG_GPIO_CFGE_GPIO39INCFG(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_CFGE_GPIO39INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO39INCFG_RDZERO 0x10000000 + +// GPIO38 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO38INTD_S 27 +#define AM_REG_GPIO_CFGE_GPIO38INTD_M 0x08000000 +#define AM_REG_GPIO_CFGE_GPIO38INTD(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_GPIO_CFGE_GPIO38INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO38INTD_INTHL 0x08000000 + +// GPIO38 output configuration. +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_S 25 +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_M 0x06000000 +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG(n) (((uint32_t)(n) << 25) & 0x06000000) +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_PUSHPULL 0x02000000 +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_OD 0x04000000 +#define AM_REG_GPIO_CFGE_GPIO38OUTCFG_TS 0x06000000 + +// GPIO38 input enable. +#define AM_REG_GPIO_CFGE_GPIO38INCFG_S 24 +#define AM_REG_GPIO_CFGE_GPIO38INCFG_M 0x01000000 +#define AM_REG_GPIO_CFGE_GPIO38INCFG(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_CFGE_GPIO38INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO38INCFG_RDZERO 0x01000000 + +// GPIO37 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO37INTD_S 23 +#define AM_REG_GPIO_CFGE_GPIO37INTD_M 0x00800000 +#define AM_REG_GPIO_CFGE_GPIO37INTD(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_CFGE_GPIO37INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO37INTD_INTHL 0x00800000 + +// GPIO37 output configuration. +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_S 21 +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_M 0x00600000 +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG(n) (((uint32_t)(n) << 21) & 0x00600000) +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_PUSHPULL 0x00200000 +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_OD 0x00400000 +#define AM_REG_GPIO_CFGE_GPIO37OUTCFG_TS 0x00600000 + +// GPIO37 input enable. +#define AM_REG_GPIO_CFGE_GPIO37INCFG_S 20 +#define AM_REG_GPIO_CFGE_GPIO37INCFG_M 0x00100000 +#define AM_REG_GPIO_CFGE_GPIO37INCFG(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_CFGE_GPIO37INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO37INCFG_RDZERO 0x00100000 + +// GPIO36 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO36INTD_S 19 +#define AM_REG_GPIO_CFGE_GPIO36INTD_M 0x00080000 +#define AM_REG_GPIO_CFGE_GPIO36INTD(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_GPIO_CFGE_GPIO36INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO36INTD_INTHL 0x00080000 + +// GPIO36 output configuration. +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_S 17 +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_M 0x00060000 +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_PUSHPULL 0x00020000 +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_OD 0x00040000 +#define AM_REG_GPIO_CFGE_GPIO36OUTCFG_TS 0x00060000 + +// GPIO36 input enable. +#define AM_REG_GPIO_CFGE_GPIO36INCFG_S 16 +#define AM_REG_GPIO_CFGE_GPIO36INCFG_M 0x00010000 +#define AM_REG_GPIO_CFGE_GPIO36INCFG(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_CFGE_GPIO36INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO36INCFG_RDZERO 0x00010000 + +// GPIO35 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO35INTD_S 15 +#define AM_REG_GPIO_CFGE_GPIO35INTD_M 0x00008000 +#define AM_REG_GPIO_CFGE_GPIO35INTD(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_CFGE_GPIO35INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO35INTD_INTHL 0x00008000 + +// GPIO35 output configuration. +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_S 13 +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_M 0x00006000 +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG(n) (((uint32_t)(n) << 13) & 0x00006000) +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_PUSHPULL 0x00002000 +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_OD 0x00004000 +#define AM_REG_GPIO_CFGE_GPIO35OUTCFG_TS 0x00006000 + +// GPIO35 input enable. +#define AM_REG_GPIO_CFGE_GPIO35INCFG_S 12 +#define AM_REG_GPIO_CFGE_GPIO35INCFG_M 0x00001000 +#define AM_REG_GPIO_CFGE_GPIO35INCFG(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_CFGE_GPIO35INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO35INCFG_RDZERO 0x00001000 + +// GPIO34 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO34INTD_S 11 +#define AM_REG_GPIO_CFGE_GPIO34INTD_M 0x00000800 +#define AM_REG_GPIO_CFGE_GPIO34INTD(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_GPIO_CFGE_GPIO34INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO34INTD_INTHL 0x00000800 + +// GPIO34 output configuration. +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_S 9 +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_M 0x00000600 +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG(n) (((uint32_t)(n) << 9) & 0x00000600) +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_PUSHPULL 0x00000200 +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_OD 0x00000400 +#define AM_REG_GPIO_CFGE_GPIO34OUTCFG_TS 0x00000600 + +// GPIO34 input enable. +#define AM_REG_GPIO_CFGE_GPIO34INCFG_S 8 +#define AM_REG_GPIO_CFGE_GPIO34INCFG_M 0x00000100 +#define AM_REG_GPIO_CFGE_GPIO34INCFG(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_CFGE_GPIO34INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO34INCFG_RDZERO 0x00000100 + +// GPIO33 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO33INTD_S 7 +#define AM_REG_GPIO_CFGE_GPIO33INTD_M 0x00000080 +#define AM_REG_GPIO_CFGE_GPIO33INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGE_GPIO33INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO33INTD_INTHL 0x00000080 + +// GPIO33 output configuration. +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_S 5 +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGE_GPIO33OUTCFG_TS 0x00000060 + +// GPIO33 input enable. +#define AM_REG_GPIO_CFGE_GPIO33INCFG_S 4 +#define AM_REG_GPIO_CFGE_GPIO33INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGE_GPIO33INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGE_GPIO33INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO33INCFG_RDZERO 0x00000010 + +// GPIO32 interrupt direction. +#define AM_REG_GPIO_CFGE_GPIO32INTD_S 3 +#define AM_REG_GPIO_CFGE_GPIO32INTD_M 0x00000008 +#define AM_REG_GPIO_CFGE_GPIO32INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGE_GPIO32INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO32INTD_INTHL 0x00000008 + +// GPIO32 output configuration. +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_S 1 +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGE_GPIO32OUTCFG_TS 0x00000006 + +// GPIO32 input enable. +#define AM_REG_GPIO_CFGE_GPIO32INCFG_S 0 +#define AM_REG_GPIO_CFGE_GPIO32INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGE_GPIO32INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGE_GPIO32INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGE_GPIO32INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGF - GPIO Configuration Register F +// +//***************************************************************************** +// GPIO47 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO47INTD_S 31 +#define AM_REG_GPIO_CFGF_GPIO47INTD_M 0x80000000 +#define AM_REG_GPIO_CFGF_GPIO47INTD(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_GPIO_CFGF_GPIO47INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO47INTD_INTHL 0x80000000 + +// GPIO47 output configuration. +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_S 29 +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_M 0x60000000 +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG(n) (((uint32_t)(n) << 29) & 0x60000000) +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_PUSHPULL 0x20000000 +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_OD 0x40000000 +#define AM_REG_GPIO_CFGF_GPIO47OUTCFG_TS 0x60000000 + +// GPIO47 input enable. +#define AM_REG_GPIO_CFGF_GPIO47INCFG_S 28 +#define AM_REG_GPIO_CFGF_GPIO47INCFG_M 0x10000000 +#define AM_REG_GPIO_CFGF_GPIO47INCFG(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_CFGF_GPIO47INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO47INCFG_RDZERO 0x10000000 + +// GPIO46 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO46INTD_S 27 +#define AM_REG_GPIO_CFGF_GPIO46INTD_M 0x08000000 +#define AM_REG_GPIO_CFGF_GPIO46INTD(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_GPIO_CFGF_GPIO46INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO46INTD_INTHL 0x08000000 + +// GPIO46 output configuration. +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_S 25 +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_M 0x06000000 +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG(n) (((uint32_t)(n) << 25) & 0x06000000) +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_PUSHPULL 0x02000000 +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_OD 0x04000000 +#define AM_REG_GPIO_CFGF_GPIO46OUTCFG_TS 0x06000000 + +// GPIO46 input enable. +#define AM_REG_GPIO_CFGF_GPIO46INCFG_S 24 +#define AM_REG_GPIO_CFGF_GPIO46INCFG_M 0x01000000 +#define AM_REG_GPIO_CFGF_GPIO46INCFG(n) (((uint32_t)(n) << 24) & 0x01000000) +#define AM_REG_GPIO_CFGF_GPIO46INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO46INCFG_RDZERO 0x01000000 + +// GPIO45 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO45INTD_S 23 +#define AM_REG_GPIO_CFGF_GPIO45INTD_M 0x00800000 +#define AM_REG_GPIO_CFGF_GPIO45INTD(n) (((uint32_t)(n) << 23) & 0x00800000) +#define AM_REG_GPIO_CFGF_GPIO45INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO45INTD_INTHL 0x00800000 + +// GPIO45 output configuration. +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_S 21 +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_M 0x00600000 +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG(n) (((uint32_t)(n) << 21) & 0x00600000) +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_PUSHPULL 0x00200000 +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_OD 0x00400000 +#define AM_REG_GPIO_CFGF_GPIO45OUTCFG_TS 0x00600000 + +// GPIO45 input enable. +#define AM_REG_GPIO_CFGF_GPIO45INCFG_S 20 +#define AM_REG_GPIO_CFGF_GPIO45INCFG_M 0x00100000 +#define AM_REG_GPIO_CFGF_GPIO45INCFG(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_CFGF_GPIO45INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO45INCFG_RDZERO 0x00100000 + +// GPIO44 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO44INTD_S 19 +#define AM_REG_GPIO_CFGF_GPIO44INTD_M 0x00080000 +#define AM_REG_GPIO_CFGF_GPIO44INTD(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_GPIO_CFGF_GPIO44INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO44INTD_INTHL 0x00080000 + +// GPIO44 output configuration. +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_S 17 +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_M 0x00060000 +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_PUSHPULL 0x00020000 +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_OD 0x00040000 +#define AM_REG_GPIO_CFGF_GPIO44OUTCFG_TS 0x00060000 + +// GPIO44 input enable. +#define AM_REG_GPIO_CFGF_GPIO44INCFG_S 16 +#define AM_REG_GPIO_CFGF_GPIO44INCFG_M 0x00010000 +#define AM_REG_GPIO_CFGF_GPIO44INCFG(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_GPIO_CFGF_GPIO44INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO44INCFG_RDZERO 0x00010000 + +// GPIO43 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO43INTD_S 15 +#define AM_REG_GPIO_CFGF_GPIO43INTD_M 0x00008000 +#define AM_REG_GPIO_CFGF_GPIO43INTD(n) (((uint32_t)(n) << 15) & 0x00008000) +#define AM_REG_GPIO_CFGF_GPIO43INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO43INTD_INTHL 0x00008000 + +// GPIO43 output configuration. +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_S 13 +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_M 0x00006000 +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG(n) (((uint32_t)(n) << 13) & 0x00006000) +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_PUSHPULL 0x00002000 +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_OD 0x00004000 +#define AM_REG_GPIO_CFGF_GPIO43OUTCFG_TS 0x00006000 + +// GPIO43 input enable. +#define AM_REG_GPIO_CFGF_GPIO43INCFG_S 12 +#define AM_REG_GPIO_CFGF_GPIO43INCFG_M 0x00001000 +#define AM_REG_GPIO_CFGF_GPIO43INCFG(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_CFGF_GPIO43INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO43INCFG_RDZERO 0x00001000 + +// GPIO42 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO42INTD_S 11 +#define AM_REG_GPIO_CFGF_GPIO42INTD_M 0x00000800 +#define AM_REG_GPIO_CFGF_GPIO42INTD(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_GPIO_CFGF_GPIO42INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO42INTD_INTHL 0x00000800 + +// GPIO42 output configuration. +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_S 9 +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_M 0x00000600 +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG(n) (((uint32_t)(n) << 9) & 0x00000600) +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_PUSHPULL 0x00000200 +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_OD 0x00000400 +#define AM_REG_GPIO_CFGF_GPIO42OUTCFG_TS 0x00000600 + +// GPIO42 input enable. +#define AM_REG_GPIO_CFGF_GPIO42INCFG_S 8 +#define AM_REG_GPIO_CFGF_GPIO42INCFG_M 0x00000100 +#define AM_REG_GPIO_CFGF_GPIO42INCFG(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_GPIO_CFGF_GPIO42INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO42INCFG_RDZERO 0x00000100 + +// GPIO41 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO41INTD_S 7 +#define AM_REG_GPIO_CFGF_GPIO41INTD_M 0x00000080 +#define AM_REG_GPIO_CFGF_GPIO41INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGF_GPIO41INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO41INTD_INTHL 0x00000080 + +// GPIO41 output configuration. +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_S 5 +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGF_GPIO41OUTCFG_TS 0x00000060 + +// GPIO41 input enable. +#define AM_REG_GPIO_CFGF_GPIO41INCFG_S 4 +#define AM_REG_GPIO_CFGF_GPIO41INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGF_GPIO41INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGF_GPIO41INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO41INCFG_RDZERO 0x00000010 + +// GPIO40 interrupt direction. +#define AM_REG_GPIO_CFGF_GPIO40INTD_S 3 +#define AM_REG_GPIO_CFGF_GPIO40INTD_M 0x00000008 +#define AM_REG_GPIO_CFGF_GPIO40INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGF_GPIO40INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO40INTD_INTHL 0x00000008 + +// GPIO40 output configuration. +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_S 1 +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGF_GPIO40OUTCFG_TS 0x00000006 + +// GPIO40 input enable. +#define AM_REG_GPIO_CFGF_GPIO40INCFG_S 0 +#define AM_REG_GPIO_CFGF_GPIO40INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGF_GPIO40INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGF_GPIO40INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGF_GPIO40INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_CFGG - GPIO Configuration Register G +// +//***************************************************************************** +// GPIO49 interrupt direction. +#define AM_REG_GPIO_CFGG_GPIO49INTD_S 7 +#define AM_REG_GPIO_CFGG_GPIO49INTD_M 0x00000080 +#define AM_REG_GPIO_CFGG_GPIO49INTD(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_GPIO_CFGG_GPIO49INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGG_GPIO49INTD_INTHL 0x00000080 + +// GPIO49 output configuration. +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_S 5 +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_M 0x00000060 +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG(n) (((uint32_t)(n) << 5) & 0x00000060) +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_PUSHPULL 0x00000020 +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_OD 0x00000040 +#define AM_REG_GPIO_CFGG_GPIO49OUTCFG_TS 0x00000060 + +// GPIO49 input enable. +#define AM_REG_GPIO_CFGG_GPIO49INCFG_S 4 +#define AM_REG_GPIO_CFGG_GPIO49INCFG_M 0x00000010 +#define AM_REG_GPIO_CFGG_GPIO49INCFG(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_CFGG_GPIO49INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGG_GPIO49INCFG_RDZERO 0x00000010 + +// GPIO48 interrupt direction. +#define AM_REG_GPIO_CFGG_GPIO48INTD_S 3 +#define AM_REG_GPIO_CFGG_GPIO48INTD_M 0x00000008 +#define AM_REG_GPIO_CFGG_GPIO48INTD(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_GPIO_CFGG_GPIO48INTD_INTLH 0x00000000 +#define AM_REG_GPIO_CFGG_GPIO48INTD_INTHL 0x00000008 + +// GPIO48 output configuration. +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_S 1 +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_M 0x00000006 +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG(n) (((uint32_t)(n) << 1) & 0x00000006) +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_DIS 0x00000000 +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_PUSHPULL 0x00000002 +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_OD 0x00000004 +#define AM_REG_GPIO_CFGG_GPIO48OUTCFG_TS 0x00000006 + +// GPIO48 input enable. +#define AM_REG_GPIO_CFGG_GPIO48INCFG_S 0 +#define AM_REG_GPIO_CFGG_GPIO48INCFG_M 0x00000001 +#define AM_REG_GPIO_CFGG_GPIO48INCFG(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_GPIO_CFGG_GPIO48INCFG_READ 0x00000000 +#define AM_REG_GPIO_CFGG_GPIO48INCFG_RDZERO 0x00000001 + +//***************************************************************************** +// +// GPIO_RDA - GPIO Input Register A +// +//***************************************************************************** +// GPIO31-0 read data. +#define AM_REG_GPIO_RDA_RDA_S 0 +#define AM_REG_GPIO_RDA_RDA_M 0xFFFFFFFF +#define AM_REG_GPIO_RDA_RDA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_RDB - GPIO Input Register B +// +//***************************************************************************** +// GPIO49-32 read data. +#define AM_REG_GPIO_RDB_RDB_S 0 +#define AM_REG_GPIO_RDB_RDB_M 0x0003FFFF +#define AM_REG_GPIO_RDB_RDB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_WTA - GPIO Output Register A +// +//***************************************************************************** +// GPIO31-0 write data. +#define AM_REG_GPIO_WTA_WTA_S 0 +#define AM_REG_GPIO_WTA_WTA_M 0xFFFFFFFF +#define AM_REG_GPIO_WTA_WTA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_WTB - GPIO Output Register B +// +//***************************************************************************** +// GPIO49-32 write data. +#define AM_REG_GPIO_WTB_WTB_S 0 +#define AM_REG_GPIO_WTB_WTB_M 0x0003FFFF +#define AM_REG_GPIO_WTB_WTB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_WTSA - GPIO Output Register A Set +// +//***************************************************************************** +// Set the GPIO31-0 write data. +#define AM_REG_GPIO_WTSA_WTSA_S 0 +#define AM_REG_GPIO_WTSA_WTSA_M 0xFFFFFFFF +#define AM_REG_GPIO_WTSA_WTSA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_WTSB - GPIO Output Register B Set +// +//***************************************************************************** +// Set the GPIO49-32 write data. +#define AM_REG_GPIO_WTSB_WTSB_S 0 +#define AM_REG_GPIO_WTSB_WTSB_M 0x0003FFFF +#define AM_REG_GPIO_WTSB_WTSB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_WTCA - GPIO Output Register A Clear +// +//***************************************************************************** +// Clear the GPIO31-0 write data. +#define AM_REG_GPIO_WTCA_WTCA_S 0 +#define AM_REG_GPIO_WTCA_WTCA_M 0xFFFFFFFF +#define AM_REG_GPIO_WTCA_WTCA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_WTCB - GPIO Output Register B Clear +// +//***************************************************************************** +// Clear the GPIO49-32 write data. +#define AM_REG_GPIO_WTCB_WTCB_S 0 +#define AM_REG_GPIO_WTCB_WTCB_M 0x0003FFFF +#define AM_REG_GPIO_WTCB_WTCB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_ENA - GPIO Enable Register A +// +//***************************************************************************** +// GPIO31-0 output enables +#define AM_REG_GPIO_ENA_ENA_S 0 +#define AM_REG_GPIO_ENA_ENA_M 0xFFFFFFFF +#define AM_REG_GPIO_ENA_ENA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_ENB - GPIO Enable Register B +// +//***************************************************************************** +// GPIO49-32 output enables +#define AM_REG_GPIO_ENB_ENB_S 0 +#define AM_REG_GPIO_ENB_ENB_M 0x0003FFFF +#define AM_REG_GPIO_ENB_ENB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_ENSA - GPIO Enable Register A Set +// +//***************************************************************************** +// Set the GPIO31-0 output enables +#define AM_REG_GPIO_ENSA_ENSA_S 0 +#define AM_REG_GPIO_ENSA_ENSA_M 0xFFFFFFFF +#define AM_REG_GPIO_ENSA_ENSA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_ENSB - GPIO Enable Register B Set +// +//***************************************************************************** +// Set the GPIO49-32 output enables +#define AM_REG_GPIO_ENSB_ENSB_S 0 +#define AM_REG_GPIO_ENSB_ENSB_M 0x0003FFFF +#define AM_REG_GPIO_ENSB_ENSB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_ENCA - GPIO Enable Register A Clear +// +//***************************************************************************** +// Clear the GPIO31-0 output enables +#define AM_REG_GPIO_ENCA_ENCA_S 0 +#define AM_REG_GPIO_ENCA_ENCA_M 0xFFFFFFFF +#define AM_REG_GPIO_ENCA_ENCA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// GPIO_ENCB - GPIO Enable Register B Clear +// +//***************************************************************************** +// Clear the GPIO49-32 output enables +#define AM_REG_GPIO_ENCB_ENCB_S 0 +#define AM_REG_GPIO_ENCB_ENCB_M 0x0003FFFF +#define AM_REG_GPIO_ENCB_ENCB(n) (((uint32_t)(n) << 0) & 0x0003FFFF) + +//***************************************************************************** +// +// GPIO_STMRCAP - STIMER Capture Control +// +//***************************************************************************** +// STIMER Capture 3 Polarity. +#define AM_REG_GPIO_STMRCAP_STPOL3_S 30 +#define AM_REG_GPIO_STMRCAP_STPOL3_M 0x40000000 +#define AM_REG_GPIO_STMRCAP_STPOL3(n) (((uint32_t)(n) << 30) & 0x40000000) +#define AM_REG_GPIO_STMRCAP_STPOL3_CAPLH 0x00000000 +#define AM_REG_GPIO_STMRCAP_STPOL3_CAPHL 0x40000000 + +// STIMER Capture 3 Select. +#define AM_REG_GPIO_STMRCAP_STSEL3_S 24 +#define AM_REG_GPIO_STMRCAP_STSEL3_M 0x3F000000 +#define AM_REG_GPIO_STMRCAP_STSEL3(n) (((uint32_t)(n) << 24) & 0x3F000000) + +// STIMER Capture 2 Polarity. +#define AM_REG_GPIO_STMRCAP_STPOL2_S 22 +#define AM_REG_GPIO_STMRCAP_STPOL2_M 0x00400000 +#define AM_REG_GPIO_STMRCAP_STPOL2(n) (((uint32_t)(n) << 22) & 0x00400000) +#define AM_REG_GPIO_STMRCAP_STPOL2_CAPLH 0x00000000 +#define AM_REG_GPIO_STMRCAP_STPOL2_CAPHL 0x00400000 + +// STIMER Capture 2 Select. +#define AM_REG_GPIO_STMRCAP_STSEL2_S 16 +#define AM_REG_GPIO_STMRCAP_STSEL2_M 0x003F0000 +#define AM_REG_GPIO_STMRCAP_STSEL2(n) (((uint32_t)(n) << 16) & 0x003F0000) + +// STIMER Capture 1 Polarity. +#define AM_REG_GPIO_STMRCAP_STPOL1_S 14 +#define AM_REG_GPIO_STMRCAP_STPOL1_M 0x00004000 +#define AM_REG_GPIO_STMRCAP_STPOL1(n) (((uint32_t)(n) << 14) & 0x00004000) +#define AM_REG_GPIO_STMRCAP_STPOL1_CAPLH 0x00000000 +#define AM_REG_GPIO_STMRCAP_STPOL1_CAPHL 0x00004000 + +// STIMER Capture 1 Select. +#define AM_REG_GPIO_STMRCAP_STSEL1_S 8 +#define AM_REG_GPIO_STMRCAP_STSEL1_M 0x00003F00 +#define AM_REG_GPIO_STMRCAP_STSEL1(n) (((uint32_t)(n) << 8) & 0x00003F00) + +// STIMER Capture 0 Polarity. +#define AM_REG_GPIO_STMRCAP_STPOL0_S 6 +#define AM_REG_GPIO_STMRCAP_STPOL0_M 0x00000040 +#define AM_REG_GPIO_STMRCAP_STPOL0(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_GPIO_STMRCAP_STPOL0_CAPLH 0x00000000 +#define AM_REG_GPIO_STMRCAP_STPOL0_CAPHL 0x00000040 + +// STIMER Capture 0 Select. +#define AM_REG_GPIO_STMRCAP_STSEL0_S 0 +#define AM_REG_GPIO_STMRCAP_STSEL0_M 0x0000003F +#define AM_REG_GPIO_STMRCAP_STSEL0(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_IOM0IRQ - IOM0 Flow Control IRQ Select +// +//***************************************************************************** +// IOMSTR0 IRQ pad select. +#define AM_REG_GPIO_IOM0IRQ_IOM0IRQ_S 0 +#define AM_REG_GPIO_IOM0IRQ_IOM0IRQ_M 0x0000003F +#define AM_REG_GPIO_IOM0IRQ_IOM0IRQ(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_IOM1IRQ - IOM1 Flow Control IRQ Select +// +//***************************************************************************** +// IOMSTR1 IRQ pad select. +#define AM_REG_GPIO_IOM1IRQ_IOM1IRQ_S 0 +#define AM_REG_GPIO_IOM1IRQ_IOM1IRQ_M 0x0000003F +#define AM_REG_GPIO_IOM1IRQ_IOM1IRQ(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_IOM2IRQ - IOM2 Flow Control IRQ Select +// +//***************************************************************************** +// IOMSTR2 IRQ pad select. +#define AM_REG_GPIO_IOM2IRQ_IOM2IRQ_S 0 +#define AM_REG_GPIO_IOM2IRQ_IOM2IRQ_M 0x0000003F +#define AM_REG_GPIO_IOM2IRQ_IOM2IRQ(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_IOM3IRQ - IOM3 Flow Control IRQ Select +// +//***************************************************************************** +// IOMSTR3 IRQ pad select. +#define AM_REG_GPIO_IOM3IRQ_IOM3IRQ_S 0 +#define AM_REG_GPIO_IOM3IRQ_IOM3IRQ_M 0x0000003F +#define AM_REG_GPIO_IOM3IRQ_IOM3IRQ(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_IOM4IRQ - IOM4 Flow Control IRQ Select +// +//***************************************************************************** +// IOMSTR4 IRQ pad select. +#define AM_REG_GPIO_IOM4IRQ_IOM4IRQ_S 0 +#define AM_REG_GPIO_IOM4IRQ_IOM4IRQ_M 0x0000003F +#define AM_REG_GPIO_IOM4IRQ_IOM4IRQ(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_IOM5IRQ - IOM5 Flow Control IRQ Select +// +//***************************************************************************** +// IOMSTR5 IRQ pad select. +#define AM_REG_GPIO_IOM5IRQ_IOM5IRQ_S 0 +#define AM_REG_GPIO_IOM5IRQ_IOM5IRQ_M 0x0000003F +#define AM_REG_GPIO_IOM5IRQ_IOM5IRQ(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// GPIO_LOOPBACK - IOM to IOS Loopback Control +// +//***************************************************************************** +// IOM to IOS loopback control. +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_S 0 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_M 0x00000007 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK(n) (((uint32_t)(n) << 0) & 0x00000007) +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP0 0x00000000 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP1 0x00000001 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP2 0x00000002 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP3 0x00000003 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP4 0x00000004 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOP5 0x00000005 +#define AM_REG_GPIO_LOOPBACK_LOOPBACK_LOOPNONE 0x00000006 + +//***************************************************************************** +// +// GPIO_GPIOOBS - GPIO Observation Mode Sample register +// +//***************************************************************************** +// Sample of the data output on the GPIO observation port. May have async +// sampling issues, as the data is not synronized to the read operation. +// Intended for debug purposes only +#define AM_REG_GPIO_GPIOOBS_OBS_DATA_S 0 +#define AM_REG_GPIO_GPIOOBS_OBS_DATA_M 0x0000FFFF +#define AM_REG_GPIO_GPIOOBS_OBS_DATA(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// GPIO_ALTPADCFGA - Alternate Pad Configuration reg0 (Pads 3,2,1,0) +// +//***************************************************************************** +// Pad 3 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGA_PAD3_SR_SR_EN 0x10000000 + +// Pad 3 high order drive strength selection. Used in conjunction with +// PAD3STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGA_PAD3_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGA_PAD3_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGA_PAD3_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 2 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGA_PAD2_SR_SR_EN 0x00100000 + +// Pad 2 high order drive strength selection. Used in conjunction with +// PAD2STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGA_PAD2_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGA_PAD2_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGA_PAD2_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 1 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGA_PAD1_SR_SR_EN 0x00001000 + +// Pad 1 high order drive strength selection. Used in conjunction with +// PAD1STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGA_PAD1_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGA_PAD1_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGA_PAD1_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 0 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGA_PAD0_SR_SR_EN 0x00000010 + +// Pad 0 high order drive strength selection. Used in conjunction with +// PAD0STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGA_PAD0_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGA_PAD0_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGA_PAD0_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGB - Alternate Pad Configuration reg1 (Pads 7,6,5,4) +// +//***************************************************************************** +// Pad 7 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGB_PAD7_SR_SR_EN 0x10000000 + +// Pad 7 high order drive strength selection. Used in conjunction with +// PAD7STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGB_PAD7_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGB_PAD7_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGB_PAD7_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 6 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGB_PAD6_SR_SR_EN 0x00100000 + +// Pad 6 high order drive strength selection. Used in conjunction with +// PAD6STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGB_PAD6_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGB_PAD6_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGB_PAD6_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 5 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGB_PAD5_SR_SR_EN 0x00001000 + +// Pad 5 high order drive strength selection. Used in conjunction with +// PAD5STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGB_PAD5_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGB_PAD5_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGB_PAD5_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 4 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGB_PAD4_SR_SR_EN 0x00000010 + +// Pad 4 high order drive strength selection. Used in conjunction with +// PAD4STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGB_PAD4_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGB_PAD4_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGB_PAD4_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGC - Alternate Pad Configuration reg2 (Pads 11,10,9,8) +// +//***************************************************************************** +// Pad 11 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGC_PAD11_SR_SR_EN 0x10000000 + +// Pad 11 high order drive strength selection. Used in conjunction with +// PAD11STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGC_PAD11_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGC_PAD11_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGC_PAD11_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 10 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGC_PAD10_SR_SR_EN 0x00100000 + +// Pad 10 high order drive strength selection. Used in conjunction with +// PAD10STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGC_PAD10_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGC_PAD10_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGC_PAD10_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 9 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGC_PAD9_SR_SR_EN 0x00001000 + +// Pad 9 high order drive strength selection. Used in conjunction with +// PAD9STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGC_PAD9_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGC_PAD9_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGC_PAD9_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 8 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGC_PAD8_SR_SR_EN 0x00000010 + +// Pad 8 high order drive strength selection. Used in conjunction with +// PAD8STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGC_PAD8_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGC_PAD8_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGC_PAD8_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGD - Alternate Pad Configuration reg3 (Pads 15,14,13,12) +// +//***************************************************************************** +// Pad 15 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGD_PAD15_SR_SR_EN 0x10000000 + +// Pad 15 high order drive strength selection. Used in conjunction with +// PAD15STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGD_PAD15_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGD_PAD15_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGD_PAD15_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 14 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGD_PAD14_SR_SR_EN 0x00100000 + +// Pad 14 high order drive strength selection. Used in conjunction with +// PAD14STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGD_PAD14_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGD_PAD14_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGD_PAD14_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 13 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGD_PAD13_SR_SR_EN 0x00001000 + +// Pad 13 high order drive strength selection. Used in conjunction with +// PAD13STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGD_PAD13_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGD_PAD13_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGD_PAD13_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 12 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGD_PAD12_SR_SR_EN 0x00000010 + +// Pad 12 high order drive strength selection. Used in conjunction with +// PAD12STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGD_PAD12_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGD_PAD12_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGD_PAD12_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGE - Alternate Pad Configuration reg4 (Pads 19,18,17,16) +// +//***************************************************************************** +// Pad 19 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGE_PAD19_SR_SR_EN 0x10000000 + +// Pad 19 high order drive strength selection. Used in conjunction with +// PAD19STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGE_PAD19_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGE_PAD19_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGE_PAD19_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 18 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGE_PAD18_SR_SR_EN 0x00100000 + +// Pad 18 high order drive strength selection. Used in conjunction with +// PAD18STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGE_PAD18_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGE_PAD18_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGE_PAD18_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 17 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGE_PAD17_SR_SR_EN 0x00001000 + +// Pad 17 high order drive strength selection. Used in conjunction with +// PAD17STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGE_PAD17_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGE_PAD17_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGE_PAD17_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 16 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGE_PAD16_SR_SR_EN 0x00000010 + +// Pad 16 high order drive strength selection. Used in conjunction with +// PAD16STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGE_PAD16_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGE_PAD16_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGE_PAD16_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGF - Alternate Pad Configuration reg5 (Pads 23,22,21,20) +// +//***************************************************************************** +// Pad 23 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGF_PAD23_SR_SR_EN 0x10000000 + +// Pad 23 high order drive strength selection. Used in conjunction with +// PAD23STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGF_PAD23_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGF_PAD23_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGF_PAD23_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 22 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGF_PAD22_SR_SR_EN 0x00100000 + +// Pad 22 high order drive strength selection. Used in conjunction with +// PAD22STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGF_PAD22_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGF_PAD22_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGF_PAD22_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 21 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGF_PAD21_SR_SR_EN 0x00001000 + +// Pad 21 high order drive strength selection. Used in conjunction with +// PAD21STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGF_PAD21_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGF_PAD21_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGF_PAD21_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 20 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGF_PAD20_SR_SR_EN 0x00000010 + +// Pad 20 high order drive strength selection. Used in conjunction with +// PAD20STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGF_PAD20_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGF_PAD20_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGF_PAD20_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGG - Alternate Pad Configuration reg6 (Pads 27,26,25,24) +// +//***************************************************************************** +// Pad 27 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGG_PAD27_SR_SR_EN 0x10000000 + +// Pad 27 high order drive strength selection. Used in conjunction with +// PAD27STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGG_PAD27_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGG_PAD27_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGG_PAD27_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 26 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGG_PAD26_SR_SR_EN 0x00100000 + +// Pad 26 high order drive strength selection. Used in conjunction with +// PAD26STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGG_PAD26_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGG_PAD26_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGG_PAD26_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 25 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGG_PAD25_SR_SR_EN 0x00001000 + +// Pad 25 high order drive strength selection. Used in conjunction with +// PAD25STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGG_PAD25_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGG_PAD25_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGG_PAD25_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 24 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGG_PAD24_SR_SR_EN 0x00000010 + +// Pad 24 high order drive strength selection. Used in conjunction with +// PAD24STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGG_PAD24_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGG_PAD24_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGG_PAD24_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGH - Alternate Pad Configuration reg7 (Pads 31,30,29,28) +// +//***************************************************************************** +// Pad 31 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGH_PAD31_SR_SR_EN 0x10000000 + +// Pad 31 high order drive strength selection. Used in conjunction with +// PAD31STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGH_PAD31_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGH_PAD31_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGH_PAD31_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 30 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGH_PAD30_SR_SR_EN 0x00100000 + +// Pad 30 high order drive strength selection. Used in conjunction with +// PAD30STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGH_PAD30_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGH_PAD30_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGH_PAD30_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 29 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGH_PAD29_SR_SR_EN 0x00001000 + +// Pad 29 high order drive strength selection. Used in conjunction with +// PAD29STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGH_PAD29_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGH_PAD29_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGH_PAD29_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 28 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGH_PAD28_SR_SR_EN 0x00000010 + +// Pad 28 high order drive strength selection. Used in conjunction with +// PAD28STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGH_PAD28_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGH_PAD28_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGH_PAD28_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGI - Alternate Pad Configuration reg8 (Pads 35,34,33,32) +// +//***************************************************************************** +// Pad 35 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGI_PAD35_SR_SR_EN 0x10000000 + +// Pad 35 high order drive strength selection. Used in conjunction with +// PAD35STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGI_PAD35_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGI_PAD35_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGI_PAD35_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 34 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGI_PAD34_SR_SR_EN 0x00100000 + +// Pad 34 high order drive strength selection. Used in conjunction with +// PAD34STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGI_PAD34_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGI_PAD34_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGI_PAD34_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 33 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGI_PAD33_SR_SR_EN 0x00001000 + +// Pad 33 high order drive strength selection. Used in conjunction with +// PAD33STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGI_PAD33_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGI_PAD33_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGI_PAD33_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 32 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGI_PAD32_SR_SR_EN 0x00000010 + +// Pad 32 high order drive strength selection. Used in conjunction with +// PAD32STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGI_PAD32_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGI_PAD32_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGI_PAD32_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGJ - Alternate Pad Configuration reg9 (Pads 39,38,37,36) +// +//***************************************************************************** +// Pad 39 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_SR_SR_EN 0x10000000 + +// Pad 39 high order drive strength selection. Used in conjunction with +// PAD39STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGJ_PAD39_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 38 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_SR_SR_EN 0x00100000 + +// Pad 38 high order drive strength selection. Used in conjunction with +// PAD38STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGJ_PAD38_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 37 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_SR_SR_EN 0x00001000 + +// Pad 37 high order drive strength selection. Used in conjunction with +// PAD37STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGJ_PAD37_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 36 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_SR_SR_EN 0x00000010 + +// Pad 36 high order drive strength selection. Used in conjunction with +// PAD36STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGJ_PAD36_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGK - Alternate Pad Configuration reg10 (Pads 43,42,41,40) +// +//***************************************************************************** +// Pad 43 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGK_PAD43_SR_SR_EN 0x10000000 + +// Pad 43 high order drive strength selection. Used in conjunction with +// PAD43STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGK_PAD43_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGK_PAD43_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGK_PAD43_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 42 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGK_PAD42_SR_SR_EN 0x00100000 + +// Pad 42 high order drive strength selection. Used in conjunction with +// PAD42STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGK_PAD42_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGK_PAD42_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGK_PAD42_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 41 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGK_PAD41_SR_SR_EN 0x00001000 + +// Pad 41 high order drive strength selection. Used in conjunction with +// PAD41STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGK_PAD41_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGK_PAD41_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGK_PAD41_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 40 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGK_PAD40_SR_SR_EN 0x00000010 + +// Pad 40 high order drive strength selection. Used in conjunction with +// PAD40STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGK_PAD40_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGK_PAD40_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGK_PAD40_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGL - Alternate Pad Configuration reg11 (Pads 47,46,45,44) +// +//***************************************************************************** +// Pad 47 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR_S 28 +#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR_M 0x10000000 +#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_GPIO_ALTPADCFGL_PAD47_SR_SR_EN 0x10000000 + +// Pad 47 high order drive strength selection. Used in conjunction with +// PAD47STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGL_PAD47_DS1_S 24 +#define AM_REG_GPIO_ALTPADCFGL_PAD47_DS1_M 0x01000000 +#define AM_REG_GPIO_ALTPADCFGL_PAD47_DS1(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Pad 46 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR_S 20 +#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR_M 0x00100000 +#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_GPIO_ALTPADCFGL_PAD46_SR_SR_EN 0x00100000 + +// Pad 46 high order drive strength selection. Used in conjunction with +// PAD46STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGL_PAD46_DS1_S 16 +#define AM_REG_GPIO_ALTPADCFGL_PAD46_DS1_M 0x00010000 +#define AM_REG_GPIO_ALTPADCFGL_PAD46_DS1(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Pad 45 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGL_PAD45_SR_SR_EN 0x00001000 + +// Pad 45 high order drive strength selection. Used in conjunction with +// PAD45STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGL_PAD45_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGL_PAD45_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGL_PAD45_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 44 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGL_PAD44_SR_SR_EN 0x00000010 + +// Pad 44 high order drive strength selection. Used in conjunction with +// PAD44STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGL_PAD44_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGL_PAD44_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGL_PAD44_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// GPIO_ALTPADCFGM - Alternate Pad Configuration reg12 (Pads 49,48) +// +//***************************************************************************** +// Pad 49 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR_S 12 +#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR_M 0x00001000 +#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_GPIO_ALTPADCFGM_PAD49_SR_SR_EN 0x00001000 + +// Pad 49 high order drive strength selection. Used in conjunction with +// PAD49STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGM_PAD49_DS1_S 8 +#define AM_REG_GPIO_ALTPADCFGM_PAD49_DS1_M 0x00000100 +#define AM_REG_GPIO_ALTPADCFGM_PAD49_DS1(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Pad 48 slew rate selection. +#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR_S 4 +#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR_M 0x00000010 +#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_GPIO_ALTPADCFGM_PAD48_SR_SR_EN 0x00000010 + +// Pad 48 high order drive strength selection. Used in conjunction with +// PAD48STRNG field to set the pad drive strength. +#define AM_REG_GPIO_ALTPADCFGM_PAD48_DS1_S 0 +#define AM_REG_GPIO_ALTPADCFGM_PAD48_DS1_M 0x00000001 +#define AM_REG_GPIO_ALTPADCFGM_PAD48_DS1(n) (((uint32_t)(n) << 0) & 0x00000001) + +#endif // AM_REG_GPIO_H diff --git a/mcu/apollo2/regs/am_reg_iomstr.h b/mcu/apollo2/regs/am_reg_iomstr.h new file mode 100644 index 0000000..e241d97 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_iomstr.h @@ -0,0 +1,588 @@ +//***************************************************************************** +// +// am_reg_iomstr.h +//! @file +//! +//! @brief Register macros for the IOMSTR module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_IOMSTR_H +#define AM_REG_IOMSTR_H + +//***************************************************************************** +// +// IOMSTR +// Instance finder. (6 instance(s) available) +// +//***************************************************************************** +#define AM_REG_IOMSTR_NUM_MODULES 6 +#define AM_REG_IOMSTRn(n) \ + (REG_IOMSTR_BASEADDR + 0x00001000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_IOMSTR_FIFO_O 0x00000000 +#define AM_REG_IOMSTR_FIFOPTR_O 0x00000100 +#define AM_REG_IOMSTR_TLNGTH_O 0x00000104 +#define AM_REG_IOMSTR_FIFOTHR_O 0x00000108 +#define AM_REG_IOMSTR_CLKCFG_O 0x0000010C +#define AM_REG_IOMSTR_CMD_O 0x00000110 +#define AM_REG_IOMSTR_CMDRPT_O 0x00000114 +#define AM_REG_IOMSTR_STATUS_O 0x00000118 +#define AM_REG_IOMSTR_CFG_O 0x0000011C +#define AM_REG_IOMSTR_INTEN_O 0x00000200 +#define AM_REG_IOMSTR_INTSTAT_O 0x00000204 +#define AM_REG_IOMSTR_INTCLR_O 0x00000208 +#define AM_REG_IOMSTR_INTSET_O 0x0000020C + +//***************************************************************************** +// +// IOMSTR_INTEN - IO Master Interrupts: Enable +// +//***************************************************************************** +// This is the arbitration loss interrupt. This error occurs if another master +// collides with an IO Master transfer. Generally, the IOM started an operation +// but found SDA already low. +#define AM_REG_IOMSTR_INTEN_ARB_S 10 +#define AM_REG_IOMSTR_INTEN_ARB_M 0x00000400 +#define AM_REG_IOMSTR_INTEN_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This is the STOP command interrupt. A STOP bit was detected by the IOM. +#define AM_REG_IOMSTR_INTEN_STOP_S 9 +#define AM_REG_IOMSTR_INTEN_STOP_M 0x00000200 +#define AM_REG_IOMSTR_INTEN_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This is the START command interrupt. A START from another master was +// detected. Software must wait for a STOP before proceeding. +#define AM_REG_IOMSTR_INTEN_START_S 8 +#define AM_REG_IOMSTR_INTEN_START_M 0x00000100 +#define AM_REG_IOMSTR_INTEN_START(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This is the illegal command interrupt. Software attempted to issue a CMD +// while another CMD was already in progress. Or an attempt was made to issue a +// non-zero-length write CMD with an empty FIFO. +#define AM_REG_IOMSTR_INTEN_ICMD_S 7 +#define AM_REG_IOMSTR_INTEN_ICMD_M 0x00000080 +#define AM_REG_IOMSTR_INTEN_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This is the illegal FIFO access interrupt. An attempt was made to read the +// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read +// CMD. +#define AM_REG_IOMSTR_INTEN_IACC_S 6 +#define AM_REG_IOMSTR_INTEN_IACC_M 0x00000040 +#define AM_REG_IOMSTR_INTEN_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This is the WTLEN interrupt. +#define AM_REG_IOMSTR_INTEN_WTLEN_S 5 +#define AM_REG_IOMSTR_INTEN_WTLEN_M 0x00000020 +#define AM_REG_IOMSTR_INTEN_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This is the I2C NAK interrupt. The expected ACK from the slave was not +// received by the IOM. +#define AM_REG_IOMSTR_INTEN_NAK_S 4 +#define AM_REG_IOMSTR_INTEN_NAK_M 0x00000010 +#define AM_REG_IOMSTR_INTEN_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This is the Write FIFO Overflow interrupt. An attempt was made to write the +// FIFO while it was full (i.e. while FIFOSIZ > 124). +#define AM_REG_IOMSTR_INTEN_FOVFL_S 3 +#define AM_REG_IOMSTR_INTEN_FOVFL_M 0x00000008 +#define AM_REG_IOMSTR_INTEN_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO +// when empty (i.e. while FIFOSIZ less than 4). +#define AM_REG_IOMSTR_INTEN_FUNDFL_S 2 +#define AM_REG_IOMSTR_INTEN_FUNDFL_M 0x00000004 +#define AM_REG_IOMSTR_INTEN_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO Threshold interrupt. +#define AM_REG_IOMSTR_INTEN_THR_S 1 +#define AM_REG_IOMSTR_INTEN_THR_M 0x00000002 +#define AM_REG_IOMSTR_INTEN_THR(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the Command Complete interrupt. +#define AM_REG_IOMSTR_INTEN_CMDCMP_S 0 +#define AM_REG_IOMSTR_INTEN_CMDCMP_M 0x00000001 +#define AM_REG_IOMSTR_INTEN_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOMSTR_INTSTAT - IO Master Interrupts: Status +// +//***************************************************************************** +// This is the arbitration loss interrupt. This error occurs if another master +// collides with an IO Master transfer. Generally, the IOM started an operation +// but found SDA already low. +#define AM_REG_IOMSTR_INTSTAT_ARB_S 10 +#define AM_REG_IOMSTR_INTSTAT_ARB_M 0x00000400 +#define AM_REG_IOMSTR_INTSTAT_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This is the STOP command interrupt. A STOP bit was detected by the IOM. +#define AM_REG_IOMSTR_INTSTAT_STOP_S 9 +#define AM_REG_IOMSTR_INTSTAT_STOP_M 0x00000200 +#define AM_REG_IOMSTR_INTSTAT_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This is the START command interrupt. A START from another master was +// detected. Software must wait for a STOP before proceeding. +#define AM_REG_IOMSTR_INTSTAT_START_S 8 +#define AM_REG_IOMSTR_INTSTAT_START_M 0x00000100 +#define AM_REG_IOMSTR_INTSTAT_START(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This is the illegal command interrupt. Software attempted to issue a CMD +// while another CMD was already in progress. Or an attempt was made to issue a +// non-zero-length write CMD with an empty FIFO. +#define AM_REG_IOMSTR_INTSTAT_ICMD_S 7 +#define AM_REG_IOMSTR_INTSTAT_ICMD_M 0x00000080 +#define AM_REG_IOMSTR_INTSTAT_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This is the illegal FIFO access interrupt. An attempt was made to read the +// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read +// CMD. +#define AM_REG_IOMSTR_INTSTAT_IACC_S 6 +#define AM_REG_IOMSTR_INTSTAT_IACC_M 0x00000040 +#define AM_REG_IOMSTR_INTSTAT_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This is the WTLEN interrupt. +#define AM_REG_IOMSTR_INTSTAT_WTLEN_S 5 +#define AM_REG_IOMSTR_INTSTAT_WTLEN_M 0x00000020 +#define AM_REG_IOMSTR_INTSTAT_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This is the I2C NAK interrupt. The expected ACK from the slave was not +// received by the IOM. +#define AM_REG_IOMSTR_INTSTAT_NAK_S 4 +#define AM_REG_IOMSTR_INTSTAT_NAK_M 0x00000010 +#define AM_REG_IOMSTR_INTSTAT_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This is the Write FIFO Overflow interrupt. An attempt was made to write the +// FIFO while it was full (i.e. while FIFOSIZ > 124). +#define AM_REG_IOMSTR_INTSTAT_FOVFL_S 3 +#define AM_REG_IOMSTR_INTSTAT_FOVFL_M 0x00000008 +#define AM_REG_IOMSTR_INTSTAT_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO +// when empty (i.e. while FIFOSIZ less than 4). +#define AM_REG_IOMSTR_INTSTAT_FUNDFL_S 2 +#define AM_REG_IOMSTR_INTSTAT_FUNDFL_M 0x00000004 +#define AM_REG_IOMSTR_INTSTAT_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO Threshold interrupt. +#define AM_REG_IOMSTR_INTSTAT_THR_S 1 +#define AM_REG_IOMSTR_INTSTAT_THR_M 0x00000002 +#define AM_REG_IOMSTR_INTSTAT_THR(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the Command Complete interrupt. +#define AM_REG_IOMSTR_INTSTAT_CMDCMP_S 0 +#define AM_REG_IOMSTR_INTSTAT_CMDCMP_M 0x00000001 +#define AM_REG_IOMSTR_INTSTAT_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOMSTR_INTCLR - IO Master Interrupts: Clear +// +//***************************************************************************** +// This is the arbitration loss interrupt. This error occurs if another master +// collides with an IO Master transfer. Generally, the IOM started an operation +// but found SDA already low. +#define AM_REG_IOMSTR_INTCLR_ARB_S 10 +#define AM_REG_IOMSTR_INTCLR_ARB_M 0x00000400 +#define AM_REG_IOMSTR_INTCLR_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This is the STOP command interrupt. A STOP bit was detected by the IOM. +#define AM_REG_IOMSTR_INTCLR_STOP_S 9 +#define AM_REG_IOMSTR_INTCLR_STOP_M 0x00000200 +#define AM_REG_IOMSTR_INTCLR_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This is the START command interrupt. A START from another master was +// detected. Software must wait for a STOP before proceeding. +#define AM_REG_IOMSTR_INTCLR_START_S 8 +#define AM_REG_IOMSTR_INTCLR_START_M 0x00000100 +#define AM_REG_IOMSTR_INTCLR_START(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This is the illegal command interrupt. Software attempted to issue a CMD +// while another CMD was already in progress. Or an attempt was made to issue a +// non-zero-length write CMD with an empty FIFO. +#define AM_REG_IOMSTR_INTCLR_ICMD_S 7 +#define AM_REG_IOMSTR_INTCLR_ICMD_M 0x00000080 +#define AM_REG_IOMSTR_INTCLR_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This is the illegal FIFO access interrupt. An attempt was made to read the +// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read +// CMD. +#define AM_REG_IOMSTR_INTCLR_IACC_S 6 +#define AM_REG_IOMSTR_INTCLR_IACC_M 0x00000040 +#define AM_REG_IOMSTR_INTCLR_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This is the WTLEN interrupt. +#define AM_REG_IOMSTR_INTCLR_WTLEN_S 5 +#define AM_REG_IOMSTR_INTCLR_WTLEN_M 0x00000020 +#define AM_REG_IOMSTR_INTCLR_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This is the I2C NAK interrupt. The expected ACK from the slave was not +// received by the IOM. +#define AM_REG_IOMSTR_INTCLR_NAK_S 4 +#define AM_REG_IOMSTR_INTCLR_NAK_M 0x00000010 +#define AM_REG_IOMSTR_INTCLR_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This is the Write FIFO Overflow interrupt. An attempt was made to write the +// FIFO while it was full (i.e. while FIFOSIZ > 124). +#define AM_REG_IOMSTR_INTCLR_FOVFL_S 3 +#define AM_REG_IOMSTR_INTCLR_FOVFL_M 0x00000008 +#define AM_REG_IOMSTR_INTCLR_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO +// when empty (i.e. while FIFOSIZ less than 4). +#define AM_REG_IOMSTR_INTCLR_FUNDFL_S 2 +#define AM_REG_IOMSTR_INTCLR_FUNDFL_M 0x00000004 +#define AM_REG_IOMSTR_INTCLR_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO Threshold interrupt. +#define AM_REG_IOMSTR_INTCLR_THR_S 1 +#define AM_REG_IOMSTR_INTCLR_THR_M 0x00000002 +#define AM_REG_IOMSTR_INTCLR_THR(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the Command Complete interrupt. +#define AM_REG_IOMSTR_INTCLR_CMDCMP_S 0 +#define AM_REG_IOMSTR_INTCLR_CMDCMP_M 0x00000001 +#define AM_REG_IOMSTR_INTCLR_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOMSTR_INTSET - IO Master Interrupts: Set +// +//***************************************************************************** +// This is the arbitration loss interrupt. This error occurs if another master +// collides with an IO Master transfer. Generally, the IOM started an operation +// but found SDA already low. +#define AM_REG_IOMSTR_INTSET_ARB_S 10 +#define AM_REG_IOMSTR_INTSET_ARB_M 0x00000400 +#define AM_REG_IOMSTR_INTSET_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This is the STOP command interrupt. A STOP bit was detected by the IOM. +#define AM_REG_IOMSTR_INTSET_STOP_S 9 +#define AM_REG_IOMSTR_INTSET_STOP_M 0x00000200 +#define AM_REG_IOMSTR_INTSET_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This is the START command interrupt. A START from another master was +// detected. Software must wait for a STOP before proceeding. +#define AM_REG_IOMSTR_INTSET_START_S 8 +#define AM_REG_IOMSTR_INTSET_START_M 0x00000100 +#define AM_REG_IOMSTR_INTSET_START(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This is the illegal command interrupt. Software attempted to issue a CMD +// while another CMD was already in progress. Or an attempt was made to issue a +// non-zero-length write CMD with an empty FIFO. +#define AM_REG_IOMSTR_INTSET_ICMD_S 7 +#define AM_REG_IOMSTR_INTSET_ICMD_M 0x00000080 +#define AM_REG_IOMSTR_INTSET_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This is the illegal FIFO access interrupt. An attempt was made to read the +// FIFO during a write CMD. Or an attempt was made to write the FIFO on a read +// CMD. +#define AM_REG_IOMSTR_INTSET_IACC_S 6 +#define AM_REG_IOMSTR_INTSET_IACC_M 0x00000040 +#define AM_REG_IOMSTR_INTSET_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This is the WTLEN interrupt. +#define AM_REG_IOMSTR_INTSET_WTLEN_S 5 +#define AM_REG_IOMSTR_INTSET_WTLEN_M 0x00000020 +#define AM_REG_IOMSTR_INTSET_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This is the I2C NAK interrupt. The expected ACK from the slave was not +// received by the IOM. +#define AM_REG_IOMSTR_INTSET_NAK_S 4 +#define AM_REG_IOMSTR_INTSET_NAK_M 0x00000010 +#define AM_REG_IOMSTR_INTSET_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This is the Write FIFO Overflow interrupt. An attempt was made to write the +// FIFO while it was full (i.e. while FIFOSIZ > 124). +#define AM_REG_IOMSTR_INTSET_FOVFL_S 3 +#define AM_REG_IOMSTR_INTSET_FOVFL_M 0x00000008 +#define AM_REG_IOMSTR_INTSET_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO +// when empty (i.e. while FIFOSIZ less than 4). +#define AM_REG_IOMSTR_INTSET_FUNDFL_S 2 +#define AM_REG_IOMSTR_INTSET_FUNDFL_M 0x00000004 +#define AM_REG_IOMSTR_INTSET_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO Threshold interrupt. +#define AM_REG_IOMSTR_INTSET_THR_S 1 +#define AM_REG_IOMSTR_INTSET_THR_M 0x00000002 +#define AM_REG_IOMSTR_INTSET_THR(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the Command Complete interrupt. +#define AM_REG_IOMSTR_INTSET_CMDCMP_S 0 +#define AM_REG_IOMSTR_INTSET_CMDCMP_M 0x00000001 +#define AM_REG_IOMSTR_INTSET_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOMSTR_FIFO - FIFO Access Port +// +//***************************************************************************** +// FIFO access port. +#define AM_REG_IOMSTR_FIFO_FIFO_S 0 +#define AM_REG_IOMSTR_FIFO_FIFO_M 0xFFFFFFFF +#define AM_REG_IOMSTR_FIFO_FIFO(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// IOMSTR_FIFOPTR - Current FIFO Pointers +// +//***************************************************************************** +// The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or +// 64-FIFOSIZ if FULLDUP = 1)). +#define AM_REG_IOMSTR_FIFOPTR_FIFOREM_S 16 +#define AM_REG_IOMSTR_FIFOPTR_FIFOREM_M 0x00FF0000 +#define AM_REG_IOMSTR_FIFOPTR_FIFOREM(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// The number of bytes currently in the FIFO. +#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_S 0 +#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_M 0x000000FF +#define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// IOMSTR_TLNGTH - Transfer Length +// +//***************************************************************************** +// Remaining transfer length. +#define AM_REG_IOMSTR_TLNGTH_TLNGTH_S 0 +#define AM_REG_IOMSTR_TLNGTH_TLNGTH_M 0x00000FFF +#define AM_REG_IOMSTR_TLNGTH_TLNGTH(n) (((uint32_t)(n) << 0) & 0x00000FFF) + +//***************************************************************************** +// +// IOMSTR_FIFOTHR - FIFO Threshold Configuration +// +//***************************************************************************** +// FIFO write threshold. +#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_S 8 +#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_M 0x00007F00 +#define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(n) (((uint32_t)(n) << 8) & 0x00007F00) + +// FIFO read threshold. +#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_S 0 +#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_M 0x0000007F +#define AM_REG_IOMSTR_FIFOTHR_FIFORTHR(n) (((uint32_t)(n) << 0) & 0x0000007F) + +//***************************************************************************** +// +// IOMSTR_CLKCFG - I/O Clock Configuration +// +//***************************************************************************** +// Clock total count minus 1. +#define AM_REG_IOMSTR_CLKCFG_TOTPER_S 24 +#define AM_REG_IOMSTR_CLKCFG_TOTPER_M 0xFF000000 +#define AM_REG_IOMSTR_CLKCFG_TOTPER(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Clock low count minus 1. +#define AM_REG_IOMSTR_CLKCFG_LOWPER_S 16 +#define AM_REG_IOMSTR_CLKCFG_LOWPER_M 0x00FF0000 +#define AM_REG_IOMSTR_CLKCFG_LOWPER(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Enable clock division by TOTPER. +#define AM_REG_IOMSTR_CLKCFG_DIVEN_S 12 +#define AM_REG_IOMSTR_CLKCFG_DIVEN_M 0x00001000 +#define AM_REG_IOMSTR_CLKCFG_DIVEN(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_IOMSTR_CLKCFG_DIVEN_DIS 0x00000000 +#define AM_REG_IOMSTR_CLKCFG_DIVEN_EN 0x00001000 + +// Enable divide by 3. +#define AM_REG_IOMSTR_CLKCFG_DIV3_S 11 +#define AM_REG_IOMSTR_CLKCFG_DIV3_M 0x00000800 +#define AM_REG_IOMSTR_CLKCFG_DIV3(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_IOMSTR_CLKCFG_DIV3_DIS 0x00000000 +#define AM_REG_IOMSTR_CLKCFG_DIV3_EN 0x00000800 + +// Select the input clock frequency. +#define AM_REG_IOMSTR_CLKCFG_FSEL_S 8 +#define AM_REG_IOMSTR_CLKCFG_FSEL_M 0x00000700 +#define AM_REG_IOMSTR_CLKCFG_FSEL(n) (((uint32_t)(n) << 8) & 0x00000700) +#define AM_REG_IOMSTR_CLKCFG_FSEL_MIN_PWR 0x00000000 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC 0x00000100 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV2 0x00000200 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV4 0x00000300 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV8 0x00000400 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV16 0x00000500 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV32 0x00000600 +#define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV64 0x00000700 + +//***************************************************************************** +// +// IOMSTR_CMD - Command Register +// +//***************************************************************************** +// This register holds the I/O Command +#define AM_REG_IOMSTR_CMD_CMD_S 0 +#define AM_REG_IOMSTR_CMD_CMD_M 0xFFFFFFFF +#define AM_REG_IOMSTR_CMD_CMD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// IOMSTR_CMDRPT - Command Repeat Register +// +//***************************************************************************** +// These bits hold the Command repeat count. +#define AM_REG_IOMSTR_CMDRPT_CMDRPT_S 0 +#define AM_REG_IOMSTR_CMDRPT_CMDRPT_M 0x0000001F +#define AM_REG_IOMSTR_CMDRPT_CMDRPT(n) (((uint32_t)(n) << 0) & 0x0000001F) + +//***************************************************************************** +// +// IOMSTR_STATUS - Status Register +// +//***************************************************************************** +// This bit indicates if the I/O state machine is IDLE. +#define AM_REG_IOMSTR_STATUS_IDLEST_S 2 +#define AM_REG_IOMSTR_STATUS_IDLEST_M 0x00000004 +#define AM_REG_IOMSTR_STATUS_IDLEST(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_IOMSTR_STATUS_IDLEST_IDLE 0x00000004 + +// This bit indicates if the I/O Command is active. +#define AM_REG_IOMSTR_STATUS_CMDACT_S 1 +#define AM_REG_IOMSTR_STATUS_CMDACT_M 0x00000002 +#define AM_REG_IOMSTR_STATUS_CMDACT(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_IOMSTR_STATUS_CMDACT_ACTIVE 0x00000002 + +// This bit indicates if an error interrupt has occurred. +#define AM_REG_IOMSTR_STATUS_ERR_S 0 +#define AM_REG_IOMSTR_STATUS_ERR_M 0x00000001 +#define AM_REG_IOMSTR_STATUS_ERR(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_IOMSTR_STATUS_ERR_ERROR 0x00000001 + +//***************************************************************************** +// +// IOMSTR_CFG - I/O Master Configuration +// +//***************************************************************************** +// This bit enables the IO Master. +#define AM_REG_IOMSTR_CFG_IFCEN_S 31 +#define AM_REG_IOMSTR_CFG_IFCEN_M 0x80000000 +#define AM_REG_IOMSTR_CFG_IFCEN(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_IOMSTR_CFG_IFCEN_DIS 0x00000000 +#define AM_REG_IOMSTR_CFG_IFCEN_EN 0x80000000 + +// This bit selects the read flow control signal polarity. +#define AM_REG_IOMSTR_CFG_RDFCPOL_S 14 +#define AM_REG_IOMSTR_CFG_RDFCPOL_M 0x00004000 +#define AM_REG_IOMSTR_CFG_RDFCPOL(n) (((uint32_t)(n) << 14) & 0x00004000) +#define AM_REG_IOMSTR_CFG_RDFCPOL_HIGH 0x00000000 +#define AM_REG_IOMSTR_CFG_RDFCPOL_LOW 0x00004000 + +// This bit selects the write flow control signal polarity. +#define AM_REG_IOMSTR_CFG_WTFCPOL_S 13 +#define AM_REG_IOMSTR_CFG_WTFCPOL_M 0x00002000 +#define AM_REG_IOMSTR_CFG_WTFCPOL(n) (((uint32_t)(n) << 13) & 0x00002000) +#define AM_REG_IOMSTR_CFG_WTFCPOL_HIGH 0x00000000 +#define AM_REG_IOMSTR_CFG_WTFCPOL_LOW 0x00002000 + +// This bit selects the write mode flow control signal. +#define AM_REG_IOMSTR_CFG_WTFCIRQ_S 12 +#define AM_REG_IOMSTR_CFG_WTFCIRQ_M 0x00001000 +#define AM_REG_IOMSTR_CFG_WTFCIRQ(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_IOMSTR_CFG_WTFCIRQ_MISO 0x00000000 +#define AM_REG_IOMSTR_CFG_WTFCIRQ_IRQ 0x00001000 + +// This bit must be left at the default value of 0. +#define AM_REG_IOMSTR_CFG_FCDEL_S 11 +#define AM_REG_IOMSTR_CFG_FCDEL_M 0x00000800 +#define AM_REG_IOMSTR_CFG_FCDEL(n) (((uint32_t)(n) << 11) & 0x00000800) + +// This bit invewrts MOSI when flow control is enabled. +#define AM_REG_IOMSTR_CFG_MOSIINV_S 10 +#define AM_REG_IOMSTR_CFG_MOSIINV_M 0x00000400 +#define AM_REG_IOMSTR_CFG_MOSIINV(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_IOMSTR_CFG_MOSIINV_NORMAL 0x00000000 +#define AM_REG_IOMSTR_CFG_MOSIINV_INVERT 0x00000400 + +// This bit enables read mode flow control. +#define AM_REG_IOMSTR_CFG_RDFC_S 9 +#define AM_REG_IOMSTR_CFG_RDFC_M 0x00000200 +#define AM_REG_IOMSTR_CFG_RDFC(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_IOMSTR_CFG_RDFC_DIS 0x00000000 +#define AM_REG_IOMSTR_CFG_RDFC_EN 0x00000200 + +// This bit enables write mode flow control. +#define AM_REG_IOMSTR_CFG_WTFC_S 8 +#define AM_REG_IOMSTR_CFG_WTFC_M 0x00000100 +#define AM_REG_IOMSTR_CFG_WTFC(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_IOMSTR_CFG_WTFC_DIS 0x00000000 +#define AM_REG_IOMSTR_CFG_WTFC_EN 0x00000100 + +// This bit selects the preread timing. +#define AM_REG_IOMSTR_CFG_STARTRD_S 4 +#define AM_REG_IOMSTR_CFG_STARTRD_M 0x00000030 +#define AM_REG_IOMSTR_CFG_STARTRD(n) (((uint32_t)(n) << 4) & 0x00000030) +#define AM_REG_IOMSTR_CFG_STARTRD_PRERD0 0x00000000 +#define AM_REG_IOMSTR_CFG_STARTRD_PRERD1 0x00000010 +#define AM_REG_IOMSTR_CFG_STARTRD_PRERD2 0x00000020 +#define AM_REG_IOMSTR_CFG_STARTRD_PRERD3 0x00000030 + +// This bit selects full duplex mode. +#define AM_REG_IOMSTR_CFG_FULLDUP_S 3 +#define AM_REG_IOMSTR_CFG_FULLDUP_M 0x00000008 +#define AM_REG_IOMSTR_CFG_FULLDUP(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_IOMSTR_CFG_FULLDUP_NORMAL 0x00000000 +#define AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP 0x00000008 + +// This bit selects SPI phase. +#define AM_REG_IOMSTR_CFG_SPHA_S 2 +#define AM_REG_IOMSTR_CFG_SPHA_M 0x00000004 +#define AM_REG_IOMSTR_CFG_SPHA(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_LEADING_EDGE 0x00000000 +#define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_TRAILING_EDGE 0x00000004 + +// This bit selects SPI polarity. +#define AM_REG_IOMSTR_CFG_SPOL_S 1 +#define AM_REG_IOMSTR_CFG_SPOL_M 0x00000002 +#define AM_REG_IOMSTR_CFG_SPOL(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_0 0x00000000 +#define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_1 0x00000002 + +// This bit selects the I/O interface. +#define AM_REG_IOMSTR_CFG_IFCSEL_S 0 +#define AM_REG_IOMSTR_CFG_IFCSEL_M 0x00000001 +#define AM_REG_IOMSTR_CFG_IFCSEL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_IOMSTR_CFG_IFCSEL_I2C 0x00000000 +#define AM_REG_IOMSTR_CFG_IFCSEL_SPI 0x00000001 + +#endif // AM_REG_IOMSTR_H diff --git a/mcu/apollo2/regs/am_reg_ioslave.h b/mcu/apollo2/regs/am_reg_ioslave.h new file mode 100644 index 0000000..6debbbf --- /dev/null +++ b/mcu/apollo2/regs/am_reg_ioslave.h @@ -0,0 +1,515 @@ +//***************************************************************************** +// +// am_reg_ioslave.h +//! @file +//! +//! @brief Register macros for the IOSLAVE module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_IOSLAVE_H +#define AM_REG_IOSLAVE_H + +//***************************************************************************** +// +// IOSLAVE +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_IOSLAVE_NUM_MODULES 1 +#define AM_REG_IOSLAVEn(n) \ + (REG_IOSLAVE_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_IOSLAVE_FIFOPTR_O 0x00000100 +#define AM_REG_IOSLAVE_FIFOCFG_O 0x00000104 +#define AM_REG_IOSLAVE_FIFOTHR_O 0x00000108 +#define AM_REG_IOSLAVE_FUPD_O 0x0000010C +#define AM_REG_IOSLAVE_FIFOCTR_O 0x00000110 +#define AM_REG_IOSLAVE_FIFOINC_O 0x00000114 +#define AM_REG_IOSLAVE_CFG_O 0x00000118 +#define AM_REG_IOSLAVE_PRENC_O 0x0000011C +#define AM_REG_IOSLAVE_IOINTCTL_O 0x00000120 +#define AM_REG_IOSLAVE_GENADD_O 0x00000124 +#define AM_REG_IOSLAVE_INTEN_O 0x00000200 +#define AM_REG_IOSLAVE_INTSTAT_O 0x00000204 +#define AM_REG_IOSLAVE_INTCLR_O 0x00000208 +#define AM_REG_IOSLAVE_INTSET_O 0x0000020C +#define AM_REG_IOSLAVE_REGACCINTEN_O 0x00000210 +#define AM_REG_IOSLAVE_REGACCINTSTAT_O 0x00000214 +#define AM_REG_IOSLAVE_REGACCINTCLR_O 0x00000218 +#define AM_REG_IOSLAVE_REGACCINTSET_O 0x0000021C + +//***************************************************************************** +// +// IOSLAVE_INTEN - IO Slave Interrupts: Enable +// +//***************************************************************************** +// Transfer complete interrupt, write to register space. +#define AM_REG_IOSLAVE_INTEN_XCMPWR_S 9 +#define AM_REG_IOSLAVE_INTEN_XCMPWR_M 0x00000200 +#define AM_REG_IOSLAVE_INTEN_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Transfer complete interrupt, write to FIFO space. +#define AM_REG_IOSLAVE_INTEN_XCMPWF_S 8 +#define AM_REG_IOSLAVE_INTEN_XCMPWF_M 0x00000100 +#define AM_REG_IOSLAVE_INTEN_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Transfer complete interrupt, read from register space. +#define AM_REG_IOSLAVE_INTEN_XCMPRR_S 7 +#define AM_REG_IOSLAVE_INTEN_XCMPRR_M 0x00000080 +#define AM_REG_IOSLAVE_INTEN_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Transfer complete interrupt, read from FIFO space. +#define AM_REG_IOSLAVE_INTEN_XCMPRF_S 6 +#define AM_REG_IOSLAVE_INTEN_XCMPRF_M 0x00000040 +#define AM_REG_IOSLAVE_INTEN_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) + +// I2C Interrupt Write interrupt. +#define AM_REG_IOSLAVE_INTEN_IOINTW_S 5 +#define AM_REG_IOSLAVE_INTEN_IOINTW_M 0x00000020 +#define AM_REG_IOSLAVE_INTEN_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) + +// I2C General Address interrupt. +#define AM_REG_IOSLAVE_INTEN_GENAD_S 4 +#define AM_REG_IOSLAVE_INTEN_GENAD_M 0x00000010 +#define AM_REG_IOSLAVE_INTEN_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) + +// FIFO Read Error interrupt. +#define AM_REG_IOSLAVE_INTEN_FRDERR_S 3 +#define AM_REG_IOSLAVE_INTEN_FRDERR_M 0x00000008 +#define AM_REG_IOSLAVE_INTEN_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) + +// FIFO Underflow interrupt. +#define AM_REG_IOSLAVE_INTEN_FUNDFL_S 2 +#define AM_REG_IOSLAVE_INTEN_FUNDFL_M 0x00000004 +#define AM_REG_IOSLAVE_INTEN_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// FIFO Overflow interrupt. +#define AM_REG_IOSLAVE_INTEN_FOVFL_S 1 +#define AM_REG_IOSLAVE_INTEN_FOVFL_M 0x00000002 +#define AM_REG_IOSLAVE_INTEN_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) + +// FIFO Size interrupt. +#define AM_REG_IOSLAVE_INTEN_FSIZE_S 0 +#define AM_REG_IOSLAVE_INTEN_FSIZE_M 0x00000001 +#define AM_REG_IOSLAVE_INTEN_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOSLAVE_INTSTAT - IO Slave Interrupts: Status +// +//***************************************************************************** +// Transfer complete interrupt, write to register space. +#define AM_REG_IOSLAVE_INTSTAT_XCMPWR_S 9 +#define AM_REG_IOSLAVE_INTSTAT_XCMPWR_M 0x00000200 +#define AM_REG_IOSLAVE_INTSTAT_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Transfer complete interrupt, write to FIFO space. +#define AM_REG_IOSLAVE_INTSTAT_XCMPWF_S 8 +#define AM_REG_IOSLAVE_INTSTAT_XCMPWF_M 0x00000100 +#define AM_REG_IOSLAVE_INTSTAT_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Transfer complete interrupt, read from register space. +#define AM_REG_IOSLAVE_INTSTAT_XCMPRR_S 7 +#define AM_REG_IOSLAVE_INTSTAT_XCMPRR_M 0x00000080 +#define AM_REG_IOSLAVE_INTSTAT_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Transfer complete interrupt, read from FIFO space. +#define AM_REG_IOSLAVE_INTSTAT_XCMPRF_S 6 +#define AM_REG_IOSLAVE_INTSTAT_XCMPRF_M 0x00000040 +#define AM_REG_IOSLAVE_INTSTAT_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) + +// I2C Interrupt Write interrupt. +#define AM_REG_IOSLAVE_INTSTAT_IOINTW_S 5 +#define AM_REG_IOSLAVE_INTSTAT_IOINTW_M 0x00000020 +#define AM_REG_IOSLAVE_INTSTAT_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) + +// I2C General Address interrupt. +#define AM_REG_IOSLAVE_INTSTAT_GENAD_S 4 +#define AM_REG_IOSLAVE_INTSTAT_GENAD_M 0x00000010 +#define AM_REG_IOSLAVE_INTSTAT_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) + +// FIFO Read Error interrupt. +#define AM_REG_IOSLAVE_INTSTAT_FRDERR_S 3 +#define AM_REG_IOSLAVE_INTSTAT_FRDERR_M 0x00000008 +#define AM_REG_IOSLAVE_INTSTAT_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) + +// FIFO Underflow interrupt. +#define AM_REG_IOSLAVE_INTSTAT_FUNDFL_S 2 +#define AM_REG_IOSLAVE_INTSTAT_FUNDFL_M 0x00000004 +#define AM_REG_IOSLAVE_INTSTAT_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// FIFO Overflow interrupt. +#define AM_REG_IOSLAVE_INTSTAT_FOVFL_S 1 +#define AM_REG_IOSLAVE_INTSTAT_FOVFL_M 0x00000002 +#define AM_REG_IOSLAVE_INTSTAT_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) + +// FIFO Size interrupt. +#define AM_REG_IOSLAVE_INTSTAT_FSIZE_S 0 +#define AM_REG_IOSLAVE_INTSTAT_FSIZE_M 0x00000001 +#define AM_REG_IOSLAVE_INTSTAT_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOSLAVE_INTCLR - IO Slave Interrupts: Clear +// +//***************************************************************************** +// Transfer complete interrupt, write to register space. +#define AM_REG_IOSLAVE_INTCLR_XCMPWR_S 9 +#define AM_REG_IOSLAVE_INTCLR_XCMPWR_M 0x00000200 +#define AM_REG_IOSLAVE_INTCLR_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Transfer complete interrupt, write to FIFO space. +#define AM_REG_IOSLAVE_INTCLR_XCMPWF_S 8 +#define AM_REG_IOSLAVE_INTCLR_XCMPWF_M 0x00000100 +#define AM_REG_IOSLAVE_INTCLR_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Transfer complete interrupt, read from register space. +#define AM_REG_IOSLAVE_INTCLR_XCMPRR_S 7 +#define AM_REG_IOSLAVE_INTCLR_XCMPRR_M 0x00000080 +#define AM_REG_IOSLAVE_INTCLR_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Transfer complete interrupt, read from FIFO space. +#define AM_REG_IOSLAVE_INTCLR_XCMPRF_S 6 +#define AM_REG_IOSLAVE_INTCLR_XCMPRF_M 0x00000040 +#define AM_REG_IOSLAVE_INTCLR_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) + +// I2C Interrupt Write interrupt. +#define AM_REG_IOSLAVE_INTCLR_IOINTW_S 5 +#define AM_REG_IOSLAVE_INTCLR_IOINTW_M 0x00000020 +#define AM_REG_IOSLAVE_INTCLR_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) + +// I2C General Address interrupt. +#define AM_REG_IOSLAVE_INTCLR_GENAD_S 4 +#define AM_REG_IOSLAVE_INTCLR_GENAD_M 0x00000010 +#define AM_REG_IOSLAVE_INTCLR_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) + +// FIFO Read Error interrupt. +#define AM_REG_IOSLAVE_INTCLR_FRDERR_S 3 +#define AM_REG_IOSLAVE_INTCLR_FRDERR_M 0x00000008 +#define AM_REG_IOSLAVE_INTCLR_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) + +// FIFO Underflow interrupt. +#define AM_REG_IOSLAVE_INTCLR_FUNDFL_S 2 +#define AM_REG_IOSLAVE_INTCLR_FUNDFL_M 0x00000004 +#define AM_REG_IOSLAVE_INTCLR_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// FIFO Overflow interrupt. +#define AM_REG_IOSLAVE_INTCLR_FOVFL_S 1 +#define AM_REG_IOSLAVE_INTCLR_FOVFL_M 0x00000002 +#define AM_REG_IOSLAVE_INTCLR_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) + +// FIFO Size interrupt. +#define AM_REG_IOSLAVE_INTCLR_FSIZE_S 0 +#define AM_REG_IOSLAVE_INTCLR_FSIZE_M 0x00000001 +#define AM_REG_IOSLAVE_INTCLR_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOSLAVE_INTSET - IO Slave Interrupts: Set +// +//***************************************************************************** +// Transfer complete interrupt, write to register space. +#define AM_REG_IOSLAVE_INTSET_XCMPWR_S 9 +#define AM_REG_IOSLAVE_INTSET_XCMPWR_M 0x00000200 +#define AM_REG_IOSLAVE_INTSET_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Transfer complete interrupt, write to FIFO space. +#define AM_REG_IOSLAVE_INTSET_XCMPWF_S 8 +#define AM_REG_IOSLAVE_INTSET_XCMPWF_M 0x00000100 +#define AM_REG_IOSLAVE_INTSET_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Transfer complete interrupt, read from register space. +#define AM_REG_IOSLAVE_INTSET_XCMPRR_S 7 +#define AM_REG_IOSLAVE_INTSET_XCMPRR_M 0x00000080 +#define AM_REG_IOSLAVE_INTSET_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Transfer complete interrupt, read from FIFO space. +#define AM_REG_IOSLAVE_INTSET_XCMPRF_S 6 +#define AM_REG_IOSLAVE_INTSET_XCMPRF_M 0x00000040 +#define AM_REG_IOSLAVE_INTSET_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) + +// I2C Interrupt Write interrupt. +#define AM_REG_IOSLAVE_INTSET_IOINTW_S 5 +#define AM_REG_IOSLAVE_INTSET_IOINTW_M 0x00000020 +#define AM_REG_IOSLAVE_INTSET_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) + +// I2C General Address interrupt. +#define AM_REG_IOSLAVE_INTSET_GENAD_S 4 +#define AM_REG_IOSLAVE_INTSET_GENAD_M 0x00000010 +#define AM_REG_IOSLAVE_INTSET_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) + +// FIFO Read Error interrupt. +#define AM_REG_IOSLAVE_INTSET_FRDERR_S 3 +#define AM_REG_IOSLAVE_INTSET_FRDERR_M 0x00000008 +#define AM_REG_IOSLAVE_INTSET_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) + +// FIFO Underflow interrupt. +#define AM_REG_IOSLAVE_INTSET_FUNDFL_S 2 +#define AM_REG_IOSLAVE_INTSET_FUNDFL_M 0x00000004 +#define AM_REG_IOSLAVE_INTSET_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// FIFO Overflow interrupt. +#define AM_REG_IOSLAVE_INTSET_FOVFL_S 1 +#define AM_REG_IOSLAVE_INTSET_FOVFL_M 0x00000002 +#define AM_REG_IOSLAVE_INTSET_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) + +// FIFO Size interrupt. +#define AM_REG_IOSLAVE_INTSET_FSIZE_S 0 +#define AM_REG_IOSLAVE_INTSET_FSIZE_M 0x00000001 +#define AM_REG_IOSLAVE_INTSET_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOSLAVE_REGACCINTEN - Register Access Interrupts: Enable +// +//***************************************************************************** +// Register access interrupts. +#define AM_REG_IOSLAVE_REGACCINTEN_REGACC_S 0 +#define AM_REG_IOSLAVE_REGACCINTEN_REGACC_M 0xFFFFFFFF +#define AM_REG_IOSLAVE_REGACCINTEN_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// IOSLAVE_REGACCINTSTAT - Register Access Interrupts: Status +// +//***************************************************************************** +// Register access interrupts. +#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_S 0 +#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_M 0xFFFFFFFF +#define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// IOSLAVE_REGACCINTCLR - Register Access Interrupts: Clear +// +//***************************************************************************** +// Register access interrupts. +#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_S 0 +#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_M 0xFFFFFFFF +#define AM_REG_IOSLAVE_REGACCINTCLR_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// IOSLAVE_REGACCINTSET - Register Access Interrupts: Set +// +//***************************************************************************** +// Register access interrupts. +#define AM_REG_IOSLAVE_REGACCINTSET_REGACC_S 0 +#define AM_REG_IOSLAVE_REGACCINTSET_REGACC_M 0xFFFFFFFF +#define AM_REG_IOSLAVE_REGACCINTSET_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// IOSLAVE_FIFOPTR - Current FIFO Pointer +// +//***************************************************************************** +// The number of bytes currently in the hardware FIFO. +#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S 8 +#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M 0x0000FF00 +#define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Current FIFO pointer. +#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S 0 +#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M 0x000000FF +#define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// IOSLAVE_FIFOCFG - FIFO Configuration +// +//***************************************************************************** +// Defines the read-only area. The IO Slave read-only area is situated in LRAM +// at (ROBASE*8) to (FIFOOBASE*8-1) +#define AM_REG_IOSLAVE_FIFOCFG_ROBASE_S 24 +#define AM_REG_IOSLAVE_FIFOCFG_ROBASE_M 0x3F000000 +#define AM_REG_IOSLAVE_FIFOCFG_ROBASE(n) (((uint32_t)(n) << 24) & 0x3F000000) + +// These bits hold the maximum FIFO address in 8 byte segments. It is also the +// beginning of the RAM area of the LRAM. Note that no RAM area is configured +// if FIFOMAX is set to 0x1F. +#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_S 8 +#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_M 0x00003F00 +#define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(n) (((uint32_t)(n) << 8) & 0x00003F00) + +// These bits hold the base address of the I/O FIFO in 8 byte segments. The IO +// Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1). +#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_S 0 +#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_M 0x0000001F +#define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(n) (((uint32_t)(n) << 0) & 0x0000001F) + +//***************************************************************************** +// +// IOSLAVE_FIFOTHR - FIFO Threshold Configuration +// +//***************************************************************************** +// FIFO size interrupt threshold. +#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_S 0 +#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_M 0x000000FF +#define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// IOSLAVE_FUPD - FIFO Update Status +// +//***************************************************************************** +// This bitfield indicates an IO read is active. +#define AM_REG_IOSLAVE_FUPD_IOREAD_S 1 +#define AM_REG_IOSLAVE_FUPD_IOREAD_M 0x00000002 +#define AM_REG_IOSLAVE_FUPD_IOREAD(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit indicates that a FIFO update is underway. +#define AM_REG_IOSLAVE_FUPD_FIFOUPD_S 0 +#define AM_REG_IOSLAVE_FUPD_FIFOUPD_M 0x00000001 +#define AM_REG_IOSLAVE_FUPD_FIFOUPD(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// IOSLAVE_FIFOCTR - Overall FIFO Counter +// +//***************************************************************************** +// Virtual FIFO byte count +#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_S 0 +#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_M 0x000003FF +#define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR(n) (((uint32_t)(n) << 0) & 0x000003FF) + +//***************************************************************************** +// +// IOSLAVE_FIFOINC - Overall FIFO Counter Increment +// +//***************************************************************************** +// Increment the Overall FIFO Counter by this value on a write +#define AM_REG_IOSLAVE_FIFOINC_FIFOINC_S 0 +#define AM_REG_IOSLAVE_FIFOINC_FIFOINC_M 0x000003FF +#define AM_REG_IOSLAVE_FIFOINC_FIFOINC(n) (((uint32_t)(n) << 0) & 0x000003FF) + +//***************************************************************************** +// +// IOSLAVE_CFG - I/O Slave Configuration +// +//***************************************************************************** +// IOSLAVE interface enable. +#define AM_REG_IOSLAVE_CFG_IFCEN_S 31 +#define AM_REG_IOSLAVE_CFG_IFCEN_M 0x80000000 +#define AM_REG_IOSLAVE_CFG_IFCEN(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_IOSLAVE_CFG_IFCEN_DIS 0x00000000 +#define AM_REG_IOSLAVE_CFG_IFCEN_EN 0x80000000 + +// 7-bit or 10-bit I2C device address. +#define AM_REG_IOSLAVE_CFG_I2CADDR_S 8 +#define AM_REG_IOSLAVE_CFG_I2CADDR_M 0x000FFF00 +#define AM_REG_IOSLAVE_CFG_I2CADDR(n) (((uint32_t)(n) << 8) & 0x000FFF00) + +// This bit holds the cycle to initiate an I/O RAM read. +#define AM_REG_IOSLAVE_CFG_STARTRD_S 4 +#define AM_REG_IOSLAVE_CFG_STARTRD_M 0x00000010 +#define AM_REG_IOSLAVE_CFG_STARTRD(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_IOSLAVE_CFG_STARTRD_LATE 0x00000000 +#define AM_REG_IOSLAVE_CFG_STARTRD_EARLY 0x00000010 + +// This bit selects the transfer bit ordering. +#define AM_REG_IOSLAVE_CFG_LSB_S 2 +#define AM_REG_IOSLAVE_CFG_LSB_M 0x00000004 +#define AM_REG_IOSLAVE_CFG_LSB(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_IOSLAVE_CFG_LSB_MSB_FIRST 0x00000000 +#define AM_REG_IOSLAVE_CFG_LSB_LSB_FIRST 0x00000004 + +// This bit selects SPI polarity. +#define AM_REG_IOSLAVE_CFG_SPOL_S 1 +#define AM_REG_IOSLAVE_CFG_SPOL_M 0x00000002 +#define AM_REG_IOSLAVE_CFG_SPOL(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3 0x00000000 +#define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2 0x00000002 + +// This bit selects the I/O interface. +#define AM_REG_IOSLAVE_CFG_IFCSEL_S 0 +#define AM_REG_IOSLAVE_CFG_IFCSEL_M 0x00000001 +#define AM_REG_IOSLAVE_CFG_IFCSEL(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_IOSLAVE_CFG_IFCSEL_I2C 0x00000000 +#define AM_REG_IOSLAVE_CFG_IFCSEL_SPI 0x00000001 + +//***************************************************************************** +// +// IOSLAVE_PRENC - I/O Slave Interrupt Priority Encode +// +//***************************************************************************** +// These bits hold the priority encode of the REGACC interrupts. +#define AM_REG_IOSLAVE_PRENC_PRENC_S 0 +#define AM_REG_IOSLAVE_PRENC_PRENC_M 0x0000001F +#define AM_REG_IOSLAVE_PRENC_PRENC(n) (((uint32_t)(n) << 0) & 0x0000001F) + +//***************************************************************************** +// +// IOSLAVE_IOINTCTL - I/O Interrupt Control +// +//***************************************************************************** +// These bits set the IOINT interrupts when written with a 1. +#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_S 24 +#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_M 0xFF000000 +#define AM_REG_IOSLAVE_IOINTCTL_IOINTSET(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// This bit clears all of the IOINT interrupts when written with a 1. +#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_S 16 +#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_M 0x00010000 +#define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR(n) (((uint32_t)(n) << 16) & 0x00010000) + +// These bits read the IOINT interrupts. +#define AM_REG_IOSLAVE_IOINTCTL_IOINT_S 8 +#define AM_REG_IOSLAVE_IOINTCTL_IOINT_M 0x0000FF00 +#define AM_REG_IOSLAVE_IOINTCTL_IOINT(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// These read-only bits indicate whether the IOINT interrupts are enabled. +#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_S 0 +#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_M 0x000000FF +#define AM_REG_IOSLAVE_IOINTCTL_IOINTEN(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// IOSLAVE_GENADD - General Address Data +// +//***************************************************************************** +// The data supplied on the last General Address reference. +#define AM_REG_IOSLAVE_GENADD_GADATA_S 0 +#define AM_REG_IOSLAVE_GENADD_GADATA_M 0x000000FF +#define AM_REG_IOSLAVE_GENADD_GADATA(n) (((uint32_t)(n) << 0) & 0x000000FF) + +#endif // AM_REG_IOSLAVE_H diff --git a/mcu/apollo2/regs/am_reg_itm.h b/mcu/apollo2/regs/am_reg_itm.h new file mode 100644 index 0000000..cc1121d --- /dev/null +++ b/mcu/apollo2/regs/am_reg_itm.h @@ -0,0 +1,659 @@ +//***************************************************************************** +// +// am_reg_itm.h +//! @file +//! +//! @brief Register macros for the ITM module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_ITM_H +#define AM_REG_ITM_H + +//***************************************************************************** +// +// ITM +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_ITM_NUM_MODULES 1 +#define AM_REG_ITMn(n) \ + (REG_ITM_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_ITM_STIM0_O 0xE0000000 +#define AM_REG_ITM_STIM1_O 0xE0000004 +#define AM_REG_ITM_STIM2_O 0xE0000008 +#define AM_REG_ITM_STIM3_O 0xE000000C +#define AM_REG_ITM_STIM4_O 0xE0000010 +#define AM_REG_ITM_STIM5_O 0xE0000014 +#define AM_REG_ITM_STIM6_O 0xE0000018 +#define AM_REG_ITM_STIM7_O 0xE000001C +#define AM_REG_ITM_STIM8_O 0xE0000020 +#define AM_REG_ITM_STIM9_O 0xE0000024 +#define AM_REG_ITM_STIM10_O 0xE0000028 +#define AM_REG_ITM_STIM11_O 0xE000002C +#define AM_REG_ITM_STIM12_O 0xE0000030 +#define AM_REG_ITM_STIM13_O 0xE0000034 +#define AM_REG_ITM_STIM14_O 0xE0000038 +#define AM_REG_ITM_STIM15_O 0xE000003C +#define AM_REG_ITM_STIM16_O 0xE0000040 +#define AM_REG_ITM_STIM17_O 0xE0000044 +#define AM_REG_ITM_STIM18_O 0xE0000048 +#define AM_REG_ITM_STIM19_O 0xE000004C +#define AM_REG_ITM_STIM20_O 0xE0000050 +#define AM_REG_ITM_STIM21_O 0xE0000054 +#define AM_REG_ITM_STIM22_O 0xE0000058 +#define AM_REG_ITM_STIM23_O 0xE000005C +#define AM_REG_ITM_STIM24_O 0xE0000060 +#define AM_REG_ITM_STIM25_O 0xE0000064 +#define AM_REG_ITM_STIM26_O 0xE0000068 +#define AM_REG_ITM_STIM27_O 0xE000006C +#define AM_REG_ITM_STIM28_O 0xE0000070 +#define AM_REG_ITM_STIM29_O 0xE0000074 +#define AM_REG_ITM_STIM30_O 0xE0000078 +#define AM_REG_ITM_STIM31_O 0xE000007C +#define AM_REG_ITM_TER_O 0xE0000E00 +#define AM_REG_ITM_TPR_O 0xE0000E40 +#define AM_REG_ITM_TCR_O 0xE0000E80 +#define AM_REG_ITM_LOCKSREG_O 0xE0000FB4 +#define AM_REG_ITM_PID4_O 0xE0000FD0 +#define AM_REG_ITM_PID5_O 0xE0000FD4 +#define AM_REG_ITM_PID6_O 0xE0000FD8 +#define AM_REG_ITM_PID7_O 0xE0000FDC +#define AM_REG_ITM_PID0_O 0xE0000FE0 +#define AM_REG_ITM_PID1_O 0xE0000FE4 +#define AM_REG_ITM_PID2_O 0xE0000FE8 +#define AM_REG_ITM_PID3_O 0xE0000FEC +#define AM_REG_ITM_CID0_O 0xE0000FF0 +#define AM_REG_ITM_CID1_O 0xE0000FF4 +#define AM_REG_ITM_CID2_O 0xE0000FF8 +#define AM_REG_ITM_CID3_O 0xE0000FFC +#define AM_REG_ITM_LOCKAREG_O 0xE0000FB0 + +//***************************************************************************** +// +// Key values. +// +//***************************************************************************** +#define AM_REG_ITM_LOCKAREG_KEYVAL 0xC5ACCE55 + +//***************************************************************************** +// +// ITM_STIM0 - Stimulus Port Register 0 +// +//***************************************************************************** +// Stimulus Port Register 0. +#define AM_REG_ITM_STIM0_STIM0_S 0 +#define AM_REG_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define AM_REG_ITM_STIM0_STIM0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM1 - Stimulus Port Register 1 +// +//***************************************************************************** +// Stimulus Port Register 1. +#define AM_REG_ITM_STIM1_STIM1_S 0 +#define AM_REG_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define AM_REG_ITM_STIM1_STIM1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM2 - Stimulus Port Register 2 +// +//***************************************************************************** +// Stimulus Port Register 2. +#define AM_REG_ITM_STIM2_STIM2_S 0 +#define AM_REG_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define AM_REG_ITM_STIM2_STIM2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM3 - Stimulus Port Register 3 +// +//***************************************************************************** +// Stimulus Port Register 3. +#define AM_REG_ITM_STIM3_STIM3_S 0 +#define AM_REG_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define AM_REG_ITM_STIM3_STIM3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM4 - Stimulus Port Register 4 +// +//***************************************************************************** +// Stimulus Port Register 4. +#define AM_REG_ITM_STIM4_STIM4_S 0 +#define AM_REG_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define AM_REG_ITM_STIM4_STIM4(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM5 - Stimulus Port Register 5 +// +//***************************************************************************** +// Stimulus Port Register 5. +#define AM_REG_ITM_STIM5_STIM5_S 0 +#define AM_REG_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define AM_REG_ITM_STIM5_STIM5(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM6 - Stimulus Port Register 6 +// +//***************************************************************************** +// Stimulus Port Register 6. +#define AM_REG_ITM_STIM6_STIM6_S 0 +#define AM_REG_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define AM_REG_ITM_STIM6_STIM6(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM7 - Stimulus Port Register 7 +// +//***************************************************************************** +// Stimulus Port Register 7. +#define AM_REG_ITM_STIM7_STIM7_S 0 +#define AM_REG_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define AM_REG_ITM_STIM7_STIM7(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM8 - Stimulus Port Register 8 +// +//***************************************************************************** +// Stimulus Port Register 8. +#define AM_REG_ITM_STIM8_STIM8_S 0 +#define AM_REG_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define AM_REG_ITM_STIM8_STIM8(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM9 - Stimulus Port Register 9 +// +//***************************************************************************** +// Stimulus Port Register 9. +#define AM_REG_ITM_STIM9_STIM9_S 0 +#define AM_REG_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define AM_REG_ITM_STIM9_STIM9(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM10 - Stimulus Port Register 10 +// +//***************************************************************************** +// Stimulus Port Register 10. +#define AM_REG_ITM_STIM10_STIM10_S 0 +#define AM_REG_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define AM_REG_ITM_STIM10_STIM10(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM11 - Stimulus Port Register 11 +// +//***************************************************************************** +// Stimulus Port Register 11. +#define AM_REG_ITM_STIM11_STIM11_S 0 +#define AM_REG_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define AM_REG_ITM_STIM11_STIM11(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM12 - Stimulus Port Register 12 +// +//***************************************************************************** +// Stimulus Port Register 12. +#define AM_REG_ITM_STIM12_STIM12_S 0 +#define AM_REG_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define AM_REG_ITM_STIM12_STIM12(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM13 - Stimulus Port Register 13 +// +//***************************************************************************** +// Stimulus Port Register 13. +#define AM_REG_ITM_STIM13_STIM13_S 0 +#define AM_REG_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define AM_REG_ITM_STIM13_STIM13(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM14 - Stimulus Port Register 14 +// +//***************************************************************************** +// Stimulus Port Register 14. +#define AM_REG_ITM_STIM14_STIM14_S 0 +#define AM_REG_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define AM_REG_ITM_STIM14_STIM14(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM15 - Stimulus Port Register 15 +// +//***************************************************************************** +// Stimulus Port Register 15. +#define AM_REG_ITM_STIM15_STIM15_S 0 +#define AM_REG_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define AM_REG_ITM_STIM15_STIM15(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM16 - Stimulus Port Register 16 +// +//***************************************************************************** +// Stimulus Port Register 16. +#define AM_REG_ITM_STIM16_STIM16_S 0 +#define AM_REG_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define AM_REG_ITM_STIM16_STIM16(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM17 - Stimulus Port Register 17 +// +//***************************************************************************** +// Stimulus Port Register 17. +#define AM_REG_ITM_STIM17_STIM17_S 0 +#define AM_REG_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define AM_REG_ITM_STIM17_STIM17(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM18 - Stimulus Port Register 18 +// +//***************************************************************************** +// Stimulus Port Register 18. +#define AM_REG_ITM_STIM18_STIM18_S 0 +#define AM_REG_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define AM_REG_ITM_STIM18_STIM18(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM19 - Stimulus Port Register 19 +// +//***************************************************************************** +// Stimulus Port Register 19. +#define AM_REG_ITM_STIM19_STIM19_S 0 +#define AM_REG_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define AM_REG_ITM_STIM19_STIM19(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM20 - Stimulus Port Register 20 +// +//***************************************************************************** +// Stimulus Port Register 20. +#define AM_REG_ITM_STIM20_STIM20_S 0 +#define AM_REG_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define AM_REG_ITM_STIM20_STIM20(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM21 - Stimulus Port Register 21 +// +//***************************************************************************** +// Stimulus Port Register 21. +#define AM_REG_ITM_STIM21_STIM21_S 0 +#define AM_REG_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define AM_REG_ITM_STIM21_STIM21(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM22 - Stimulus Port Register 22 +// +//***************************************************************************** +// Stimulus Port Register 22. +#define AM_REG_ITM_STIM22_STIM22_S 0 +#define AM_REG_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define AM_REG_ITM_STIM22_STIM22(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM23 - Stimulus Port Register 23 +// +//***************************************************************************** +// Stimulus Port Register 23. +#define AM_REG_ITM_STIM23_STIM23_S 0 +#define AM_REG_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define AM_REG_ITM_STIM23_STIM23(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM24 - Stimulus Port Register 24 +// +//***************************************************************************** +// Stimulus Port Register 24. +#define AM_REG_ITM_STIM24_STIM24_S 0 +#define AM_REG_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define AM_REG_ITM_STIM24_STIM24(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM25 - Stimulus Port Register 25 +// +//***************************************************************************** +// Stimulus Port Register 25. +#define AM_REG_ITM_STIM25_STIM25_S 0 +#define AM_REG_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define AM_REG_ITM_STIM25_STIM25(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM26 - Stimulus Port Register 26 +// +//***************************************************************************** +// Stimulus Port Register 26. +#define AM_REG_ITM_STIM26_STIM26_S 0 +#define AM_REG_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define AM_REG_ITM_STIM26_STIM26(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM27 - Stimulus Port Register 27 +// +//***************************************************************************** +// Stimulus Port Register 27. +#define AM_REG_ITM_STIM27_STIM27_S 0 +#define AM_REG_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define AM_REG_ITM_STIM27_STIM27(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM28 - Stimulus Port Register 28 +// +//***************************************************************************** +// Stimulus Port Register 28. +#define AM_REG_ITM_STIM28_STIM28_S 0 +#define AM_REG_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define AM_REG_ITM_STIM28_STIM28(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM29 - Stimulus Port Register 29 +// +//***************************************************************************** +// Stimulus Port Register 29. +#define AM_REG_ITM_STIM29_STIM29_S 0 +#define AM_REG_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define AM_REG_ITM_STIM29_STIM29(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM30 - Stimulus Port Register 30 +// +//***************************************************************************** +// Stimulus Port Register 30. +#define AM_REG_ITM_STIM30_STIM30_S 0 +#define AM_REG_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define AM_REG_ITM_STIM30_STIM30(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_STIM31 - Stimulus Port Register 31 +// +//***************************************************************************** +// Stimulus Port Register 31. +#define AM_REG_ITM_STIM31_STIM31_S 0 +#define AM_REG_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define AM_REG_ITM_STIM31_STIM31(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_TER - Trace Enable Register. +// +//***************************************************************************** +// Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.. +#define AM_REG_ITM_TER_STIMENA_S 0 +#define AM_REG_ITM_TER_STIMENA_M 0xFFFFFFFF +#define AM_REG_ITM_TER_STIMENA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_TPR - Trace Privilege Register. +// +//***************************************************************************** +// Bit mask to enable tracing on ITM stimulus ports. bit[0] = stimulus +// ports[7:0], bit[1] = stimulus ports[15:8], bit[2] = stimulus ports[23:16], +// bit[3] = stimulus ports[31:24]. +#define AM_REG_ITM_TPR_PRIVMASK_S 0 +#define AM_REG_ITM_TPR_PRIVMASK_M 0x0000000F +#define AM_REG_ITM_TPR_PRIVMASK(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// ITM_TCR - Trace Control Register. +// +//***************************************************************************** +// Set when ITM events present and being drained. +#define AM_REG_ITM_TCR_BUSY_S 23 +#define AM_REG_ITM_TCR_BUSY_M 0x00800000 +#define AM_REG_ITM_TCR_BUSY(n) (((uint32_t)(n) << 23) & 0x00800000) + +// ATB ID for CoreSight system. +#define AM_REG_ITM_TCR_ATB_ID_S 16 +#define AM_REG_ITM_TCR_ATB_ID_M 0x007F0000 +#define AM_REG_ITM_TCR_ATB_ID(n) (((uint32_t)(n) << 16) & 0x007F0000) + +// Global Timestamp Frequency. +#define AM_REG_ITM_TCR_TS_FREQ_S 10 +#define AM_REG_ITM_TCR_TS_FREQ_M 0x00000C00 +#define AM_REG_ITM_TCR_TS_FREQ(n) (((uint32_t)(n) << 10) & 0x00000C00) + +// Timestamp prescaler: 0b00 = no prescaling 0b01 = divide by 4 0b10 = divide by +// 16 0b11 = divide by 64. +#define AM_REG_ITM_TCR_TS_PRESCALE_S 8 +#define AM_REG_ITM_TCR_TS_PRESCALE_M 0x00000300 +#define AM_REG_ITM_TCR_TS_PRESCALE(n) (((uint32_t)(n) << 8) & 0x00000300) + +// Enable SWV (Serial Wire Viewer) behavior - count on TPIUEMIT and TPIUBAUD: +// Aka SWOENA Enables asynchronous clocking of the timestamp counter. +#define AM_REG_ITM_TCR_SWV_ENABLE_S 4 +#define AM_REG_ITM_TCR_SWV_ENABLE_M 0x00000010 +#define AM_REG_ITM_TCR_SWV_ENABLE(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Enables the DWT stimulus. +#define AM_REG_ITM_TCR_DWT_ENABLE_S 3 +#define AM_REG_ITM_TCR_DWT_ENABLE_M 0x00000008 +#define AM_REG_ITM_TCR_DWT_ENABLE(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Enables sync packets for TPIU. +#define AM_REG_ITM_TCR_SYNC_ENABLE_S 2 +#define AM_REG_ITM_TCR_SYNC_ENABLE_M 0x00000004 +#define AM_REG_ITM_TCR_SYNC_ENABLE(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when the +// timestamp counter overflows. Timestamps are emitted during idle times after a +// fixed number of cycles. This provides a time reference for packets and inter- +// packet gaps. +#define AM_REG_ITM_TCR_TS_ENABLE_S 1 +#define AM_REG_ITM_TCR_TS_ENABLE_M 0x00000002 +#define AM_REG_ITM_TCR_TS_ENABLE(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Enable ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define AM_REG_ITM_TCR_ITM_ENABLE_S 0 +#define AM_REG_ITM_TCR_ITM_ENABLE_M 0x00000001 +#define AM_REG_ITM_TCR_ITM_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// ITM_LOCKSREG - Lock Status Register +// +//***************************************************************************** +// You cannot implement 8-bit lock accesses. +#define AM_REG_ITM_LOCKSREG_BYTEACC_S 2 +#define AM_REG_ITM_LOCKSREG_BYTEACC_M 0x00000004 +#define AM_REG_ITM_LOCKSREG_BYTEACC(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define AM_REG_ITM_LOCKSREG_ACCESS_S 1 +#define AM_REG_ITM_LOCKSREG_ACCESS_M 0x00000002 +#define AM_REG_ITM_LOCKSREG_ACCESS(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Indicates that a lock mechanism exists for this component. +#define AM_REG_ITM_LOCKSREG_PRESENT_S 0 +#define AM_REG_ITM_LOCKSREG_PRESENT_M 0x00000001 +#define AM_REG_ITM_LOCKSREG_PRESENT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// ITM_PID4 - Peripheral Identification Register 4 +// +//***************************************************************************** +// Peripheral Identification 4. +#define AM_REG_ITM_PID4_PID4_S 0 +#define AM_REG_ITM_PID4_PID4_M 0xFFFFFFFF +#define AM_REG_ITM_PID4_PID4(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID5 - Peripheral Identification Register 5 +// +//***************************************************************************** +// Peripheral Identification 5. +#define AM_REG_ITM_PID5_PID5_S 0 +#define AM_REG_ITM_PID5_PID5_M 0xFFFFFFFF +#define AM_REG_ITM_PID5_PID5(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID6 - Peripheral Identification Register 6 +// +//***************************************************************************** +// Peripheral Identification 6. +#define AM_REG_ITM_PID6_PID6_S 0 +#define AM_REG_ITM_PID6_PID6_M 0xFFFFFFFF +#define AM_REG_ITM_PID6_PID6(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID7 - Peripheral Identification Register 7 +// +//***************************************************************************** +// Peripheral Identification 7. +#define AM_REG_ITM_PID7_PID7_S 0 +#define AM_REG_ITM_PID7_PID7_M 0xFFFFFFFF +#define AM_REG_ITM_PID7_PID7(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID0 - Peripheral Identification Register 0 +// +//***************************************************************************** +// Peripheral Identification 0. +#define AM_REG_ITM_PID0_PID0_S 0 +#define AM_REG_ITM_PID0_PID0_M 0xFFFFFFFF +#define AM_REG_ITM_PID0_PID0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID1 - Peripheral Identification Register 1 +// +//***************************************************************************** +// Peripheral Identification 1. +#define AM_REG_ITM_PID1_PID1_S 0 +#define AM_REG_ITM_PID1_PID1_M 0xFFFFFFFF +#define AM_REG_ITM_PID1_PID1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID2 - Peripheral Identification Register 2 +// +//***************************************************************************** +// Peripheral Identification 2. +#define AM_REG_ITM_PID2_PID2_S 0 +#define AM_REG_ITM_PID2_PID2_M 0xFFFFFFFF +#define AM_REG_ITM_PID2_PID2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_PID3 - Peripheral Identification Register 3 +// +//***************************************************************************** +// Peripheral Identification 3. +#define AM_REG_ITM_PID3_PID3_S 0 +#define AM_REG_ITM_PID3_PID3_M 0xFFFFFFFF +#define AM_REG_ITM_PID3_PID3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_CID0 - Component Identification Register 1 +// +//***************************************************************************** +// Component Identification 1. +#define AM_REG_ITM_CID0_CID0_S 0 +#define AM_REG_ITM_CID0_CID0_M 0xFFFFFFFF +#define AM_REG_ITM_CID0_CID0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_CID1 - Component Identification Register 1 +// +//***************************************************************************** +// Component Identification 1. +#define AM_REG_ITM_CID1_CID1_S 0 +#define AM_REG_ITM_CID1_CID1_M 0xFFFFFFFF +#define AM_REG_ITM_CID1_CID1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_CID2 - Component Identification Register 2 +// +//***************************************************************************** +// Component Identification 2. +#define AM_REG_ITM_CID2_CID2_S 0 +#define AM_REG_ITM_CID2_CID2_M 0xFFFFFFFF +#define AM_REG_ITM_CID2_CID2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// ITM_CID3 - Component Identification Register 3 +// +//***************************************************************************** +// Component Identification 3. +#define AM_REG_ITM_CID3_CID3_S 0 +#define AM_REG_ITM_CID3_CID3_M 0xFFFFFFFF +#define AM_REG_ITM_CID3_CID3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +#endif // AM_REG_ITM_H diff --git a/mcu/apollo2/regs/am_reg_jedec.h b/mcu/apollo2/regs/am_reg_jedec.h new file mode 100644 index 0000000..393c6c6 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_jedec.h @@ -0,0 +1,216 @@ +//***************************************************************************** +// +// am_reg_jedec.h +//! @file +//! +//! @brief Register macros for the JEDEC module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_JEDEC_H +#define AM_REG_JEDEC_H + +//***************************************************************************** +// +// JEDEC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_JEDEC_NUM_MODULES 1 +#define AM_REG_JEDECn(n) \ + (REG_JEDEC_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_JEDEC_PID4_O 0xF0000FD0 +#define AM_REG_JEDEC_PID5_O 0xF0000FD4 +#define AM_REG_JEDEC_PID6_O 0xF0000FD8 +#define AM_REG_JEDEC_PID7_O 0xF0000FDC +#define AM_REG_JEDEC_PID0_O 0xF0000FE0 +#define AM_REG_JEDEC_PID1_O 0xF0000FE4 +#define AM_REG_JEDEC_PID2_O 0xF0000FE8 +#define AM_REG_JEDEC_PID3_O 0xF0000FEC +#define AM_REG_JEDEC_CID0_O 0xF0000FF0 +#define AM_REG_JEDEC_CID1_O 0xF0000FF4 +#define AM_REG_JEDEC_CID2_O 0xF0000FF8 +#define AM_REG_JEDEC_CID3_O 0xF0000FFC + +//***************************************************************************** +// +// JEDEC_PID4 - JEP Continuation Register +// +//***************************************************************************** +// Contains the JEP Continuation bits. +#define AM_REG_JEDEC_PID4_JEPCONT_S 0 +#define AM_REG_JEDEC_PID4_JEPCONT_M 0x0000000F +#define AM_REG_JEDEC_PID4_JEPCONT(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// JEDEC_PID5 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define AM_REG_JEDEC_PID5_VALUE_S 0 +#define AM_REG_JEDEC_PID5_VALUE_M 0xFFFFFFFF +#define AM_REG_JEDEC_PID5_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// JEDEC_PID6 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define AM_REG_JEDEC_PID6_VALUE_S 0 +#define AM_REG_JEDEC_PID6_VALUE_M 0xFFFFFFFF +#define AM_REG_JEDEC_PID6_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// JEDEC_PID7 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define AM_REG_JEDEC_PID7_VALUE_S 0 +#define AM_REG_JEDEC_PID7_VALUE_M 0xFFFFFFFF +#define AM_REG_JEDEC_PID7_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// JEDEC_PID0 - Ambiq Partnum low byte +// +//***************************************************************************** +// Contains the low 8 bits of the Ambiq Micro device part number. +#define AM_REG_JEDEC_PID0_PNL8_S 0 +#define AM_REG_JEDEC_PID0_PNL8_M 0x000000FF +#define AM_REG_JEDEC_PID0_PNL8(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble. +// +//***************************************************************************** +// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID +// is therefore 0x9B. +#define AM_REG_JEDEC_PID1_JEPIDL_S 4 +#define AM_REG_JEDEC_PID1_JEPIDL_M 0x000000F0 +#define AM_REG_JEDEC_PID1_JEPIDL(n) (((uint32_t)(n) << 4) & 0x000000F0) + +// Contains the high 4 bits of the Ambiq Micro device part number. +#define AM_REG_JEDEC_PID1_PNH4_S 0 +#define AM_REG_JEDEC_PID1_PNH4_M 0x0000000F +#define AM_REG_JEDEC_PID1_PNH4(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble +// +//***************************************************************************** +// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also +// MCUCTRL.CHIPREV). Note that this field will change with each revision of the +// chip. +#define AM_REG_JEDEC_PID2_CHIPREVH4_S 4 +#define AM_REG_JEDEC_PID2_CHIPREVH4_M 0x000000F0 +#define AM_REG_JEDEC_PID2_CHIPREVH4(n) (((uint32_t)(n) << 4) & 0x000000F0) + +// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this +// field is hard-coded to 1. The full JEPID is therefore 0x9B. +#define AM_REG_JEDEC_PID2_JEPIDH_S 0 +#define AM_REG_JEDEC_PID2_JEPIDH_M 0x0000000F +#define AM_REG_JEDEC_PID2_JEPIDH(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// JEDEC_PID3 - Ambiq chip revision high-nibble. +// +//***************************************************************************** +// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also +// MCUCTRL.CHIPREV). Note that this field will change with each revision of the +// chip. +#define AM_REG_JEDEC_PID3_CHIPREVL4_S 4 +#define AM_REG_JEDEC_PID3_CHIPREVL4_M 0x000000F0 +#define AM_REG_JEDEC_PID3_CHIPREVL4(n) (((uint32_t)(n) << 4) & 0x000000F0) + +// This field is hard-coded to 0x0. +#define AM_REG_JEDEC_PID3_ZERO_S 0 +#define AM_REG_JEDEC_PID3_ZERO_M 0x0000000F +#define AM_REG_JEDEC_PID3_ZERO(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// JEDEC_CID0 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID0. +#define AM_REG_JEDEC_CID0_CID_S 0 +#define AM_REG_JEDEC_CID0_CID_M 0x000000FF +#define AM_REG_JEDEC_CID0_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// JEDEC_CID1 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID1. +#define AM_REG_JEDEC_CID1_CID_S 0 +#define AM_REG_JEDEC_CID1_CID_M 0x000000FF +#define AM_REG_JEDEC_CID1_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// JEDEC_CID2 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID2. +#define AM_REG_JEDEC_CID2_CID_S 0 +#define AM_REG_JEDEC_CID2_CID_M 0x000000FF +#define AM_REG_JEDEC_CID2_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// JEDEC_CID3 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID3. +#define AM_REG_JEDEC_CID3_CID_S 0 +#define AM_REG_JEDEC_CID3_CID_M 0x000000FF +#define AM_REG_JEDEC_CID3_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) + +#endif // AM_REG_JEDEC_H diff --git a/mcu/apollo2/regs/am_reg_macros.h b/mcu/apollo2/regs/am_reg_macros.h new file mode 100644 index 0000000..45452d7 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_macros.h @@ -0,0 +1,367 @@ +//***************************************************************************** +// +// am_reg_macros.h +//! @file +//! +//! @brief Helper macros for using hardware registers. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_REG_MACROS_H +#define AM_REG_MACROS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Include the inline assembly macros. +// +//***************************************************************************** +#include "am_reg_macros_asm.h" + +//***************************************************************************** +// +// High-level Helper Macros. +// +// Usage: +// +// For direct 32-bit access to a register, use AM_REGVAL: +// AM_REGVAL(REG_VCOMP_BASEADDR + AM_VCOMP_VCMPCFG_O) |= 0xDEADBEEF; +// +// The AM_REG macro can also be used as a shorthand version of AM_REGVAL: +// AM_REG(VCOMP, VCMPCFG) |= 0xDEADBEEF; +// +// The AM_REGn macro is used for accessing registers of peripherals with +// multiple instances, such as IOMSTR. +// AM_REGn(IOMSTR, 1, CLKCFG) |= 0xDEADBEEF; +// +// To write to a specific bitfield within a register, use AM_BFW or AM_BFWn: +// AM_BFW(CTIMER, 0, CTCTRL0, TMRB0FN, 0x3); +// +// To read a field, use AM_BFR or AM_BFRn: +// ui32Timer0Fn = AM_BFR((CTIMER, 0, CTCTRL0, TMRB0FN); +// +// Note: +// +// AM_REGn, AM_BFW and AM_BFR are concatenation-based, which means that +// standalone macro definitions should not be used for the 'module', 'reg', and +// 'field' arguments.All macro names in the various peripheral header files are +// written in one of the following forms: +// - AM_REG_##module_reg_O +// - AM_REG_##module_reg_field_S +// - AM_REG_##module_reg_field_M +// +// The "module", "reg" and "field" fragments may be used as valid arguments to +// the AM_REGn, AM_BFW, and AM_BFR macros, all of which are able to perform the +// necessary concatenation operations to reconstruct the full macros and look +// up the appropriate base address for the instance number given. For +// peripherals with only one instance, use instance number 0. +// +// The AM_REGVAL macro does not perform any concatenation operations, so the +// complete macro name (including any suffix) must be specified. +// +//***************************************************************************** +#define AM_REGVAL(x) (*((volatile uint32_t *)(x))) +#define AM_REGVAL_FLOAT(x) (*((volatile float *)(x))) + +//***************************************************************************** +// +// Register access macros for single-instance modules +// AM_REG - Write a register of a module. +// AM_BFW - Write a value to a bitfield of a register. +// AM_BFWe - Use a defined enum value to write a value to a register bitfield. +// AM_BFR - Read a bitfield value from a register. +// AM_BFM - Read and mask a bitfield from a register, but leave the value in +// its bit position. Useful for comparing with enums. +// +// AM_BFV - Move a value to a bitfield. This macro is used for creating a +// value, it does not modify any register. +// AM_BFX - Extract the value of a bitfield from a 32-bit value, such as that +// read from a register. Does not read or modify any register. +// +//***************************************************************************** +#define AM_REG(module, reg) \ + /*AM_REGn(m, 0, r) */ \ + (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) + +#define AM_BFW(module, reg, field, value) \ + /* AM_BFWn(m,0,r,f,v) */ \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \ + AM_REG_##module##_##reg##_##field##_M) ) + +#define AM_BFWe(module, reg, field, enumval) \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (AM_REG_##module##_##reg##_##field##_##enumval)) + +#define AM_BFR(module, reg, field) \ + /* AM_BFRn(m,0,r,f) */ \ + ( ( (uint32_t) \ + (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \ + AM_REG_##module##_##reg##_##field##_M ) >> \ + AM_REG_##module##_##reg##_##field##_S ) + +#define AM_BFM(module, reg, field) \ + /* AM_BFMn(m,0,r,f) */ \ + ( (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \ + AM_REG_##module##_##reg##_##field##_M) + +#define AM_BFV(module, reg, field, value) \ + (((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \ + AM_REG_##module##_##reg##_##field##_M) + +#define AM_BFX(module, reg, field, value) \ + (((uint32_t)(value) & AM_REG_##module##_##reg##_##field##_M) >> \ + AM_REG_##module##_##reg##_##field##_S) + + + +//***************************************************************************** +// +// Register access macros for multi-instance modules +// AM_REGADDRn - Calc the register address inside a multiple instance module. +// AM_REGn - Write a register of a multiple instance module. +// AM_BFWn - Write a value to a bitfield of a register in a multiple instance. +// AM_BFWen - Use a defined enum value to write a value to a bitfield of a +// register in a multiple instance. +// AM_BFRn - Read a bitfield value from a register in a multiple instance. +// AM_BFMn - Read and mask a bitfield, but leave the value in its bit position. +// (Useful for comparing with enums.) +// +//***************************************************************************** +#define AM_REGADDRn(module, instance, reg) \ + (AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O) + + +#define AM_REGn(module, instance, reg) \ + (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) + +#define AM_BFWn(module, instance, reg, field, value) \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \ + AM_REG_##module##_##reg##_##field##_M) ) + +#define AM_BFWen(module, instance, reg, field, enumval) \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (AM_REG_##module##_##reg##_##field##_##enumval)) + +#define AM_BFRn(module, instance, reg, field) \ + ( ( (uint32_t) \ + (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \ + AM_REG_##module##_##reg##_##field##_M ) >> \ + AM_REG_##module##_##reg##_##field##_S ) + +#define AM_BFMn(module, instance, reg, field) \ + ( (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \ + AM_REG_##module##_##reg##_##field##_M) + +//***************************************************************************** +// +// "Atomic" register access macros - use when a read-modify-write is required. +// +// These macros will be slower than the normal macros, but they will also +// guarantee threadsafe hardware access. +// +// These macros require a nesting-friendly critical section implementation. If +// you are using the HAL, you can use the default definitions below. If not, +// you will need to supply your own. +// +// Atomic register access macros usage: +// AM_REGa - Write a register of a single instance module. Provide operator +// (&,|,etc) to perform that operation on the reg using value, or +// no operator to simply write the value atomically. +// AM_REGa_SET - Set bits in a single instance module according to the mask. +// AM_REGa_CLR - Clear bits in a single instance module according to the mask. +// AM_REGan - Multiple module version of AM_REGa. +// AM_REGan_SET - Multiple instance version of AM_REGa_SET. +// AM_REGan_CLR - Multiple instance version of AM_REGa_CLR. +// AM_BFWa - Write a value to a register bitfield. +// AM_BFWae - Use a defined enum value to write a value to a bitfield. +// AM_BFWan - Write a value to a bitfield of a register in a multiple instance. +// AM_BFWaen - Use a defined enum value to write a value to a bitfield of a +// register in a multiple instance. +// +//***************************************************************************** + +#define AM_REGan(module, instance, reg, operator, value) \ + AM_CRITICAL_BEGIN \ + /* AM_REGn(m, i, r) = (value) */ \ + (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) operator##= (value); \ + AM_CRITICAL_END + +#define AM_REGan_SET(module, instance, reg, mask) \ + AM_CRITICAL_BEGIN \ + (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) |= (mask); \ + AM_CRITICAL_END + +#define AM_REGan_CLR(module, instance, reg, mask) \ + AM_CRITICAL_BEGIN \ + (*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) &= (~mask); \ + AM_CRITICAL_END + +#define AM_REGa(module, reg, operator, value) \ + /* AM_REGan(m,0,r,op,v) */ \ + AM_CRITICAL_BEGIN \ + (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) operator##= (value); \ + AM_CRITICAL_END + +#define AM_REGa_CLR(module, reg, mask) \ + /* AM_REGan_CLR(m, 0, r, m) */ \ + AM_CRITICAL_BEGIN \ + (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) &= (~mask); \ + AM_CRITICAL_END + +#define AM_REGa_SET(module, reg, mask) \ + /* AM_REGan_SET(m, 0, r, m) */ \ + AM_CRITICAL_BEGIN \ + (*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) |= (mask); \ + AM_CRITICAL_END + +#define AM_BFWa(module, reg, field, value) \ + AM_CRITICAL_BEGIN \ + /* AM_BFW(module, reg, field, value); */ \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \ + AM_REG_##module##_##reg##_##field##_M) ); \ + AM_CRITICAL_END + +#define AM_BFWae(module, reg, field, enumval) \ + AM_CRITICAL_BEGIN \ + /* AM_BFWe(module, reg, field, enumval); */ \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(0) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (AM_REG_##module##_##reg##_##field##_##enumval)); \ + AM_CRITICAL_END + +#define AM_BFWan(module, instance, reg, field, value) \ + AM_CRITICAL_BEGIN \ + /* AM_BFWn(module, instance, reg, field, enumval); */ \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (((uint32_t)(value) << AM_REG_##module##_##reg##_##field##_S) & \ + AM_REG_##module##_##reg##_##field##_M) ); \ + AM_CRITICAL_END + +#define AM_BFWaen(module, instance, reg, field, enumval) \ + AM_CRITICAL_BEGIN \ + /* AM_BFWen(module, instance reg, field, enumval); */ \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) = \ + ((*((volatile uint32_t *)(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O))) & \ + (~AM_REG_##module##_##reg##_##field##_M)) | \ + (AM_REG_##module##_##reg##_##field##_##enumval)); \ + AM_CRITICAL_END + +//***************************************************************************** +// +// Other helper Macros. +// +// Note: These macros make use of macro concatenation, so the '_S' or '_M' +// suffix on a register bitfield macro should not be supplied by the user. +// The macro will apply each suffix as needed. +// +//***************************************************************************** + +// +// AM_ENUMX extracts a register bitfield enumeration to the bit 0 position, +// which makes it possible to use enums directly with existing macros such +// as AM_BFR() or AM_BFW(). +// Brief overview: bitfield enumerations are pre-shifted such that the defined +// value lines up with the bitfield. This is convenient for many operations, +// but not so when using AM_BFR() to read the value of a register bitfield +// as AM_BFR() shifts the bitfield value to the bit 0 position. +// Note that this type of bitfield extraction is Cortex efficient via the +// UBFX (unsigned bit field extract) instruction. +// +// Alternately, AM_BFM() can also be used. AM_BFM() reads a register and masks +// the bitfield value (without shifting), thereby allowing direct comparison +// with a defined enum. +// +// Examples: +// if ( AM_BFR(CLKGEN, CCTRL, CORESEL) == +// AM_ENUMX(CLKGEN, CCTRL, CORESEL, HFRC) ) +// +// or alternatively: +// if ( AM_BFM(CLKGEN, CCTRL, CORESEL) == AM_REG_CLKGEN_CCTRL_CORESEL_HFRC ) +// +#define AM_ENUMX(module, reg, field, enumname) \ + ((AM_REG_##module##_##reg##_##field##_##enumname) >> \ + (AM_REG_##module##_##reg##_##field##_S)) + +// +// AM_WRITE_SM performs a shift/mask operation to prepare the value 'x' to be +// written to the register field 'field'. +// +// For example: +// AM_REGVAL(ui32Base + AM_VCOMP_VCMP_CFG_O) |= +// AM_WRITE_SM(AM_VCOMP_VCMP_CFG_LVLSEL, ui32Value); +// +#define AM_WRITE_SM(field, x) (((x) << field##_S) & field##_M) + +// +// AM_READ_SM performs a shift/mask operation to make it easier to interpret +// the value of a given bitfield. This is essentially the reverse of the +// AM_WRITE_SM operation. In most cases, you will want to use the shorter +// AM_BFR macro instead of this one. +// +// For example: +// ui32Value = AM_READ_SM(AM_VCOMP_VCMP_CFG_NSEL, +// AM_REGVAL(ui32Base + AM_VCOMP_VCMP_CFG_O)); +// +#define AM_READ_SM(field, x) (((x) & field##_M) >> field##_S) + +#ifdef __cplusplus +} +#endif + +#endif // AM_REG_MACROS_H + diff --git a/mcu/apollo2/regs/am_reg_macros_asm.h b/mcu/apollo2/regs/am_reg_macros_asm.h new file mode 100644 index 0000000..5234e7c --- /dev/null +++ b/mcu/apollo2/regs/am_reg_macros_asm.h @@ -0,0 +1,195 @@ +//***************************************************************************** +// +// am_reg_macros_asm.h +//! @file +//! +//! @brief Inline assembly macros. Initially for critical section handling in +//! protecting hardware registers. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_REG_MACROS_ASM_H +#define AM_REG_MACROS_ASM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Critical section assembly macros +// +// These macros implement critical section protection using inline assembly +// for various compilers. They are intended to be used in other register +// macros or directly in sections of code. +// +// Important usage note: These macros create a local scope and therefore MUST +// be used in pairs. +// +//***************************************************************************** +#define AM_CRITICAL_BEGIN \ + if ( 1 ) \ + { \ + volatile uint32_t ui32Primask_04172010; \ + ui32Primask_04172010 = am_hal_interrupt_master_disable(); + +#define AM_CRITICAL_END \ + am_hal_interrupt_master_set(ui32Primask_04172010); \ + } + +//***************************************************************************** +// +// A collection of some common inline assembly instructions / intrinsics. +// +//***************************************************************************** +// +// AM_ASM_BKPT(n) +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_BKPT(n) __breakpoint(n) +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_BKPT(n) __asm(" bkpt "#n); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_BKPT(n) __asm(" bkpt "#n); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_BKPT(n) asm(" bkpt "#n); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// +// AM_ASM_WFI +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_WFI __wfi(); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_WFI __asm(" wfi"); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_WFI __asm(" wfi"); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_WFI asm(" wfi"); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// +// AM_ASM_WFE +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_WFE __wfe(); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_WFE __asm(" wfe"); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_WFE __asm(" wfe"); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_WFE asm(" wfe"); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// +// AM_ASM_SEV +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_SEV __sev(); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_SEV __asm(" sev"); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_SEV __asm(" sev"); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_SEV asm(" sev"); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// +// AM_ASM_NOP +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_NOP __nop(); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_NOP __asm(" nop"); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_NOP __asm(" nop"); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_NOP asm(" nop"); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// +// AM_ASM_DSB +// In cmsis_armcc.h, __DSB() is defined as __dsb(0xF). +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_DSB __dsb(15); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_DSB __asm(" dsb #15"); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_DSB __asm(" dsb #15"); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_DSB asm(" dsb #15"); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// +// AM_ASM_ISB +// In cmsis_armcc.h, __ISB() is defined as __isb(0xF). +// +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +#define AM_ASM_ISB __isb(15); +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +#define AM_ASM_ISB __asm(" isb #15"); +#elif defined(__GNUC_STDC_INLINE__) +#define AM_ASM_ISB __asm(" isb #15"); +#elif defined(__IAR_SYSTEMS_ICC__) +#define AM_ASM_ISB asm(" isb #15"); +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // AM_REG_MACROS_ASM_H + diff --git a/mcu/apollo2/regs/am_reg_mcuctrl.h b/mcu/apollo2/regs/am_reg_mcuctrl.h new file mode 100644 index 0000000..8359604 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_mcuctrl.h @@ -0,0 +1,636 @@ +//***************************************************************************** +// +// am_reg_mcuctrl.h +//! @file +//! +//! @brief Register macros for the MCUCTRL module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_MCUCTRL_H +#define AM_REG_MCUCTRL_H + +//***************************************************************************** +// +// MCUCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_MCUCTRL_NUM_MODULES 1 +#define AM_REG_MCUCTRLn(n) \ + (REG_MCUCTRL_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_MCUCTRL_CHIP_INFO_O 0x00000000 +#define AM_REG_MCUCTRL_CHIPID0_O 0x00000004 +#define AM_REG_MCUCTRL_CHIPID1_O 0x00000008 +#define AM_REG_MCUCTRL_CHIPREV_O 0x0000000C +#define AM_REG_MCUCTRL_VENDORID_O 0x00000010 +#define AM_REG_MCUCTRL_DEBUGGER_O 0x00000014 +#define AM_REG_MCUCTRL_BUCK_O 0x00000060 +#define AM_REG_MCUCTRL_BUCK3_O 0x00000068 +#define AM_REG_MCUCTRL_LDOREG1_O 0x00000080 +#define AM_REG_MCUCTRL_LDOREG3_O 0x00000088 +#define AM_REG_MCUCTRL_BODPORCTRL_O 0x00000100 +#define AM_REG_MCUCTRL_ADCPWRDLY_O 0x00000104 +#define AM_REG_MCUCTRL_ADCCAL_O 0x0000010C +#define AM_REG_MCUCTRL_ADCBATTLOAD_O 0x00000110 +#define AM_REG_MCUCTRL_BUCKTRIM_O 0x00000114 +#define AM_REG_MCUCTRL_XTALGENCTRL_O 0x00000124 +#define AM_REG_MCUCTRL_BOOTLOADERLOW_O 0x000001A0 +#define AM_REG_MCUCTRL_SHADOWVALID_O 0x000001A4 +#define AM_REG_MCUCTRL_ICODEFAULTADDR_O 0x000001C0 +#define AM_REG_MCUCTRL_DCODEFAULTADDR_O 0x000001C4 +#define AM_REG_MCUCTRL_SYSFAULTADDR_O 0x000001C8 +#define AM_REG_MCUCTRL_FAULTSTATUS_O 0x000001CC +#define AM_REG_MCUCTRL_FAULTCAPTUREEN_O 0x000001D0 +#define AM_REG_MCUCTRL_DBGR1_O 0x00000200 +#define AM_REG_MCUCTRL_DBGR2_O 0x00000204 +#define AM_REG_MCUCTRL_PMUENABLE_O 0x00000220 +#define AM_REG_MCUCTRL_TPIUCTRL_O 0x00000250 + +//***************************************************************************** +// +// Key values. +// +//***************************************************************************** + +//***************************************************************************** +// +// MCUCTRL_CHIP_INFO - Chip Information Register +// +//***************************************************************************** +// BCD part number. +#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_S 0 +#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 0x03000000 +#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO 0x01000000 +#define AM_REG_MCUCTRL_CHIP_INFO_PARTNUM_PN_M 0xFF000000 + +//***************************************************************************** +// +// MCUCTRL_CHIPID0 - Unique Chip ID 0 +// +//***************************************************************************** +// Unique chip ID 0. +#define AM_REG_MCUCTRL_CHIPID0_VALUE_S 0 +#define AM_REG_MCUCTRL_CHIPID0_VALUE_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_CHIPID0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_MCUCTRL_CHIPID0_VALUE_APOLLO2 0x00000000 + +//***************************************************************************** +// +// MCUCTRL_CHIPID1 - Unique Chip ID 1 +// +//***************************************************************************** +// Unique chip ID 1. +#define AM_REG_MCUCTRL_CHIPID1_VALUE_S 0 +#define AM_REG_MCUCTRL_CHIPID1_VALUE_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_CHIPID1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_MCUCTRL_CHIPID1_VALUE_APOLLO2 0x00000000 + +//***************************************************************************** +// +// MCUCTRL_CHIPREV - Chip Revision +// +//***************************************************************************** +// Major Revision ID. +#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_S 4 +#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_M 0x000000F0 +#define AM_REG_MCUCTRL_CHIPREV_REVMAJ(n) (((uint32_t)(n) << 4) & 0x000000F0) +#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_B 0x00000020 +#define AM_REG_MCUCTRL_CHIPREV_REVMAJ_A 0x00000010 + +// Minor Revision ID. +#define AM_REG_MCUCTRL_CHIPREV_REVMIN_S 0 +#define AM_REG_MCUCTRL_CHIPREV_REVMIN_M 0x0000000F +#define AM_REG_MCUCTRL_CHIPREV_REVMIN(n) (((uint32_t)(n) << 0) & 0x0000000F) +#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 0x00000000 +#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2 0x00000002 + +//***************************************************************************** +// +// MCUCTRL_VENDORID - Unique Vendor ID +// +//***************************************************************************** +// Unique Vendor ID +#define AM_REG_MCUCTRL_VENDORID_VALUE_S 0 +#define AM_REG_MCUCTRL_VENDORID_VALUE_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_VENDORID_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_MCUCTRL_VENDORID_VALUE_AMBIQ 0x414D4251 + +//***************************************************************************** +// +// MCUCTRL_DEBUGGER - Debugger Access Control +// +//***************************************************************************** +// Lockout of debugger (SWD). +#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT_S 0 +#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT_M 0x00000001 +#define AM_REG_MCUCTRL_DEBUGGER_LOCKOUT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// MCUCTRL_BUCK - Analog Buck Control +// +//***************************************************************************** +// Reset control override for Mem Buck; 0=enabled, 1=reset; Value is propagated +// only when the BUCKSWE bit is active, otherwise contrl is from the power +// control module. +#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST_S 7 +#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST_M 0x00000080 +#define AM_REG_MCUCTRL_BUCK_MEMBUCKRST(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Reset control override for Core Buck; 0=enabled, 1=reset; Value is propagated +// only when the BUCKSWE bit is active, otherwise control is from the power +// control module. +#define AM_REG_MCUCTRL_BUCK_COREBUCKRST_S 6 +#define AM_REG_MCUCTRL_BUCK_COREBUCKRST_M 0x00000040 +#define AM_REG_MCUCTRL_BUCK_COREBUCKRST(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Not used. Additional control of buck is available in the power control +// module +#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM_S 5 +#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM_M 0x00000020 +#define AM_REG_MCUCTRL_BUCK_BYPBUCKMEM(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Memory buck power down override. 1=Powered Down; 0=Enabled; Value is +// propagated only when the BUCKSWE bit is active, otherwise control is from the +// power control module. +#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_S 4 +#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_M 0x00000010 +#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_MCUCTRL_BUCK_MEMBUCKPWD_EN 0x00000000 + +// HFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the +// hfrc_freq_clkgen internal bus (see internal Shelby-1473) +#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA_S 3 +#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA_M 0x00000008 +#define AM_REG_MCUCTRL_BUCK_SLEEPBUCKANA(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Core buck power down override. 1=Powered Down; 0=Enabled; Value is propagated +// only when the BUCKSWE bit is active, otherwise control is from the power +// control module. +#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_S 2 +#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_M 0x00000004 +#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_MCUCTRL_BUCK_COREBUCKPWD_EN 0x00000000 + +// Not used. Additional control of buck is available in the power control +// module +#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE_S 1 +#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE_M 0x00000002 +#define AM_REG_MCUCTRL_BUCK_BYPBUCKCORE(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Buck Register Software Override Enable. This will enable the override values +// for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to +// the control logic, instead of the normal power control module signal. Note - +// Must take care to have correct value for ALL the register bits when this SWE +// is enabled. +#define AM_REG_MCUCTRL_BUCK_BUCKSWE_S 0 +#define AM_REG_MCUCTRL_BUCK_BUCKSWE_M 0x00000001 +#define AM_REG_MCUCTRL_BUCK_BUCKSWE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_BUCK_BUCKSWE_OVERRIDE_DIS 0x00000000 +#define AM_REG_MCUCTRL_BUCK_BUCKSWE_OVERRIDE_EN 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_BUCK3 - Buck control reg 3 +// +//***************************************************************************** +// MEM Buck low TON trim value +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON_S 18 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON_M 0x003C0000 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKLOTON(n) (((uint32_t)(n) << 18) & 0x003C0000) + +// MEM Buck burst enable 0=disable, 0=disabled, 1=enable. +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN_S 17 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN_M 0x00020000 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKBURSTEN(n) (((uint32_t)(n) << 17) & 0x00020000) + +// Memory buck zero crossing trim value +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM_S 13 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM_M 0x0001E000 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKZXTRIM(n) (((uint32_t)(n) << 13) & 0x0001E000) + +// Hysterisis trim for mem buck +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_S 11 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM_M 0x00001800 +#define AM_REG_MCUCTRL_BUCK3_MEMBUCKHYSTTRIM(n) (((uint32_t)(n) << 11) & 0x00001800) + +// Core Buck low TON trim value +#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON_S 7 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON_M 0x00000780 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKLOTON(n) (((uint32_t)(n) << 7) & 0x00000780) + +// Core Buck burst enable. 0=disabled, 1=enabled +#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN_S 6 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN_M 0x00000040 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKBURSTEN(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Core buck zero crossing trim value +#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM_S 2 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM_M 0x0000003C +#define AM_REG_MCUCTRL_BUCK3_COREBUCKZXTRIM(n) (((uint32_t)(n) << 2) & 0x0000003C) + +// Hysterisis trim for core buck +#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM_S 0 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM_M 0x00000003 +#define AM_REG_MCUCTRL_BUCK3_COREBUCKHYSTTRIM(n) (((uint32_t)(n) << 0) & 0x00000003) + +//***************************************************************************** +// +// MCUCTRL_LDOREG1 - Analog LDO Reg 1 +// +//***************************************************************************** +// CORE LDO IBIAS Trim +#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM_S 20 +#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM_M 0x00100000 +#define AM_REG_MCUCTRL_LDOREG1_CORELDOIBSTRM(n) (((uint32_t)(n) << 20) & 0x00100000) + +// CORE LDO Low Power Trim +#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM_S 14 +#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM_M 0x000FC000 +#define AM_REG_MCUCTRL_LDOREG1_CORELDOLPTRIM(n) (((uint32_t)(n) << 14) & 0x000FC000) + +// CORE LDO tempco trim (R3). +#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3_S 10 +#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3_M 0x00003C00 +#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR3(n) (((uint32_t)(n) << 10) & 0x00003C00) + +// CORE LDO Active mode ouput trim (R1). +#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1_S 0 +#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1_M 0x000003FF +#define AM_REG_MCUCTRL_LDOREG1_TRIMCORELDOR1(n) (((uint32_t)(n) << 0) & 0x000003FF) + +//***************************************************************************** +// +// MCUCTRL_LDOREG3 - LDO Control Register 3 +// +//***************************************************************************** +// MEM LDO active mode trim (R1). +#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1_S 12 +#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1_M 0x0003F000 +#define AM_REG_MCUCTRL_LDOREG3_TRIMMEMLDOR1(n) (((uint32_t)(n) << 12) & 0x0003F000) + +// MEM LDO TRIM for low power mode with ADC active +#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_S 6 +#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM_M 0x00000FC0 +#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPALTTRIM(n) (((uint32_t)(n) << 6) & 0x00000FC0) + +// MEM LDO TRIM for low power mode with ADC inactive +#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM_S 0 +#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM_M 0x0000003F +#define AM_REG_MCUCTRL_LDOREG3_MEMLDOLPTRIM(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// MCUCTRL_BODPORCTRL - BOD and PDR control Register +// +//***************************************************************************** +// BOD External Reference Select. +#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_S 3 +#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_M 0x00000008 +#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_MCUCTRL_BODPORCTRL_BODEXTREFSEL_SELECT 0x00000008 + +// PDR External Reference Select. +#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_S 2 +#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_M 0x00000004 +#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_MCUCTRL_BODPORCTRL_PDREXTREFSEL_SELECT 0x00000004 + +// BOD Power Down. +#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_S 1 +#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_M 0x00000002 +#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_MCUCTRL_BODPORCTRL_PWDBOD_PWR_DN 0x00000002 + +// PDR Power Down. +#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_S 0 +#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_M 0x00000001 +#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_BODPORCTRL_PWDPDR_PWR_DN 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_ADCPWRDLY - ADC Power Up Delay Control +// +//***************************************************************************** +// ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = +// 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2. +#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1_S 8 +#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1_M 0x0000FF00 +#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for +// ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2. +#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0_S 0 +#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0_M 0x000000FF +#define AM_REG_MCUCTRL_ADCPWRDLY_ADCPWR0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// MCUCTRL_ADCCAL - ADC Calibration Control +// +//***************************************************************************** +// Status for ADC Calibration +#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_S 1 +#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_M 0x00000002 +#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE 0x00000000 +#define AM_REG_MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE 0x00000002 + +// Run ADC Calibration on initial power up sequence +#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_S 0 +#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_M 0x00000001 +#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_DIS 0x00000000 +#define AM_REG_MCUCTRL_ADCCAL_CALONPWRUP_EN 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_ADCBATTLOAD - ADC Battery Load Enable +// +//***************************************************************************** +// Enable the ADC battery load resistor +#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_S 0 +#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_M 0x00000001 +#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS 0x00000000 +#define AM_REG_MCUCTRL_ADCBATTLOAD_BATTLOAD_EN 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_BUCKTRIM - Trim settings for Core and Mem buck modules +// +//***************************************************************************** +// RESERVED. +#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2_S 24 +#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2_M 0x3F000000 +#define AM_REG_MCUCTRL_BUCKTRIM_RSVD2(n) (((uint32_t)(n) << 24) & 0x3F000000) + +// Core Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO +// for the full trim value. +#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI_S 16 +#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI_M 0x000F0000 +#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_HI(n) (((uint32_t)(n) << 16) & 0x000F0000) + +// Core Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI +// for the full trim value. +#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO_S 8 +#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO_M 0x00003F00 +#define AM_REG_MCUCTRL_BUCKTRIM_COREBUCKR1_LO(n) (((uint32_t)(n) << 8) & 0x00003F00) + +// Trim values for BUCK regulator. +#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1_S 0 +#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1_M 0x0000003F +#define AM_REG_MCUCTRL_BUCKTRIM_MEMBUCKR1(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// MCUCTRL_XTALGENCTRL - XTAL Oscillator General Control +// +//***************************************************************************** +// XTAL IBIAS Kick start trim . This trim value is used during the startup +// process to enable a faster lock and is applied when the kickstart signal is +// active. +#define AM_REG_MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_S 8 +#define AM_REG_MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_M 0x00003F00 +#define AM_REG_MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM(n) (((uint32_t)(n) << 8) & 0x00003F00) + +// XTAL IBIAS trim +#define AM_REG_MCUCTRL_XTALGENCTRL_XTALBIASTRIM_S 2 +#define AM_REG_MCUCTRL_XTALGENCTRL_XTALBIASTRIM_M 0x000000FC +#define AM_REG_MCUCTRL_XTALGENCTRL_XTALBIASTRIM(n) (((uint32_t)(n) << 2) & 0x000000FC) + +// Auto-calibration delay control +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_S 0 +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_M 0x00000003 +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP(n) (((uint32_t)(n) << 0) & 0x00000003) +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_1SEC 0x00000000 +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_2SEC 0x00000001 +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_4SEC 0x00000002 +#define AM_REG_MCUCTRL_XTALGENCTRL_ACWARMUP_8SEC 0x00000003 + +//***************************************************************************** +// +// MCUCTRL_BOOTLOADERLOW - Determines whether the bootloader code is visible at +// address 0x00000000 +// +//***************************************************************************** +// Determines whether the bootloader code is visible at address 0x00000000 or +// not. +#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_S 0 +#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_M 0x00000001 +#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_BOOTLOADERLOW_VALUE_ADDR0 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_SHADOWVALID - Register to indicate whether the shadow registers have +// been successfully loaded from the Flash Information Space. +// +//***************************************************************************** +// Indicates whether the bootloader should sleep or deep sleep if no image +// loaded. +#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_S 1 +#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_M 0x00000002 +#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_MCUCTRL_SHADOWVALID_BL_DSLEEP_DEEPSLEEP 0x00000002 + +// Indicates whether the shadow registers contain valid data from the Flash +// Information Space. +#define AM_REG_MCUCTRL_SHADOWVALID_VALID_S 0 +#define AM_REG_MCUCTRL_SHADOWVALID_VALID_M 0x00000001 +#define AM_REG_MCUCTRL_SHADOWVALID_VALID(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_SHADOWVALID_VALID_VALID 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_ICODEFAULTADDR - ICODE bus address which was present when a bus fault +// occurred. +// +//***************************************************************************** +// The ICODE bus address observed when a Bus Fault occurred. Once an address is +// captured in this field, it is held until the corresponding Fault Observed bit +// is cleared in the FAULTSTATUS register. +#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR_S 0 +#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_ICODEFAULTADDR_ADDR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// MCUCTRL_DCODEFAULTADDR - DCODE bus address which was present when a bus fault +// occurred. +// +//***************************************************************************** +// The DCODE bus address observed when a Bus Fault occurred. Once an address is +// captured in this field, it is held until the corresponding Fault Observed bit +// is cleared in the FAULTSTATUS register. +#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR_S 0 +#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_DCODEFAULTADDR_ADDR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// MCUCTRL_SYSFAULTADDR - System bus address which was present when a bus fault +// occurred. +// +//***************************************************************************** +// SYS bus address observed when a Bus Fault occurred. Once an address is +// captured in this field, it is held until the corresponding Fault Observed bit +// is cleared in the FAULTSTATUS register. +#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR_S 0 +#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_SYSFAULTADDR_ADDR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// MCUCTRL_FAULTSTATUS - Reflects the status of the bus decoders' fault +// detection. Any write to this register will clear all of the status bits +// within the register. +// +//***************************************************************************** +// SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and +// the SYSFAULTADDR register will contain the bus address which generated the +// fault. +#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_S 2 +#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_M 0x00000004 +#define AM_REG_MCUCTRL_FAULTSTATUS_SYS(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_NOFAULT 0x00000000 +#define AM_REG_MCUCTRL_FAULTSTATUS_SYS_FAULT 0x00000004 + +// DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, +// and the DCODEFAULTADDR register will contain the bus address which generated +// the fault. +#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_S 1 +#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M 0x00000002 +#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_NOFAULT 0x00000000 +#define AM_REG_MCUCTRL_FAULTSTATUS_DCODE_FAULT 0x00000002 + +// The ICODE Bus Decoder Fault Detected bit. When set, a fault has been +// detected, and the ICODEFAULTADDR register will contain the bus address which +// generated the fault. +#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_S 0 +#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M 0x00000001 +#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_NOFAULT 0x00000000 +#define AM_REG_MCUCTRL_FAULTSTATUS_ICODE_FAULT 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_FAULTCAPTUREEN - Enable the fault capture registers +// +//***************************************************************************** +// Fault Capture Enable field. When set, the Fault Capture monitors are enabled +// and addresses which generate a hard fault are captured into the FAULTADDR +// registers. +#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_S 0 +#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_M 0x00000001 +#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_DIS 0x00000000 +#define AM_REG_MCUCTRL_FAULTCAPTUREEN_ENABLE_EN 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_DBGR1 - Read-only debug register 1 +// +//***************************************************************************** +// Read-only register for communication validation +#define AM_REG_MCUCTRL_DBGR1_ONETO8_S 0 +#define AM_REG_MCUCTRL_DBGR1_ONETO8_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_DBGR1_ONETO8(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// MCUCTRL_DBGR2 - Read-only debug register 2 +// +//***************************************************************************** +// Read-only register for communication validation +#define AM_REG_MCUCTRL_DBGR2_COOLCODE_S 0 +#define AM_REG_MCUCTRL_DBGR2_COOLCODE_M 0xFFFFFFFF +#define AM_REG_MCUCTRL_DBGR2_COOLCODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// MCUCTRL_PMUENABLE - Control bit to enable/disable the PMU +// +//***************************************************************************** +// PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the +// lowest power consuming Deep Sleep mode upon execution of a WFI instruction +// (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When +// cleared, regardless of the requested sleep mode, the PMU will not enter the +// lowest power Deep Sleep mode, instead entering the Sleep mode. +#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_S 0 +#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_M 0x00000001 +#define AM_REG_MCUCTRL_PMUENABLE_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_DIS 0x00000000 +#define AM_REG_MCUCTRL_PMUENABLE_ENABLE_EN 0x00000001 + +//***************************************************************************** +// +// MCUCTRL_TPIUCTRL - TPIU Control Register. Determines the clock enable and +// frequency for the M4's TPIU interface. +// +//***************************************************************************** +// This field selects the frequency of the ARM M4 TPIU port. +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_S 8 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_M 0x00000700 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(n) (((uint32_t)(n) << 8) & 0x00000700) +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_LOW_PWR 0x00000000 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz 0x00000000 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_2 0x00000100 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_8 0x00000200 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_16 0x00000300 +#define AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_HFRC_DIV_32 0x00000400 + +// TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be +// streamed out of the MCU's SWO port using the ARM ITM and TPIU modules. +#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_S 0 +#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_M 0x00000001 +#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS 0x00000000 +#define AM_REG_MCUCTRL_TPIUCTRL_ENABLE_EN 0x00000001 + +#endif // AM_REG_MCUCTRL_H diff --git a/mcu/apollo2/regs/am_reg_nvic.h b/mcu/apollo2/regs/am_reg_nvic.h new file mode 100644 index 0000000..6647388 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_nvic.h @@ -0,0 +1,326 @@ +//***************************************************************************** +// +// am_reg_nvic.h +//! @file +//! +//! @brief Register macros for the NVIC module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_NVIC_H +#define AM_REG_NVIC_H + +//***************************************************************************** +// +// NVIC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_NVIC_NUM_MODULES 1 +#define AM_REG_NVICn(n) \ + (REG_NVIC_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_NVIC_ISER0_O 0xE000E100 +#define AM_REG_NVIC_ICER0_O 0xE000E180 +#define AM_REG_NVIC_ISPR0_O 0xE000E200 +#define AM_REG_NVIC_ICPR0_O 0xE000E280 +#define AM_REG_NVIC_IABR0_O 0xE000E300 +#define AM_REG_NVIC_IPR0_O 0xE000E400 +#define AM_REG_NVIC_IPR1_O 0xE000E404 +#define AM_REG_NVIC_IPR2_O 0xE000E408 +#define AM_REG_NVIC_IPR3_O 0xE000E40C +#define AM_REG_NVIC_IPR4_O 0xE000E410 +#define AM_REG_NVIC_IPR5_O 0xE000E414 +#define AM_REG_NVIC_IPR6_O 0xE000E418 +#define AM_REG_NVIC_IPR7_O 0xE000E41C + +//***************************************************************************** +// +// NVIC_ISER0 - Interrupt Set-Enable Register 0 +// +//***************************************************************************** +// NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0. +#define AM_REG_NVIC_ISER0_BITS_S 0 +#define AM_REG_NVIC_ISER0_BITS_M 0xFFFFFFFF +#define AM_REG_NVIC_ISER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// NVIC_ICER0 - Interrupt Clear-Enable Register 0 +// +//***************************************************************************** +// NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0. +#define AM_REG_NVIC_ICER0_BITS_S 0 +#define AM_REG_NVIC_ICER0_BITS_M 0xFFFFFFFF +#define AM_REG_NVIC_ICER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// NVIC_ISPR0 - Interrupt Set-Pending Register 0 +// +//***************************************************************************** +// NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0. +#define AM_REG_NVIC_ISPR0_BITS_S 0 +#define AM_REG_NVIC_ISPR0_BITS_M 0xFFFFFFFF +#define AM_REG_NVIC_ISPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// NVIC_ICPR0 - Interrupt Clear-Pending Register 0 +// +//***************************************************************************** +// NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0. +#define AM_REG_NVIC_ICPR0_BITS_S 0 +#define AM_REG_NVIC_ICPR0_BITS_M 0xFFFFFFFF +#define AM_REG_NVIC_ICPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// NVIC_IABR0 - Interrupt Active Bit Register 0 +// +//***************************************************************************** +// NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0. +#define AM_REG_NVIC_IABR0_BITS_S 0 +#define AM_REG_NVIC_IABR0_BITS_M 0xFFFFFFFF +#define AM_REG_NVIC_IABR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// NVIC_IPR0 - Interrupt Priority Register 0 +// +//***************************************************************************** +// Priority assignment for interrupt vector 3. +#define AM_REG_NVIC_IPR0_PRI_N3_S 24 +#define AM_REG_NVIC_IPR0_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR0_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 2. +#define AM_REG_NVIC_IPR0_PRI_N2_S 16 +#define AM_REG_NVIC_IPR0_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR0_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 1. +#define AM_REG_NVIC_IPR0_PRI_N1_S 8 +#define AM_REG_NVIC_IPR0_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR0_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 0. +#define AM_REG_NVIC_IPR0_PRI_N0_S 0 +#define AM_REG_NVIC_IPR0_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR0_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR1 - Interrupt Priority Register 1 +// +//***************************************************************************** +// Priority assignment for interrupt vector 7. +#define AM_REG_NVIC_IPR1_PRI_N3_S 24 +#define AM_REG_NVIC_IPR1_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR1_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 6. +#define AM_REG_NVIC_IPR1_PRI_N2_S 16 +#define AM_REG_NVIC_IPR1_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR1_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 5. +#define AM_REG_NVIC_IPR1_PRI_N1_S 8 +#define AM_REG_NVIC_IPR1_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR1_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 4. +#define AM_REG_NVIC_IPR1_PRI_N0_S 0 +#define AM_REG_NVIC_IPR1_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR1_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR2 - Interrupt Priority Register 2 +// +//***************************************************************************** +// Priority assignment for interrupt vector 11. +#define AM_REG_NVIC_IPR2_PRI_N3_S 24 +#define AM_REG_NVIC_IPR2_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR2_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 10. +#define AM_REG_NVIC_IPR2_PRI_N2_S 16 +#define AM_REG_NVIC_IPR2_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR2_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 9. +#define AM_REG_NVIC_IPR2_PRI_N1_S 8 +#define AM_REG_NVIC_IPR2_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR2_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 8. +#define AM_REG_NVIC_IPR2_PRI_N0_S 0 +#define AM_REG_NVIC_IPR2_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR2_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR3 - Interrupt Priority Register 3 +// +//***************************************************************************** +// Priority assignment for interrupt vector 15. +#define AM_REG_NVIC_IPR3_PRI_N3_S 24 +#define AM_REG_NVIC_IPR3_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR3_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 14. +#define AM_REG_NVIC_IPR3_PRI_N2_S 16 +#define AM_REG_NVIC_IPR3_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR3_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 13. +#define AM_REG_NVIC_IPR3_PRI_N1_S 8 +#define AM_REG_NVIC_IPR3_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR3_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 12. +#define AM_REG_NVIC_IPR3_PRI_N0_S 0 +#define AM_REG_NVIC_IPR3_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR3_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR4 - Interrupt Priority Register 4 +// +//***************************************************************************** +// Priority assignment for interrupt vector 19. +#define AM_REG_NVIC_IPR4_PRI_N3_S 24 +#define AM_REG_NVIC_IPR4_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR4_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 18. +#define AM_REG_NVIC_IPR4_PRI_N2_S 16 +#define AM_REG_NVIC_IPR4_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR4_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 17. +#define AM_REG_NVIC_IPR4_PRI_N1_S 8 +#define AM_REG_NVIC_IPR4_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR4_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 16. +#define AM_REG_NVIC_IPR4_PRI_N0_S 0 +#define AM_REG_NVIC_IPR4_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR4_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR5 - Interrupt Priority Register 5 +// +//***************************************************************************** +// Priority assignment for interrupt vector 23. +#define AM_REG_NVIC_IPR5_PRI_N3_S 24 +#define AM_REG_NVIC_IPR5_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR5_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 22. +#define AM_REG_NVIC_IPR5_PRI_N2_S 16 +#define AM_REG_NVIC_IPR5_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR5_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 21. +#define AM_REG_NVIC_IPR5_PRI_N1_S 8 +#define AM_REG_NVIC_IPR5_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR5_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 20. +#define AM_REG_NVIC_IPR5_PRI_N0_S 0 +#define AM_REG_NVIC_IPR5_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR5_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR6 - Interrupt Priority Register 6 +// +//***************************************************************************** +// Priority assignment for interrupt vector 27. +#define AM_REG_NVIC_IPR6_PRI_N3_S 24 +#define AM_REG_NVIC_IPR6_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR6_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 26. +#define AM_REG_NVIC_IPR6_PRI_N2_S 16 +#define AM_REG_NVIC_IPR6_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR6_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 25. +#define AM_REG_NVIC_IPR6_PRI_N1_S 8 +#define AM_REG_NVIC_IPR6_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR6_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 24. +#define AM_REG_NVIC_IPR6_PRI_N0_S 0 +#define AM_REG_NVIC_IPR6_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR6_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// NVIC_IPR7 - Interrupt Priority Register 7 +// +//***************************************************************************** +// Priority assignment for interrupt vector 31. +#define AM_REG_NVIC_IPR7_PRI_N3_S 24 +#define AM_REG_NVIC_IPR7_PRI_N3_M 0xFF000000 +#define AM_REG_NVIC_IPR7_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority assignment for interrupt vector 30. +#define AM_REG_NVIC_IPR7_PRI_N2_S 16 +#define AM_REG_NVIC_IPR7_PRI_N2_M 0x00FF0000 +#define AM_REG_NVIC_IPR7_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority assignment for interrupt vector 29. +#define AM_REG_NVIC_IPR7_PRI_N1_S 8 +#define AM_REG_NVIC_IPR7_PRI_N1_M 0x0000FF00 +#define AM_REG_NVIC_IPR7_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority assignment for interrupt vector 28. +#define AM_REG_NVIC_IPR7_PRI_N0_S 0 +#define AM_REG_NVIC_IPR7_PRI_N0_M 0x000000FF +#define AM_REG_NVIC_IPR7_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) + +#endif // AM_REG_NVIC_H diff --git a/mcu/apollo2/regs/am_reg_pdm.h b/mcu/apollo2/regs/am_reg_pdm.h new file mode 100644 index 0000000..f12447b --- /dev/null +++ b/mcu/apollo2/regs/am_reg_pdm.h @@ -0,0 +1,375 @@ +//***************************************************************************** +// +// am_reg_pdm.h +//! @file +//! +//! @brief Register macros for the PDM module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_PDM_H +#define AM_REG_PDM_H + +//***************************************************************************** +// +// PDM +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_PDM_NUM_MODULES 1 +#define AM_REG_PDMn(n) \ + (REG_PDM_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_PDM_PCFG_O 0x00000000 +#define AM_REG_PDM_VCFG_O 0x00000004 +#define AM_REG_PDM_FR_O 0x00000008 +#define AM_REG_PDM_FRD_O 0x0000000C +#define AM_REG_PDM_FLUSH_O 0x00000010 +#define AM_REG_PDM_FTHR_O 0x00000014 +#define AM_REG_PDM_INTEN_O 0x00000200 +#define AM_REG_PDM_INTSTAT_O 0x00000204 +#define AM_REG_PDM_INTCLR_O 0x00000208 +#define AM_REG_PDM_INTSET_O 0x0000020C + +//***************************************************************************** +// +// PDM_INTEN - IO Master Interrupts: Enable +// +//***************************************************************************** +// This is the FIFO underflow interrupt. +#define AM_REG_PDM_INTEN_UNDFL_S 2 +#define AM_REG_PDM_INTEN_UNDFL_M 0x00000004 +#define AM_REG_PDM_INTEN_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO overflow interrupt. +#define AM_REG_PDM_INTEN_OVF_S 1 +#define AM_REG_PDM_INTEN_OVF_M 0x00000002 +#define AM_REG_PDM_INTEN_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the FIFO threshold interrupt. +#define AM_REG_PDM_INTEN_THR_S 0 +#define AM_REG_PDM_INTEN_THR_M 0x00000001 +#define AM_REG_PDM_INTEN_THR(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// PDM_INTSTAT - IO Master Interrupts: Status +// +//***************************************************************************** +// This is the FIFO underflow interrupt. +#define AM_REG_PDM_INTSTAT_UNDFL_S 2 +#define AM_REG_PDM_INTSTAT_UNDFL_M 0x00000004 +#define AM_REG_PDM_INTSTAT_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO overflow interrupt. +#define AM_REG_PDM_INTSTAT_OVF_S 1 +#define AM_REG_PDM_INTSTAT_OVF_M 0x00000002 +#define AM_REG_PDM_INTSTAT_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the FIFO threshold interrupt. +#define AM_REG_PDM_INTSTAT_THR_S 0 +#define AM_REG_PDM_INTSTAT_THR_M 0x00000001 +#define AM_REG_PDM_INTSTAT_THR(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// PDM_INTCLR - IO Master Interrupts: Clear +// +//***************************************************************************** +// This is the FIFO underflow interrupt. +#define AM_REG_PDM_INTCLR_UNDFL_S 2 +#define AM_REG_PDM_INTCLR_UNDFL_M 0x00000004 +#define AM_REG_PDM_INTCLR_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO overflow interrupt. +#define AM_REG_PDM_INTCLR_OVF_S 1 +#define AM_REG_PDM_INTCLR_OVF_M 0x00000002 +#define AM_REG_PDM_INTCLR_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the FIFO threshold interrupt. +#define AM_REG_PDM_INTCLR_THR_S 0 +#define AM_REG_PDM_INTCLR_THR_M 0x00000001 +#define AM_REG_PDM_INTCLR_THR(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// PDM_INTSET - IO Master Interrupts: Set +// +//***************************************************************************** +// This is the FIFO underflow interrupt. +#define AM_REG_PDM_INTSET_UNDFL_S 2 +#define AM_REG_PDM_INTSET_UNDFL_M 0x00000004 +#define AM_REG_PDM_INTSET_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This is the FIFO overflow interrupt. +#define AM_REG_PDM_INTSET_OVF_S 1 +#define AM_REG_PDM_INTSET_OVF_M 0x00000002 +#define AM_REG_PDM_INTSET_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This is the FIFO threshold interrupt. +#define AM_REG_PDM_INTSET_THR_S 0 +#define AM_REG_PDM_INTSET_THR_M 0x00000001 +#define AM_REG_PDM_INTSET_THR(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// PDM_PCFG - PDM Configuration Register +// +//***************************************************************************** +// Left/right channel swap. +#define AM_REG_PDM_PCFG_LRSWAP_S 31 +#define AM_REG_PDM_PCFG_LRSWAP_M 0x80000000 +#define AM_REG_PDM_PCFG_LRSWAP(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_PDM_PCFG_LRSWAP_EN 0x80000000 +#define AM_REG_PDM_PCFG_LRSWAP_NOSWAP 0x00000000 + +// Right channel PGA gain. +#define AM_REG_PDM_PCFG_PGARIGHT_S 27 +#define AM_REG_PDM_PCFG_PGARIGHT_M 0x78000000 +#define AM_REG_PDM_PCFG_PGARIGHT(n) (((uint32_t)(n) << 27) & 0x78000000) +#define AM_REG_PDM_PCFG_PGARIGHT_M15DB 0x78000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M300DB 0x70000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M45DB 0x68000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M60DB 0x60000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M75DB 0x58000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M90DB 0x50000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M105DB 0x48000000 +#define AM_REG_PDM_PCFG_PGARIGHT_M120DB 0x40000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P105DB 0x38000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P90DB 0x30000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P75DB 0x28000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P60DB 0x20000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P45DB 0x18000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P30DB 0x10000000 +#define AM_REG_PDM_PCFG_PGARIGHT_P15DB 0x08000000 +#define AM_REG_PDM_PCFG_PGARIGHT_0DB 0x00000000 + +// Left channel PGA gain. +#define AM_REG_PDM_PCFG_PGALEFT_S 23 +#define AM_REG_PDM_PCFG_PGALEFT_M 0x07800000 +#define AM_REG_PDM_PCFG_PGALEFT(n) (((uint32_t)(n) << 23) & 0x07800000) +#define AM_REG_PDM_PCFG_PGALEFT_M15DB 0x07800000 +#define AM_REG_PDM_PCFG_PGALEFT_M300DB 0x07000000 +#define AM_REG_PDM_PCFG_PGALEFT_M45DB 0x06800000 +#define AM_REG_PDM_PCFG_PGALEFT_M60DB 0x06000000 +#define AM_REG_PDM_PCFG_PGALEFT_M75DB 0x05800000 +#define AM_REG_PDM_PCFG_PGALEFT_M90DB 0x05000000 +#define AM_REG_PDM_PCFG_PGALEFT_M105DB 0x04800000 +#define AM_REG_PDM_PCFG_PGALEFT_M120DB 0x04000000 +#define AM_REG_PDM_PCFG_PGALEFT_P105DB 0x03800000 +#define AM_REG_PDM_PCFG_PGALEFT_P90DB 0x03000000 +#define AM_REG_PDM_PCFG_PGALEFT_P75DB 0x02800000 +#define AM_REG_PDM_PCFG_PGALEFT_P60DB 0x02000000 +#define AM_REG_PDM_PCFG_PGALEFT_P45DB 0x01800000 +#define AM_REG_PDM_PCFG_PGALEFT_P30DB 0x01000000 +#define AM_REG_PDM_PCFG_PGALEFT_P15DB 0x00800000 +#define AM_REG_PDM_PCFG_PGALEFT_0DB 0x00000000 + +// PDM_CLK frequency divisor. +#define AM_REG_PDM_PCFG_MCLKDIV_S 17 +#define AM_REG_PDM_PCFG_MCLKDIV_M 0x00060000 +#define AM_REG_PDM_PCFG_MCLKDIV(n) (((uint32_t)(n) << 17) & 0x00060000) +#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4 0x00060000 +#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3 0x00040000 +#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2 0x00020000 +#define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1 0x00000000 + +// SINC decimation rate. +#define AM_REG_PDM_PCFG_SINCRATE_S 10 +#define AM_REG_PDM_PCFG_SINCRATE_M 0x0001FC00 +#define AM_REG_PDM_PCFG_SINCRATE(n) (((uint32_t)(n) << 10) & 0x0001FC00) + +// High pass filter disable. +#define AM_REG_PDM_PCFG_ADCHPD_S 9 +#define AM_REG_PDM_PCFG_ADCHPD_M 0x00000200 +#define AM_REG_PDM_PCFG_ADCHPD(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_PDM_PCFG_ADCHPD_EN 0x00000000 +#define AM_REG_PDM_PCFG_ADCHPD_DIS 0x00000200 + +// High pass filter coefficients. +#define AM_REG_PDM_PCFG_HPCUTOFF_S 5 +#define AM_REG_PDM_PCFG_HPCUTOFF_M 0x000001E0 +#define AM_REG_PDM_PCFG_HPCUTOFF(n) (((uint32_t)(n) << 5) & 0x000001E0) + +// Number of clocks during gain-setting changes. +#define AM_REG_PDM_PCFG_CYCLES_S 2 +#define AM_REG_PDM_PCFG_CYCLES_M 0x0000001C +#define AM_REG_PDM_PCFG_CYCLES(n) (((uint32_t)(n) << 2) & 0x0000001C) + +// Soft mute control. +#define AM_REG_PDM_PCFG_SOFTMUTE_S 1 +#define AM_REG_PDM_PCFG_SOFTMUTE_M 0x00000002 +#define AM_REG_PDM_PCFG_SOFTMUTE(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_PDM_PCFG_SOFTMUTE_EN 0x00000002 +#define AM_REG_PDM_PCFG_SOFTMUTE_DIS 0x00000000 + +// Data Streaming Control. +#define AM_REG_PDM_PCFG_PDMCORE_S 0 +#define AM_REG_PDM_PCFG_PDMCORE_M 0x00000001 +#define AM_REG_PDM_PCFG_PDMCORE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_PDM_PCFG_PDMCORE_EN 0x00000001 +#define AM_REG_PDM_PCFG_PDMCORE_DIS 0x00000000 + +//***************************************************************************** +// +// PDM_VCFG - Voice Configuration Register +// +//***************************************************************************** +// Enable the IO clock. +#define AM_REG_PDM_VCFG_IOCLKEN_S 31 +#define AM_REG_PDM_VCFG_IOCLKEN_M 0x80000000 +#define AM_REG_PDM_VCFG_IOCLKEN(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_PDM_VCFG_IOCLKEN_DIS 0x00000000 +#define AM_REG_PDM_VCFG_IOCLKEN_EN 0x80000000 + +// Reset the IP core. +#define AM_REG_PDM_VCFG_RSTB_S 30 +#define AM_REG_PDM_VCFG_RSTB_M 0x40000000 +#define AM_REG_PDM_VCFG_RSTB(n) (((uint32_t)(n) << 30) & 0x40000000) +#define AM_REG_PDM_VCFG_RSTB_RESET 0x00000000 +#define AM_REG_PDM_VCFG_RSTB_NORM 0x40000000 + +// Select the PDM input clock. +#define AM_REG_PDM_VCFG_PDMCLKSEL_S 27 +#define AM_REG_PDM_VCFG_PDMCLKSEL_M 0x38000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL(n) (((uint32_t)(n) << 27) & 0x38000000) +#define AM_REG_PDM_VCFG_PDMCLKSEL_DISABLE 0x00000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_12MHz 0x08000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_6MHz 0x10000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_3MHz 0x18000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz 0x20000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_750KHz 0x28000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_375KHz 0x30000000 +#define AM_REG_PDM_VCFG_PDMCLKSEL_187KHz 0x38000000 + +// Enable the serial clock. +#define AM_REG_PDM_VCFG_PDMCLK_S 26 +#define AM_REG_PDM_VCFG_PDMCLK_M 0x04000000 +#define AM_REG_PDM_VCFG_PDMCLK(n) (((uint32_t)(n) << 26) & 0x04000000) +#define AM_REG_PDM_VCFG_PDMCLK_DIS 0x00000000 +#define AM_REG_PDM_VCFG_PDMCLK_EN 0x04000000 + +// I2S interface enable. +#define AM_REG_PDM_VCFG_I2SMODE_S 20 +#define AM_REG_PDM_VCFG_I2SMODE_M 0x00100000 +#define AM_REG_PDM_VCFG_I2SMODE(n) (((uint32_t)(n) << 20) & 0x00100000) +#define AM_REG_PDM_VCFG_I2SMODE_DIS 0x00000000 +#define AM_REG_PDM_VCFG_I2SMODE_EN 0x00100000 + +// I2S BCLK input inversion. +#define AM_REG_PDM_VCFG_BCLKINV_S 19 +#define AM_REG_PDM_VCFG_BCLKINV_M 0x00080000 +#define AM_REG_PDM_VCFG_BCLKINV(n) (((uint32_t)(n) << 19) & 0x00080000) +#define AM_REG_PDM_VCFG_BCLKINV_INV 0x00000000 +#define AM_REG_PDM_VCFG_BCLKINV_NORM 0x00080000 + +// PDM clock sampling delay. +#define AM_REG_PDM_VCFG_DMICKDEL_S 17 +#define AM_REG_PDM_VCFG_DMICKDEL_M 0x00020000 +#define AM_REG_PDM_VCFG_DMICKDEL(n) (((uint32_t)(n) << 17) & 0x00020000) +#define AM_REG_PDM_VCFG_DMICKDEL_0CYC 0x00000000 +#define AM_REG_PDM_VCFG_DMICKDEL_1CYC 0x00020000 + +// Select PDM input clock source. +#define AM_REG_PDM_VCFG_SELAP_S 16 +#define AM_REG_PDM_VCFG_SELAP_M 0x00010000 +#define AM_REG_PDM_VCFG_SELAP(n) (((uint32_t)(n) << 16) & 0x00010000) +#define AM_REG_PDM_VCFG_SELAP_I2S 0x00010000 +#define AM_REG_PDM_VCFG_SELAP_INTERNAL 0x00000000 + +// PCM data packing enable. +#define AM_REG_PDM_VCFG_PCMPACK_S 8 +#define AM_REG_PDM_VCFG_PCMPACK_M 0x00000100 +#define AM_REG_PDM_VCFG_PCMPACK(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_PDM_VCFG_PCMPACK_DIS 0x00000000 +#define AM_REG_PDM_VCFG_PCMPACK_EN 0x00000100 + +// Set PCM channels. +#define AM_REG_PDM_VCFG_CHSET_S 3 +#define AM_REG_PDM_VCFG_CHSET_M 0x00000018 +#define AM_REG_PDM_VCFG_CHSET(n) (((uint32_t)(n) << 3) & 0x00000018) +#define AM_REG_PDM_VCFG_CHSET_DIS 0x00000000 +#define AM_REG_PDM_VCFG_CHSET_LEFT 0x00000008 +#define AM_REG_PDM_VCFG_CHSET_RIGHT 0x00000010 +#define AM_REG_PDM_VCFG_CHSET_STEREO 0x00000018 + +//***************************************************************************** +// +// PDM_FR - Voice Status Register +// +//***************************************************************************** +// Valid 32-bit entries currently in the FIFO. +#define AM_REG_PDM_FR_FIFOCNT_S 0 +#define AM_REG_PDM_FR_FIFOCNT_M 0x000001FF +#define AM_REG_PDM_FR_FIFOCNT(n) (((uint32_t)(n) << 0) & 0x000001FF) + +//***************************************************************************** +// +// PDM_FRD - FIFO Read +// +//***************************************************************************** +// FIFO read data. +#define AM_REG_PDM_FRD_FIFOREAD_S 0 +#define AM_REG_PDM_FRD_FIFOREAD_M 0xFFFFFFFF +#define AM_REG_PDM_FRD_FIFOREAD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// PDM_FLUSH - FIFO Flush +// +//***************************************************************************** +// FIFO FLUSH. +#define AM_REG_PDM_FLUSH_FIFOFLUSH_S 0 +#define AM_REG_PDM_FLUSH_FIFOFLUSH_M 0x00000001 +#define AM_REG_PDM_FLUSH_FIFOFLUSH(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// PDM_FTHR - FIFO Threshold +// +//***************************************************************************** +// FIFO interrupt threshold. +#define AM_REG_PDM_FTHR_FIFOTHR_S 0 +#define AM_REG_PDM_FTHR_FIFOTHR_M 0x000000FF +#define AM_REG_PDM_FTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF) + +#endif // AM_REG_PDM_H diff --git a/mcu/apollo2/regs/am_reg_pwrctrl.h b/mcu/apollo2/regs/am_reg_pwrctrl.h new file mode 100644 index 0000000..5fd0f8f --- /dev/null +++ b/mcu/apollo2/regs/am_reg_pwrctrl.h @@ -0,0 +1,486 @@ +//***************************************************************************** +// +// am_reg_pwrctrl.h +//! @file +//! +//! @brief Register macros for the PWRCTRL module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_PWRCTRL_H +#define AM_REG_PWRCTRL_H + +//***************************************************************************** +// +// PWRCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_PWRCTRL_NUM_MODULES 1 +#define AM_REG_PWRCTRLn(n) \ + (REG_PWRCTRL_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_PWRCTRL_SUPPLYSRC_O 0x00000000 +#define AM_REG_PWRCTRL_POWERSTATUS_O 0x00000004 +#define AM_REG_PWRCTRL_DEVICEEN_O 0x00000008 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_O 0x0000000C +#define AM_REG_PWRCTRL_MEMEN_O 0x00000010 +#define AM_REG_PWRCTRL_PWRONSTATUS_O 0x00000014 +#define AM_REG_PWRCTRL_SRAMCTRL_O 0x00000018 +#define AM_REG_PWRCTRL_ADCSTATUS_O 0x0000001C +#define AM_REG_PWRCTRL_MISCOPT_O 0x00000020 + +//***************************************************************************** +// +// PWRCTRL_SUPPLYSRC - Memory and Core Voltage Supply Source Select Register +// +//***************************************************************************** +// Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in +// DEEP SLEEP. If all the devices are off then this does not matter and LDO (low +// power mode) is used +#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_S 2 +#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M 0x00000004 +#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN 0x00000004 + +// Enables and Selects the Core Buck as the supply for the low-voltage power +// domain. +#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_S 1 +#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M 0x00000002 +#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_EN 0x00000002 + +// Enables and select the Memory Buck as the supply for the Flash and SRAM power +// domain. +#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_S 0 +#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M 0x00000001 +#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN 0x00000001 + +//***************************************************************************** +// +// PWRCTRL_POWERSTATUS - Power Status Register for MCU supplies and peripherals +// +//***************************************************************************** +// Indicates whether the Core low-voltage domain is supplied from the LDO or the +// Buck. +#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_S 1 +#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M 0x00000002 +#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_LDO 0x00000000 +#define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_BUCK 0x00000002 + +// Indicate whether the Memory power domain is supplied from the LDO or the +// Buck. +#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_S 0 +#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M 0x00000001 +#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_LDO 0x00000000 +#define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_BUCK 0x00000001 + +//***************************************************************************** +// +// PWRCTRL_DEVICEEN - DEVICE ENABLES for SHELBY +// +//***************************************************************************** +// Enable PDM Digital Block +#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_S 10 +#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_M 0x00000400 +#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_EN 0x00000400 +#define AM_REG_PWRCTRL_DEVICEEN_PWRPDM_DIS 0x00000000 + +// Enable ADC Digital Block +#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_S 9 +#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_M 0x00000200 +#define AM_REG_PWRCTRL_DEVICEEN_PWRADC(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_EN 0x00000200 +#define AM_REG_PWRCTRL_DEVICEEN_PWRADC_DIS 0x00000000 + +// Enable UART 1 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_S 8 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_M 0x00000100 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_EN 0x00000100 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART1_DIS 0x00000000 + +// Enable UART 0 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_S 7 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_M 0x00000080 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_EN 0x00000080 +#define AM_REG_PWRCTRL_DEVICEEN_PWRUART0_DIS 0x00000000 + +// Enable IO MASTER 5 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_S 6 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M 0x00000040 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN 0x00000040 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_DIS 0x00000000 + +// Enable IO MASTER 4 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_S 5 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M 0x00000020 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN 0x00000020 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_DIS 0x00000000 + +// Enable IO MASTER 3 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_S 4 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M 0x00000010 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN 0x00000010 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_DIS 0x00000000 + +// Enable IO MASTER 2 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_S 3 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M 0x00000008 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN 0x00000008 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_DIS 0x00000000 + +// Enable IO MASTER 1 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_S 2 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M 0x00000004 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN 0x00000004 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_DIS 0x00000000 + +// Enable IO MASTER 0 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_S 1 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M 0x00000002 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN 0x00000002 +#define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_DIS 0x00000000 + +// Enable IO SLAVE +#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_S 0 +#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M 0x00000001 +#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN 0x00000001 +#define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_DIS 0x00000000 + +//***************************************************************************** +// +// PWRCTRL_SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode +// +//***************************************************************************** +// Enable CACHE BANKS to power down in deep sleep +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_S 31 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_M 0x80000000 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_EN 0x80000000 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_DIS 0x00000000 + +// Selects which SRAM banks are powered down in deep sleep mode, causing the +// contents of the bank to be lost. +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_S 0 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_M 0x000007FF +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN(n) (((uint32_t)(n) << 0) & 0x000007FF) +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_NONE 0x00000000 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM0 0x00000001 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM1 0x00000002 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM2 0x00000004 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM3 0x00000008 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP1 0x00000010 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP2 0x00000020 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP3 0x00000040 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP4 0x00000080 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP5 0x00000100 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP6 0x00000200 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP7 0x00000400 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM8K 0x00000001 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM16K 0x00000003 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM32K 0x0000000F +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM64K 0x0000001F +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM128K 0x0000007F +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER8K 0x000007FE +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER16K 0x000007FC +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER24K 0x000007F8 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER32K 0x000007F0 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER64K 0x000007E0 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER128K 0x00000780 +#define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALL 0x000007FF + +//***************************************************************************** +// +// PWRCTRL_MEMEN - Disables individual banks of the MEMORY array +// +//***************************************************************************** +// Enable CACHE BANK 2 +#define AM_REG_PWRCTRL_MEMEN_CACHEB2_S 31 +#define AM_REG_PWRCTRL_MEMEN_CACHEB2_M 0x80000000 +#define AM_REG_PWRCTRL_MEMEN_CACHEB2(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_PWRCTRL_MEMEN_CACHEB2_EN 0x80000000 +#define AM_REG_PWRCTRL_MEMEN_CACHEB2_DIS 0x00000000 + +// Enable CACHE BANK 0 +#define AM_REG_PWRCTRL_MEMEN_CACHEB0_S 29 +#define AM_REG_PWRCTRL_MEMEN_CACHEB0_M 0x20000000 +#define AM_REG_PWRCTRL_MEMEN_CACHEB0(n) (((uint32_t)(n) << 29) & 0x20000000) +#define AM_REG_PWRCTRL_MEMEN_CACHEB0_EN 0x20000000 +#define AM_REG_PWRCTRL_MEMEN_CACHEB0_DIS 0x00000000 + +// Enable FLASH1 +#define AM_REG_PWRCTRL_MEMEN_FLASH1_S 12 +#define AM_REG_PWRCTRL_MEMEN_FLASH1_M 0x00001000 +#define AM_REG_PWRCTRL_MEMEN_FLASH1(n) (((uint32_t)(n) << 12) & 0x00001000) +#define AM_REG_PWRCTRL_MEMEN_FLASH1_EN 0x00001000 +#define AM_REG_PWRCTRL_MEMEN_FLASH1_DIS 0x00000000 + +// Enable FLASH 0 +#define AM_REG_PWRCTRL_MEMEN_FLASH0_S 11 +#define AM_REG_PWRCTRL_MEMEN_FLASH0_M 0x00000800 +#define AM_REG_PWRCTRL_MEMEN_FLASH0(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_PWRCTRL_MEMEN_FLASH0_EN 0x00000800 +#define AM_REG_PWRCTRL_MEMEN_FLASH0_DIS 0x00000000 + +// Enables power for selected SRAM banks (else an access to its address space to +// generate a Hard Fault). +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_S 0 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_M 0x000007FF +#define AM_REG_PWRCTRL_MEMEN_SRAMEN(n) (((uint32_t)(n) << 0) & 0x000007FF) +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_NONE 0x00000000 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 0x00000001 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 0x00000002 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2 0x00000004 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM3 0x00000008 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP1 0x00000010 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2 0x00000020 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP3 0x00000040 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 0x00000080 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5 0x00000100 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6 0x00000200 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP7 0x00000400 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K 0x00000001 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K 0x00000003 +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K 0x0000000F +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K 0x0000001F +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K 0x0000007F +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K 0x000007FF +#define AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL 0x000007FF + +//***************************************************************************** +// +// PWRCTRL_PWRONSTATUS - POWER ON Status +// +//***************************************************************************** +// This bit is 1 if power is supplied to CACHE BANK 2 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_S 21 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M 0x00200000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2(n) (((uint32_t)(n) << 21) & 0x00200000) + +// This bit is 1 if power is supplied to CACHE BANK 0 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_S 19 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M 0x00080000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0(n) (((uint32_t)(n) << 19) & 0x00080000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP7 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_S 18 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M 0x00040000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM(n) (((uint32_t)(n) << 18) & 0x00040000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP6 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_S 17 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M 0x00020000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM(n) (((uint32_t)(n) << 17) & 0x00020000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP5 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_S 16 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M 0x00010000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM(n) (((uint32_t)(n) << 16) & 0x00010000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP4 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_S 15 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M 0x00008000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM(n) (((uint32_t)(n) << 15) & 0x00008000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP3 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_S 14 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M 0x00004000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM(n) (((uint32_t)(n) << 14) & 0x00004000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP2 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_S 13 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M 0x00002000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM(n) (((uint32_t)(n) << 13) & 0x00002000) + +// This bit is 1 if power is supplied to SRAM domain PD_GRP1 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_S 12 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M 0x00001000 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM(n) (((uint32_t)(n) << 12) & 0x00001000) + +// This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_S 11 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M 0x00000800 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3(n) (((uint32_t)(n) << 11) & 0x00000800) + +// This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_S 10 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M 0x00000400 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This bit is 1 if power is supplied to SRAM domain SRAM0_1 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_S 9 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M 0x00000200 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This bit is 1 if power is supplied to SRAM domain SRAM0_0 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_S 8 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M 0x00000100 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit is 1 if power is supplied to domain PD_ADC +#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_S 7 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M 0x00000080 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDADC(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This bit is 1 if power is supplied to domain PD_FLAM1 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_S 6 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M 0x00000040 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This bit is 1 if power is supplied to domain PD_FLAM0 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_S 5 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M 0x00000020 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This bit is 1 if power is supplied to domain PD_PDM +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_S 4 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M 0x00000010 +#define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit is 1 if power is supplied to power domain C, which supplies IOM3-5. +#define AM_REG_PWRCTRL_PWRONSTATUS_PDC_S 3 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDC_M 0x00000008 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDC(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit is 1 if power is supplied to power domain B, which supplies IOM0-2. +#define AM_REG_PWRCTRL_PWRONSTATUS_PDB_S 2 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDB_M 0x00000004 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDB(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit is 1 if power is supplied to power domain A, which supplies IOS and +// UART0,1. +#define AM_REG_PWRCTRL_PWRONSTATUS_PDA_S 1 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDA_M 0x00000002 +#define AM_REG_PWRCTRL_PWRONSTATUS_PDA(n) (((uint32_t)(n) << 1) & 0x00000002) + +//***************************************************************************** +// +// PWRCTRL_SRAMCTRL - SRAM Control register +// +//***************************************************************************** +// Enables top-level clock gating in the SRAM block. This bit should be enabled +// for lowest power operation. +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_S 2 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_M 0x00000004 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN 0x00000004 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_DIS 0x00000000 + +// Enables individual per-RAM clock gating in the SRAM block. This bit should +// be enabled for lowest power operation. +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_S 1 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_M 0x00000002 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN 0x00000002 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_DIS 0x00000000 + +// Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will +// be put into light sleep mode while inactive. NOTE: if the SRAM is actively +// used, this may have an adverse affect on power since entering/exiting LS mode +// may consume more power than would be saved. +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_S 0 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_M 0x00000001 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_EN 0x00000001 +#define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS 0x00000000 + +//***************************************************************************** +// +// PWRCTRL_ADCSTATUS - Power Status Register for ADC Block +// +//***************************************************************************** +// This bit indicates that the ADC REFBUF is powered down +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_S 5 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_M 0x00000020 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This bit indicates that the ADC REFKEEP is powered down +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_S 4 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_M 0x00000010 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit indicates that the ADC VBAT resistor divider is powered down +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_S 3 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_M 0x00000008 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit indicates that the ADC temperature sensor input buffer is powered +// down +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_S 2 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_M 0x00000004 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit indicates that the ADC Band Gap is powered down +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_S 1 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_M 0x00000002 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit indicates that the ADC is powered down +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_S 0 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_M 0x00000001 +#define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// PWRCTRL_MISCOPT - Power Optimization Control Bits +// +//***************************************************************************** +// Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep +// even when the ctimers or stimers are running +#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_S 2 +#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_M 0x00000004 +#define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS(n) (((uint32_t)(n) << 2) & 0x00000004) + +#endif // AM_REG_PWRCTRL_H diff --git a/mcu/apollo2/regs/am_reg_rstgen.h b/mcu/apollo2/regs/am_reg_rstgen.h new file mode 100644 index 0000000..c88c116 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_rstgen.h @@ -0,0 +1,212 @@ +//***************************************************************************** +// +// am_reg_rstgen.h +//! @file +//! +//! @brief Register macros for the RSTGEN module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_RSTGEN_H +#define AM_REG_RSTGEN_H + +//***************************************************************************** +// +// RSTGEN +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_RSTGEN_NUM_MODULES 1 +#define AM_REG_RSTGENn(n) \ + (REG_RSTGEN_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_RSTGEN_CFG_O 0x00000000 +#define AM_REG_RSTGEN_SWPOI_O 0x00000004 +#define AM_REG_RSTGEN_SWPOR_O 0x00000008 +#define AM_REG_RSTGEN_STAT_O 0x0000000C +#define AM_REG_RSTGEN_CLRSTAT_O 0x00000010 +#define AM_REG_RSTGEN_TPIU_RST_O 0x00000014 +#define AM_REG_RSTGEN_INTEN_O 0x00000200 +#define AM_REG_RSTGEN_INTSTAT_O 0x00000204 +#define AM_REG_RSTGEN_INTCLR_O 0x00000208 +#define AM_REG_RSTGEN_INTSET_O 0x0000020C + +//***************************************************************************** +// +// RSTGEN_INTEN - Reset Interrupt register: Enable +// +//***************************************************************************** +// Enables an interrupt that triggers when VCC is below BODH level. +#define AM_REG_RSTGEN_INTEN_BODH_S 0 +#define AM_REG_RSTGEN_INTEN_BODH_M 0x00000001 +#define AM_REG_RSTGEN_INTEN_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_INTSTAT - Reset Interrupt register: Status +// +//***************************************************************************** +// Enables an interrupt that triggers when VCC is below BODH level. +#define AM_REG_RSTGEN_INTSTAT_BODH_S 0 +#define AM_REG_RSTGEN_INTSTAT_BODH_M 0x00000001 +#define AM_REG_RSTGEN_INTSTAT_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_INTCLR - Reset Interrupt register: Clear +// +//***************************************************************************** +// Enables an interrupt that triggers when VCC is below BODH level. +#define AM_REG_RSTGEN_INTCLR_BODH_S 0 +#define AM_REG_RSTGEN_INTCLR_BODH_M 0x00000001 +#define AM_REG_RSTGEN_INTCLR_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_INTSET - Reset Interrupt register: Set +// +//***************************************************************************** +// Enables an interrupt that triggers when VCC is below BODH level. +#define AM_REG_RSTGEN_INTSET_BODH_S 0 +#define AM_REG_RSTGEN_INTSET_BODH_M 0x00000001 +#define AM_REG_RSTGEN_INTSET_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_CFG - Configuration Register +// +//***************************************************************************** +// Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured +// for WDT reset. +#define AM_REG_RSTGEN_CFG_WDREN_S 1 +#define AM_REG_RSTGEN_CFG_WDREN_M 0x00000002 +#define AM_REG_RSTGEN_CFG_WDREN(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Brown out high (2.1v) reset enable. +#define AM_REG_RSTGEN_CFG_BODHREN_S 0 +#define AM_REG_RSTGEN_CFG_BODHREN_M 0x00000001 +#define AM_REG_RSTGEN_CFG_BODHREN(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_SWPOI - Software POI Reset +// +//***************************************************************************** +// 0x1B generates a software POI reset. +#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_S 0 +#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_M 0x000000FF +#define AM_REG_RSTGEN_SWPOI_SWPOIKEY(n) (((uint32_t)(n) << 0) & 0x000000FF) +#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE 0x0000001B + +//***************************************************************************** +// +// RSTGEN_SWPOR - Software POR Reset +// +//***************************************************************************** +// 0xD4 generates a software POR reset. +#define AM_REG_RSTGEN_SWPOR_SWPORKEY_S 0 +#define AM_REG_RSTGEN_SWPOR_SWPORKEY_M 0x000000FF +#define AM_REG_RSTGEN_SWPOR_SWPORKEY(n) (((uint32_t)(n) << 0) & 0x000000FF) +#define AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE 0x000000D4 + +//***************************************************************************** +// +// RSTGEN_STAT - Status Register +// +//***************************************************************************** +// Reset was initiated by a Watchdog Timer Reset. +#define AM_REG_RSTGEN_STAT_WDRSTAT_S 6 +#define AM_REG_RSTGEN_STAT_WDRSTAT_M 0x00000040 +#define AM_REG_RSTGEN_STAT_WDRSTAT(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Reset was a initiated by Debugger Reset. +#define AM_REG_RSTGEN_STAT_DBGRSTAT_S 5 +#define AM_REG_RSTGEN_STAT_DBGRSTAT_M 0x00000020 +#define AM_REG_RSTGEN_STAT_DBGRSTAT(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Reset was a initiated by Software POI Reset. +#define AM_REG_RSTGEN_STAT_POIRSTAT_S 4 +#define AM_REG_RSTGEN_STAT_POIRSTAT_M 0x00000010 +#define AM_REG_RSTGEN_STAT_POIRSTAT(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Reset was a initiated by SW POR or AIRCR Reset. +#define AM_REG_RSTGEN_STAT_SWRSTAT_S 3 +#define AM_REG_RSTGEN_STAT_SWRSTAT_M 0x00000008 +#define AM_REG_RSTGEN_STAT_SWRSTAT(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Reset was initiated by a Brown-Out Reset. +#define AM_REG_RSTGEN_STAT_BORSTAT_S 2 +#define AM_REG_RSTGEN_STAT_BORSTAT_M 0x00000004 +#define AM_REG_RSTGEN_STAT_BORSTAT(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Reset was initiated by a Power-On Reset. +#define AM_REG_RSTGEN_STAT_PORSTAT_S 1 +#define AM_REG_RSTGEN_STAT_PORSTAT_M 0x00000002 +#define AM_REG_RSTGEN_STAT_PORSTAT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Reset was initiated by an External Reset. +#define AM_REG_RSTGEN_STAT_EXRSTAT_S 0 +#define AM_REG_RSTGEN_STAT_EXRSTAT_M 0x00000001 +#define AM_REG_RSTGEN_STAT_EXRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_CLRSTAT - Clear the status register +// +//***************************************************************************** +// Writing a 1 to this bit clears all bits in the RST_STAT. +#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_S 0 +#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_M 0x00000001 +#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RSTGEN_TPIU_RST - TPIU reset +// +//***************************************************************************** +// Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' +// to clear the reset. +#define AM_REG_RSTGEN_TPIU_RST_TPIURST_S 0 +#define AM_REG_RSTGEN_TPIU_RST_TPIURST_M 0x00000001 +#define AM_REG_RSTGEN_TPIU_RST_TPIURST(n) (((uint32_t)(n) << 0) & 0x00000001) + +#endif // AM_REG_RSTGEN_H diff --git a/mcu/apollo2/regs/am_reg_rtc.h b/mcu/apollo2/regs/am_reg_rtc.h new file mode 100644 index 0000000..392f8c3 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_rtc.h @@ -0,0 +1,327 @@ +//***************************************************************************** +// +// am_reg_rtc.h +//! @file +//! +//! @brief Register macros for the RTC module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_RTC_H +#define AM_REG_RTC_H + +//***************************************************************************** +// +// RTC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_RTC_NUM_MODULES 1 +#define AM_REG_RTCn(n) \ + (REG_RTC_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_RTC_CTRLOW_O 0x00000000 +#define AM_REG_RTC_CTRUP_O 0x00000004 +#define AM_REG_RTC_ALMLOW_O 0x00000008 +#define AM_REG_RTC_ALMUP_O 0x0000000C +#define AM_REG_RTC_RTCCTL_O 0x00000010 +#define AM_REG_RTC_INTEN_O 0x000000C0 +#define AM_REG_RTC_INTSTAT_O 0x000000C4 +#define AM_REG_RTC_INTCLR_O 0x000000C8 +#define AM_REG_RTC_INTSET_O 0x000000CC + +//***************************************************************************** +// +// RTC_INTEN - RTC Interrupt Register: Enable +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_RTC_INTEN_ALM_S 3 +#define AM_REG_RTC_INTEN_ALM_M 0x00000008 +#define AM_REG_RTC_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_RTC_INTEN_OF_S 2 +#define AM_REG_RTC_INTEN_OF_M 0x00000004 +#define AM_REG_RTC_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_RTC_INTEN_ACC_S 1 +#define AM_REG_RTC_INTEN_ACC_M 0x00000002 +#define AM_REG_RTC_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_RTC_INTEN_ACF_S 0 +#define AM_REG_RTC_INTEN_ACF_M 0x00000001 +#define AM_REG_RTC_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RTC_INTSTAT - RTC Interrupt Register: Status +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_RTC_INTSTAT_ALM_S 3 +#define AM_REG_RTC_INTSTAT_ALM_M 0x00000008 +#define AM_REG_RTC_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_RTC_INTSTAT_OF_S 2 +#define AM_REG_RTC_INTSTAT_OF_M 0x00000004 +#define AM_REG_RTC_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_RTC_INTSTAT_ACC_S 1 +#define AM_REG_RTC_INTSTAT_ACC_M 0x00000002 +#define AM_REG_RTC_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_RTC_INTSTAT_ACF_S 0 +#define AM_REG_RTC_INTSTAT_ACF_M 0x00000001 +#define AM_REG_RTC_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RTC_INTCLR - RTC Interrupt Register: Clear +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_RTC_INTCLR_ALM_S 3 +#define AM_REG_RTC_INTCLR_ALM_M 0x00000008 +#define AM_REG_RTC_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_RTC_INTCLR_OF_S 2 +#define AM_REG_RTC_INTCLR_OF_M 0x00000004 +#define AM_REG_RTC_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_RTC_INTCLR_ACC_S 1 +#define AM_REG_RTC_INTCLR_ACC_M 0x00000002 +#define AM_REG_RTC_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_RTC_INTCLR_ACF_S 0 +#define AM_REG_RTC_INTCLR_ACF_M 0x00000001 +#define AM_REG_RTC_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RTC_INTSET - RTC Interrupt Register: Set +// +//***************************************************************************** +// RTC Alarm interrupt +#define AM_REG_RTC_INTSET_ALM_S 3 +#define AM_REG_RTC_INTSET_ALM_M 0x00000008 +#define AM_REG_RTC_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// XT Oscillator Fail interrupt +#define AM_REG_RTC_INTSET_OF_S 2 +#define AM_REG_RTC_INTSET_OF_M 0x00000004 +#define AM_REG_RTC_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Autocalibration Complete interrupt +#define AM_REG_RTC_INTSET_ACC_S 1 +#define AM_REG_RTC_INTSET_ACC_M 0x00000002 +#define AM_REG_RTC_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Autocalibration Fail interrupt +#define AM_REG_RTC_INTSET_ACF_S 0 +#define AM_REG_RTC_INTSET_ACF_M 0x00000001 +#define AM_REG_RTC_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// RTC_CTRLOW - RTC Counters Lower +// +//***************************************************************************** +// Hours Counter +#define AM_REG_RTC_CTRLOW_CTRHR_S 24 +#define AM_REG_RTC_CTRLOW_CTRHR_M 0x3F000000 +#define AM_REG_RTC_CTRLOW_CTRHR(n) (((uint32_t)(n) << 24) & 0x3F000000) + +// Minutes Counter +#define AM_REG_RTC_CTRLOW_CTRMIN_S 16 +#define AM_REG_RTC_CTRLOW_CTRMIN_M 0x007F0000 +#define AM_REG_RTC_CTRLOW_CTRMIN(n) (((uint32_t)(n) << 16) & 0x007F0000) + +// Seconds Counter +#define AM_REG_RTC_CTRLOW_CTRSEC_S 8 +#define AM_REG_RTC_CTRLOW_CTRSEC_M 0x00007F00 +#define AM_REG_RTC_CTRLOW_CTRSEC(n) (((uint32_t)(n) << 8) & 0x00007F00) + +// 100ths of a second Counter +#define AM_REG_RTC_CTRLOW_CTR100_S 0 +#define AM_REG_RTC_CTRLOW_CTR100_M 0x000000FF +#define AM_REG_RTC_CTRLOW_CTR100(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// RTC_CTRUP - RTC Counters Upper +// +//***************************************************************************** +// Counter read error status +#define AM_REG_RTC_CTRUP_CTERR_S 31 +#define AM_REG_RTC_CTRUP_CTERR_M 0x80000000 +#define AM_REG_RTC_CTRUP_CTERR(n) (((uint32_t)(n) << 31) & 0x80000000) +#define AM_REG_RTC_CTRUP_CTERR_NOERR 0x00000000 +#define AM_REG_RTC_CTRUP_CTERR_RDERR 0x80000000 + +// Century enable +#define AM_REG_RTC_CTRUP_CEB_S 28 +#define AM_REG_RTC_CTRUP_CEB_M 0x10000000 +#define AM_REG_RTC_CTRUP_CEB(n) (((uint32_t)(n) << 28) & 0x10000000) +#define AM_REG_RTC_CTRUP_CEB_DIS 0x00000000 +#define AM_REG_RTC_CTRUP_CEB_EN 0x10000000 + +// Century +#define AM_REG_RTC_CTRUP_CB_S 27 +#define AM_REG_RTC_CTRUP_CB_M 0x08000000 +#define AM_REG_RTC_CTRUP_CB(n) (((uint32_t)(n) << 27) & 0x08000000) +#define AM_REG_RTC_CTRUP_CB_2000 0x00000000 +#define AM_REG_RTC_CTRUP_CB_1900_2100 0x08000000 + +// Weekdays Counter +#define AM_REG_RTC_CTRUP_CTRWKDY_S 24 +#define AM_REG_RTC_CTRUP_CTRWKDY_M 0x07000000 +#define AM_REG_RTC_CTRUP_CTRWKDY(n) (((uint32_t)(n) << 24) & 0x07000000) + +// Years Counter +#define AM_REG_RTC_CTRUP_CTRYR_S 16 +#define AM_REG_RTC_CTRUP_CTRYR_M 0x00FF0000 +#define AM_REG_RTC_CTRUP_CTRYR(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Months Counter +#define AM_REG_RTC_CTRUP_CTRMO_S 8 +#define AM_REG_RTC_CTRUP_CTRMO_M 0x00001F00 +#define AM_REG_RTC_CTRUP_CTRMO(n) (((uint32_t)(n) << 8) & 0x00001F00) + +// Date Counter +#define AM_REG_RTC_CTRUP_CTRDATE_S 0 +#define AM_REG_RTC_CTRUP_CTRDATE_M 0x0000003F +#define AM_REG_RTC_CTRUP_CTRDATE(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// RTC_ALMLOW - RTC Alarms Lower +// +//***************************************************************************** +// Hours Alarm +#define AM_REG_RTC_ALMLOW_ALMHR_S 24 +#define AM_REG_RTC_ALMLOW_ALMHR_M 0x3F000000 +#define AM_REG_RTC_ALMLOW_ALMHR(n) (((uint32_t)(n) << 24) & 0x3F000000) + +// Minutes Alarm +#define AM_REG_RTC_ALMLOW_ALMMIN_S 16 +#define AM_REG_RTC_ALMLOW_ALMMIN_M 0x007F0000 +#define AM_REG_RTC_ALMLOW_ALMMIN(n) (((uint32_t)(n) << 16) & 0x007F0000) + +// Seconds Alarm +#define AM_REG_RTC_ALMLOW_ALMSEC_S 8 +#define AM_REG_RTC_ALMLOW_ALMSEC_M 0x00007F00 +#define AM_REG_RTC_ALMLOW_ALMSEC(n) (((uint32_t)(n) << 8) & 0x00007F00) + +// 100ths of a second Alarm +#define AM_REG_RTC_ALMLOW_ALM100_S 0 +#define AM_REG_RTC_ALMLOW_ALM100_M 0x000000FF +#define AM_REG_RTC_ALMLOW_ALM100(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// RTC_ALMUP - RTC Alarms Upper +// +//***************************************************************************** +// Weekdays Alarm +#define AM_REG_RTC_ALMUP_ALMWKDY_S 16 +#define AM_REG_RTC_ALMUP_ALMWKDY_M 0x00070000 +#define AM_REG_RTC_ALMUP_ALMWKDY(n) (((uint32_t)(n) << 16) & 0x00070000) + +// Months Alarm +#define AM_REG_RTC_ALMUP_ALMMO_S 8 +#define AM_REG_RTC_ALMUP_ALMMO_M 0x00001F00 +#define AM_REG_RTC_ALMUP_ALMMO(n) (((uint32_t)(n) << 8) & 0x00001F00) + +// Date Alarm +#define AM_REG_RTC_ALMUP_ALMDATE_S 0 +#define AM_REG_RTC_ALMUP_ALMDATE_M 0x0000003F +#define AM_REG_RTC_ALMUP_ALMDATE(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// RTC_RTCCTL - RTC Control Register +// +//***************************************************************************** +// Hours Counter mode +#define AM_REG_RTC_RTCCTL_HR1224_S 5 +#define AM_REG_RTC_RTCCTL_HR1224_M 0x00000020 +#define AM_REG_RTC_RTCCTL_HR1224(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_RTC_RTCCTL_HR1224_24HR 0x00000000 +#define AM_REG_RTC_RTCCTL_HR1224_12HR 0x00000020 + +// RTC input clock control +#define AM_REG_RTC_RTCCTL_RSTOP_S 4 +#define AM_REG_RTC_RTCCTL_RSTOP_M 0x00000010 +#define AM_REG_RTC_RTCCTL_RSTOP(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_RTC_RTCCTL_RSTOP_RUN 0x00000000 +#define AM_REG_RTC_RTCCTL_RSTOP_STOP 0x00000010 + +// Alarm repeat interval +#define AM_REG_RTC_RTCCTL_RPT_S 1 +#define AM_REG_RTC_RTCCTL_RPT_M 0x0000000E +#define AM_REG_RTC_RTCCTL_RPT(n) (((uint32_t)(n) << 1) & 0x0000000E) +#define AM_REG_RTC_RTCCTL_RPT_DIS 0x00000000 +#define AM_REG_RTC_RTCCTL_RPT_YEAR 0x00000002 +#define AM_REG_RTC_RTCCTL_RPT_MONTH 0x00000004 +#define AM_REG_RTC_RTCCTL_RPT_WEEK 0x00000006 +#define AM_REG_RTC_RTCCTL_RPT_DAY 0x00000008 +#define AM_REG_RTC_RTCCTL_RPT_HR 0x0000000A +#define AM_REG_RTC_RTCCTL_RPT_MIN 0x0000000C +#define AM_REG_RTC_RTCCTL_RPT_SEC 0x0000000E + +// Counter write control +#define AM_REG_RTC_RTCCTL_WRTC_S 0 +#define AM_REG_RTC_RTCCTL_WRTC_M 0x00000001 +#define AM_REG_RTC_RTCCTL_WRTC(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_RTC_RTCCTL_WRTC_DIS 0x00000000 +#define AM_REG_RTC_RTCCTL_WRTC_EN 0x00000001 + +#endif // AM_REG_RTC_H diff --git a/mcu/apollo2/regs/am_reg_sysctrl.h b/mcu/apollo2/regs/am_reg_sysctrl.h new file mode 100644 index 0000000..2b74d12 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_sysctrl.h @@ -0,0 +1,697 @@ +//***************************************************************************** +// +// am_reg_sysctrl.h +//! @file +//! +//! @brief Register macros for the SYSCTRL module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_SYSCTRL_H +#define AM_REG_SYSCTRL_H + +//***************************************************************************** +// +// SYSCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_SYSCTRL_NUM_MODULES 1 +#define AM_REG_SYSCTRLn(n) \ + (REG_SYSCTRL_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_SYSCTRL_ICTR_O 0xE000E004 +#define AM_REG_SYSCTRL_ACTLR_O 0xE000E008 +#define AM_REG_SYSCTRL_ICSR_O 0xE000ED04 +#define AM_REG_SYSCTRL_VTOR_O 0xE000ED08 +#define AM_REG_SYSCTRL_AIRCR_O 0xE000ED0C +#define AM_REG_SYSCTRL_SCR_O 0xE000ED10 +#define AM_REG_SYSCTRL_CCR_O 0xE000ED14 +#define AM_REG_SYSCTRL_SHPR1_O 0xE000ED18 +#define AM_REG_SYSCTRL_SHPR2_O 0xE000ED1C +#define AM_REG_SYSCTRL_SHPR3_O 0xE000ED20 +#define AM_REG_SYSCTRL_SHCSR_O 0xE000ED24 +#define AM_REG_SYSCTRL_CFSR_O 0xE000ED28 +#define AM_REG_SYSCTRL_HFSR_O 0xE000ED2C +#define AM_REG_SYSCTRL_MMFAR_O 0xE000ED34 +#define AM_REG_SYSCTRL_BFAR_O 0xE000ED38 +#define AM_REG_SYSCTRL_CPACR_O 0xE000ED88 +#define AM_REG_SYSCTRL_DEMCR_O 0xE000EDFC +#define AM_REG_SYSCTRL_STIR_O 0xE000EF00 +#define AM_REG_SYSCTRL_FPCCR_O 0xE000EF34 +#define AM_REG_SYSCTRL_FPCAR_O 0xE000EF38 +#define AM_REG_SYSCTRL_FPDSCR_O 0xE000EF3C + +//***************************************************************************** +// +// SYSCTRL_ICTR - Interrupt Controller Type Register (NVIC) +// +//***************************************************************************** +// Total number of interrupt lines in groups of 32. +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_S 0 +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_M 0x0000000F +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// SYSCTRL_ACTLR - Auxilliary Control Register +// +//***************************************************************************** +// Disables lazy stacking of floating point context. +#define AM_REG_SYSCTRL_ACTLR_DISFPCA_S 9 +#define AM_REG_SYSCTRL_ACTLR_DISFPCA_M 0x00000200 +#define AM_REG_SYSCTRL_ACTLR_DISFPCA(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Disables floating point instructions completing out of order with respect to +// integer instructions. +#define AM_REG_SYSCTRL_ACTLR_DISOOFP_S 8 +#define AM_REG_SYSCTRL_ACTLR_DISOOFP_M 0x00000100 +#define AM_REG_SYSCTRL_ACTLR_DISOOFP(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Disables folding of IT instructions. +#define AM_REG_SYSCTRL_ACTLR_DISFOLD_S 2 +#define AM_REG_SYSCTRL_ACTLR_DISFOLD_M 0x00000004 +#define AM_REG_SYSCTRL_ACTLR_DISFOLD(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Disables write buffer use during default memory map accesses. +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_S 1 +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_M 0x00000002 +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Disables interruption of multi-cycle instructions. +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_S 0 +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_M 0x00000001 +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSCTRL_ICSR - Interrupt Control and State Register +// +//***************************************************************************** +// Pend an NMI exception. +#define AM_REG_SYSCTRL_ICSR_NMIPENDSET_S 31 +#define AM_REG_SYSCTRL_ICSR_NMIPENDSET_M 0x80000000 +#define AM_REG_SYSCTRL_ICSR_NMIPENDSET(n) (((uint32_t)(n) << 31) & 0x80000000) + +// Set the PendSV interrupt as pending. +#define AM_REG_SYSCTRL_ICSR_PENDSVSET_S 28 +#define AM_REG_SYSCTRL_ICSR_PENDSVSET_M 0x10000000 +#define AM_REG_SYSCTRL_ICSR_PENDSVSET(n) (((uint32_t)(n) << 28) & 0x10000000) + +// Remove the pending status of the PendSV exception. +#define AM_REG_SYSCTRL_ICSR_PENDSVCLR_S 27 +#define AM_REG_SYSCTRL_ICSR_PENDSVCLR_M 0x08000000 +#define AM_REG_SYSCTRL_ICSR_PENDSVCLR(n) (((uint32_t)(n) << 27) & 0x08000000) + +// Set the SysTick exception as pending. +#define AM_REG_SYSCTRL_ICSR_PENDSTSET_S 26 +#define AM_REG_SYSCTRL_ICSR_PENDSTSET_M 0x04000000 +#define AM_REG_SYSCTRL_ICSR_PENDSTSET(n) (((uint32_t)(n) << 26) & 0x04000000) + +// Remove the pending status of the SysTick exception. +#define AM_REG_SYSCTRL_ICSR_PENDSTCLR_S 25 +#define AM_REG_SYSCTRL_ICSR_PENDSTCLR_M 0x02000000 +#define AM_REG_SYSCTRL_ICSR_PENDSTCLR(n) (((uint32_t)(n) << 25) & 0x02000000) + +// Indicates whether a pending exception will be serviced on exit from debug +// halt state. +#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_S 23 +#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT_M 0x00800000 +#define AM_REG_SYSCTRL_ICSR_ISRPREEMPT(n) (((uint32_t)(n) << 23) & 0x00800000) + +// Indicates whether an external interrupt, generated by the NVIC, is pending. +#define AM_REG_SYSCTRL_ICSR_ISRPENDING_S 22 +#define AM_REG_SYSCTRL_ICSR_ISRPENDING_M 0x00400000 +#define AM_REG_SYSCTRL_ICSR_ISRPENDING(n) (((uint32_t)(n) << 22) & 0x00400000) + +// The exception number of the highest priority pending exception. +#define AM_REG_SYSCTRL_ICSR_VECTPENDING_S 12 +#define AM_REG_SYSCTRL_ICSR_VECTPENDING_M 0x001FF000 +#define AM_REG_SYSCTRL_ICSR_VECTPENDING(n) (((uint32_t)(n) << 12) & 0x001FF000) + +// Indicates whether there is an active exception other than the exception shown +// by IPSR. +#define AM_REG_SYSCTRL_ICSR_RETTOBASE_S 11 +#define AM_REG_SYSCTRL_ICSR_RETTOBASE_M 0x00000800 +#define AM_REG_SYSCTRL_ICSR_RETTOBASE(n) (((uint32_t)(n) << 11) & 0x00000800) + +// The exception number of the current executing exception. +#define AM_REG_SYSCTRL_ICSR_VECTACTIVE_S 0 +#define AM_REG_SYSCTRL_ICSR_VECTACTIVE_M 0x000001FF +#define AM_REG_SYSCTRL_ICSR_VECTACTIVE(n) (((uint32_t)(n) << 0) & 0x000001FF) + +//***************************************************************************** +// +// SYSCTRL_VTOR - Vector Table Offset Register. +// +//***************************************************************************** +// Vector table base address. +#define AM_REG_SYSCTRL_VTOR_VALUE_S 0 +#define AM_REG_SYSCTRL_VTOR_VALUE_M 0xFFFFFFFF +#define AM_REG_SYSCTRL_VTOR_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// SYSCTRL_AIRCR - Application Interrupt and Reset Control Register. +// +//***************************************************************************** +// Register writes must write 0x5FA to this field, otherwise the write is +// ignored. +#define AM_REG_SYSCTRL_AIRCR_VECTKEY_S 16 +#define AM_REG_SYSCTRL_AIRCR_VECTKEY_M 0xFFFF0000 +#define AM_REG_SYSCTRL_AIRCR_VECTKEY(n) (((uint32_t)(n) << 16) & 0xFFFF0000) + +// Indicates endianness of memory architecture. (Little = 0, Big = 1) +#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_S 15 +#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS_M 0x00008000 +#define AM_REG_SYSCTRL_AIRCR_ENDIANNESS(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Priority grouping, indicates the binary point position. +#define AM_REG_SYSCTRL_AIRCR_PRIGROUP_S 8 +#define AM_REG_SYSCTRL_AIRCR_PRIGROUP_M 0x00000700 +#define AM_REG_SYSCTRL_AIRCR_PRIGROUP(n) (((uint32_t)(n) << 8) & 0x00000700) + +// Writing a 1 to this bit reqests a local reset. +#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_S 2 +#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ_M 0x00000004 +#define AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Writing a 1 to this bit clears all active state information for fixed and +// configurable exceptions. +#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_S 1 +#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define AM_REG_SYSCTRL_AIRCR_VECTCLRACTIVE(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Writing a 1 to this bit causes a local system reset. +#define AM_REG_SYSCTRL_AIRCR_VECTRESET_S 0 +#define AM_REG_SYSCTRL_AIRCR_VECTRESET_M 0x00000001 +#define AM_REG_SYSCTRL_AIRCR_VECTRESET(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSCTRL_SCR - System Control Register. +// +//***************************************************************************** +// Determines whether a pending interrupt is a wakeup event. +#define AM_REG_SYSCTRL_SCR_SEVONPEND_S 4 +#define AM_REG_SYSCTRL_SCR_SEVONPEND_M 0x00000010 +#define AM_REG_SYSCTRL_SCR_SEVONPEND(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Determines whether the sleep mode should be regular or deep sleep +#define AM_REG_SYSCTRL_SCR_SLEEPDEEP_S 2 +#define AM_REG_SYSCTRL_SCR_SLEEPDEEP_M 0x00000004 +#define AM_REG_SYSCTRL_SCR_SLEEPDEEP(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Determines whether the processor shoudl automatically sleep when an ISR +// returns to the base-level. +#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_S 1 +#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT_M 0x00000002 +#define AM_REG_SYSCTRL_SCR_SLEEPONEXIT(n) (((uint32_t)(n) << 1) & 0x00000002) + +//***************************************************************************** +// +// SYSCTRL_CCR - Configuration and Control Register. +// +//***************************************************************************** +// Set to force 8-byte alignment for the stack pointer. +#define AM_REG_SYSCTRL_CCR_STKALIGN_S 9 +#define AM_REG_SYSCTRL_CCR_STKALIGN_M 0x00000200 +#define AM_REG_SYSCTRL_CCR_STKALIGN(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Set to ignore precise data access faults during hard fault handlers. +#define AM_REG_SYSCTRL_CCR_BFHFNMIGN_S 8 +#define AM_REG_SYSCTRL_CCR_BFHFNMIGN_M 0x00000100 +#define AM_REG_SYSCTRL_CCR_BFHFNMIGN(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Set to enable trapping on divide-by-zero. +#define AM_REG_SYSCTRL_CCR_DIV0TRP_S 4 +#define AM_REG_SYSCTRL_CCR_DIV0TRP_M 0x00000010 +#define AM_REG_SYSCTRL_CCR_DIV0TRP(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Set to enable trapping of unaligned word or halfword accesses. +#define AM_REG_SYSCTRL_CCR_UNALIGNTRP_S 3 +#define AM_REG_SYSCTRL_CCR_UNALIGNTRP_M 0x00000008 +#define AM_REG_SYSCTRL_CCR_UNALIGNTRP(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Set to allow unpriveleged software to access the STIR +#define AM_REG_SYSCTRL_CCR_USERSETMPEND_S 1 +#define AM_REG_SYSCTRL_CCR_USERSETMPEND_M 0x00000002 +#define AM_REG_SYSCTRL_CCR_USERSETMPEND(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Set to enable the processor to enter Thread mode at an execution priority +// other than base level. +#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_S 0 +#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA_M 0x00000001 +#define AM_REG_SYSCTRL_CCR_NONBASETHRDENA(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSCTRL_SHPR1 - System Handler Priority Register 1. +// +//***************************************************************************** +// Reserved for priority of system handler 7. +#define AM_REG_SYSCTRL_SHPR1_PRI_7_S 24 +#define AM_REG_SYSCTRL_SHPR1_PRI_7_M 0xFF000000 +#define AM_REG_SYSCTRL_SHPR1_PRI_7(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority of system handler 6, UsageFault. +#define AM_REG_SYSCTRL_SHPR1_PRI_6_S 16 +#define AM_REG_SYSCTRL_SHPR1_PRI_6_M 0x00FF0000 +#define AM_REG_SYSCTRL_SHPR1_PRI_6(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Priority of system handler 5, BusFault. +#define AM_REG_SYSCTRL_SHPR1_PRI_5_S 8 +#define AM_REG_SYSCTRL_SHPR1_PRI_5_M 0x0000FF00 +#define AM_REG_SYSCTRL_SHPR1_PRI_5(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority of system handler 4, MemManage. +#define AM_REG_SYSCTRL_SHPR1_PRI_4_S 0 +#define AM_REG_SYSCTRL_SHPR1_PRI_4_M 0x000000FF +#define AM_REG_SYSCTRL_SHPR1_PRI_4(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// SYSCTRL_SHPR2 - System Handler Priority Register 2. +// +//***************************************************************************** +// Priority of system handler 11, SVCall. +#define AM_REG_SYSCTRL_SHPR2_PRI_11_S 24 +#define AM_REG_SYSCTRL_SHPR2_PRI_11_M 0xFF000000 +#define AM_REG_SYSCTRL_SHPR2_PRI_11(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Reserved for priority of system handler 10. +#define AM_REG_SYSCTRL_SHPR2_PRI_10_S 16 +#define AM_REG_SYSCTRL_SHPR2_PRI_10_M 0x00FF0000 +#define AM_REG_SYSCTRL_SHPR2_PRI_10(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Reserved for priority of system handler 9. +#define AM_REG_SYSCTRL_SHPR2_PRI_9_S 8 +#define AM_REG_SYSCTRL_SHPR2_PRI_9_M 0x0000FF00 +#define AM_REG_SYSCTRL_SHPR2_PRI_9(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Reserved for priority of system handler 8. +#define AM_REG_SYSCTRL_SHPR2_PRI_8_S 0 +#define AM_REG_SYSCTRL_SHPR2_PRI_8_M 0x000000FF +#define AM_REG_SYSCTRL_SHPR2_PRI_8(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// SYSCTRL_SHPR3 - System Handler Priority Register 3. +// +//***************************************************************************** +// Priority of system handler 15, SysTick. +#define AM_REG_SYSCTRL_SHPR3_PRI_15_S 24 +#define AM_REG_SYSCTRL_SHPR3_PRI_15_M 0xFF000000 +#define AM_REG_SYSCTRL_SHPR3_PRI_15(n) (((uint32_t)(n) << 24) & 0xFF000000) + +// Priority of system handler 14, PendSV. +#define AM_REG_SYSCTRL_SHPR3_PRI_14_S 16 +#define AM_REG_SYSCTRL_SHPR3_PRI_14_M 0x00FF0000 +#define AM_REG_SYSCTRL_SHPR3_PRI_14(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// Reserved for priority of system handler 13. +#define AM_REG_SYSCTRL_SHPR3_PRI_13_S 8 +#define AM_REG_SYSCTRL_SHPR3_PRI_13_M 0x0000FF00 +#define AM_REG_SYSCTRL_SHPR3_PRI_13(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// Priority of system handler 12, DebugMonitor. +#define AM_REG_SYSCTRL_SHPR3_PRI_12_S 0 +#define AM_REG_SYSCTRL_SHPR3_PRI_12_M 0x000000FF +#define AM_REG_SYSCTRL_SHPR3_PRI_12(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// SYSCTRL_SHCSR - System Handler Control and State Register. +// +//***************************************************************************** +// Set to enable UsageFault. +#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_S 18 +#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA_M 0x00040000 +#define AM_REG_SYSCTRL_SHCSR_USAGEFAULTENA(n) (((uint32_t)(n) << 18) & 0x00040000) + +// Set to enable BusFault. +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_S 17 +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA_M 0x00020000 +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTENA(n) (((uint32_t)(n) << 17) & 0x00020000) + +// Set to enable MemManageFault. +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_S 16 +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA_M 0x00010000 +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTENA(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Set to pend the SVCall exception. +#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_S 15 +#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED_M 0x00008000 +#define AM_REG_SYSCTRL_SHCSR_SVCALLPENDED(n) (((uint32_t)(n) << 15) & 0x00008000) + +// Set to pend the BusFault exception. +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_S 14 +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTPENDED(n) (((uint32_t)(n) << 14) & 0x00004000) + +// Set to pend the MemManageFault exception. +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_S 13 +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTPENDED(n) (((uint32_t)(n) << 13) & 0x00002000) + +// Set to pend the UsageFault exception. +#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_S 12 +#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED_M 0x00001000 +#define AM_REG_SYSCTRL_SHCSR_USGFAULTPENDED(n) (((uint32_t)(n) << 12) & 0x00001000) + +// Set when SysTick is active. +#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_S 11 +#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT_M 0x00000800 +#define AM_REG_SYSCTRL_SHCSR_SYSTICKACT(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Set when PendSV is active. +#define AM_REG_SYSCTRL_SHCSR_PENDSVACT_S 10 +#define AM_REG_SYSCTRL_SHCSR_PENDSVACT_M 0x00000400 +#define AM_REG_SYSCTRL_SHCSR_PENDSVACT(n) (((uint32_t)(n) << 10) & 0x00000400) + +// Set when Monitor is active. +#define AM_REG_SYSCTRL_SHCSR_MONITORACT_S 8 +#define AM_REG_SYSCTRL_SHCSR_MONITORACT_M 0x00000100 +#define AM_REG_SYSCTRL_SHCSR_MONITORACT(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Set when SVCall is active. +#define AM_REG_SYSCTRL_SHCSR_SVCALLACT_S 7 +#define AM_REG_SYSCTRL_SHCSR_SVCALLACT_M 0x00000080 +#define AM_REG_SYSCTRL_SHCSR_SVCALLACT(n) (((uint32_t)(n) << 7) & 0x00000080) + +// Set when UsageFault is active. +#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_S 3 +#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT_M 0x00000008 +#define AM_REG_SYSCTRL_SHCSR_USGFAULTACT(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Set when BusFault is active. +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_S 1 +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT_M 0x00000002 +#define AM_REG_SYSCTRL_SHCSR_BUSFAULTACT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Set when MemManageFault is active. +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_S 0 +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT_M 0x00000001 +#define AM_REG_SYSCTRL_SHCSR_MEMFAULTACT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSCTRL_CFSR - Configurable Fault Status Register. +// +//***************************************************************************** +// Divide by zero error has occurred. +#define AM_REG_SYSCTRL_CFSR_DIVBYZERO_S 25 +#define AM_REG_SYSCTRL_CFSR_DIVBYZERO_M 0x02000000 +#define AM_REG_SYSCTRL_CFSR_DIVBYZERO(n) (((uint32_t)(n) << 25) & 0x02000000) + +// Unaligned access error has occurred. +#define AM_REG_SYSCTRL_CFSR_UNALIGNED_S 24 +#define AM_REG_SYSCTRL_CFSR_UNALIGNED_M 0x01000000 +#define AM_REG_SYSCTRL_CFSR_UNALIGNED(n) (((uint32_t)(n) << 24) & 0x01000000) + +// A coprocessor access error has occurred. +#define AM_REG_SYSCTRL_CFSR_NOCP_S 19 +#define AM_REG_SYSCTRL_CFSR_NOCP_M 0x00080000 +#define AM_REG_SYSCTRL_CFSR_NOCP(n) (((uint32_t)(n) << 19) & 0x00080000) + +// An integrity check error has occurred on EXC_RETURN. +#define AM_REG_SYSCTRL_CFSR_INVPC_S 18 +#define AM_REG_SYSCTRL_CFSR_INVPC_M 0x00040000 +#define AM_REG_SYSCTRL_CFSR_INVPC(n) (((uint32_t)(n) << 18) & 0x00040000) + +// Instruction executed with invalid EPSR.T or EPSR.IT field. +#define AM_REG_SYSCTRL_CFSR_INVSTATE_S 17 +#define AM_REG_SYSCTRL_CFSR_INVSTATE_M 0x00020000 +#define AM_REG_SYSCTRL_CFSR_INVSTATE(n) (((uint32_t)(n) << 17) & 0x00020000) + +// Processor attempted to execute an undefined instruction. +#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_S 16 +#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR_M 0x00010000 +#define AM_REG_SYSCTRL_CFSR_UNDEFINSTR(n) (((uint32_t)(n) << 16) & 0x00010000) + +// BFAR has valid contents. +#define AM_REG_SYSCTRL_CFSR_BFARVALID_S 15 +#define AM_REG_SYSCTRL_CFSR_BFARVALID_M 0x00008000 +#define AM_REG_SYSCTRL_CFSR_BFARVALID(n) (((uint32_t)(n) << 15) & 0x00008000) + +// A bus fault occurred during FP lazy state preservation. +#define AM_REG_SYSCTRL_CFSR_LSPERR_S 13 +#define AM_REG_SYSCTRL_CFSR_LSPERR_M 0x00002000 +#define AM_REG_SYSCTRL_CFSR_LSPERR(n) (((uint32_t)(n) << 13) & 0x00002000) + +// A derived bus fault has occurred on exception entry. +#define AM_REG_SYSCTRL_CFSR_STKERR_S 12 +#define AM_REG_SYSCTRL_CFSR_STKERR_M 0x00001000 +#define AM_REG_SYSCTRL_CFSR_STKERR(n) (((uint32_t)(n) << 12) & 0x00001000) + +// A derived bus fault has occurred on exception return. +#define AM_REG_SYSCTRL_CFSR_UNSTKERR_S 11 +#define AM_REG_SYSCTRL_CFSR_UNSTKERR_M 0x00000800 +#define AM_REG_SYSCTRL_CFSR_UNSTKERR(n) (((uint32_t)(n) << 11) & 0x00000800) + +// Imprecise data access error has occurred. +#define AM_REG_SYSCTRL_CFSR_IMPRECISERR_S 10 +#define AM_REG_SYSCTRL_CFSR_IMPRECISERR_M 0x00000400 +#define AM_REG_SYSCTRL_CFSR_IMPRECISERR(n) (((uint32_t)(n) << 10) & 0x00000400) + +// A precise data access has occurrred. The faulting address is in BFAR. +#define AM_REG_SYSCTRL_CFSR_PRECISERR_S 9 +#define AM_REG_SYSCTRL_CFSR_PRECISERR_M 0x00000200 +#define AM_REG_SYSCTRL_CFSR_PRECISERR(n) (((uint32_t)(n) << 9) & 0x00000200) + +// A bus fault on an instruction prefetch has occurred. +#define AM_REG_SYSCTRL_CFSR_IBUSERR_S 8 +#define AM_REG_SYSCTRL_CFSR_IBUSERR_M 0x00000100 +#define AM_REG_SYSCTRL_CFSR_IBUSERR(n) (((uint32_t)(n) << 8) & 0x00000100) + +// MMAR has valid contents. +#define AM_REG_SYSCTRL_CFSR_MMARVALID_S 7 +#define AM_REG_SYSCTRL_CFSR_MMARVALID_M 0x00000080 +#define AM_REG_SYSCTRL_CFSR_MMARVALID(n) (((uint32_t)(n) << 7) & 0x00000080) + +// MemManage fault occurred during FP lazy state preservation. +#define AM_REG_SYSCTRL_CFSR_MLSPERR_S 5 +#define AM_REG_SYSCTRL_CFSR_MLSPERR_M 0x00000020 +#define AM_REG_SYSCTRL_CFSR_MLSPERR(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Derived MemManage fault occurred on exception entry. +#define AM_REG_SYSCTRL_CFSR_MSTKERR_S 4 +#define AM_REG_SYSCTRL_CFSR_MSTKERR_M 0x00000010 +#define AM_REG_SYSCTRL_CFSR_MSTKERR(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Derived MemManage fault occurred on exception return. +#define AM_REG_SYSCTRL_CFSR_MUNSTKER_S 3 +#define AM_REG_SYSCTRL_CFSR_MUNSTKER_M 0x00000008 +#define AM_REG_SYSCTRL_CFSR_MUNSTKER(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Data access violation. Address is in MMAR. +#define AM_REG_SYSCTRL_CFSR_DACCVIOL_S 1 +#define AM_REG_SYSCTRL_CFSR_DACCVIOL_M 0x00000002 +#define AM_REG_SYSCTRL_CFSR_DACCVIOL(n) (((uint32_t)(n) << 1) & 0x00000002) + +// MPU or Execute Never default memory map access violation. +#define AM_REG_SYSCTRL_CFSR_IACCVIOL_S 0 +#define AM_REG_SYSCTRL_CFSR_IACCVIOL_M 0x00000001 +#define AM_REG_SYSCTRL_CFSR_IACCVIOL(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSCTRL_HFSR - Hard Fault Status Register. +// +//***************************************************************************** +// Debug event has occurred. +#define AM_REG_SYSCTRL_HFSR_DEBUGEVT_S 31 +#define AM_REG_SYSCTRL_HFSR_DEBUGEVT_M 0x80000000 +#define AM_REG_SYSCTRL_HFSR_DEBUGEVT(n) (((uint32_t)(n) << 31) & 0x80000000) + +// Processor has elevated a configurable-priority fault to a HardFault. +#define AM_REG_SYSCTRL_HFSR_FORCED_S 30 +#define AM_REG_SYSCTRL_HFSR_FORCED_M 0x40000000 +#define AM_REG_SYSCTRL_HFSR_FORCED(n) (((uint32_t)(n) << 30) & 0x40000000) + +// Vector table read fault has occurred. +#define AM_REG_SYSCTRL_HFSR_VECTTBL_S 1 +#define AM_REG_SYSCTRL_HFSR_VECTTBL_M 0x00000002 +#define AM_REG_SYSCTRL_HFSR_VECTTBL(n) (((uint32_t)(n) << 1) & 0x00000002) + +//***************************************************************************** +// +// SYSCTRL_MMFAR - MemManage Fault Address Register. +// +//***************************************************************************** +// Address of the memory location that caused an MMU fault. +#define AM_REG_SYSCTRL_MMFAR_ADDRESS_S 0 +#define AM_REG_SYSCTRL_MMFAR_ADDRESS_M 0xFFFFFFFF +#define AM_REG_SYSCTRL_MMFAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// SYSCTRL_BFAR - Bus Fault Address Register. +// +//***************************************************************************** +// Address of the memory location that caused an Bus fault. +#define AM_REG_SYSCTRL_BFAR_ADDRESS_S 0 +#define AM_REG_SYSCTRL_BFAR_ADDRESS_M 0xFFFFFFFF +#define AM_REG_SYSCTRL_BFAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// SYSCTRL_CPACR - Coprocessor Access Control Register. +// +//***************************************************************************** +// Access priveleges for the Floating point unit. Must always match CP10. +#define AM_REG_SYSCTRL_CPACR_CP11_S 22 +#define AM_REG_SYSCTRL_CPACR_CP11_M 0x00C00000 +#define AM_REG_SYSCTRL_CPACR_CP11(n) (((uint32_t)(n) << 22) & 0x00C00000) + +// Access priveleges for the Floating point unit. Must always match CP11. +#define AM_REG_SYSCTRL_CPACR_CP10_S 20 +#define AM_REG_SYSCTRL_CPACR_CP10_M 0x00300000 +#define AM_REG_SYSCTRL_CPACR_CP10(n) (((uint32_t)(n) << 20) & 0x00300000) + +//***************************************************************************** +// +// SYSCTRL_DEMCR - Debug Exception and Monitor Control Register +// +//***************************************************************************** +// Global enable for all DWT and ITM features. +#define AM_REG_SYSCTRL_DEMCR_TRCENA_S 24 +#define AM_REG_SYSCTRL_DEMCR_TRCENA_M 0x01000000 +#define AM_REG_SYSCTRL_DEMCR_TRCENA(n) (((uint32_t)(n) << 24) & 0x01000000) + +//***************************************************************************** +// +// SYSCTRL_STIR - Software Triggered Interrupt Register +// +//***************************************************************************** +// Vector number of the interrupt that should be triggered. +#define AM_REG_SYSCTRL_STIR_INTID_S 0 +#define AM_REG_SYSCTRL_STIR_INTID_M 0xFFFFFFFF +#define AM_REG_SYSCTRL_STIR_INTID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// SYSCTRL_FPCCR - Floating-Point Context Control Register. +// +//***************************************************************************** +// Set to enable automatic saving of FP registers on exception entry. +#define AM_REG_SYSCTRL_FPCCR_ASPEN_S 31 +#define AM_REG_SYSCTRL_FPCCR_ASPEN_M 0x80000000 +#define AM_REG_SYSCTRL_FPCCR_ASPEN(n) (((uint32_t)(n) << 31) & 0x80000000) + +// Set to enable lazy context saving of FP registers on exception entry. +#define AM_REG_SYSCTRL_FPCCR_LSPEN_S 30 +#define AM_REG_SYSCTRL_FPCCR_LSPEN_M 0x40000000 +#define AM_REG_SYSCTRL_FPCCR_LSPEN(n) (((uint32_t)(n) << 30) & 0x40000000) + +// Able to set DebugMonitor exception to pending on last FP stack allocation. +#define AM_REG_SYSCTRL_FPCCR_MONRDY_S 8 +#define AM_REG_SYSCTRL_FPCCR_MONRDY_M 0x00000100 +#define AM_REG_SYSCTRL_FPCCR_MONRDY(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Able to set BusFault exception to pending on last FP stack allocation. +#define AM_REG_SYSCTRL_FPCCR_BFRDY_S 6 +#define AM_REG_SYSCTRL_FPCCR_BFRDY_M 0x00000040 +#define AM_REG_SYSCTRL_FPCCR_BFRDY(n) (((uint32_t)(n) << 6) & 0x00000040) + +// Able to set MemManage exception to pending on last FP stack allocation. +#define AM_REG_SYSCTRL_FPCCR_MMRDY_S 5 +#define AM_REG_SYSCTRL_FPCCR_MMRDY_M 0x00000020 +#define AM_REG_SYSCTRL_FPCCR_MMRDY(n) (((uint32_t)(n) << 5) & 0x00000020) + +// Able to set HardFault exception to pending on last FP stack allocation. +#define AM_REG_SYSCTRL_FPCCR_HFRDY_S 4 +#define AM_REG_SYSCTRL_FPCCR_HFRDY_M 0x00000010 +#define AM_REG_SYSCTRL_FPCCR_HFRDY(n) (((uint32_t)(n) << 4) & 0x00000010) + +// Running from Thread mode on last FP stack allocation. +#define AM_REG_SYSCTRL_FPCCR_THREAD_S 3 +#define AM_REG_SYSCTRL_FPCCR_THREAD_M 0x00000008 +#define AM_REG_SYSCTRL_FPCCR_THREAD(n) (((uint32_t)(n) << 3) & 0x00000008) + +// Running from unprivileged mode on last FP stack allocation. +#define AM_REG_SYSCTRL_FPCCR_USER_S 1 +#define AM_REG_SYSCTRL_FPCCR_USER_M 0x00000002 +#define AM_REG_SYSCTRL_FPCCR_USER(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Lazy state preservation is active. +#define AM_REG_SYSCTRL_FPCCR_LSPACT_S 0 +#define AM_REG_SYSCTRL_FPCCR_LSPACT_M 0x00000001 +#define AM_REG_SYSCTRL_FPCCR_LSPACT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSCTRL_FPCAR - Floating-Point Context Address Register. +// +//***************************************************************************** +// Address of the unpopulated floating-point register space allocated on the +// exception stack frame. +#define AM_REG_SYSCTRL_FPCAR_ADDRESS_S 0 +#define AM_REG_SYSCTRL_FPCAR_ADDRESS_M 0xFFFFFFFF +#define AM_REG_SYSCTRL_FPCAR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) + +//***************************************************************************** +// +// SYSCTRL_FPDSCR - Floating-Point Default Status Control Register. +// +//***************************************************************************** +// Default value for FPSCR.AHP. +#define AM_REG_SYSCTRL_FPDSCR_AHP_S 26 +#define AM_REG_SYSCTRL_FPDSCR_AHP_M 0x04000000 +#define AM_REG_SYSCTRL_FPDSCR_AHP(n) (((uint32_t)(n) << 26) & 0x04000000) + +// Default value for FPSCR.DN. +#define AM_REG_SYSCTRL_FPDSCR_DN_S 25 +#define AM_REG_SYSCTRL_FPDSCR_DN_M 0x02000000 +#define AM_REG_SYSCTRL_FPDSCR_DN(n) (((uint32_t)(n) << 25) & 0x02000000) + +// Default value for FPSCR.FZ. +#define AM_REG_SYSCTRL_FPDSCR_FZ_S 24 +#define AM_REG_SYSCTRL_FPDSCR_FZ_M 0x01000000 +#define AM_REG_SYSCTRL_FPDSCR_FZ(n) (((uint32_t)(n) << 24) & 0x01000000) + +// Default value for FPSCR.RMode. +#define AM_REG_SYSCTRL_FPDSCR_RMODE_S 22 +#define AM_REG_SYSCTRL_FPDSCR_RMODE_M 0x00C00000 +#define AM_REG_SYSCTRL_FPDSCR_RMODE(n) (((uint32_t)(n) << 22) & 0x00C00000) + +#endif // AM_REG_SYSCTRL_H diff --git a/mcu/apollo2/regs/am_reg_systick.h b/mcu/apollo2/regs/am_reg_systick.h new file mode 100644 index 0000000..b2b8c6c --- /dev/null +++ b/mcu/apollo2/regs/am_reg_systick.h @@ -0,0 +1,138 @@ +//***************************************************************************** +// +// am_reg_systick.h +//! @file +//! +//! @brief Register macros for the SYSTICK module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_SYSTICK_H +#define AM_REG_SYSTICK_H + +//***************************************************************************** +// +// SYSTICK +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_SYSTICK_NUM_MODULES 1 +#define AM_REG_SYSTICKn(n) \ + (REG_SYSTICK_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_SYSTICK_SYSTCSR_O 0xE000E010 +#define AM_REG_SYSTICK_SYSTRVR_O 0xE000E014 +#define AM_REG_SYSTICK_SYSTCVR_O 0xE000E018 +#define AM_REG_SYSTICK_SYSTCALIB_O 0xE000E01C + +//***************************************************************************** +// +// SYSTICK_SYSTCSR - SysTick Control and Status Register. +// +//***************************************************************************** +// Returns 1 if timer counted to 0 since last time this was read. +#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_S 16 +#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG_M 0x00010000 +#define AM_REG_SYSTICK_SYSTCSR_COUNTFLAG(n) (((uint32_t)(n) << 16) & 0x00010000) + +// Enables SysTick exception request. Software can use COUNTFLAG to determine if +// SysTick has ever counted to zero. 0 = counting down to zero does not assert +// the SysTick exception request; 1 = counting down to zero asserts the SysTick +// exception request. +#define AM_REG_SYSTICK_SYSTCSR_TICKINT_S 1 +#define AM_REG_SYSTICK_SYSTCSR_TICKINT_M 0x00000002 +#define AM_REG_SYSTICK_SYSTCSR_TICKINT(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Enables the counter. 0 = counter disabled; 1 = counter enabled. +#define AM_REG_SYSTICK_SYSTCSR_ENABLE_S 0 +#define AM_REG_SYSTICK_SYSTCSR_ENABLE_M 0x00000001 +#define AM_REG_SYSTICK_SYSTCSR_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// SYSTICK_SYSTRVR - SysTick Reload Value Register. +// +//***************************************************************************** +// Value to load into the SYSTCVR register when the counter is enabled and when +// it reaches 0. +#define AM_REG_SYSTICK_SYSTRVR_RELOAD_S 0 +#define AM_REG_SYSTICK_SYSTRVR_RELOAD_M 0x00FFFFFF +#define AM_REG_SYSTICK_SYSTRVR_RELOAD(n) (((uint32_t)(n) << 0) & 0x00FFFFFF) + +//***************************************************************************** +// +// SYSTICK_SYSTCVR - SysTick Current Value Register. +// +//***************************************************************************** +// Reads return the current value of the SysTick counter. A write of any value +// clears the field to 0, and also clears the SYSTCSR COUNTFLAG bit to 0. +#define AM_REG_SYSTICK_SYSTCVR_CURRENT_S 0 +#define AM_REG_SYSTICK_SYSTCVR_CURRENT_M 0x00FFFFFF +#define AM_REG_SYSTICK_SYSTCVR_CURRENT(n) (((uint32_t)(n) << 0) & 0x00FFFFFF) + +//***************************************************************************** +// +// SYSTICK_SYSTCALIB - SysTick Calibration Value Register. +// +//***************************************************************************** +// Indicates whether the device provides a reference clock to the processor. 0 = +// reference clock provided; 1 = no reference clock provided. If your device +// does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one +// and ignores writes. +#define AM_REG_SYSTICK_SYSTCALIB_NOREF_S 31 +#define AM_REG_SYSTICK_SYSTCALIB_NOREF_M 0x80000000 +#define AM_REG_SYSTICK_SYSTCALIB_NOREF(n) (((uint32_t)(n) << 31) & 0x80000000) + +// Indicates whether the TENMS value is exact. 0 = TENMS value is exact; 1 = +// TENMS value is inexact, or not given. An inexact TENMS value can affect the +// suitability of SysTick as a software real time clock. +#define AM_REG_SYSTICK_SYSTCALIB_SKEW_S 30 +#define AM_REG_SYSTICK_SYSTCALIB_SKEW_M 0x40000000 +#define AM_REG_SYSTICK_SYSTCALIB_SKEW(n) (((uint32_t)(n) << 30) & 0x40000000) + +// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If +// the value reads as zero, the calibration value is not known. +#define AM_REG_SYSTICK_SYSTCALIB_TENMS_S 0 +#define AM_REG_SYSTICK_SYSTCALIB_TENMS_M 0x00FFFFFF +#define AM_REG_SYSTICK_SYSTCALIB_TENMS(n) (((uint32_t)(n) << 0) & 0x00FFFFFF) + +#endif // AM_REG_SYSTICK_H diff --git a/mcu/apollo2/regs/am_reg_tpiu.h b/mcu/apollo2/regs/am_reg_tpiu.h new file mode 100644 index 0000000..f8becb9 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_tpiu.h @@ -0,0 +1,165 @@ +//***************************************************************************** +// +// am_reg_tpiu.h +//! @file +//! +//! @brief Register macros for the TPIU module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_TPIU_H +#define AM_REG_TPIU_H + +//***************************************************************************** +// +// TPIU +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_TPIU_NUM_MODULES 1 +#define AM_REG_TPIUn(n) \ + (REG_TPIU_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_TPIU_SSPSR_O 0xE0040000 +#define AM_REG_TPIU_CSPSR_O 0xE0040004 +#define AM_REG_TPIU_ACPR_O 0xE0040010 +#define AM_REG_TPIU_SPPR_O 0xE00400F0 +#define AM_REG_TPIU_FFCR_O 0xE0040304 +#define AM_REG_TPIU_ITCTRL_O 0xE0040F00 +#define AM_REG_TPIU_TYPE_O 0xE0040FC8 + +//***************************************************************************** +// +// TPIU_SSPSR - Supported Parallel Port Sizes. +// +//***************************************************************************** +// Parallel Port Width 1 supported +#define AM_REG_TPIU_SSPSR_SWIDTH0_S 0 +#define AM_REG_TPIU_SSPSR_SWIDTH0_M 0x00000001 +#define AM_REG_TPIU_SSPSR_SWIDTH0(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// TPIU_CSPSR - Current Parallel Port Size. +// +//***************************************************************************** +// One-hot representation of the current port width. +#define AM_REG_TPIU_CSPSR_CWIDTH_S 0 +#define AM_REG_TPIU_CSPSR_CWIDTH_M 0xFFFFFFFF +#define AM_REG_TPIU_CSPSR_CWIDTH(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) +#define AM_REG_TPIU_CSPSR_CWIDTH_1BIT 0x00000001 + +//***************************************************************************** +// +// TPIU_ACPR - Asynchronous Clock Prescaler. +// +//***************************************************************************** +// Prescaler value for the baudrate of SWO. +#define AM_REG_TPIU_ACPR_SWOSCALER_S 0 +#define AM_REG_TPIU_ACPR_SWOSCALER_M 0x0000FFFF +#define AM_REG_TPIU_ACPR_SWOSCALER(n) (((uint32_t)(n) << 0) & 0x0000FFFF) +#define AM_REG_TPIU_ACPR_SWOSCALER_115200 0x00000033 + +//***************************************************************************** +// +// TPIU_SPPR - Selected Pin Protocol. +// +//***************************************************************************** +// Selects the protocol used for trace output. +#define AM_REG_TPIU_SPPR_TXMODE_S 0 +#define AM_REG_TPIU_SPPR_TXMODE_M 0x00000003 +#define AM_REG_TPIU_SPPR_TXMODE(n) (((uint32_t)(n) << 0) & 0x00000003) +#define AM_REG_TPIU_SPPR_TXMODE_PARALLEL 0x00000000 +#define AM_REG_TPIU_SPPR_TXMODE_MANCHESTER 0x00000001 +#define AM_REG_TPIU_SPPR_TXMODE_NRZ 0x00000002 +#define AM_REG_TPIU_SPPR_TXMODE_UART 0x00000002 + +//***************************************************************************** +// +// TPIU_FFCR - Formatter and Flush Control Register. +// +//***************************************************************************** +// Enable continuous formatting. +#define AM_REG_TPIU_FFCR_ENFCONT_S 1 +#define AM_REG_TPIU_FFCR_ENFCONT_M 0x00000002 +#define AM_REG_TPIU_FFCR_ENFCONT(n) (((uint32_t)(n) << 1) & 0x00000002) + +//***************************************************************************** +// +// TPIU_ITCTRL - Specifies normal or integration mode for the TPIU. +// +//***************************************************************************** +// Specifies the current mode for the TPIU. +#define AM_REG_TPIU_ITCTRL_MODE_S 0 +#define AM_REG_TPIU_ITCTRL_MODE_M 0x00000003 +#define AM_REG_TPIU_ITCTRL_MODE(n) (((uint32_t)(n) << 0) & 0x00000003) +#define AM_REG_TPIU_ITCTRL_MODE_NORMAL 0x00000000 +#define AM_REG_TPIU_ITCTRL_MODE_TEST 0x00000001 +#define AM_REG_TPIU_ITCTRL_MODE_DATA_TEST 0x00000002 + +//***************************************************************************** +// +// TPIU_TYPE - TPIU Type. +// +//***************************************************************************** +// 1 Indicates UART/NRZ support. +#define AM_REG_TPIU_TYPE_NRZVALID_S 11 +#define AM_REG_TPIU_TYPE_NRZVALID_M 0x00000800 +#define AM_REG_TPIU_TYPE_NRZVALID(n) (((uint32_t)(n) << 11) & 0x00000800) + +// 1 Indicates Manchester support. +#define AM_REG_TPIU_TYPE_MANCVALID_S 10 +#define AM_REG_TPIU_TYPE_MANCVALID_M 0x00000400 +#define AM_REG_TPIU_TYPE_MANCVALID(n) (((uint32_t)(n) << 10) & 0x00000400) + +// 0 Indicates Parallel Trace support. +#define AM_REG_TPIU_TYPE_PTINVALID_S 9 +#define AM_REG_TPIU_TYPE_PTINVALID_M 0x00000200 +#define AM_REG_TPIU_TYPE_PTINVALID(n) (((uint32_t)(n) << 9) & 0x00000200) + +// FIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size +// of 8 bytes. +#define AM_REG_TPIU_TYPE_FIFOSZ_S 6 +#define AM_REG_TPIU_TYPE_FIFOSZ_M 0x000001C0 +#define AM_REG_TPIU_TYPE_FIFOSZ(n) (((uint32_t)(n) << 6) & 0x000001C0) + +#endif // AM_REG_TPIU_H diff --git a/mcu/apollo2/regs/am_reg_uart.h b/mcu/apollo2/regs/am_reg_uart.h new file mode 100644 index 0000000..2ab9863 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_uart.h @@ -0,0 +1,613 @@ +//***************************************************************************** +// +// am_reg_uart.h +//! @file +//! +//! @brief Register macros for the UART module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_UART_H +#define AM_REG_UART_H + +//***************************************************************************** +// +// UART +// Instance finder. (2 instance(s) available) +// +//***************************************************************************** +#define AM_REG_UART_NUM_MODULES 2 +#define AM_REG_UARTn(n) \ + (REG_UART_BASEADDR + 0x00001000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_UART_DR_O 0x00000000 +#define AM_REG_UART_RSR_O 0x00000004 +#define AM_REG_UART_FR_O 0x00000018 +#define AM_REG_UART_ILPR_O 0x00000020 +#define AM_REG_UART_IBRD_O 0x00000024 +#define AM_REG_UART_FBRD_O 0x00000028 +#define AM_REG_UART_LCRH_O 0x0000002C +#define AM_REG_UART_CR_O 0x00000030 +#define AM_REG_UART_IFLS_O 0x00000034 +#define AM_REG_UART_IER_O 0x00000038 +#define AM_REG_UART_IES_O 0x0000003C +#define AM_REG_UART_MIS_O 0x00000040 +#define AM_REG_UART_IEC_O 0x00000044 + +//***************************************************************************** +// +// UART_DR - UART Data Register +// +//***************************************************************************** +// This is the overrun error indicator. +#define AM_REG_UART_DR_OEDATA_S 11 +#define AM_REG_UART_DR_OEDATA_M 0x00000800 +#define AM_REG_UART_DR_OEDATA(n) (((uint32_t)(n) << 11) & 0x00000800) +#define AM_REG_UART_DR_OEDATA_NOERR 0x00000000 +#define AM_REG_UART_DR_OEDATA_ERR 0x00000800 + +// This is the break error indicator. +#define AM_REG_UART_DR_BEDATA_S 10 +#define AM_REG_UART_DR_BEDATA_M 0x00000400 +#define AM_REG_UART_DR_BEDATA(n) (((uint32_t)(n) << 10) & 0x00000400) +#define AM_REG_UART_DR_BEDATA_NOERR 0x00000000 +#define AM_REG_UART_DR_BEDATA_ERR 0x00000400 + +// This is the parity error indicator. +#define AM_REG_UART_DR_PEDATA_S 9 +#define AM_REG_UART_DR_PEDATA_M 0x00000200 +#define AM_REG_UART_DR_PEDATA(n) (((uint32_t)(n) << 9) & 0x00000200) +#define AM_REG_UART_DR_PEDATA_NOERR 0x00000000 +#define AM_REG_UART_DR_PEDATA_ERR 0x00000200 + +// This is the framing error indicator. +#define AM_REG_UART_DR_FEDATA_S 8 +#define AM_REG_UART_DR_FEDATA_M 0x00000100 +#define AM_REG_UART_DR_FEDATA(n) (((uint32_t)(n) << 8) & 0x00000100) +#define AM_REG_UART_DR_FEDATA_NOERR 0x00000000 +#define AM_REG_UART_DR_FEDATA_ERR 0x00000100 + +// This is the UART data port. +#define AM_REG_UART_DR_DATA_S 0 +#define AM_REG_UART_DR_DATA_M 0x000000FF +#define AM_REG_UART_DR_DATA(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// UART_RSR - UART Status Register +// +//***************************************************************************** +// This is the overrun error indicator. +#define AM_REG_UART_RSR_OESTAT_S 3 +#define AM_REG_UART_RSR_OESTAT_M 0x00000008 +#define AM_REG_UART_RSR_OESTAT(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_UART_RSR_OESTAT_NOERR 0x00000000 +#define AM_REG_UART_RSR_OESTAT_ERR 0x00000008 + +// This is the break error indicator. +#define AM_REG_UART_RSR_BESTAT_S 2 +#define AM_REG_UART_RSR_BESTAT_M 0x00000004 +#define AM_REG_UART_RSR_BESTAT(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_UART_RSR_BESTAT_NOERR 0x00000000 +#define AM_REG_UART_RSR_BESTAT_ERR 0x00000004 + +// This is the parity error indicator. +#define AM_REG_UART_RSR_PESTAT_S 1 +#define AM_REG_UART_RSR_PESTAT_M 0x00000002 +#define AM_REG_UART_RSR_PESTAT(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_UART_RSR_PESTAT_NOERR 0x00000000 +#define AM_REG_UART_RSR_PESTAT_ERR 0x00000002 + +// This is the framing error indicator. +#define AM_REG_UART_RSR_FESTAT_S 0 +#define AM_REG_UART_RSR_FESTAT_M 0x00000001 +#define AM_REG_UART_RSR_FESTAT(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_UART_RSR_FESTAT_NOERR 0x00000000 +#define AM_REG_UART_RSR_FESTAT_ERR 0x00000001 + +//***************************************************************************** +// +// UART_FR - Flag Register +// +//***************************************************************************** +// This bit holds the transmit BUSY indicator. +#define AM_REG_UART_FR_TXBUSY_S 8 +#define AM_REG_UART_FR_TXBUSY_M 0x00000100 +#define AM_REG_UART_FR_TXBUSY(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit holds the transmit FIFO empty indicator. +#define AM_REG_UART_FR_TXFE_S 7 +#define AM_REG_UART_FR_TXFE_M 0x00000080 +#define AM_REG_UART_FR_TXFE(n) (((uint32_t)(n) << 7) & 0x00000080) +#define AM_REG_UART_FR_TXFE_XMTFIFO_EMPTY 0x00000080 + +// This bit holds the receive FIFO full indicator. +#define AM_REG_UART_FR_RXFF_S 6 +#define AM_REG_UART_FR_RXFF_M 0x00000040 +#define AM_REG_UART_FR_RXFF(n) (((uint32_t)(n) << 6) & 0x00000040) +#define AM_REG_UART_FR_RXFF_RCVFIFO_FULL 0x00000040 + +// This bit holds the transmit FIFO full indicator. +#define AM_REG_UART_FR_TXFF_S 5 +#define AM_REG_UART_FR_TXFF_M 0x00000020 +#define AM_REG_UART_FR_TXFF(n) (((uint32_t)(n) << 5) & 0x00000020) +#define AM_REG_UART_FR_TXFF_XMTFIFO_FULL 0x00000020 + +// This bit holds the receive FIFO empty indicator. +#define AM_REG_UART_FR_RXFE_S 4 +#define AM_REG_UART_FR_RXFE_M 0x00000010 +#define AM_REG_UART_FR_RXFE(n) (((uint32_t)(n) << 4) & 0x00000010) +#define AM_REG_UART_FR_RXFE_RCVFIFO_EMPTY 0x00000010 + +// This bit holds the busy indicator. +#define AM_REG_UART_FR_BUSY_S 3 +#define AM_REG_UART_FR_BUSY_M 0x00000008 +#define AM_REG_UART_FR_BUSY(n) (((uint32_t)(n) << 3) & 0x00000008) +#define AM_REG_UART_FR_BUSY_BUSY 0x00000008 + +// This bit holds the data carrier detect indicator. +#define AM_REG_UART_FR_DCD_S 2 +#define AM_REG_UART_FR_DCD_M 0x00000004 +#define AM_REG_UART_FR_DCD(n) (((uint32_t)(n) << 2) & 0x00000004) +#define AM_REG_UART_FR_DCD_DETECTED 0x00000004 + +// This bit holds the data set ready indicator. +#define AM_REG_UART_FR_DSR_S 1 +#define AM_REG_UART_FR_DSR_M 0x00000002 +#define AM_REG_UART_FR_DSR(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_UART_FR_DSR_READY 0x00000002 + +// This bit holds the clear to send indicator. +#define AM_REG_UART_FR_CTS_S 0 +#define AM_REG_UART_FR_CTS_M 0x00000001 +#define AM_REG_UART_FR_CTS(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_UART_FR_CTS_CLEARTOSEND 0x00000001 + +//***************************************************************************** +// +// UART_ILPR - IrDA Counter +// +//***************************************************************************** +// These bits hold the IrDA counter divisor. +#define AM_REG_UART_ILPR_ILPDVSR_S 0 +#define AM_REG_UART_ILPR_ILPDVSR_M 0x000000FF +#define AM_REG_UART_ILPR_ILPDVSR(n) (((uint32_t)(n) << 0) & 0x000000FF) + +//***************************************************************************** +// +// UART_IBRD - Integer Baud Rate Divisor +// +//***************************************************************************** +// These bits hold the baud integer divisor. +#define AM_REG_UART_IBRD_DIVINT_S 0 +#define AM_REG_UART_IBRD_DIVINT_M 0x0000FFFF +#define AM_REG_UART_IBRD_DIVINT(n) (((uint32_t)(n) << 0) & 0x0000FFFF) + +//***************************************************************************** +// +// UART_FBRD - Fractional Baud Rate Divisor +// +//***************************************************************************** +// These bits hold the baud fractional divisor. +#define AM_REG_UART_FBRD_DIVFRAC_S 0 +#define AM_REG_UART_FBRD_DIVFRAC_M 0x0000003F +#define AM_REG_UART_FBRD_DIVFRAC(n) (((uint32_t)(n) << 0) & 0x0000003F) + +//***************************************************************************** +// +// UART_LCRH - Line Control High +// +//***************************************************************************** +// This bit holds the stick parity select. +#define AM_REG_UART_LCRH_SPS_S 7 +#define AM_REG_UART_LCRH_SPS_M 0x00000080 +#define AM_REG_UART_LCRH_SPS(n) (((uint32_t)(n) << 7) & 0x00000080) + +// These bits hold the write length. +#define AM_REG_UART_LCRH_WLEN_S 5 +#define AM_REG_UART_LCRH_WLEN_M 0x00000060 +#define AM_REG_UART_LCRH_WLEN(n) (((uint32_t)(n) << 5) & 0x00000060) + +// This bit holds the FIFO enable. +#define AM_REG_UART_LCRH_FEN_S 4 +#define AM_REG_UART_LCRH_FEN_M 0x00000010 +#define AM_REG_UART_LCRH_FEN(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit holds the two stop bits select. +#define AM_REG_UART_LCRH_STP2_S 3 +#define AM_REG_UART_LCRH_STP2_M 0x00000008 +#define AM_REG_UART_LCRH_STP2(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit holds the even parity select. +#define AM_REG_UART_LCRH_EPS_S 2 +#define AM_REG_UART_LCRH_EPS_M 0x00000004 +#define AM_REG_UART_LCRH_EPS(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit holds the parity enable. +#define AM_REG_UART_LCRH_PEN_S 1 +#define AM_REG_UART_LCRH_PEN_M 0x00000002 +#define AM_REG_UART_LCRH_PEN(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit holds the break set. +#define AM_REG_UART_LCRH_BRK_S 0 +#define AM_REG_UART_LCRH_BRK_M 0x00000001 +#define AM_REG_UART_LCRH_BRK(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// UART_CR - Control Register +// +//***************************************************************************** +// This bit enables CTS hardware flow control. +#define AM_REG_UART_CR_CTSEN_S 15 +#define AM_REG_UART_CR_CTSEN_M 0x00008000 +#define AM_REG_UART_CR_CTSEN(n) (((uint32_t)(n) << 15) & 0x00008000) + +// This bit enables RTS hardware flow control. +#define AM_REG_UART_CR_RTSEN_S 14 +#define AM_REG_UART_CR_RTSEN_M 0x00004000 +#define AM_REG_UART_CR_RTSEN(n) (((uint32_t)(n) << 14) & 0x00004000) + +// This bit holds modem Out2. +#define AM_REG_UART_CR_OUT2_S 13 +#define AM_REG_UART_CR_OUT2_M 0x00002000 +#define AM_REG_UART_CR_OUT2(n) (((uint32_t)(n) << 13) & 0x00002000) + +// This bit holds modem Out1. +#define AM_REG_UART_CR_OUT1_S 12 +#define AM_REG_UART_CR_OUT1_M 0x00001000 +#define AM_REG_UART_CR_OUT1(n) (((uint32_t)(n) << 12) & 0x00001000) + +// This bit enables request to send. +#define AM_REG_UART_CR_RTS_S 11 +#define AM_REG_UART_CR_RTS_M 0x00000800 +#define AM_REG_UART_CR_RTS(n) (((uint32_t)(n) << 11) & 0x00000800) + +// This bit enables data transmit ready. +#define AM_REG_UART_CR_DTR_S 10 +#define AM_REG_UART_CR_DTR_M 0x00000400 +#define AM_REG_UART_CR_DTR(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This bit is the receive enable. +#define AM_REG_UART_CR_RXE_S 9 +#define AM_REG_UART_CR_RXE_M 0x00000200 +#define AM_REG_UART_CR_RXE(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This bit is the transmit enable. +#define AM_REG_UART_CR_TXE_S 8 +#define AM_REG_UART_CR_TXE_M 0x00000100 +#define AM_REG_UART_CR_TXE(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit is the loopback enable. +#define AM_REG_UART_CR_LBE_S 7 +#define AM_REG_UART_CR_LBE_M 0x00000080 +#define AM_REG_UART_CR_LBE(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This bitfield is the UART clock select. +#define AM_REG_UART_CR_CLKSEL_S 4 +#define AM_REG_UART_CR_CLKSEL_M 0x00000070 +#define AM_REG_UART_CR_CLKSEL(n) (((uint32_t)(n) << 4) & 0x00000070) +#define AM_REG_UART_CR_CLKSEL_NOCLK 0x00000000 +#define AM_REG_UART_CR_CLKSEL_24MHZ 0x00000010 +#define AM_REG_UART_CR_CLKSEL_12MHZ 0x00000020 +#define AM_REG_UART_CR_CLKSEL_6MHZ 0x00000030 +#define AM_REG_UART_CR_CLKSEL_3MHZ 0x00000040 +#define AM_REG_UART_CR_CLKSEL_RSVD5 0x00000050 +#define AM_REG_UART_CR_CLKSEL_RSVD6 0x00000060 +#define AM_REG_UART_CR_CLKSEL_RSVD7 0x00000070 + +// This bit is the UART clock enable. +#define AM_REG_UART_CR_CLKEN_S 3 +#define AM_REG_UART_CR_CLKEN_M 0x00000008 +#define AM_REG_UART_CR_CLKEN(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit is the SIR low power select. +#define AM_REG_UART_CR_SIRLP_S 2 +#define AM_REG_UART_CR_SIRLP_M 0x00000004 +#define AM_REG_UART_CR_SIRLP(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit is the SIR ENDEC enable. +#define AM_REG_UART_CR_SIREN_S 1 +#define AM_REG_UART_CR_SIREN_M 0x00000002 +#define AM_REG_UART_CR_SIREN(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit is the UART enable. +#define AM_REG_UART_CR_UARTEN_S 0 +#define AM_REG_UART_CR_UARTEN_M 0x00000001 +#define AM_REG_UART_CR_UARTEN(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// UART_IFLS - FIFO Interrupt Level Select +// +//***************************************************************************** +// These bits hold the receive FIFO interrupt level. +#define AM_REG_UART_IFLS_RXIFLSEL_S 3 +#define AM_REG_UART_IFLS_RXIFLSEL_M 0x00000038 +#define AM_REG_UART_IFLS_RXIFLSEL(n) (((uint32_t)(n) << 3) & 0x00000038) + +// These bits hold the transmit FIFO interrupt level. +#define AM_REG_UART_IFLS_TXIFLSEL_S 0 +#define AM_REG_UART_IFLS_TXIFLSEL_M 0x00000007 +#define AM_REG_UART_IFLS_TXIFLSEL(n) (((uint32_t)(n) << 0) & 0x00000007) + +//***************************************************************************** +// +// UART_IER - Interrupt Enable +// +//***************************************************************************** +// This bit holds the overflow interrupt enable. +#define AM_REG_UART_IER_OEIM_S 10 +#define AM_REG_UART_IER_OEIM_M 0x00000400 +#define AM_REG_UART_IER_OEIM(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This bit holds the break error interrupt enable. +#define AM_REG_UART_IER_BEIM_S 9 +#define AM_REG_UART_IER_BEIM_M 0x00000200 +#define AM_REG_UART_IER_BEIM(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This bit holds the parity error interrupt enable. +#define AM_REG_UART_IER_PEIM_S 8 +#define AM_REG_UART_IER_PEIM_M 0x00000100 +#define AM_REG_UART_IER_PEIM(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit holds the framing error interrupt enable. +#define AM_REG_UART_IER_FEIM_S 7 +#define AM_REG_UART_IER_FEIM_M 0x00000080 +#define AM_REG_UART_IER_FEIM(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This bit holds the receive timeout interrupt enable. +#define AM_REG_UART_IER_RTIM_S 6 +#define AM_REG_UART_IER_RTIM_M 0x00000040 +#define AM_REG_UART_IER_RTIM(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This bit holds the transmit interrupt enable. +#define AM_REG_UART_IER_TXIM_S 5 +#define AM_REG_UART_IER_TXIM_M 0x00000020 +#define AM_REG_UART_IER_TXIM(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This bit holds the receive interrupt enable. +#define AM_REG_UART_IER_RXIM_S 4 +#define AM_REG_UART_IER_RXIM_M 0x00000010 +#define AM_REG_UART_IER_RXIM(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit holds the modem DSR interrupt enable. +#define AM_REG_UART_IER_DSRMIM_S 3 +#define AM_REG_UART_IER_DSRMIM_M 0x00000008 +#define AM_REG_UART_IER_DSRMIM(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit holds the modem DCD interrupt enable. +#define AM_REG_UART_IER_DCDMIM_S 2 +#define AM_REG_UART_IER_DCDMIM_M 0x00000004 +#define AM_REG_UART_IER_DCDMIM(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit holds the modem CTS interrupt enable. +#define AM_REG_UART_IER_CTSMIM_S 1 +#define AM_REG_UART_IER_CTSMIM_M 0x00000002 +#define AM_REG_UART_IER_CTSMIM(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit holds the modem TXCMP interrupt enable. +#define AM_REG_UART_IER_TXCMPMIM_S 0 +#define AM_REG_UART_IER_TXCMPMIM_M 0x00000001 +#define AM_REG_UART_IER_TXCMPMIM(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// UART_IES - Interrupt Status +// +//***************************************************************************** +// This bit holds the overflow interrupt status. +#define AM_REG_UART_IES_OERIS_S 10 +#define AM_REG_UART_IES_OERIS_M 0x00000400 +#define AM_REG_UART_IES_OERIS(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This bit holds the break error interrupt status. +#define AM_REG_UART_IES_BERIS_S 9 +#define AM_REG_UART_IES_BERIS_M 0x00000200 +#define AM_REG_UART_IES_BERIS(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This bit holds the parity error interrupt status. +#define AM_REG_UART_IES_PERIS_S 8 +#define AM_REG_UART_IES_PERIS_M 0x00000100 +#define AM_REG_UART_IES_PERIS(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit holds the framing error interrupt status. +#define AM_REG_UART_IES_FERIS_S 7 +#define AM_REG_UART_IES_FERIS_M 0x00000080 +#define AM_REG_UART_IES_FERIS(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This bit holds the receive timeout interrupt status. +#define AM_REG_UART_IES_RTRIS_S 6 +#define AM_REG_UART_IES_RTRIS_M 0x00000040 +#define AM_REG_UART_IES_RTRIS(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This bit holds the transmit interrupt status. +#define AM_REG_UART_IES_TXRIS_S 5 +#define AM_REG_UART_IES_TXRIS_M 0x00000020 +#define AM_REG_UART_IES_TXRIS(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This bit holds the receive interrupt status. +#define AM_REG_UART_IES_RXRIS_S 4 +#define AM_REG_UART_IES_RXRIS_M 0x00000010 +#define AM_REG_UART_IES_RXRIS(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit holds the modem DSR interrupt status. +#define AM_REG_UART_IES_DSRMRIS_S 3 +#define AM_REG_UART_IES_DSRMRIS_M 0x00000008 +#define AM_REG_UART_IES_DSRMRIS(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit holds the modem DCD interrupt status. +#define AM_REG_UART_IES_DCDMRIS_S 2 +#define AM_REG_UART_IES_DCDMRIS_M 0x00000004 +#define AM_REG_UART_IES_DCDMRIS(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit holds the modem CTS interrupt status. +#define AM_REG_UART_IES_CTSMRIS_S 1 +#define AM_REG_UART_IES_CTSMRIS_M 0x00000002 +#define AM_REG_UART_IES_CTSMRIS(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit holds the modem TXCMP interrupt status. +#define AM_REG_UART_IES_TXCMPMRIS_S 0 +#define AM_REG_UART_IES_TXCMPMRIS_M 0x00000001 +#define AM_REG_UART_IES_TXCMPMRIS(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// UART_MIS - Masked Interrupt Status +// +//***************************************************************************** +// This bit holds the overflow interrupt status masked. +#define AM_REG_UART_MIS_OEMIS_S 10 +#define AM_REG_UART_MIS_OEMIS_M 0x00000400 +#define AM_REG_UART_MIS_OEMIS(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This bit holds the break error interrupt status masked. +#define AM_REG_UART_MIS_BEMIS_S 9 +#define AM_REG_UART_MIS_BEMIS_M 0x00000200 +#define AM_REG_UART_MIS_BEMIS(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This bit holds the parity error interrupt status masked. +#define AM_REG_UART_MIS_PEMIS_S 8 +#define AM_REG_UART_MIS_PEMIS_M 0x00000100 +#define AM_REG_UART_MIS_PEMIS(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit holds the framing error interrupt status masked. +#define AM_REG_UART_MIS_FEMIS_S 7 +#define AM_REG_UART_MIS_FEMIS_M 0x00000080 +#define AM_REG_UART_MIS_FEMIS(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This bit holds the receive timeout interrupt status masked. +#define AM_REG_UART_MIS_RTMIS_S 6 +#define AM_REG_UART_MIS_RTMIS_M 0x00000040 +#define AM_REG_UART_MIS_RTMIS(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This bit holds the transmit interrupt status masked. +#define AM_REG_UART_MIS_TXMIS_S 5 +#define AM_REG_UART_MIS_TXMIS_M 0x00000020 +#define AM_REG_UART_MIS_TXMIS(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This bit holds the receive interrupt status masked. +#define AM_REG_UART_MIS_RXMIS_S 4 +#define AM_REG_UART_MIS_RXMIS_M 0x00000010 +#define AM_REG_UART_MIS_RXMIS(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit holds the modem DSR interrupt status masked. +#define AM_REG_UART_MIS_DSRMMIS_S 3 +#define AM_REG_UART_MIS_DSRMMIS_M 0x00000008 +#define AM_REG_UART_MIS_DSRMMIS(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit holds the modem DCD interrupt status masked. +#define AM_REG_UART_MIS_DCDMMIS_S 2 +#define AM_REG_UART_MIS_DCDMMIS_M 0x00000004 +#define AM_REG_UART_MIS_DCDMMIS(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit holds the modem CTS interrupt status masked. +#define AM_REG_UART_MIS_CTSMMIS_S 1 +#define AM_REG_UART_MIS_CTSMMIS_M 0x00000002 +#define AM_REG_UART_MIS_CTSMMIS(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit holds the modem TXCMP interrupt status masked. +#define AM_REG_UART_MIS_TXCMPMMIS_S 0 +#define AM_REG_UART_MIS_TXCMPMMIS_M 0x00000001 +#define AM_REG_UART_MIS_TXCMPMMIS(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// UART_IEC - Interrupt Clear +// +//***************************************************************************** +// This bit holds the overflow interrupt clear. +#define AM_REG_UART_IEC_OEIC_S 10 +#define AM_REG_UART_IEC_OEIC_M 0x00000400 +#define AM_REG_UART_IEC_OEIC(n) (((uint32_t)(n) << 10) & 0x00000400) + +// This bit holds the break error interrupt clear. +#define AM_REG_UART_IEC_BEIC_S 9 +#define AM_REG_UART_IEC_BEIC_M 0x00000200 +#define AM_REG_UART_IEC_BEIC(n) (((uint32_t)(n) << 9) & 0x00000200) + +// This bit holds the parity error interrupt clear. +#define AM_REG_UART_IEC_PEIC_S 8 +#define AM_REG_UART_IEC_PEIC_M 0x00000100 +#define AM_REG_UART_IEC_PEIC(n) (((uint32_t)(n) << 8) & 0x00000100) + +// This bit holds the framing error interrupt clear. +#define AM_REG_UART_IEC_FEIC_S 7 +#define AM_REG_UART_IEC_FEIC_M 0x00000080 +#define AM_REG_UART_IEC_FEIC(n) (((uint32_t)(n) << 7) & 0x00000080) + +// This bit holds the receive timeout interrupt clear. +#define AM_REG_UART_IEC_RTIC_S 6 +#define AM_REG_UART_IEC_RTIC_M 0x00000040 +#define AM_REG_UART_IEC_RTIC(n) (((uint32_t)(n) << 6) & 0x00000040) + +// This bit holds the transmit interrupt clear. +#define AM_REG_UART_IEC_TXIC_S 5 +#define AM_REG_UART_IEC_TXIC_M 0x00000020 +#define AM_REG_UART_IEC_TXIC(n) (((uint32_t)(n) << 5) & 0x00000020) + +// This bit holds the receive interrupt clear. +#define AM_REG_UART_IEC_RXIC_S 4 +#define AM_REG_UART_IEC_RXIC_M 0x00000010 +#define AM_REG_UART_IEC_RXIC(n) (((uint32_t)(n) << 4) & 0x00000010) + +// This bit holds the modem DSR interrupt clear. +#define AM_REG_UART_IEC_DSRMIC_S 3 +#define AM_REG_UART_IEC_DSRMIC_M 0x00000008 +#define AM_REG_UART_IEC_DSRMIC(n) (((uint32_t)(n) << 3) & 0x00000008) + +// This bit holds the modem DCD interrupt clear. +#define AM_REG_UART_IEC_DCDMIC_S 2 +#define AM_REG_UART_IEC_DCDMIC_M 0x00000004 +#define AM_REG_UART_IEC_DCDMIC(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bit holds the modem CTS interrupt clear. +#define AM_REG_UART_IEC_CTSMIC_S 1 +#define AM_REG_UART_IEC_CTSMIC_M 0x00000002 +#define AM_REG_UART_IEC_CTSMIC(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit holds the modem TXCMP interrupt clear. +#define AM_REG_UART_IEC_TXCMPMIC_S 0 +#define AM_REG_UART_IEC_TXCMPMIC_M 0x00000001 +#define AM_REG_UART_IEC_TXCMPMIC(n) (((uint32_t)(n) << 0) & 0x00000001) + +#endif // AM_REG_UART_H diff --git a/mcu/apollo2/regs/am_reg_vcomp.h b/mcu/apollo2/regs/am_reg_vcomp.h new file mode 100644 index 0000000..7e8116c --- /dev/null +++ b/mcu/apollo2/regs/am_reg_vcomp.h @@ -0,0 +1,201 @@ +//***************************************************************************** +// +// am_reg_vcomp.h +//! @file +//! +//! @brief Register macros for the VCOMP module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_VCOMP_H +#define AM_REG_VCOMP_H + +//***************************************************************************** +// +// VCOMP +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_VCOMP_NUM_MODULES 1 +#define AM_REG_VCOMPn(n) \ + (REG_VCOMP_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_VCOMP_CFG_O 0x00000000 +#define AM_REG_VCOMP_STAT_O 0x00000004 +#define AM_REG_VCOMP_PWDKEY_O 0x00000008 +#define AM_REG_VCOMP_INTEN_O 0x00000200 +#define AM_REG_VCOMP_INTSTAT_O 0x00000204 +#define AM_REG_VCOMP_INTCLR_O 0x00000208 +#define AM_REG_VCOMP_INTSET_O 0x0000020C + +//***************************************************************************** +// +// Key values. +// +//***************************************************************************** +#define AM_REG_VCOMP_PWDKEY_KEYVAL 0x00000037 + +//***************************************************************************** +// +// VCOMP_INTEN - Voltage Comparator Interrupt registers: Enable +// +//***************************************************************************** +// This bit is the vcompout high interrupt. +#define AM_REG_VCOMP_INTEN_OUTHI_S 1 +#define AM_REG_VCOMP_INTEN_OUTHI_M 0x00000002 +#define AM_REG_VCOMP_INTEN_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit is the vcompout low interrupt. +#define AM_REG_VCOMP_INTEN_OUTLOW_S 0 +#define AM_REG_VCOMP_INTEN_OUTLOW_M 0x00000001 +#define AM_REG_VCOMP_INTEN_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// VCOMP_INTSTAT - Voltage Comparator Interrupt registers: Status +// +//***************************************************************************** +// This bit is the vcompout high interrupt. +#define AM_REG_VCOMP_INTSTAT_OUTHI_S 1 +#define AM_REG_VCOMP_INTSTAT_OUTHI_M 0x00000002 +#define AM_REG_VCOMP_INTSTAT_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit is the vcompout low interrupt. +#define AM_REG_VCOMP_INTSTAT_OUTLOW_S 0 +#define AM_REG_VCOMP_INTSTAT_OUTLOW_M 0x00000001 +#define AM_REG_VCOMP_INTSTAT_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// VCOMP_INTCLR - Voltage Comparator Interrupt registers: Clear +// +//***************************************************************************** +// This bit is the vcompout high interrupt. +#define AM_REG_VCOMP_INTCLR_OUTHI_S 1 +#define AM_REG_VCOMP_INTCLR_OUTHI_M 0x00000002 +#define AM_REG_VCOMP_INTCLR_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit is the vcompout low interrupt. +#define AM_REG_VCOMP_INTCLR_OUTLOW_S 0 +#define AM_REG_VCOMP_INTCLR_OUTLOW_M 0x00000001 +#define AM_REG_VCOMP_INTCLR_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// VCOMP_INTSET - Voltage Comparator Interrupt registers: Set +// +//***************************************************************************** +// This bit is the vcompout high interrupt. +#define AM_REG_VCOMP_INTSET_OUTHI_S 1 +#define AM_REG_VCOMP_INTSET_OUTHI_M 0x00000002 +#define AM_REG_VCOMP_INTSET_OUTHI(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bit is the vcompout low interrupt. +#define AM_REG_VCOMP_INTSET_OUTLOW_S 0 +#define AM_REG_VCOMP_INTSET_OUTLOW_M 0x00000001 +#define AM_REG_VCOMP_INTSET_OUTLOW(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// VCOMP_CFG - Configuration Register +// +//***************************************************************************** +// When the reference input NSEL is set to NSEL_DAC, this bitfield selects the +// voltage level for the negative input to the comparator. +#define AM_REG_VCOMP_CFG_LVLSEL_S 16 +#define AM_REG_VCOMP_CFG_LVLSEL_M 0x000F0000 +#define AM_REG_VCOMP_CFG_LVLSEL(n) (((uint32_t)(n) << 16) & 0x000F0000) +#define AM_REG_VCOMP_CFG_LVLSEL_0P58V 0x00000000 +#define AM_REG_VCOMP_CFG_LVLSEL_0P77V 0x00010000 +#define AM_REG_VCOMP_CFG_LVLSEL_0P97V 0x00020000 +#define AM_REG_VCOMP_CFG_LVLSEL_1P16V 0x00030000 +#define AM_REG_VCOMP_CFG_LVLSEL_1P35V 0x00040000 +#define AM_REG_VCOMP_CFG_LVLSEL_1P55V 0x00050000 +#define AM_REG_VCOMP_CFG_LVLSEL_1P74V 0x00060000 +#define AM_REG_VCOMP_CFG_LVLSEL_1P93V 0x00070000 +#define AM_REG_VCOMP_CFG_LVLSEL_2P13V 0x00080000 +#define AM_REG_VCOMP_CFG_LVLSEL_2P32V 0x00090000 +#define AM_REG_VCOMP_CFG_LVLSEL_2P51V 0x000A0000 +#define AM_REG_VCOMP_CFG_LVLSEL_2P71V 0x000B0000 +#define AM_REG_VCOMP_CFG_LVLSEL_2P90V 0x000C0000 +#define AM_REG_VCOMP_CFG_LVLSEL_3P09V 0x000D0000 +#define AM_REG_VCOMP_CFG_LVLSEL_3P29V 0x000E0000 +#define AM_REG_VCOMP_CFG_LVLSEL_3P48V 0x000F0000 + +// This bitfield selects the negative input to the comparator. +#define AM_REG_VCOMP_CFG_NSEL_S 8 +#define AM_REG_VCOMP_CFG_NSEL_M 0x00000300 +#define AM_REG_VCOMP_CFG_NSEL(n) (((uint32_t)(n) << 8) & 0x00000300) +#define AM_REG_VCOMP_CFG_NSEL_VREFEXT1 0x00000000 +#define AM_REG_VCOMP_CFG_NSEL_VREFEXT2 0x00000100 +#define AM_REG_VCOMP_CFG_NSEL_VREFEXT3 0x00000200 +#define AM_REG_VCOMP_CFG_NSEL_DAC 0x00000300 + +// This bitfield selects the positive input to the comparator. +#define AM_REG_VCOMP_CFG_PSEL_S 0 +#define AM_REG_VCOMP_CFG_PSEL_M 0x00000003 +#define AM_REG_VCOMP_CFG_PSEL(n) (((uint32_t)(n) << 0) & 0x00000003) +#define AM_REG_VCOMP_CFG_PSEL_VDDADJ 0x00000000 +#define AM_REG_VCOMP_CFG_PSEL_VTEMP 0x00000001 +#define AM_REG_VCOMP_CFG_PSEL_VEXT1 0x00000002 +#define AM_REG_VCOMP_CFG_PSEL_VEXT2 0x00000003 + +//***************************************************************************** +// +// VCOMP_STAT - Status Register +// +//***************************************************************************** +// This bit indicates the power down state of the voltage comparator. +#define AM_REG_VCOMP_STAT_PWDSTAT_S 1 +#define AM_REG_VCOMP_STAT_PWDSTAT_M 0x00000002 +#define AM_REG_VCOMP_STAT_PWDSTAT(n) (((uint32_t)(n) << 1) & 0x00000002) +#define AM_REG_VCOMP_STAT_PWDSTAT_POWERED_DOWN 0x00000002 + +// This bit is 1 if the positive input of the comparator is greater than the +// negative input. +#define AM_REG_VCOMP_STAT_CMPOUT_S 0 +#define AM_REG_VCOMP_STAT_CMPOUT_M 0x00000001 +#define AM_REG_VCOMP_STAT_CMPOUT(n) (((uint32_t)(n) << 0) & 0x00000001) +#define AM_REG_VCOMP_STAT_CMPOUT_VOUT_LOW 0x00000000 +#define AM_REG_VCOMP_STAT_CMPOUT_VOUT_HIGH 0x00000001 + +#endif // AM_REG_VCOMP_H diff --git a/mcu/apollo2/regs/am_reg_wdt.h b/mcu/apollo2/regs/am_reg_wdt.h new file mode 100644 index 0000000..b736076 --- /dev/null +++ b/mcu/apollo2/regs/am_reg_wdt.h @@ -0,0 +1,190 @@ +//***************************************************************************** +// +// am_reg_wdt.h +//! @file +//! +//! @brief Register macros for the WDT module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro, Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.5.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef AM_REG_WDT_H +#define AM_REG_WDT_H + +//***************************************************************************** +// +// WDT +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_WDT_NUM_MODULES 1 +#define AM_REG_WDTn(n) \ + (REG_WDT_BASEADDR + 0x00000000 * n) + +//***************************************************************************** +// +// Register offsets. +// +//***************************************************************************** +#define AM_REG_WDT_CFG_O 0x00000000 +#define AM_REG_WDT_RSTRT_O 0x00000004 +#define AM_REG_WDT_LOCK_O 0x00000008 +#define AM_REG_WDT_COUNT_O 0x0000000C +#define AM_REG_WDT_INTEN_O 0x00000200 +#define AM_REG_WDT_INTSTAT_O 0x00000204 +#define AM_REG_WDT_INTCLR_O 0x00000208 +#define AM_REG_WDT_INTSET_O 0x0000020C + +//***************************************************************************** +// +// WDT_INTEN - WDT Interrupt register: Enable +// +//***************************************************************************** +// Watchdog Timer Interrupt. +#define AM_REG_WDT_INTEN_WDTINT_S 0 +#define AM_REG_WDT_INTEN_WDTINT_M 0x00000001 +#define AM_REG_WDT_INTEN_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// WDT_INTSTAT - WDT Interrupt register: Status +// +//***************************************************************************** +// Watchdog Timer Interrupt. +#define AM_REG_WDT_INTSTAT_WDTINT_S 0 +#define AM_REG_WDT_INTSTAT_WDTINT_M 0x00000001 +#define AM_REG_WDT_INTSTAT_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// WDT_INTCLR - WDT Interrupt register: Clear +// +//***************************************************************************** +// Watchdog Timer Interrupt. +#define AM_REG_WDT_INTCLR_WDTINT_S 0 +#define AM_REG_WDT_INTCLR_WDTINT_M 0x00000001 +#define AM_REG_WDT_INTCLR_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// WDT_INTSET - WDT Interrupt register: Set +// +//***************************************************************************** +// Watchdog Timer Interrupt. +#define AM_REG_WDT_INTSET_WDTINT_S 0 +#define AM_REG_WDT_INTSET_WDTINT_M 0x00000001 +#define AM_REG_WDT_INTSET_WDTINT(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// WDT_CFG - Configuration Register +// +//***************************************************************************** +// Select the frequency for the WDT. All values not enumerated below are +// undefined. +#define AM_REG_WDT_CFG_CLKSEL_S 24 +#define AM_REG_WDT_CFG_CLKSEL_M 0x07000000 +#define AM_REG_WDT_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x07000000) +#define AM_REG_WDT_CFG_CLKSEL_OFF 0x00000000 +#define AM_REG_WDT_CFG_CLKSEL_128HZ 0x01000000 +#define AM_REG_WDT_CFG_CLKSEL_16HZ 0x02000000 +#define AM_REG_WDT_CFG_CLKSEL_1HZ 0x03000000 +#define AM_REG_WDT_CFG_CLKSEL_1_16HZ 0x04000000 + +// This bitfield is the compare value for counter bits 7:0 to generate a +// watchdog interrupt. +#define AM_REG_WDT_CFG_INTVAL_S 16 +#define AM_REG_WDT_CFG_INTVAL_M 0x00FF0000 +#define AM_REG_WDT_CFG_INTVAL(n) (((uint32_t)(n) << 16) & 0x00FF0000) + +// This bitfield is the compare value for counter bits 7:0 to generate a +// watchdog reset. +#define AM_REG_WDT_CFG_RESVAL_S 8 +#define AM_REG_WDT_CFG_RESVAL_M 0x0000FF00 +#define AM_REG_WDT_CFG_RESVAL(n) (((uint32_t)(n) << 8) & 0x0000FF00) + +// This bitfield enables the WDT reset. +#define AM_REG_WDT_CFG_RESEN_S 2 +#define AM_REG_WDT_CFG_RESEN_M 0x00000004 +#define AM_REG_WDT_CFG_RESEN(n) (((uint32_t)(n) << 2) & 0x00000004) + +// This bitfield enables the WDT interrupt. Note : This bit must be set before +// the interrupt status bit will reflect a watchdog timer expiration. The IER +// interrupt register must also be enabled for a WDT interrupt to be sent to the +// NVIC. +#define AM_REG_WDT_CFG_INTEN_S 1 +#define AM_REG_WDT_CFG_INTEN_M 0x00000002 +#define AM_REG_WDT_CFG_INTEN(n) (((uint32_t)(n) << 1) & 0x00000002) + +// This bitfield enables the WDT. +#define AM_REG_WDT_CFG_WDTEN_S 0 +#define AM_REG_WDT_CFG_WDTEN_M 0x00000001 +#define AM_REG_WDT_CFG_WDTEN(n) (((uint32_t)(n) << 0) & 0x00000001) + +//***************************************************************************** +// +// WDT_RSTRT - Restart the watchdog timer +// +//***************************************************************************** +// Writing 0xB2 to WDTRSTRT restarts the watchdog timer. +#define AM_REG_WDT_RSTRT_RSTRT_S 0 +#define AM_REG_WDT_RSTRT_RSTRT_M 0x000000FF +#define AM_REG_WDT_RSTRT_RSTRT(n) (((uint32_t)(n) << 0) & 0x000000FF) +#define AM_REG_WDT_RSTRT_RSTRT_KEYVALUE 0x000000B2 + +//***************************************************************************** +// +// WDT_LOCK - Locks the WDT +// +//***************************************************************************** +// Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be +// written and WDTEN is set. +#define AM_REG_WDT_LOCK_LOCK_S 0 +#define AM_REG_WDT_LOCK_LOCK_M 0x000000FF +#define AM_REG_WDT_LOCK_LOCK(n) (((uint32_t)(n) << 0) & 0x000000FF) +#define AM_REG_WDT_LOCK_LOCK_KEYVALUE 0x0000003A + +//***************************************************************************** +// +// WDT_COUNT - Current Counter Value for WDT +// +//***************************************************************************** +// Read-Only current value of the WDT counter +#define AM_REG_WDT_COUNT_COUNT_S 0 +#define AM_REG_WDT_COUNT_COUNT_M 0x000000FF +#define AM_REG_WDT_COUNT_COUNT(n) (((uint32_t)(n) << 0) & 0x000000FF) + +#endif // AM_REG_WDT_H