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drivers: gpio: Add support for RZ/A3M
Add GPIO driver support for RZ/A3M Signed-off-by: Nhut Nguyen <[email protected]>
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4 files changed

+290
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‎drivers/gpio/gpio_renesas_rz.h

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \
1616
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \
1717
defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) || \
18-
defined(CONFIG_SOC_SERIES_RZV2N)
18+
defined(CONFIG_SOC_SERIES_RZV2N) || defined(CONFIG_SOC_SERIES_RZA3M)
1919
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
2020

2121
#if defined(CONFIG_SOC_SERIES_RZG3S)
@@ -40,6 +40,18 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23
4040
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
4141
47, 52, 56, 58, 63, 66, 70, 72, 76};
4242

43+
#elif defined(CONFIG_SOC_SERIES_RZA3M)
44+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P01)
45+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM01)
46+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC01)
47+
#define GPIO_RZ_MAX_PORT_NUM 24
48+
#define GPIO_RZ_TINT_IRQ_OFFSET 476
49+
#define R_INTC R_INTC_IA55
50+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IA55->TSCR &= ~BIT(tint_num))
51+
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 42,
52+
47, 52, 56, 0, 0, 0, 0, 0, 0, 0,
53+
58, 64, 67, 72};
54+
4355
#elif defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZV2N)
4456
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20)
4557
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20)

‎dts/arm64/renesas/rz/rza/r9a07g066.dtsi

Lines changed: 256 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,262 @@
5858
compatible = "renesas,rza-pinctrl";
5959
reg = <0x11030000 DT_SIZE_K(64)>;
6060
reg-names = "pinctrl";
61+
62+
gpio: gpio-common {
63+
compatible = "renesas,rz-gpio-int";
64+
interrupts =
65+
<GIC_SPI 444 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
66+
<GIC_SPI 445 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
67+
<GIC_SPI 446 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
68+
<GIC_SPI 447 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
69+
<GIC_SPI 448 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
70+
<GIC_SPI 449 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
71+
<GIC_SPI 450 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
72+
<GIC_SPI 451 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
73+
<GIC_SPI 452 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
74+
<GIC_SPI 453 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
75+
<GIC_SPI 454 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
76+
<GIC_SPI 455 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
77+
<GIC_SPI 456 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
78+
<GIC_SPI 457 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
79+
<GIC_SPI 458 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
80+
<GIC_SPI 459 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
81+
<GIC_SPI 460 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
82+
<GIC_SPI 461 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
83+
<GIC_SPI 462 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
84+
<GIC_SPI 463 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
85+
<GIC_SPI 464 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
86+
<GIC_SPI 465 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
87+
<GIC_SPI 466 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
88+
<GIC_SPI 467 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
89+
<GIC_SPI 468 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
90+
<GIC_SPI 469 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
91+
<GIC_SPI 470 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
92+
<GIC_SPI 471 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
93+
<GIC_SPI 472 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
94+
<GIC_SPI 473 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
95+
<GIC_SPI 474 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
96+
<GIC_SPI 475 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
97+
#address-cells = <1>;
98+
#size-cells = <0>;
99+
status = "disabled";
100+
101+
gpio0: gpio@f00 {
102+
compatible = "renesas,rz-gpio";
103+
gpio-controller;
104+
#gpio-cells = <2>;
105+
ngpios = <4>;
106+
reg = <0xf00>;
107+
status = "disabled";
108+
};
109+
110+
gpio1: gpio@1000 {
111+
compatible = "renesas,rz-gpio";
112+
gpio-controller;
113+
#gpio-cells = <2>;
114+
ngpios = <5>;
115+
reg = <0x1000>;
116+
status = "disabled";
117+
};
118+
119+
gpio2: gpio@1100 {
120+
compatible = "renesas,rz-gpio";
121+
gpio-controller;
122+
#gpio-cells = <2>;
123+
ngpios = <4>;
124+
reg = <0x1100>;
125+
status = "disabled";
126+
};
127+
128+
gpio3: gpio@1200 {
129+
compatible = "renesas,rz-gpio";
130+
gpio-controller;
131+
#gpio-cells = <2>;
132+
ngpios = <4>;
133+
reg = <0x1200>;
134+
status = "disabled";
135+
};
136+
137+
gpio4: gpio@1300 {
138+
compatible = "renesas,rz-gpio";
139+
gpio-controller;
140+
#gpio-cells = <2>;
141+
ngpios = <6>;
142+
reg = <0x1300>;
143+
status = "disabled";
144+
};
145+
146+
gpio5: gpio@1400 {
147+
compatible = "renesas,rz-gpio";
148+
gpio-controller;
149+
#gpio-cells = <2>;
150+
ngpios = <5>;
151+
reg = <0x1400>;
152+
status = "disabled";
153+
};
154+
155+
gpio6: gpio@1500 {
156+
compatible = "renesas,rz-gpio";
157+
gpio-controller;
158+
#gpio-cells = <2>;
159+
ngpios = <5>;
160+
reg = <0x1500>;
161+
status = "disabled";
162+
};
163+
164+
gpio7: gpio@1600 {
165+
compatible = "renesas,rz-gpio";
166+
gpio-controller;
167+
#gpio-cells = <2>;
168+
ngpios = <2>;
169+
reg = <0x1600>;
170+
status = "disabled";
171+
};
172+
173+
gpio8: gpio@1700 {
174+
compatible = "renesas,rz-gpio";
175+
gpio-controller;
176+
#gpio-cells = <2>;
177+
ngpios = <4>;
178+
reg = <0x1700>;
179+
status = "disabled";
180+
};
181+
182+
gpio9: gpio@1800 {
183+
compatible = "renesas,rz-gpio";
184+
gpio-controller;
185+
#gpio-cells = <2>;
186+
ngpios = <5>;
187+
reg = <0x1800>;
188+
status = "disabled";
189+
};
190+
191+
gpio10: gpio@1900 {
192+
compatible = "renesas,rz-gpio";
193+
gpio-controller;
194+
#gpio-cells = <2>;
195+
ngpios = <4>;
196+
reg = <0x1900>;
197+
status = "disabled";
198+
};
199+
200+
gpio11: gpio@1a00 {
201+
compatible = "renesas,rz-gpio";
202+
gpio-controller;
203+
#gpio-cells = <2>;
204+
ngpios = <4>;
205+
reg = <0x1a00>;
206+
status = "disabled";
207+
};
208+
209+
gpio12: gpio@1b00 {
210+
compatible = "renesas,rz-gpio";
211+
gpio-controller;
212+
#gpio-cells = <2>;
213+
ngpios = <2>;
214+
reg = <0x1b00>;
215+
status = "disabled";
216+
};
217+
218+
gpio13: gpio@1c00 {
219+
compatible = "renesas,rz-gpio";
220+
gpio-controller;
221+
#gpio-cells = <2>;
222+
ngpios = <0>;
223+
reg = <0x1c00>;
224+
status = "disabled";
225+
};
226+
227+
gpio14: gpio@1d00 {
228+
compatible = "renesas,rz-gpio";
229+
gpio-controller;
230+
#gpio-cells = <2>;
231+
ngpios = <0>;
232+
reg = <0x1d00>;
233+
status = "disabled";
234+
};
235+
236+
gpio15: gpio@1e00 {
237+
compatible = "renesas,rz-gpio";
238+
gpio-controller;
239+
#gpio-cells = <2>;
240+
ngpios = <0>;
241+
reg = <0x1e00>;
242+
status = "disabled";
243+
};
244+
245+
gpio16: gpio@1f00 {
246+
compatible = "renesas,rz-gpio";
247+
gpio-controller;
248+
#gpio-cells = <2>;
249+
ngpios = <0>;
250+
reg = <0x1f00>;
251+
status = "disabled";
252+
};
253+
254+
gpio17: gpio@2000 {
255+
compatible = "renesas,rz-gpio";
256+
gpio-controller;
257+
#gpio-cells = <2>;
258+
ngpios = <0>;
259+
reg = <0x2000>;
260+
status = "disabled";
261+
};
262+
263+
gpio18: gpio@2100 {
264+
compatible = "renesas,rz-gpio";
265+
gpio-controller;
266+
#gpio-cells = <2>;
267+
ngpios = <0>;
268+
reg = <0x2100>;
269+
status = "disabled";
270+
};
271+
272+
gpio19: gpio@2200 {
273+
compatible = "renesas,rz-gpio";
274+
gpio-controller;
275+
#gpio-cells = <2>;
276+
ngpios = <0>;
277+
reg = <0x2200>;
278+
status = "disabled";
279+
};
280+
281+
gpio20: gpio@0 {
282+
compatible = "renesas,rz-gpio";
283+
gpio-controller;
284+
#gpio-cells = <2>;
285+
ngpios = <6>;
286+
reg = <0x0>;
287+
status = "disabled";
288+
};
289+
290+
gpio21: gpio@100 {
291+
compatible = "renesas,rz-gpio";
292+
gpio-controller;
293+
#gpio-cells = <2>;
294+
ngpios = <3>;
295+
reg = <0x100>;
296+
status = "disabled";
297+
};
298+
299+
gpio22: gpio@300 {
300+
compatible = "renesas,rz-gpio";
301+
gpio-controller;
302+
#gpio-cells = <2>;
303+
ngpios = <5>;
304+
reg = <0x300>;
305+
status = "disabled";
306+
};
307+
308+
gpio23: gpio@400 {
309+
compatible = "renesas,rz-gpio";
310+
gpio-controller;
311+
#gpio-cells = <2>;
312+
ngpios = <2>;
313+
reg = <0x400>;
314+
status = "disabled";
315+
};
316+
};
61317
};
62318

63319
scif0: serial@1004b800 {

‎tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.conf

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
CONFIG_SKIP_PULL_TEST=y

‎tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.overlay

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
/*
2+
* Copyright (c) 2025 Renesas Electronics Corporation
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
/ {
7+
resources {
8+
compatible = "test-gpio-basic-api";
9+
out-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
10+
in-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
11+
};
12+
};
13+
14+
&gpio5 {
15+
status = "okay";
16+
};
17+
18+
&gpio8 {
19+
status = "okay";
20+
};

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