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drivers: pwm: introduce ti_am3352_ecap
This patch adds driver support for TI ECAP module which can capture an external input or work as a standalone APWM generator. Signed-off-by: Amneesh Singh <[email protected]>
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‎drivers/pwm/CMakeLists.txt

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@@ -54,3 +54,4 @@ zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RZ_GPT pwm_renesas_rz_gpt.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SHELL pwm_shell.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_TI_AM3352_ECAP pwm_ti_am3352_ecap.c)

‎drivers/pwm/Kconfig

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@@ -122,4 +122,6 @@ source "drivers/pwm/Kconfig.fake"
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source "drivers/pwm/Kconfig.renesas_rz"
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source "drivers/pwm/Kconfig.ti_am3352_ecap"
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endif # PWM

‎drivers/pwm/Kconfig.ti_am3352_ecap

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# Copyright (c) 2025 Texas Instruments
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# SPDX-License-Identifier: Apache-2.0
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config PWM_TI_AM3352_ECAP
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bool "TI ECAP based PWM controller"
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default y
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depends on DT_HAS_TI_AM3352_ECAP_ENABLED
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help
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Enable ECAP controller for TI SoCs

‎drivers/pwm/pwm_ti_am3352_ecap.c

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/*
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* Copyright (c) 2025 Texas Instruments Incorporated
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ti_ecap);
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#define DT_DRV_COMPAT ti_am3352_ecap
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struct ti_ecap_regs {
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uint8_t RESERVED_1[0xC];
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volatile uint32_t CAP2;
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volatile uint32_t CAP3;
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volatile uint32_t CAP4;
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uint8_t RESERVED_2[0x10];
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volatile uint32_t ECCTL;
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volatile uint32_t ECINT_EN_FLG;
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volatile uint32_t ECINT_CLR_FRC;
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};
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/* ECAP Control Register */
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#define TI_ECAP_ECCTL_APWMPOL BIT(26)
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#define TI_ECAP_ECCTL_CAP_APWM BIT(25)
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#define TI_ECAP_ECCTL_SYNCO_SEL GENMASK(23, 22)
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#define TI_ECAP_ECCTL_TSCNTSTP BIT(20)
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#define TI_ECAP_ECCTL_REARM_RESET BIT(19)
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#define TI_ECAP_ECCTL_STOPVALUE GENMASK(18, 17)
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#define TI_ECAP_ECCTL_STOPVALUE_EVT3 (0x2)
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#define TI_ECAP_ECCTL_CONT_ONESHT BIT(16)
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#define TI_ECAP_ECCTL_CAPLDEN BIT(8)
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#define TI_ECAP_ECCTL_CTRRST3 BIT(5)
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#define TI_ECAP_ECCTL_CAP3POL BIT(4)
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#define TI_ECAP_ECCTL_CTRRST2 BIT(3)
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#define TI_ECAP_ECCTL_CAP2POL BIT(2)
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#define TI_ECAP_ECCTL_CTRRST1 BIT(1)
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#define TI_ECAP_ECCTL_CAP1POL BIT(0)
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/* ECAP Interrupt Enable and Flag Register */
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#define TI_ECAP_ECINT_EN_CNTOVF_FLG BIT(21)
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#define TI_ECAP_ECINT_EN_CEVT3_FLG BIT(19)
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#define TI_ECAP_ECINT_EN_CNTOVF BIT(5)
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#define TI_ECAP_ECINT_EN_CEVT3 BIT(3)
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/* ECAP Interrupt Clear and Force Register */
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#define TI_ECAP_ECINT_CLR_CNTOVF BIT(5)
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#define TI_ECAP_ECINT_CLR_CEVT3 BIT(3)
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#define TI_ECAP_ECINT_CLR_INT BIT(0)
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#define DEV_CFG(dev) ((const struct ti_ecap_cfg *)(dev)->config)
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#define DEV_DATA(dev) ((struct ti_ecap_data *)(dev)->data)
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#define DEV_REGS(dev) ((struct ti_ecap_regs *)DEVICE_MMIO_GET(dev))
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struct ti_ecap_capture_data {
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pwm_capture_callback_handler_t callback;
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void *user_data;
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bool capture_period;
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bool capture_pulse;
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bool continuous;
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};
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struct ti_ecap_cfg {
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DEVICE_MMIO_ROM;
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void (*irq_config_func)();
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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uint32_t clock_frequency;
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const struct pinctrl_dev_config *pcfg;
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};
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struct ti_ecap_data {
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DEVICE_MMIO_RAM;
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struct ti_ecap_capture_data cpt;
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};
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static int ti_ecap_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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ARG_UNUSED(channel);
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struct ti_ecap_regs *regs = DEV_REGS(dev);
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uint32_t ecctl;
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ecctl = regs->ECCTL;
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/* enable apwm and counter */
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ecctl |= (TI_ECAP_ECCTL_TSCNTSTP | TI_ECAP_ECCTL_CAP_APWM);
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/* polarity */
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if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL) {
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ecctl &= ~TI_ECAP_ECCTL_APWMPOL;
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} else {
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ecctl |= TI_ECAP_ECCTL_APWMPOL;
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}
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/* update shadow period and shadow cmp registers in apwm mode */
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regs->CAP3 = period_cycles;
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regs->CAP4 = pulse_cycles;
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/* update ecctl */
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regs->ECCTL = ecctl;
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return 0;
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}
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static int ti_ecap_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
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{
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ARG_UNUSED(channel);
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const struct ti_ecap_cfg *cfg = DEV_CFG(dev);
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if (cfg->clock_dev != NULL) {
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return clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys,
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(uint32_t *)cycles);
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}
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if (cfg->clock_frequency != 0U) {
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*cycles = cfg->clock_frequency;
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return 0;
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}
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return -ENOTSUP;
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}
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#ifdef CONFIG_PWM_CAPTURE
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static int ti_ecap_enable_capture(const struct device *dev, uint32_t channel)
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{
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ARG_UNUSED(channel);
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struct ti_ecap_capture_data *cpt = &DEV_DATA(dev)->cpt;
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struct ti_ecap_regs *regs = DEV_REGS(dev);
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/* enable interrupt for 3rd event */
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regs->ECINT_EN_FLG |= (TI_ECAP_ECINT_EN_CEVT3 | TI_ECAP_ECINT_EN_CNTOVF);
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/* start counter and enable loading capture registers */
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regs->ECCTL |= (TI_ECAP_ECCTL_TSCNTSTP | TI_ECAP_ECCTL_CAPLDEN);
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if (!cpt->continuous) {
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/* rearms one shot */
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regs->ECCTL |= TI_ECAP_ECCTL_REARM_RESET;
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}
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return 0;
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}
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static int ti_ecap_disable_capture(const struct device *dev, uint32_t channel)
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{
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ARG_UNUSED(channel);
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struct ti_ecap_regs *regs = DEV_REGS(dev);
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/* disable interrupts */
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regs->ECINT_EN_FLG &= ~(TI_ECAP_ECINT_EN_CEVT3 | TI_ECAP_ECINT_EN_CNTOVF);
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/* stop counter and disable loading capture registers */
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regs->ECCTL &= ~(TI_ECAP_ECCTL_TSCNTSTP | TI_ECAP_ECCTL_CAPLDEN);
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return 0;
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}
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static int ti_ecap_configure_capture(const struct device *dev, uint32_t channel, pwm_flags_t flags,
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pwm_capture_callback_handler_t cb, void *user_data)
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{
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ARG_UNUSED(channel);
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struct ti_ecap_capture_data *cpt = &DEV_DATA(dev)->cpt;
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struct ti_ecap_regs *regs = DEV_REGS(dev);
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uint32_t ecctl;
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cpt->callback = cb;
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cpt->user_data = user_data;
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cpt->capture_period = !!(flags & PWM_CAPTURE_TYPE_PERIOD);
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cpt->capture_pulse = !!(flags & PWM_CAPTURE_TYPE_PULSE);
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cpt->continuous = !!(flags & PWM_CAPTURE_MODE_CONTINUOUS);
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/* disable interrupts */
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regs->ECINT_EN_FLG &= ~(TI_ECAP_ECINT_EN_CEVT3 | TI_ECAP_ECINT_EN_CNTOVF);
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/* clear event flags */
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regs->ECINT_CLR_FRC |=
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(TI_ECAP_ECINT_CLR_CNTOVF | TI_ECAP_ECINT_CLR_CEVT3 | TI_ECAP_ECINT_CLR_INT);
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ecctl = regs->ECCTL;
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if (cpt->continuous) {
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/* continuous */
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ecctl &= ~TI_ECAP_ECCTL_CONT_ONESHT;
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} else {
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/* single shot */
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ecctl |= TI_ECAP_ECCTL_CONT_ONESHT;
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}
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/* we only care about first 3 events */
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ecctl &= ~TI_ECAP_ECCTL_STOPVALUE;
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ecctl |= FIELD_PREP(TI_ECAP_ECCTL_STOPVALUE, TI_ECAP_ECCTL_STOPVALUE_EVT3);
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/* configure capture timestamp to reset after edge to capture delta */
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ecctl |= (TI_ECAP_ECCTL_CTRRST1 | TI_ECAP_ECCTL_CTRRST2 | TI_ECAP_ECCTL_CTRRST3);
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if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL) {
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/* active high */
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ecctl &= ~TI_ECAP_ECCTL_CAP1POL; /* cap 1 - rising edge */
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ecctl |= TI_ECAP_ECCTL_CAP2POL; /* cap 2 - falling edge */
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ecctl &= ~TI_ECAP_ECCTL_CAP3POL; /* cap 3 - rising edge */
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} else {
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ecctl |= TI_ECAP_ECCTL_CAP1POL; /* cap 1 - falling edge */
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ecctl &= ~TI_ECAP_ECCTL_CAP2POL; /* cap 2 - rising edge */
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ecctl |= TI_ECAP_ECCTL_CAP3POL; /* cap 3 - falling edge */
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}
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/* stop counter and disable loading capture registers */
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ecctl &= ~(TI_ECAP_ECCTL_TSCNTSTP | TI_ECAP_ECCTL_CAPLDEN);
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/* enable capture mode and disable APWM */
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ecctl &= ~TI_ECAP_ECCTL_CAP_APWM;
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regs->ECCTL = ecctl;
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return 0;
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}
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#endif /* CONFIG_PWM_CAPTURE */
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static int ti_ecap_init(const struct device *dev)
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{
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const struct ti_ecap_cfg *cfg = DEV_CFG(dev);
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int ret;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("Fail to configure pinctrl\n");
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return ret;
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}
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cfg->irq_config_func();
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return 0;
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}
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static void ti_ecap_isr(const struct device *dev)
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{
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struct ti_ecap_capture_data *cpt = &DEV_DATA(dev)->cpt;
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struct ti_ecap_regs *regs = DEV_REGS(dev);
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uint32_t period = 0;
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uint32_t pulse = 0;
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uint32_t ecint_en_flg = regs->ECINT_EN_FLG;
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if (ecint_en_flg & TI_ECAP_ECINT_EN_CNTOVF_FLG) {
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if (cpt->callback != NULL) {
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cpt->callback(dev, 0, period, pulse, -ERANGE, cpt->user_data);
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}
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/* clear event */
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regs->ECINT_CLR_FRC |= TI_ECAP_ECINT_CLR_CNTOVF;
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} else if (ecint_en_flg & TI_ECAP_ECINT_EN_CEVT3_FLG) {
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uint32_t cap2 = regs->CAP2;
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uint32_t cap3 = regs->CAP3;
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if (cpt->capture_period) {
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period = cap2 + cap3;
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}
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if (cpt->capture_pulse) {
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pulse = cap2;
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}
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if (cpt->callback != NULL) {
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cpt->callback(dev, 0, period, pulse, 0, cpt->user_data);
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}
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/* clear event */
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regs->ECINT_CLR_FRC |= TI_ECAP_ECINT_CLR_CEVT3;
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}
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/* clear global interrupt */
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regs->ECINT_CLR_FRC |= TI_ECAP_ECINT_CLR_INT;
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}
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static DEVICE_API(pwm, ti_ecap_api) = {
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.set_cycles = ti_ecap_set_cycles,
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.get_cycles_per_sec = ti_ecap_get_cycles_per_sec,
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#ifdef CONFIG_PWM_CAPTURE
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.enable_capture = ti_ecap_enable_capture,
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.disable_capture = ti_ecap_disable_capture,
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.configure_capture = ti_ecap_configure_capture,
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#endif /* CONFIG_PWM_CAPTURE */
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};
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#define TI_ECAP_CLK_CONFIG(n) \
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COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(n, fck), ( \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, fck)), \
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME( \
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n, fck, clk_id), \
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.clock_frequency = 0 \
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), ( \
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.clock_dev = NULL, \
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.clock_subsys = NULL, \
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.clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 0) \
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) \
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)
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#define TI_ECAP_INIT(n) \
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static void ti_ecap_irq_config_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), ti_ecap_isr, \
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DEVICE_DT_INST_GET(n), DT_INST_IRQ(n, flags)); \
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irq_enable(DT_INST_IRQN(n)); \
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} \
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\
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static struct ti_ecap_cfg ti_ecap_config_##n = { \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
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TI_ECAP_CLK_CONFIG(n), \
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.irq_config_func = ti_ecap_irq_config_func_##n, \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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}; \
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\
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static struct ti_ecap_data ti_ecap_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, ti_ecap_init, NULL, &ti_ecap_data_##n, &ti_ecap_config_##n, \
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POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, &ti_ecap_api);
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DT_INST_FOREACH_STATUS_OKAY(TI_ECAP_INIT)

‎dts/bindings/pwm/ti,am3352-ecap.yaml

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# Copyright (c) 2025 Texas Instruments
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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description: TI SOC ECAP based PWM controller
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include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
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compatible: "ti,am3352-ecap"
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clock-frequency:
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type: int
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description: Optional peripheral frequency to use if the clock is absent
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"#pwm-cells":
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const: 3
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pwm-cells:
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- channel
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- period
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- flags

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