diff --git a/boards/st/nucleo_c092rc/Kconfig.nucleo_c092rc b/boards/st/nucleo_c092rc/Kconfig.nucleo_c092rc new file mode 100644 index 0000000000000..08155f315a4f4 --- /dev/null +++ b/boards/st/nucleo_c092rc/Kconfig.nucleo_c092rc @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_C092RC + select SOC_STM32C092XX diff --git a/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi b/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi new file mode 100644 index 0000000000000..434823b1fe273 --- /dev/null +++ b/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 4 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 4 0>, /* A4 */ + <5 0 &gpioc 5 0>, /* A5 */ + <6 0 &gpiob 7 0>, /* D0 */ + <7 0 &gpiob 6 0>, /* D1 */ + <8 0 &gpioa 10 0>, /* D2 */ + <9 0 &gpioc 7 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpioc 8 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioa 9 0>, /* D8 */ + <15 0 &gpiob 3 0>, /* D9 */ + <16 0 &gpioa 15 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_i2c: &i2c1 {}; +arduino_spi: &spi1 {}; +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_c092rc/board.cmake b/boards/st/nucleo_c092rc/board.cmake new file mode 100644 index 0000000000000..6c121eff82fac --- /dev/null +++ b/boards/st/nucleo_c092rc/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(jlink "--device=STM32C092RC" "--speed=4000") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_c092rc/board.yml b/boards/st/nucleo_c092rc/board.yml new file mode 100644 index 0000000000000..4667317a04186 --- /dev/null +++ b/boards/st/nucleo_c092rc/board.yml @@ -0,0 +1,6 @@ +board: + name: nucleo_c092rc + full_name: Nucleo C092RC + vendor: st + socs: + - name: stm32c092xx diff --git a/boards/st/nucleo_c092rc/doc/img/st_nucleo_c092rc.webp b/boards/st/nucleo_c092rc/doc/img/st_nucleo_c092rc.webp new file mode 100644 index 0000000000000..3addcf00ee2d9 Binary files /dev/null and b/boards/st/nucleo_c092rc/doc/img/st_nucleo_c092rc.webp differ diff --git a/boards/st/nucleo_c092rc/doc/index.rst b/boards/st/nucleo_c092rc/doc/index.rst new file mode 100644 index 0000000000000..3547334d43f47 --- /dev/null +++ b/boards/st/nucleo_c092rc/doc/index.rst @@ -0,0 +1,125 @@ +.. zephyr:board:: nucleo_c092rc + +Overview +******** +The STM32 Nucleo-64 development board, featuring the STM32C092RC MCU, +supports both Arduino and ST morpho connectivity, +and includes a CAN FD interface with an onboard transceiver. + +.. image:: img/st_nucleo_c092rc.webp + :align: center + :alt: Nucleo C092RC development board + +More information about the board can be found at the `Nucleo C092RC website`_. + +Hardware +******** +Nucleo C092RC provides the following hardware components: + +- STM32 microcontroller in 64-pin package featuring 256 Kbytes of Flash memory + and 30 Kbytes of SRAM. + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Current consumption measurement (IDD) + +- Five LEDs: + + - Two user LEDs (LD1, LD2), one power LED (LD3), + one STLINK LED (LD4), and one USB power fault LED (LD5) + +- Three push-buttons: USER, RESET, BOOT + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector + +- Board connectors: + + - Arduino* Uno V3 expansion connector + - ST morpho extension pin header + - CAN FD interface with on-board transceiver + +More information about STM32C092RC can be found here: +`STM32C0x1 reference manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- CAN RX/TX/STBY: PD0/PD1/PD2 +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- LD1 : PA5 +- LD2 : PC9 +- SPI1 NSS/SCK/MISO/MOSI : PA15/PA5/PA6/PA7 (Arduino SPI) +- UART_1 TX/RX : PB6/PB7 (Arduino Serial) +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- USER_PB : PC13 + + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Nucleo C092RC board includes an ST-LINK/V2-1 embedded debug tool interface. + +Applications for the ``nucleo_c092rc`` board can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, an external JLink (Software and Documentation Package Version >= v8.12e) +can also be used to flash the board using the ``--runner`` option: + +.. code-block:: console + + $ west flash --runner jlink + + +Flashing an application to Nucleo C092RC +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_c092rc + :goals: build flash + +You will see the LED blinking every second. + +References +********** + +.. target-notes:: + +.. _Nucleo C092RC website: + https://www.st.com/en/evaluation-tools/nucleo-c092rc.html + +.. _STM32C0x1 reference manual: + https://www.st.com/resource/en/reference_manual/rm0490-stm32c0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/um3353-stm32-nucleo64-board-mb2046-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_c092rc/nucleo_c092rc.dts b/boards/st/nucleo_c092rc/nucleo_c092rc.dts new file mode 100644 index 0000000000000..35e73a041510b --- /dev/null +++ b/boards/st/nucleo_c092rc/nucleo_c092rc.dts @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32C092RC-NUCLEO board"; + compatible = "st,stm32c092rc-nucleo"; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,canbus = &fdcan1; + }; + + leds: leds { + compatible = "gpio-leds"; + + green_led_1: led_1 { + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + + blue_led: led_2 { + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "User LD2"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + green_pwm_led: green_pwm_led { + pwms = <&pwm1 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "user button"; + gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; + zephyr,code = ; + }; + }; + + transceiver0: can-phy0 { + compatible = "microchip,mcp2562fd", "can-transceiver-gpio"; + standby-gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + #phy-cells = <0>; + }; + + aliases { + led0 = &green_led_1; + led1 = &blue_led; + pwm-led0 = &green_pwm_led; + sw0 = &user_button; + watchdog0 = &iwdg; + die-temp0 = &die_temp; + volt-sensor0 = &vref; + }; +}; + +&pwr { + wkup-pin@2 { + reg = <0x2>; + wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>; + }; + wkup-pin@5 { + reg = <0x5>; + wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; + }; + wkup-pin@6 { + reg = <0x6>; + wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; + }; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&rcc { + clocks = <&clk_hse>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK(APB1, 10)>, + <&rcc STM32_SRC_LSE RTC_SEL(1)>; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&timers1 { + st,prescaler = <10000>; + status = "okay"; + + pwm1: pwm { + pinctrl-0 = <&tim1_ch1_pa5>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&spi1 { + /* Note: PA5 is shared with green led0 */ + pinctrl-0 = <&spi1_nss_pa15 &spi1_sck_pa5 + &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc1 { + pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>; + pinctrl-names = "default"; + st,adc-clock-source = "ASYNC"; + clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, + <&rcc STM32_SRC_HSI ADC_SEL(2)>; + st,adc-prescaler = <4>; + status = "okay"; + vref-mv = <3300>; +}; + +&die_temp { + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; + +/* Make sure SB11, SB12, and SB13 are closed (default configuration). + * Close JP9 to enable 120 Ohm termination on the board. + */ +&fdcan1 { + clocks = <&rcc STM32_CLOCK(APB1, 12)>, + <&rcc STM32_SRC_HSE FDCAN_SEL(2)>; + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + pinctrl-names = "default"; + phys = <&transceiver0>; + status = "okay"; +}; diff --git a/boards/st/nucleo_c092rc/nucleo_c092rc.yaml b/boards/st/nucleo_c092rc/nucleo_c092rc.yaml new file mode 100644 index 0000000000000..2c85dda6f59a3 --- /dev/null +++ b/boards/st/nucleo_c092rc/nucleo_c092rc.yaml @@ -0,0 +1,24 @@ +identifier: nucleo_c092rc +name: ST Nucleo C092RC +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - can + - counter + - dma + - gpio + - i2c + - pwm + - rtc + - spi + - watchdog +ram: 30 +flash: 256 +vendor: st diff --git a/boards/st/nucleo_c092rc/nucleo_c092rc_defconfig b/boards/st/nucleo_c092rc/nucleo_c092rc_defconfig new file mode 100644 index 0000000000000..54e1485b78d79 --- /dev/null +++ b/boards/st/nucleo_c092rc/nucleo_c092rc_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable serial +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi index e5545e8b05f71..9698c990e3180 100644 --- a/dts/arm/st/c0/stm32c0.dtsi +++ b/dts/arm/st/c0/stm32c0.dtsi @@ -313,6 +313,11 @@ status = "disabled"; #pwm-cells = <3>; }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; }; timers3: timers@40000400 { @@ -330,6 +335,11 @@ status = "disabled"; #pwm-cells = <3>; }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; }; timers14: timers@40002000 { @@ -347,6 +357,11 @@ status = "disabled"; #pwm-cells = <3>; }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; }; timers16: timers@40014400 { @@ -364,6 +379,11 @@ status = "disabled"; #pwm-cells = <3>; }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; }; timers17: timers@40014800 { @@ -381,6 +401,11 @@ status = "disabled"; #pwm-cells = <3>; }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; }; i2c1: i2c@40005400 { diff --git a/dts/arm/st/c0/stm32c091.dtsi b/dts/arm/st/c0/stm32c091.dtsi new file mode 100644 index 0000000000000..5fb3f47cd5843 --- /dev/null +++ b/dts/arm/st/c0/stm32c091.dtsi @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* STM32C091 is a superset of the C071 with the exception of USB support. + * Since C071 provides the same set of peripheral as the C051, + * along with the addition of USB, once the C051 is introduced, + * it can be included instead, and the delete-node can be removed. + */ +/delete-node/ &usb; +/delete-node/ &usb_fs_phy; + +/ { + soc { + compatible = "st,stm32c091", "st,stm32c0", "simple-bus"; + + timers15: timers@40014000 { + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc STM32_CLOCK(APB1_2, 16)>; + resets = <&rctl STM32_RESET(APB1H, 16)>; + interrupts = <20 0>; + interrupt-names = "global"; + st,prescaler = <0>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + + usart3: serial@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; + resets = <&rctl STM32_RESET(APB1L, 18)>; + interrupts = <29 0>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; + resets = <&rctl STM32_RESET(APB1L, 19)>; + interrupts = <29 0>; + status = "disabled"; + }; + + dma1: dma@40020000 { + interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; + dma-requests = <7>; + }; + + dmamux1: dmamux@40020800 { + dma-channels = <7>; + dma-requests = <53>; + }; + }; +}; diff --git a/dts/arm/st/c0/stm32c091Xb.dtsi b/dts/arm/st/c0/stm32c091Xb.dtsi new file mode 100644 index 0000000000000..d1cd06a0eca21 --- /dev/null +++ b/dts/arm/st/c0/stm32c091Xb.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(36)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(128)>; + }; + }; + }; +}; diff --git a/dts/arm/st/c0/stm32c091Xc.dtsi b/dts/arm/st/c0/stm32c091Xc.dtsi new file mode 100644 index 0000000000000..4b1a595b0e238 --- /dev/null +++ b/dts/arm/st/c0/stm32c091Xc.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(36)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(256)>; + }; + }; + }; +}; diff --git a/dts/arm/st/c0/stm32c092.dtsi b/dts/arm/st/c0/stm32c092.dtsi new file mode 100644 index 0000000000000..fd90eab4215c2 --- /dev/null +++ b/dts/arm/st/c0/stm32c092.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + compatible = "st,stm32c092", "st,stm32c0", "simple-bus"; + + fdcan1: can@40006400 { + compatible = "st,stm32-fdcan"; + reg = <0x40006400 0x400>, <0x4000b400 0x350>; + reg-names = "m_can", "message_ram"; + interrupts = <30 0>, <31 0>; + interrupt-names = "int0", "int1"; + clocks = <&rcc STM32_CLOCK(APB1, 12)>; + bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/st/c0/stm32c092Xb.dtsi b/dts/arm/st/c0/stm32c092Xb.dtsi new file mode 100644 index 0000000000000..889f658029f14 --- /dev/null +++ b/dts/arm/st/c0/stm32c092Xb.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(30)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(128)>; + }; + }; + }; +}; diff --git a/dts/arm/st/c0/stm32c092Xc.dtsi b/dts/arm/st/c0/stm32c092Xc.dtsi new file mode 100644 index 0000000000000..e814ddb4be968 --- /dev/null +++ b/dts/arm/st/c0/stm32c092Xc.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(30)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(256)>; + }; + }; + }; +}; diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h index db156eff349a3..64e83494eedca 100644 --- a/include/zephyr/dt-bindings/clock/stm32c0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32c0_clock.h @@ -42,6 +42,7 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) +#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) #define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) diff --git a/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_c092rc.overlay b/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_c092rc.overlay new file mode 100644 index 0000000000000..8f0f2c9a05695 --- /dev/null +++ b/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_c092rc.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + wkup-src = &user_button; + }; +}; + +&pwr { + status = "okay"; +}; diff --git a/samples/boards/st/power_mgmt/wkup_pins/sample.yaml b/samples/boards/st/power_mgmt/wkup_pins/sample.yaml index d6d697ba15d71..8485d597317d7 100644 --- a/samples/boards/st/power_mgmt/wkup_pins/sample.yaml +++ b/samples/boards/st/power_mgmt/wkup_pins/sample.yaml @@ -6,6 +6,7 @@ tests: filter: dt_enabled_alias_with_parent_compat("wkup-src", "gpio-keys") and dt_compat_enabled("st,stm32-pwr") platform_allow: + - nucleo_c092rc - nucleo_g031k8 - nucleo_l4r5zi - nucleo_u575zi_q diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml index ce20e7d6f2f88..76fd943ad3e16 100644 --- a/soc/st/stm32/soc.yml +++ b/soc/st/stm32/soc.yml @@ -6,6 +6,8 @@ family: - name: stm32c011xx - name: stm32c031xx - name: stm32c071xx + - name: stm32c091xx + - name: stm32c092xx - name: stm32f0x socs: - name: stm32f030x6 diff --git a/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c091xx b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c091xx new file mode 100644 index 0000000000000..110a15ec0c538 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c091xx @@ -0,0 +1,12 @@ +# STMicroelectronics STM32C091xx MCU + +# Copyright (c) 2024 STMicroelectronics +# Copyright (c) 2025 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32C091XX + +config NUM_IRQS + default 30 + +endif # SOC_STM32C091XX diff --git a/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c092xx b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c092xx new file mode 100644 index 0000000000000..f1b6027792fb3 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c092xx @@ -0,0 +1,12 @@ +# STMicroelectronics STM32C092xx MCU + +# Copyright (c) 2024 STMicroelectronics +# Copyright (c) 2025 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32C092XX + +config NUM_IRQS + default 32 + +endif # SOC_STM32C092XX diff --git a/soc/st/stm32/stm32c0x/Kconfig.soc b/soc/st/stm32/stm32c0x/Kconfig.soc index adf62f3c56983..8d366a619fab5 100644 --- a/soc/st/stm32/stm32c0x/Kconfig.soc +++ b/soc/st/stm32/stm32c0x/Kconfig.soc @@ -22,7 +22,17 @@ config SOC_STM32C071XX bool select SOC_SERIES_STM32C0X +config SOC_STM32C091XX + bool + select SOC_SERIES_STM32C0X + +config SOC_STM32C092XX + bool + select SOC_SERIES_STM32C0X + config SOC default "stm32c011xx" if SOC_STM32C011XX default "stm32c031xx" if SOC_STM32C031XX default "stm32c071xx" if SOC_STM32C071XX + default "stm32c091xx" if SOC_STM32C091XX + default "stm32c092xx" if SOC_STM32C092XX diff --git a/tests/drivers/adc/adc_api/boards/nucleo_c092rc.overlay b/tests/drivers/adc/adc_api/boards/nucleo_c092rc.overlay new file mode 100644 index 0000000000000..213402933affd --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/nucleo_c092rc.overlay @@ -0,0 +1,26 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2025 STMicroelectronics + * Copyright (c) 2025 Thomas Stranger + */ + +/ { + zephyr,user { + /* adjust channel number according to pinmux in board.dts */ + io-channels = <&adc1 0>; + }; +}; + +&adc1 { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/nucleo_c092rc.overlay b/tests/drivers/counter/counter_basic_api/boards/nucleo_c092rc.overlay new file mode 100644 index 0000000000000..841b7b212fbed --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/nucleo_c092rc.overlay @@ -0,0 +1,41 @@ +&timers2 { + st,prescaler = <79>; + counter { + status = "okay"; + }; +}; + +&timers3 { + st,prescaler = <79>; + counter { + status = "okay"; + }; +}; + +&timers14 { + st,prescaler = <79>; + counter { + status = "okay"; + }; +}; + +&timers15 { + st,prescaler = <79>; + counter { + status = "okay"; + }; +}; + +&timers16 { + st,prescaler = <79>; + counter { + status = "okay"; + }; +}; + +&timers17 { + st,prescaler = <79>; + counter { + status = "okay"; + }; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay new file mode 100644 index 0000000000000..ac4070fe63372 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&usart4 { + /* available on ST morpho connector CN10 pins 4 and 22 */ + pinctrl-0 = <&usart4_tx_pc1 &usart4_rx_pc0>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + + +dut: &usart4 { + dmas = <&dmamux1 5 57 STM32_DMA_PERIPH_TX>, + <&dmamux1 6 56 STM32_DMA_PERIPH_RX>; + dma-names = "tx", "rx"; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +};