Skip to content
View SudeepJoshi22's full-sized avatar

Organizations

@RVECE-A-RISC-V-Community

Block or report SudeepJoshi22

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
SudeepJoshi22/README.md
  • 👋 Hi, I’m @SudeepJoshi22
  • 👀 I’m interested in ... Computer Architecture, VLSI, and Analog Electronics
  • 🌱 I’m currently learning ... RISC-V ISA and Microarchitecures
  • 💞️ I’m looking to collaborate on ... RISC-V projects
  • 📫 How to reach me ... follow me on Linkedin: https://www.linkedin.com/in/sudeep-joshi-569951207/

Popular repositories Loading

  1. Minor-Project-2023-RISC-V-processor Minor-Project-2023-RISC-V-processor Public

    Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our…

    Verilog 11 1

  2. DHRUT-V DHRUT-V Public

    5-Stage Pipelined Custom RISC-V core

    Verilog 2

  3. CORDIC-Unit CORDIC-Unit Public

    CORDIC Unit Design and Synthesis Using Verilog HDL and YOSYS

    Python 1

  4. Small_Projects Small_Projects Public

    C 1

  5. FFT_HARDWARE FFT_HARDWARE Public

    FFT Hardware written in TL-Verilog.

    Verilog 1

  6. cocotb-tutorial cocotb-tutorial Public

    Learning Cocotb

    Python 1