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Update tb.v #25

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b0eceb5
Update tb.v
JorgeArias8644 Jun 3, 2025
7baf71b
Update Makefile
JorgeArias8644 Jun 3, 2025
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2 changes: 1 addition & 1 deletion test/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
SIM ?= icarus
TOPLEVEL_LANG ?= verilog
SRC_DIR = $(PWD)/../src
PROJECT_SOURCES = project.v
PROJECT_SOURCES = tt_um_JorgeArias8644.v alu_1bit.v alu_8bit.v mux2.v mux4.v xor3a1n.v CLA.v

ifneq ($(GATES),yes)

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2 changes: 1 addition & 1 deletion test/tb.v
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Expand Up @@ -24,7 +24,7 @@ module tb ();
wire [7:0] uio_oe;

// Replace tt_um_example with your module name:
tt_um_example user_project (
tt_um_JorgeArias8644 user_project (
.ui_in (ui_in), // Dedicated inputs
.uo_out (uo_out), // Dedicated outputs
.uio_in (uio_in), // IOs: Input path
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