update proyect

docs/info.md

@@ -9,12 +9,27 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+Este proyecto implementa un multiplexor de 4 a 1 en Verilog, que permite seleccionar una de cuatro señales de entrada (d0, d1, d2, d3) mediante una señal de control de 2 bits (s).
+La placa Basys 3 utiliza una FPGA Xilinx Artix-7, por lo que el multiplexor puede ser sintetizado y probado en hardware real. Al asignar s, la salida mux4_out tomará el valor de la entrada correspondiente.
+El multiplexor puede ser útil en diversas aplicaciones, como selección de datos en sistemas digitales, procesadores, o manejo de señales en módulos más grandes.
+
 
 ## How to test
 
-Explain how to use your project
+Para probar el módulo en la Basys 3:
+- Conexión de entradas y salidas:
+- Asignar d0-d3 a los switches (SW0-SW3) de la Basys 3.
+- Asignar s[1] y s[0] a los switches (SW4-SW5) para controlar la selección de entrada.
+- Dirigir mux4_out a un LED para visualizar el resultado.
+- Compilación y síntesis:
+- Escribir el código en Vivado.
+- Implementar la síntesis y programar la FPGA con el archivo bitstream generado.
+- Pruebas funcionales:
+- Cambiar los valores de los switches y verificar que la salida en el LED corresponde con el comportamiento esperado del multiplexor.
+
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+- Basys 3 FPGA Board
+- Built-in LEDs (para visualizar la salida mux4_out)
+- Built-in switches (para manejar las entradas d0-d3 y selección s)

info.yaml

@@ -1,39 +1,44 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
+  title:        "alu_8_bits"      # Project title
+  author:       "Jorge"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
+  description:  "ALU de 8 bits 4 funciones"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_JorgeArias8644"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "project.v"
+    - "tt_um_JorgeArias8644.v"
+    - "alu_1bit.v"
+    - "CLA.v"
+    - "mux2.v"
+    - "mux4.v"
+    - "xor3a1n.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
+  ui[0]: "[7:0]a"
+  ui[1]: "[7:0]b"
+  ui[2]: "[1:0]S"
+  ui[3]: "clk"
   ui[4]: ""
   ui[5]: ""
   ui[6]: ""
   ui[7]: ""
 
   # Outputs
-  uo[0]: ""
+  uo[0]: "[7:0] Result"
   uo[1]: ""
   uo[2]: ""
   uo[3]: ""

src/CLA.v

@@ -0,0 +1,19 @@
+module CLA (                         // Carry Lookahead Adder 1-bit
+            input  a,                // Input vaiable a
+            input  b,                // Input variable b
+            input  Cin,              // Input variable Carry In          
+            output Sum,              // Output variable resultado de la suma
+            output Cout              // Output variable de carry out
+            );
+
+    wire G;                          // Generate
+    wire P;                          // Propagate
+
+    assign G = a & b;
+    assign P = a ^ b;
+
+    assign Sum = P ^ Cin;
+
+    assign Cout = G | (P & Cin);
+
+endmodule

src/alu_1bit.v

@@ -0,0 +1,27 @@
+module alu_1bit(
+                input  at,bt,
+                input  [1:0]ALUcontrol,
+                output result
+               );
+           wire int1,int2,int3,sum_out,cout_sum,mym;
+          //  reg n;
+
+           assign int1 = at & bt;
+           assign int2 = at | bt;
+           assign int3 = ~bt;
+
+   // Instanciando multiplexor de dos entradas a 1 salida con selector de 1 bit
+   mux2 mux2_1(.d0(bt),.d1(int3),.mux2_out(mym),.s(ALUcontrol[0]));
+   // Instanciando Sumador de tipo Carry Lookahead Adder
+   CLA Carry_Lookahead_Adder(.a(at),.b(mym),.Cin(ALUcontrol[0]),.Sum(sum_out),.Cout(cout_sum));
+   // Instanciando multiplexor de 4 entradas a 1 salida con selector de 2 bits
+   mux4 mux4_1(.d0(sum_out),.d1(sum_out),.d2(int1),.d3(int2),.mux4_out(result),.s(ALUcontrol));
+   // Instanciando compuerta XOR de 3 entradas y 1 salida negativa
+ //  xor_3a1n xor31 (.a1(at),.a2(bt),.a3(ALUcontrol[0]),.y2(V));
+
+/*    always @* begin 
+       Z = ~& result;
+       C = ~ALUcontrol[1] & cout_sum;
+    end
+*/                
+endmodule

src/alu_8bits.v

@@ -0,0 +1,23 @@
+module alu_8bits(
+                      input  [7:0]  a, // input a
+                      input  [15:8] b, // input b
+                      input  [1:0]  S, // input ALU control
+                      output [7:0]  Result //output Resultado de las operaciones
+                      );
+    // Instanciando ALU 1-bit para el bit 0
+    alu_1bit alu_bit0(.at(a[0]),.bt(b[8]),.ALUcontrol(S),.result(Result[0]));
+    // Instanciando ALU 1-bit para el bit 1
+    alu_1bit alu_bit1(.at(a[1]),.bt(b[9]),.ALUcontrol(S),.result(Result[1]));    
+    // Instanciando ALU 1-bit para el bit 2
+    alu_1bit alu_bit2(.at(a[2]),.bt(b[10]),.ALUcontrol(S),.result(Result[2]));    
+    // Instanciando ALU 1-bit para el bit 3
+    alu_1bit alu_bit3(.at(a[3]),.bt(b[11]),.ALUcontrol(S),.result(Result[3]));    
+    // Instanciando ALU 1-bit para el bit 4
+    alu_1bit alu_bit4(.at(a[4]),.bt(b[12]),.ALUcontrol(S),.result(Result[4]));    
+    // Instanciando ALU 1-bit para el bit 5
+    alu_1bit alu_bit5(.at(a[5]),.bt(b[13]),.ALUcontrol(S),.result(Result[5]));    
+    // Instanciando ALU 1-bit para el bit 6
+    alu_1bit alu_bit6(.at(a[6]),.bt(b[14]),.ALUcontrol(S),.result(Result[6]));    
+    // Instanciando ALU 1-bit para el bit 7
+    alu_1bit alu_bit7(.at(a[7]),.bt(b[15]),.ALUcontrol(S),.result(Result[7]));  
+endmodule

src/mux2.v

@@ -0,0 +1,9 @@
+// Multiplexor de 2 entradas a una salida con selector
+module mux2(
+            input d0, d1,
+            input s,
+            output mux2_out
+            );
+
+       assign mux2_out = s ? d1 : d0;
+endmodule

src/mux4.v

@@ -0,0 +1,10 @@
+// Multiplexor de 4 entradas, 1 salida y selector de entrada de 2 bits
+
+module mux4(
+             input d0,d1,d2,d3,
+             input [1:0]s,
+             output mux4_out 
+            );
+           assign mux4_out = s[1] ? (s[0]?d3:d2)
+                                  : (s[0]?d1:d0);
+endmodule

src/tt_um_JorgeArias8644.v

@@ -0,0 +1,35 @@
+`default_nettype none
+`include "alu_8bits.v"
+module tt_um_JorgeArias8644 (
+    input  wire [7:0] ui_in,
+    output wire [7:0] uo_out,
+    input  wire [7:0] uio_in,
+    output wire [7:0] uio_out,
+    output wire [7:0] uio_oe,
+    input  wire clk,
+    input  wire ena,
+    input  wire rst_n
+);
+
+    // Señales internas
+    wire [7:0] a = ui_in;         // A y B son iguales aquí
+    wire [7:0] b = ui_in;
+    wire [1:0] S = ui_in[1:0];    // Selector de operación
+    wire [7:0] R;                 // Resultado de la ALU
+
+    // Instancia del módulo ALU
+    alu_8bits alu_inst (
+        .a(a),
+        .b(b),
+        .S(S),
+        .Result(R)
+    );
+
+    // Asignación de salida
+    assign uo_out = R;
+
+    // No se usan los pines uio, se ponen en alta impedancia
+    assign uio_out = 8'b0;
+    assign uio_oe  = 8'b0;
+
+endmodule

src/xor3a1n.v

@@ -0,0 +1,5 @@
+module xor_3a1n(input a1,a2,a3,output y2);
+             wire y1;
+                    assign y1 = a1 ^ a2;
+                    assign y2 = ~(y1 ^ a3);
+endmodule

test/Makefile

@@ -1,42 +1,40 @@
 # Makefile
-# See https://docs.cocotb.org/en/stable/quickstart.html for more info
+# Simulación con Cocotb
 
-# defaults
+# Configuración por defecto
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+
+# Lista de archivos Verilog del proyecto
+PROJECT_SOURCES = ../src/tt_um_JorgeArias8644.v ../src/alu_8bit.v ../src/alu_1bit.v ../src/mux2.v ../src/mux4.v ../src/CLA.v ../src/xor3a1n.v
 
 ifneq ($(GATES),yes)
 
-# RTL simulation:
-SIM_BUILD				= sim_build/rtl
+# Simulación RTL
+SIM_BUILD = sim_build/rtl
 VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
 
 else
 
-# Gate level simulation:
-SIM_BUILD				= sim_build/gl
-COMPILE_ARGS    += -DGL_TEST
-COMPILE_ARGS    += -DFUNCTIONAL
-COMPILE_ARGS    += -DSIM
+# Simulación a nivel de compuertas
+SIM_BUILD = sim_build/gl
+COMPILE_ARGS += -DGL_TEST -DFUNCTIONAL -DSIM
 VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
 VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v
-
-# this gets copied in by the GDS action workflow
 VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
 
 endif
 
-# Allow sharing configuration between design and testbench via `include`:
-COMPILE_ARGS 		+= -I$(SRC_DIR)
+# Compartir configuración entre diseño y testbench
+COMPILE_ARGS += -I$(SRC_DIR)
 
-# Include the testbench sources:
+# Incluir el testbench
 VERILOG_SOURCES += $(PWD)/tb.v
-TOPLEVEL = tb
+TOPLEVEL = tt_um_JorgeArias8644
 
-# MODULE is the basename of the Python test file
+# Archivo de prueba en Python
 MODULE = test
 
-# include cocotb's make rules to take care of the simulator setup
+# Incluir reglas de Cocotb
 include $(shell cocotb-config --makefiles)/Makefile.sim

test/tb.v

@@ -14,17 +14,16 @@ module tb ();
   end
 
   // Wire up the inputs and outputs:
-  reg clk;
-  reg rst_n;
-  reg ena;
-  reg [7:0] ui_in;
-  reg [7:0] uio_in;
-  wire [7:0] uo_out;
-  wire [7:0] uio_out;
-  wire [7:0] uio_oe;
+input  [7:0] ui_in,
+output [7:0] uo_out,
+input  [7:0] uio_in,
+output [7:0] uio_oe,
+input clk,
+input ena,
+input rst_n
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_JorgeArias8644 (
       .ui_in  (ui_in),    // Dedicated inputs
       .uo_out (uo_out),   // Dedicated outputs
       .uio_in (uio_in),   // IOs: Input path

test/test.py

@@ -1,40 +1,38 @@
-# SPDX-FileCopyrightText: © 2024 Tiny Tapeout
-# SPDX-License-Identifier: Apache-2.0
-
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import ClockCycles
-
-
-@cocotb.test()
-async def test_project(dut):
-    dut._log.info("Start")
-
-    # Set the clock period to 10 us (100 KHz)
-    clock = Clock(dut.clk, 10, units="us")
-    cocotb.start_soon(clock.start())
-
-    # Reset
-    dut._log.info("Reset")
-    dut.ena.value = 1
-    dut.ui_in.value = 0
-    dut.uio_in.value = 0
-    dut.rst_n.value = 0
-    await ClockCycles(dut.clk, 10)
-    dut.rst_n.value = 1
-
-    dut._log.info("Test project behavior")
-
-    # Set the input values you want to test
-    dut.ui_in.value = 20
-    dut.uio_in.value = 30
-
-    # Wait for one clock cycle to see the output values
-    await ClockCycles(dut.clk, 1)
-
-    # The following assersion is just an example of how to check the output values.
-    # Change it to match the actual expected output of your module:
-    assert dut.uo_out.value == 50
-
-    # Keep testing the module by changing the input values, waiting for
-    # one or more clock cycles, and asserting the expected output values.
+`default_nettype none
+`timescale 1ns / 1ps
+
+/* This testbench just instantiates the module and makes some convenient wires
+   that can be driven / tested by the cocotb test.py.
+*/
+module tb ();
+
+  // Dump the signals to a VCD file. You can view it with gtkwave or surfer.
+  initial begin
+    $dumpfile("tb.vcd");
+    $dumpvars(0, tb);
+    #1;
+  end
+
+  // Wire up the inputs and outputs:
+  reg clk;
+  reg rst_n;
+  reg ena;
+  reg [7:0] ui_in;
+  reg [7:0] uio_in;
+  wire [7:0] uo_out;
+  wire [7:0] uio_out;
+  wire [7:0] uio_oe;
+
+  // Replace tt_um_example with your module name:
+  tt_um_example user_project (
+      .ui_in  (ui_in),    // Dedicated inputs
+      .uo_out (uo_out),   // Dedicated outputs
+      .uio_in (uio_in),   // IOs: Input path
+      .uio_out(uio_out),  // IOs: Output path
+      .uio_oe (uio_oe),   // IOs: Enable path (active high: 0=input, 1=output)
+      .ena    (ena),      // enable - goes high when design is selected
+      .clk    (clk),      // clock
+      .rst_n  (rst_n)     // not reset
+  );
+
+endmodule