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@dlech dlech commented Jun 5, 2025

PR Description

Add pullup to I2C1 SDA/SCL pins in the ad411x_ad717x project. These are connected to an EEPROM on the EVAL board. Neither the DE10-Nano or the EVAL board has pullup resistors on this bus, so we need to do the pullup in the FPGA.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

Add pullup to I2C1 SDA/SCL pins in the ad411x_ad717x project. These are
connected to an EEPROM on the EVAL board. Neither the DE10-Nano or the
EVAL board has pullup resistors on this bus, so we need to do the pullup
in the FPGA.

Signed-off-by: David Lechner <[email protected]>
@dlech dlech requested review from sarpadi and PIoandan as code owners June 5, 2025 17:32
@gastmaier
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Was this tested?
My understanding is that even if there is no resistor soldered, there are DNI slots to solder, either in the eval or carrier.
(I need to look the schematics)

@dlech
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dlech commented Jun 5, 2025

I see. It is on the DE10-Nano board. (I don't see anything like that on the eval board.)

image

So we expect everyone to solder on the resistors?

@dlech
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dlech commented Jun 5, 2025

And yes, I did test with Linux. Without this change, communication fails (logic analyzer shows both SDA and SCL signals always low). With the change, I am able to read from the EEPROM.

root@de10-nano-dlech:~# cat /sys/bus/i2c/devices/1-0056/1-00560/nvmem 
ADISDP�e`q�xEVAL-AD4112SDZ�AD4112 Evaluation Board60657100000000B8'6060eb1f-7535-4edb-b9f9-a1f8bf52b6c4

@gastmaier
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So if it works I leave to the maintainers decide hehe
IMO if there is DNI in the eval, yes.

I promptly replied because when I started messing with i3c my conclusion was that the fpga pull-up was too weak to provide a rising time small to be reliable sampled at the clock edge. But I believe that conclusion was for the Coraz7. If it works with de10nano, cool.

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2 participants