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Pull requests: llvm/circt

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Pull requests list

[Moore] Add WaitDelayOp, support delay control in ImportVerilog ImportVerilog Moore
#8884 opened Aug 23, 2025 by fabianschuiki Loading…
[Moore] Add more precise conversion ops ImportVerilog Moore
#8883 opened Aug 22, 2025 by fabianschuiki Loading…
[FSMToSMT]
#8882 opened Aug 22, 2025 by luisacicolini • Draft
[circt-synth] Parallel Prefix Lowering Performance Bug Fix
#8881 opened Aug 22, 2025 by cowardsa Loading…
1
[ESI] Add serde capabilities to ESI C++ runtime types ESI
#8879 opened Aug 21, 2025 by mortbopet Loading…
11
[FIRRTL] Add InferDomains pass
#8877 opened Aug 20, 2025 by seldridge • Draft
[LLHD] Remove redundant destination operands from wait operation
#8870 opened Aug 18, 2025 by mvpant • Draft
1
[circt-opt] Add pass --convert-core-to-fsm
#8852 opened Aug 14, 2025 by AtticusKuhn Loading…
18
[SV] Remove extract-test-code
#8846 opened Aug 12, 2025 by rwy7 Loading…
5
[FIRRTL] Domains: Operation Approach
#8843 opened Aug 12, 2025 by seldridge Loading…
12
Add check for casting bundle with elements in different directions
#8750 opened Jul 21, 2025 by unlsycn Loading…
1
Inline input-only modules
#8739 opened Jul 18, 2025 by rwy7 • Draft
1
[hw] Add container op
#8704 opened Jul 14, 2025 by seldridge Loading…
2
Remove single state restriction on FSM to SV
#8665 opened Jul 8, 2025 by jpienaar Loading…
3
[ImportVerilog][CAPI] Add interfaces to allow external use
#8563 opened Jun 13, 2025 by SpriteOvO • Draft
3
[hw] Add hw.donttouch operation
#8547 opened Jun 9, 2025 by seldridge Loading…
13
[CMake] Allow Python discovery from virtual environment
#8520 opened May 30, 2025 by hamidelmaazouz Loading…
5
[SharedResourcesProblem] [Simplex Scheduler] Simplex scheduler deals with multiple resource constraints
#8480 opened May 13, 2025 by jiahanxie353 Loading…
3
[SCFToCalyx] Modify top-level function in place and propagate external memory allocations
#8446 opened Apr 25, 2025 by jiahanxie353 Loading…
[ci] Bump CI images
#8445 opened Apr 25, 2025 by seldridge Loading…
3
[ImportVerilog] Convert the unpacked array to a simple bit vector
#8392 opened Apr 4, 2025 by AnnuCode Loading…
2
When replacing a register with its reset value, attempt width coercion FIRRTL Involving the `firrtl` dialect
#8379 opened Apr 1, 2025 by rwy7 Loading…
[ImportVerilog]add support for String literal operations
#8309 opened Mar 10, 2025 by ChenXo0 • Draft
2
Add a few mux-of-const and reg-of-and/or canonicalizers. FIRRTL Involving the `firrtl` dialect
#8307 opened Mar 7, 2025 by rwy7 Loading…
18
[circt-verilog-lsp] Add hover support
#8304 opened Mar 6, 2025 by uenoku Loading…
4
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