Routing Failure When Mapping Adders in benchmark_sweep/vtr_benchmarks Task

[code-joswin]

Hi @tangxifan ,

I’m currently running the benchmark_sweep/vtr_benchmarks task using the below custom architecture that includes mapped adders. My goal is to utilize the carry adder chains defined in the following architecture files:

arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml

The default configuration in the [SYNTHESIS_PARAM] section of the task.conf file of this task maps bram and dsp (mult_36). I am trying to include the adder map by including the following line in task.conf:
bench_yosys_adder_map_verilog_common=${PATH:OPENFPGA_PATH}/work_openfpga/openfpga_yosys_techlib/openfpga_arith_map.v

I’ve also added the adder module definition manually into:
${PATH:OPENFPGA_PATH}/work_openfpga/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v

In the synthesis script (bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys), I inserted the following block (after mapping multipliers and before coarse synthesis):

#Map Adders 
wreduce t:$add  # Break down wide adders into 1-bit operations
stat -width
techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
stat -width
opt -fast -nodffe -nosdff
opt_expr
opt_merge
opt_clean
opt -nodffe -nosdff

The benchmark I'm running is:
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v

Issue:

The synthesis runs successfully, but during the repack stage of VPR, I encounter the following error in vpr_stdout.log:

No possible routing path from 'adder[1].sumout[0]' to 'ff[1].D[0]': needed for net '$auto$maccmap.cc:245:synth$34522[0]' from net pin '$auto$maccmap.cc:240:synth$34521.CARRY[1].sumout[0]' to net pin 'wrapper_norm_corr_20_inst_p.corr_20_inst.inst_corr_20.lrexrre_reg[0].D[0]'
Routing was impossible from source pin 'clb[0]/fle[0]/fabric[0]/adder[1].sumout[0]' to sink pin 'clb[0]/fle[0]/fabric[0]/ff[1].D[0]'!
Routing failed for sink pin 'clb[0]/fle[0]/fabric[0]/ff[1].D[0]'!
Net 37 '$auto$maccmap.cc:245:synth$34522[0]' is impossible to route within proposed clb cluster
Net source pin:
clb[0]/fle[0]/fabric[0]/adder[1].sumout[0]
Net sink pins:
clb[0]/fle[0]/fabric[0]/ff[1].D[0]
Please check your architecture XML to see if it is routable
Reroute failed

From the Pb type usage stats in the same log, I can see that the adder blocks are being mapped:

Pb types usage...
  io                   : 278
   inpad               : 133
   outpad              : 145
  clb                  : 846
   fle                 : 7759
    ble5               : 10304
     lut5              : 7033
      lut              : 7033
     ff                : 9944
    arithmetic         : 2365
     lut4              : 44
      lut              : 44
     adder             : 2365
     ff                : 1228
    ble6               : 790
     lut6              : 790
      lut              : 790
     ff                : 617
  mult_36              : 152
   mult_36x36_slice    : 152
    mult_36x36         : 152

However, the error relates specifically to routing between the adder and FF within the fabric, not inside the arithmetic block.

This routing failure only occurs with more complex benchmarks like stereovision1. Simpler benchmarks like stereovision3 do not exhibit this issue.

Request:

Could you help diagnose this issue? It seems related to intra-CLB routing between adder and ff blocks inside the fabric block. I’ve reviewed the architecture XML but couldn’t identify a connectivity or pin-class issue.

I would appreciate your guidance on resolving this so I can use the adder chains defined in my architecture effectively.

Thanks in advance!