Routing Failure During Repack in VPR while Mapping Adder Chains.

[code-joswin]

Describe the bug
While mapping the stereovision1 benchmark RTL in the fpga_verilog/adder/hard_adder task, I am facing an error during the repack phase in VPR. The error seen in vpr_stdout.log looks as follows:

No possible routing path from 'adder[1].sumout[0]' to 'ff[1].D[0]': needed for net '$auto$maccmap.cc:245:synth$33499[0]' from net pin '$auto$maccmap.cc:240:synth$33498.CARRY[1].sumout[0]' to net pin 'wrapper_norm_corr_20_inst_p.corr_20_inst.inst_corr_12.limxrim_reg[0].D[0]'
Routing was impossible from source pin 'clb[0]/fle[0]/fabric[0]/adder[1].sumout[0]' to sink pin 'clb[0]/fle[0]/fabric[0]/ff[1].D[0]'!
Routing failed for sink pin 'clb[0]/fle[0]/fabric[0]/ff[1].D[0]'!
Net 37 '$auto$maccmap.cc:245:synth$33499[0]' is impossible to route within proposed clb cluster
	Net source pin:
		clb[0]/fle[0]/fabric[0]/adder[1].sumout[0]
	Net sink pins:
		clb[0]/fle[0]/fabric[0]/ff[1].D[0]
Please check your architecture XML to see if it is routable
Reroute failed

To Reproduce
Steps to reproduce the behavior:

1. Execute OpenFPGA task:

• fpga_verilog/adder/hard_adder
• use this benchmark in the task.conf file: bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v
  bench1_top = sv_chip1_hierarchy_no_mem
• added --verbose switch to the repack command in the file: openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
  which is defined again in task.conf file of the task.

Expected behavior
The above mentioned error can be seen in vpr_stdout.log and openfpgashell.log files

Additional context
The issue is seen whenever I am trying to map complex benchmark RTL's to adders chains which are defined in the VPR XML, specifically the adder chain defined under mode in the VPR XML. Another way to reproduce this issue is highlighted in: [https://github.com//discussions/2010]

Could you please look into this and suggest any fix?