drivers: flash: stm32_qspi: Fix configuration & erase in dual-flash mode #93234
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In multiple places, "#if DT_PROP(DT_NODELABEL(quadspi), dual_flash) && defined(QUADSPI_CR_DFM)" was used to guard sections specific to the dual-flash feature. This is quite long and "#ifdef STM32_QSPI_DOUBLE_FLASH" is now used instead. Note the presence of QUADSPI_CR_DFM is no more checked. This is not considered as an issue since when QUADSPI_CR_DFM is not available, the QSPI hardware doesn't support dual-flash mode so this mode must not be enabled in the devicetree. With that change, enabling dual-flash mode when not available causes a compile-time error. Signed-off-by: Thomas Altenbach <[email protected]>
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This was referenced Jul 17, 2025
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The 'qspi_read_status_register' routine implements the reading of a flash memory's status register. This routine is used anytime reading a status register is needed, except in 'qspi_wait_until_ready'. This commit moves the read routine to be able to use it in 'qspi_wait_until_ready'. The 'qspi_write_status_register' is also moved to keep it close to the read routine. Signed-off-by: Thomas Altenbach <[email protected]>
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@FRASTM Thanks for reviewing and testing! I applied your suggestion :) |
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@etienne-lms @GeorgeCGV Suggested changes applied |
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When dual-flash mode is enabled, two identical flash memories are connected to the QUADSPI peripheral, each having its own set of registers. This means that when reading or writing a flash register, this has to be made for both flash memories. For example, when reading a status register (1 byte), the QUADSPI peripheral must be configured to read two bytes of data, which correspond respectively to the value of the register in the first and second flash memory. Same thing when writing. Before this commit, when dual-flash mode was enabled, only the register of the first flash memory was considered, which means the second flash memory could be incorrectly configured and that any write/erase operation could be considered as completed too early, if the operation takes more time to complete for the second flash memory. Signed-off-by: Thomas Altenbach <[email protected]>
When dual-flash mode is enabled, even bytes are written to the first flash memory and odd bytes to the second flash memory. This means, from the flash driver's point of view, the size of a flash page is twice the size of a single flash memory's page. So if each flash memory has 256-byte pages, 512 bytes should be used as page size by the flash driver. Using 256 bytes was working fine but is suboptimal. Signed-off-by: Thomas Altenbach <[email protected]>
When dual-flash mode is enabled, any erase operation is executed on both flash memories in parallel. This means from the flash driver's point of view, the size of a given sector/block is twice the size of a sector/block on a single flash memory. For example, assuming 4-KiB sectors for each flash memory, if the flash driver is asked to erase at address 0x0000, the erase size must be a multiple of 8 KiB since each sector erase operation will cause a 4-KiB sector to erased in each flash memory. Before this commit, the doubled erase size was only considered in 'setup_pages_layout'. Now, the actual sizes of the erase operations are properly set in the flash driver's data and are used everywhere in the driver. Signed-off-by: Thomas Altenbach <[email protected]>
When a board contains two identical flash memories configured in parallel dual-flash mode, the actual sector size is twice the sector size of a single flash memory. So, assuming 4-KiB sectors for each flash memory, any erase operation must be 8-KiB aligned. This commit updates the start offset and sector size in the spi_flash sample to be properly aligned when a dual-flash configuration is used. At the moment, this is only supported for STM32-based boards and QSPI flash memories. Signed-off-by: Thomas Altenbach <[email protected]>
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JarmouniA
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Jul 22, 2025
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Jul 22, 2025
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Removing the backport tag. Eventhough it has been carefully and reviewed, I prefer to remain on the safe side and avoid disturbing v4.2.0 with this for now. |
erwango
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Jul 23, 2025
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When dual-flash mode is enabled, two identical flash memories are connected to the QUADSPI peripheral and are accessed in parallel. This means in particular that:
That was not properly handled by the QSPI flash driver, which might lead to errors when reading, erasing or programming data. In particular, this fixes #93153.
The changes were tested on a STM32H747I-DISCO board, in both single- and dual-flash configuration. It was ensured that the
drivers/spi_flashsample runs without errors and that the status register can be properly read/written.