Microchip sama7g5 tc driver #93401

MCHP-MPU-Solutions-SHA · 2025-07-21T05:15:42Z

Add tc driver and device for Microchip sama7g5

Copilot

Pull Request Overview

This PR adds Timer Counter (TC) driver support for the Microchip SAMA7G5 SoC. The implementation provides a counter driver with alarm and top value functionality for embedded timer applications.

Key changes include:

New TC counter driver implementation with alarm channels and top value support
Device tree bindings and hardware definitions for TC0 and TC1 timer blocks
PMC clock configuration for TC channels in early SoC initialization

Reviewed Changes

Copilot reviewed 9 out of 9 changed files in this pull request and generated 4 comments.

Show a summary per file

File	Description
drivers/counter/counter_mchp_sam_tc.c	Complete TC driver implementation with counter, alarm, and top value APIs
dts/bindings/counter/microchip,sam-tc.yaml	Device tree binding specification for TC hardware configuration
dts/arm/microchip/sam/sama7g5.dtsi	Hardware definitions for TC0/TC1 timer blocks with 6 channels total
soc/microchip/sam/sama7g5/soc.c	MMU regions and PMC clock initialization for TC peripherals
drivers/counter/Kconfig.mchp_sam_tc	Kconfig option for enabling the TC driver
drivers/counter/Kconfig	Integration of TC driver Kconfig
drivers/counter/CMakeLists.txt	Build system integration for TC driver
samples/drivers/counter/alarm/src/main.c	Sample application support for TC counter
boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts	Board-specific TC channel enablement and clock configuration

Copilot · 2025-07-21T05:53:13Z

drivers/counter/counter_mchp_sam_tc.c

+	USEC_PER_SEC,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128,
+	DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency),
+	USEC_PER_SEC,
+	USEC_PER_SEC,
+	USEC_PER_SEC,


The sam_tc_input_freq_table array contains hardcoded frequency values that may not be accurate for all configurations. Consider making this configurable or deriving values from device tree properties to improve maintainability across different board configurations.

Suggested change

USEC_PER_SEC,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128,

DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency),

USEC_PER_SEC,

USEC_PER_SEC,

USEC_PER_SEC,

DT_PROP(DT_PATH(clocks, main_clk), clock_frequency), /* Main clock frequency */

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8, /* MCK1 divided by 8 */

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32, /* MCK1 divided by 32 */

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128, /* MCK1 divided by 128 */

DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency), /* Slow crystal frequency */

DT_PROP(DT_PATH(clocks, main_clk), clock_frequency), /* Main clock frequency (fallback) */

DT_PROP(DT_PATH(clocks, main_clk), clock_frequency), /* Main clock frequency (fallback) */

DT_PROP(DT_PATH(clocks, main_clk), clock_frequency), /* Main clock frequency (fallback) */

Remember that mck1 must be fixed at compile time and can not change during runtime.

Many thanks for review.
Got it, and codes has been updated with the Copilot's comments.

Following @TonyHan11 suggestions, all hard-coded clock frequencies has been removed from the driver file.
Here we use clock_control_get_rate() to get the frequency dynamically.

Copilot · 2025-07-21T05:53:13Z

soc/microchip/sam/sama7g5/soc.c

+	/* Enable Generic clock for TC0 channels, frequency is 66.667MHz */
+	PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
+			    PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |
+			    PMC_PCR_PID(ID_TC0_CHANNEL0);
+	PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
+			    PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |
+			    PMC_PCR_PID(ID_TC0_CHANNEL1);
+	PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
+			    PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |
+			    PMC_PCR_PID(ID_TC0_CHANNEL2);
+
+	/* Enable Generic clock for TC1 channels, frequency is 66.667MHz */
+	PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
+			    PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |
+			    PMC_PCR_PID(ID_TC1_CHANNEL0);
+	PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
+			    PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |
+			    PMC_PCR_PID(ID_TC1_CHANNEL1);
+	PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
+			    PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |
+			    PMC_PCR_PID(ID_TC1_CHANNEL2);


The clock configuration code for TC channels contains significant duplication. Consider extracting this into a helper function or loop to reduce code repetition and improve maintainability.

Suggested change

/* Enable Generic clock for TC0 channels, frequency is 66.667MHz */

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(ID_TC0_CHANNEL0);

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(ID_TC0_CHANNEL1);

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(ID_TC0_CHANNEL2);

/* Enable Generic clock for TC1 channels, frequency is 66.667MHz */

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(ID_TC1_CHANNEL0);

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(ID_TC1_CHANNEL1);

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(ID_TC1_CHANNEL2);

/* Helper function to configure TC channels */

static void configure_tc_channel(uint32_t channel_id) {

PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |

PMC_PCR_GCLKDIV(6 - 1) | PMC_PCR_GCLKCSS_SYSPLL |

PMC_PCR_PID(channel_id);

}

/* Enable Generic clock for TC0 channels, frequency is 66.667MHz */

configure_tc_channel(ID_TC0_CHANNEL0);

configure_tc_channel(ID_TC0_CHANNEL1);

configure_tc_channel(ID_TC0_CHANNEL2);

/* Enable Generic clock for TC1 channels, frequency is 66.667MHz */

configure_tc_channel(ID_TC1_CHANNEL0);

configure_tc_channel(ID_TC1_CHANNEL1);

configure_tc_channel(ID_TC1_CHANNEL2);

Good advice, and codes has been updated.

Copilot · 2025-07-21T05:53:14Z

drivers/counter/counter_mchp_sam_tc.c

+
+	config->irq_config_func(dev);
+
+	LOG_INF("Device %s initialized, reg:0x%08x cs:%d freq:%u channels:%u top_alarm:%u\n\r",


The log message contains a Windows-style line ending (\n\r). In embedded systems, typically only \n is used. Consider removing the \r for consistency with standard practices.

Suggested change

LOG_INF("Device %s initialized, reg:0x%08x cs:%d freq:%u channels:%u top_alarm:%u\n\r",

LOG_INF("Device %s initialized, reg:0x%08x cs:%d freq:%u channels:%u top_alarm:%u\n",

No need for any line ending, actually

All LOG_foo already add new line. I recommend you drop all \n and \r.

Many thanks for review.
Got it, codes has been updated.

Copilot · 2025-07-21T05:53:14Z

drivers/counter/counter_mchp_sam_tc.c

+	USEC_PER_SEC,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128,
+	DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency),
+	USEC_PER_SEC,
+	USEC_PER_SEC,
+	USEC_PER_SEC,


USEC_PER_SEC (1000000) appears to be used as a placeholder frequency value in multiple array positions. This magic number usage makes the code unclear. Consider using a named constant or documenting why this specific value is used for these clock selections.

Suggested change

USEC_PER_SEC,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128,

DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency),

USEC_PER_SEC,

USEC_PER_SEC,

USEC_PER_SEC,

TC_INPUT_FREQ_PLACEHOLDER,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32,

DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128,

DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency),

TC_INPUT_FREQ_PLACEHOLDER,

TC_INPUT_FREQ_PLACEHOLDER,

TC_INPUT_FREQ_PLACEHOLDER,

Codes has been updated, and remove these unused array member.

Codes has been updated, and remove all hard-coded clock frequencies.

nandojve · 2025-07-21T05:50:13Z

boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts

@@ -29,6 +29,10 @@
 		slow_xtal {
 			clock-frequency = <32768>;
 		};
+
+		mck1 {
+			clock-frequency = <200000000>;


DT_FREQ_M(200)

Codes has been updated.

nandojve · 2025-07-21T05:52:29Z

dts/arm/microchip/sam/sama7g5.dtsi

+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 88>;
+				assigned-clock-rates = <66666666>;


The assigned-clock-rates has a default value, no need to add then here. Same with clock-selection. If intention is avoid user iteration with this properties this could cause misleading configuration. You can drop the default and use required: true to force always a definition.

Codes has been updated in dtsi and dts file, delete assignment operations for "assigned-clock-rates" and "clock-selection".

The "assigned-clock-rates" has been removed, and we will get the clock rates from clock_control_get_rate().

samples/drivers/counter/alarm/src/main.c

nandojve · 2025-07-21T06:03:26Z

drivers/counter/counter_mchp_sam_tc.c

+
+	config->irq_config_func(dev);
+
+	LOG_INF("Device %s initialized, reg:0x%08x cs:%d freq:%u channels:%u top_alarm:%u\n\r",


All LOG_foo already add new line. I recommend you drop all \n and \r.

nandojve · 2025-07-21T06:07:45Z

drivers/counter/counter_mchp_sam_tc.c

+	USEC_PER_SEC,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 8,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 32,
+	DT_PROP(DT_PATH(clocks, mck1), clock_frequency) / 128,
+	DT_PROP(DT_PATH(clocks, slow_xtal), clock_frequency),
+	USEC_PER_SEC,
+	USEC_PER_SEC,
+	USEC_PER_SEC,


Remember that mck1 must be fixed at compile time and can not change during runtime.

kartben · 2025-07-21T05:53:42Z

dts/bindings/counter/microchip,sam-tc.yaml

+
+  assigned-clock-rates:
+    type: int
+    default: 66666667


Default value needs to be explained in the description

Added description for this default value in yaml file.

The "assigned-clock-rates" has been removed, and we will get the clock rates from clock_control_get_rate().

kartben · 2025-07-21T05:55:51Z

drivers/counter/counter_mchp_sam_tc.c

+
+	config->irq_config_func(dev);
+
+	LOG_INF("Device %s initialized, reg:0x%08x cs:%d freq:%u channels:%u top_alarm:%u\n\r",


No need for any line ending, actually

TonyHan11 · 2025-07-22T06:54:14Z

As the TC (Timer Counter) on sama7g54 is quite similar to the one on samx7x, it's better to reuse the driver already existed (drivers/counter/counter_sam_tc.c).

TonyHan11 · 2025-07-23T04:24:08Z

dts/arm/microchip/sam/sama7g5.dtsi

+			};
+
+			tc0_ch1: timer@e2814040 {
+				compatible = "microchip,sam-tc";


It would be more reasonable for registering tc0 and tc1 as the Zephyr devices than registering every channels of tc0/1.

The existing driver registers tc0/1/2 as the Zephyr devices and only use the channel 0 for acting as the counter.

It is possible to upgrade the structure to the following:

tc0: timer@e2814000 { compatible = "microchip,sam-tc"; ... tc0_ch0: tc0_ch0@0 { compatible = "microchip,sam-tc-channel"; ... }; tc0_ch1: tc0_ch1@40 { compatible = "microchip,sam-tc-channel"; ... }; tc0_ch2: tc0_ch2@80 { compatible = "microchip,sam-tc-channel"; ... }; }; tc1: timer@e0800000 { compatible = "microchip,sam-tc"; ... };

The driver code might be like the following:

struct sam_tc_config { ... struct sam_tc_channel_data *const *data; }; /* array for channels */ \ static struct sam_tc_channel_data *const \ sam_tc_##n##_channel_datas \ [DT_INST_FOREACH_CHILD_SEP_VARGS( \ n, DT_NODE_HAS_COMPAT, (+), microchip_sam_tc_channel)] = { \ DT_INST_FOREACH_CHILD_STATUS_OKAY(n, ...) \ }; \ static const struct sam_tc_config sam_tc_##n##_config = { \ ... \ .data = sam_tc_##n##_channel_datas, \ }; \ static int sam_tc_start(const struct device *dev) { const struct sam_tc_config *config = dev->config; /* get channel id according to dev->data */ int channel_id = ((struct sam_tc_channel_data *const *)dev->data) - config->data; /* start tc channel x */ ... }

And operating a dedicated channel in the tc0/1 devices could be:

dev->data = ... counter_start(dev);

The current implementation from Zephyr may have problems with Alarms. This is an open issue #85018 that has some information. It will be nice if the driver is planned to address the issue and have full capability of usage.

A little updates for the end of above comment on operating a dedicated channel: defined every channel is as a device too and it's no need to change dev->data before calling counter_start(dev);.

The current implementation from Zephyr may have problems with Alarms. This is an open issue #85018 that has some information. It will be nice if the driver is planned to address the issue and have full capability of usage.

I have share a patch for fix it in #85018

After discuss with Tony, we will try to register mchp_sam_tc device follow this way in the next stage.

MCHP-MPU-Solutions-SHA · 2025-07-23T08:00:50Z

As the TC (Timer Counter) on sama7g54 is quite similar to the one on samx7x, it's better to reuse the driver already existed (drivers/counter/counter_sam_tc.c).

After discussed with Tony, we will not maintain / reuse the SAM MCU TC driver, SAM MPU has it's own TC driver (mchp_sam_tc).

nandojve

Maybe look inside tests, like https://github.com/zephyrproject-rtos/zephyr/tree/main/tests/drivers/counter/counter_basic_api and make sure they will run.

BTW, you can add an special entry here if needed

https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/drivers/counter/counter_basic_api/testcase.yaml

nandojve · 2025-07-26T10:26:29Z

drivers/counter/CMakeLists.txt

@@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_RTC_STM32           counter_ll_stm32
 zephyr_library_sources_ifdef(CONFIG_COUNTER_TIMER_STM32         counter_ll_stm32_timer.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_SAM_TC              counter_sam_tc.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_SAM0_TC32           counter_sam0_tc32.c)
+zephyr_library_sources_ifdef(CONFIG_COUNTER_MCHP_SAM_TC         counter_mchp_sam_tc.c)


This commit should be after the dtsi inside dts folder.
Try to keep in mind that first came the dependency and then you can use it.

Understand, add a new commit for updating CMakelists,txt.

nandojve · 2025-07-26T10:26:45Z

drivers/counter/Kconfig

@@ -124,4 +124,6 @@ source "drivers/counter/Kconfig.cc23x0_lgpt"

 source "drivers/counter/Kconfig.mspm0"

+source "drivers/counter/Kconfig.mchp_sam_tc"


sort by name

nandojve · 2025-07-26T10:28:59Z

boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts

+&tc0_ch0 {
+	status = "okay";
+};


Do you want to have all the TC enables in the board all the time ?
BTW, what are the speeds ?

Maybe you could keep board clean and setup overlays when appropriated.

Yes, it's not necessary to enable all TCs in the dts.
Just keep one enabled in the dts.

BTW, what are the speeds ?
--> by default GCLK will be selected as the clock source of TC (clock-selection = 0), and the frequency of source clock will be get via sam_tc_get_freq() function call dynamically, normally it's 200MHz / 3 = 66.667MHz.

Add driver for sama7g5 Timer Counter (TC) Signed-off-by: CHEN Xing <[email protected]>

Add tc0, tc1 devices to sama7g5 Signed-off-by: CHEN Xing <[email protected]>

Add support for mchp_sam_tc driver in counter Signed-off-by: CHEN Xing <[email protected]>

Add tc0, tc1 devices for sama7g5-ek Signed-off-by: CHEN Xing <[email protected]>

Add tc0_ch0 device for sama7g5 in alarm sample Signed-off-by: CHEN Xing <[email protected]>

Enable test support for microchip,sam-tc Signed-off-by: CHEN Xing <[email protected]>

MCHP-MPU-Solutions-SHA · 2025-07-28T08:56:52Z

Maybe look inside tests, like https://github.com/zephyrproject-rtos/zephyr/tree/main/tests/drivers/counter/counter_basic_api and make sure they will run.

BTW, you can add an special entry here if needed

https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/drivers/counter/counter_basic_api/testcase.yaml

MCHP-MPU-Solutions-SHA · 2025-07-28T09:00:06Z

Maybe look inside tests, like https://github.com/zephyrproject-rtos/zephyr/tree/main/tests/drivers/counter/counter_basic_api and make sure they will run.

BTW, you can add an special entry here if needed

https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/drivers/counter/counter_basic_api/testcase.yaml

Thanks for this suggestion, I have enable microchip,sam-tc support in counter_basic_api test.

sonarqubecloud · 2025-07-28T09:22:45Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

mchp-asif · 2025-07-28T10:18:19Z

@MCHP-MPU-Solutions-SHA Please ensure that the file namings are as per the microchip's RFC here : RFC

zephyrbot added platform: Microchip SAM Microchip SAM Platform (formerly Atmel SAM) platform: Microchip MEC Microchip MEC Platform area: Samples Samples area: Counter labels Jul 21, 2025

zephyrbot requested review from albertofloyd, jvasanth1, kartben, mnkp, nandojve, nashif, nordic-krch, pdgendt, stephanosio and VenkatKotakonda July 21, 2025 05:16

zephyrbot assigned nordic-krch Jul 21, 2025

kartben requested a review from Copilot July 21, 2025 05:52

Copilot AI reviewed Jul 21, 2025

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nandojve requested changes Jul 21, 2025

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kartben reviewed Jul 21, 2025

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MCHP-MPU-Solutions-SHA force-pushed the sama7g5_tc branch from c7138f0 to 87b6149 Compare July 22, 2025 06:37

TonyHan11 reviewed Jul 23, 2025

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MCHP-MPU-Solutions-SHA force-pushed the sama7g5_tc branch from 87b6149 to 640f08e Compare July 23, 2025 07:51

MCHP-MPU-Solutions-SHA requested a review from nandojve July 23, 2025 08:05

nandojve requested changes Jul 26, 2025

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MCHP-MPU-Solutions-SHA added 4 commits July 28, 2025 15:59

drivers: counter: add tc for sama7g5

7b47d33

Add driver for sama7g5 Timer Counter (TC) Signed-off-by: CHEN Xing <[email protected]>

dts: arm: microchip: sam: add tc device to sama7g5

769cba1

Add tc0, tc1 devices to sama7g5 Signed-off-by: CHEN Xing <[email protected]>

drivers: counter: Add support for mchp_sam_tc

90ce2c7

Add support for mchp_sam_tc driver in counter Signed-off-by: CHEN Xing <[email protected]>

boards: microchip: sam: add tc device for sama7g5-ek

0a21852

Add tc0, tc1 devices for sama7g5-ek Signed-off-by: CHEN Xing <[email protected]>

MCHP-MPU-Solutions-SHA added 2 commits July 28, 2025 16:17

samples: drivers: counter: alarm: add tc device for sama7g5

5efd191

Add tc0_ch0 device for sama7g5 in alarm sample Signed-off-by: CHEN Xing <[email protected]>

tests: counter: add support for microchip,sam-tc

1f66e3a

Enable test support for microchip,sam-tc Signed-off-by: CHEN Xing <[email protected]>

MCHP-MPU-Solutions-SHA force-pushed the sama7g5_tc branch from 640f08e to 1f66e3a Compare July 28, 2025 08:55

MCHP-MPU-Solutions-SHA closed this Jul 28, 2025

MCHP-MPU-Solutions-SHA reopened this Jul 28, 2025

albertofloyd removed their request for review August 4, 2025 20:45


		config->irq_config_func(dev);

		LOG_INF("Device %s initialized, reg:0x%08x cs:%d freq:%u channels:%u top_alarm:%u\n\r",

		@@ -124,4 +124,6 @@ source "drivers/counter/Kconfig.cc23x0_lgpt"

		source "drivers/counter/Kconfig.mspm0"

		source "drivers/counter/Kconfig.mchp_sam_tc"

Microchip sama7g5 tc driver #93401

Are you sure you want to change the base?

Microchip sama7g5 tc driver #93401

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MCHP-MPU-Solutions-SHA commented Jul 21, 2025

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TonyHan11 commented Jul 22, 2025

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MCHP-MPU-Solutions-SHA commented Jul 23, 2025

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