Skip to content

project/ad4062: Resolve critical warnings #1882

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
Open

project/ad4062: Resolve critical warnings #1882

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
608165d
fix: ad4062: coraz7s: Wrong constraints por name
gastmaier Aug 18, 2025
3c432fc
fix: library/i3c_controller: associate reset_n with s_axi_aclk
gastmaier Aug 18, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,8 @@ adi_set_ports_dependency "offload_trigger" \

set cc [ipx::current_core]

ipx::associate_bus_interfaces -clock s_axi_aclk -reset reset_n $cc

## ID
set_property -dict [list \
"value_validation_type" "range_long" \
Expand Down
24 changes: 12 additions & 12 deletions projects/ad4062_ardz/coraz7s/system_constr.xdc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,14 +11,14 @@ set i3c_clk clk_fpga_0

# Input data driven the peripherals toggles every 4 cycles max (PP) of the capture clock
# gets registered by rx_reg
set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -setup 4
set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -hold 3
set_multicycle_path -from [get_ports iic_ard_sda] -to [get_clocks $i3c_clk] -setup 4
set_multicycle_path -from [get_ports iic_ard_sda] -to [get_clocks $i3c_clk] -hold 3

# Output data toggles every 2 cycles max of the capture clock (PP)
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -setup 2
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -hold 1
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -setup 2
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -hold 1
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_sda] -setup 2
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_sda] -hold 1
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_scl] -setup 2
set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_scl] -hold 1

# Notes
# tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns.
Expand All @@ -29,11 +29,11 @@ set tsco_max 12;
set tsco_min 8;
set trc_dly_max 1;
set trc_dly_min 0;
set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports i3c_sda]
set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports i3c_sda]
set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports iic_ard_sda]
set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports iic_ard_sda]
set tsu 2;
set thd 0;
set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_sda]
set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_sda]
set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_scl]
set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_scl]
set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports iic_ard_sda]
set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports iic_ard_sda]
set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports iic_ard_scl]
set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports iic_ard_scl]